arm: vf610: fix double iomux configuration for vf610twr board
[u-boot/qq2440-u-boot.git] / drivers / spi / sh_spi.c
blob7ca5e363da707ae5fe63dc421e0811c11b41ef77
1 /*
2 * SH SPI driver
4 * Copyright (C) 2011-2012 Renesas Solutions Corp.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <common.h>
22 #include <malloc.h>
23 #include <spi.h>
24 #include <asm/io.h>
25 #include "sh_spi.h"
27 static void sh_spi_write(unsigned long data, unsigned long *reg)
29 writel(data, reg);
32 static unsigned long sh_spi_read(unsigned long *reg)
34 return readl(reg);
37 static void sh_spi_set_bit(unsigned long val, unsigned long *reg)
39 unsigned long tmp;
41 tmp = sh_spi_read(reg);
42 tmp |= val;
43 sh_spi_write(tmp, reg);
46 static void sh_spi_clear_bit(unsigned long val, unsigned long *reg)
48 unsigned long tmp;
50 tmp = sh_spi_read(reg);
51 tmp &= ~val;
52 sh_spi_write(tmp, reg);
55 static void clear_fifo(struct sh_spi *ss)
57 sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2);
58 sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2);
61 static int recvbuf_wait(struct sh_spi *ss)
63 while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) {
64 if (ctrlc())
65 return 1;
66 udelay(10);
68 return 0;
71 static int write_fifo_empty_wait(struct sh_spi *ss)
73 while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) {
74 if (ctrlc())
75 return 1;
76 udelay(10);
78 return 0;
81 void spi_init(void)
85 static void sh_spi_set_cs(struct sh_spi *ss, unsigned int cs)
87 unsigned long val = 0;
89 if (cs & 0x01)
90 val |= SH_SPI_SSS0;
91 if (cs & 0x02)
92 val |= SH_SPI_SSS1;
94 sh_spi_clear_bit(SH_SPI_SSS0 | SH_SPI_SSS1, &ss->regs->cr4);
95 sh_spi_set_bit(val, &ss->regs->cr4);
98 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
99 unsigned int max_hz, unsigned int mode)
101 struct sh_spi *ss;
103 if (!spi_cs_is_valid(bus, cs))
104 return NULL;
106 ss = spi_alloc_slave(struct sh_spi, bus, cs);
107 if (!ss)
108 return NULL;
110 ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE;
112 /* SPI sycle stop */
113 sh_spi_write(0xfe, &ss->regs->cr1);
114 /* CR1 init */
115 sh_spi_write(0x00, &ss->regs->cr1);
116 /* CR3 init */
117 sh_spi_write(0x00, &ss->regs->cr3);
118 sh_spi_set_cs(ss, cs);
120 clear_fifo(ss);
122 /* 1/8 clock */
123 sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2);
124 udelay(10);
126 return &ss->slave;
129 void spi_free_slave(struct spi_slave *slave)
131 struct sh_spi *spi = to_sh_spi(slave);
133 free(spi);
136 int spi_claim_bus(struct spi_slave *slave)
138 return 0;
141 void spi_release_bus(struct spi_slave *slave)
143 struct sh_spi *ss = to_sh_spi(slave);
145 sh_spi_write(sh_spi_read(&ss->regs->cr1) &
146 ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1);
149 static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data,
150 unsigned int len, unsigned long flags)
152 int i, cur_len, ret = 0;
153 int remain = (int)len;
155 if (len >= SH_SPI_FIFO_SIZE)
156 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
158 while (remain > 0) {
159 cur_len = (remain < SH_SPI_FIFO_SIZE) ?
160 remain : SH_SPI_FIFO_SIZE;
161 for (i = 0; i < cur_len &&
162 !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) &&
163 !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF);
164 i++)
165 sh_spi_write(tx_data[i], &ss->regs->tbr_rbr);
167 cur_len = i;
169 if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) {
170 /* Abort the transaction */
171 flags |= SPI_XFER_END;
172 sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4);
173 ret = 1;
174 break;
177 remain -= cur_len;
178 tx_data += cur_len;
180 if (remain > 0)
181 write_fifo_empty_wait(ss);
184 if (flags & SPI_XFER_END) {
185 sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
186 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
187 udelay(100);
188 write_fifo_empty_wait(ss);
191 return ret;
194 static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data,
195 unsigned int len, unsigned long flags)
197 int i;
199 if (len > SH_SPI_MAX_BYTE)
200 sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3);
201 else
202 sh_spi_write(len, &ss->regs->cr3);
204 sh_spi_clear_bit(SH_SPI_SSD | SH_SPI_SSDB, &ss->regs->cr1);
205 sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1);
207 for (i = 0; i < len; i++) {
208 if (recvbuf_wait(ss))
209 return 0;
211 rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr);
213 sh_spi_write(0, &ss->regs->cr3);
215 return 0;
218 int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
219 void *din, unsigned long flags)
221 struct sh_spi *ss = to_sh_spi(slave);
222 const unsigned char *tx_data = dout;
223 unsigned char *rx_data = din;
224 unsigned int len = bitlen / 8;
225 int ret = 0;
227 if (flags & SPI_XFER_BEGIN)
228 sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA,
229 &ss->regs->cr1);
231 if (tx_data)
232 ret = sh_spi_send(ss, tx_data, len, flags);
234 if (ret == 0 && rx_data)
235 ret = sh_spi_receive(ss, rx_data, len, flags);
237 if (flags & SPI_XFER_END) {
238 sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1);
239 udelay(100);
241 sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD,
242 &ss->regs->cr1);
243 clear_fifo(ss);
246 return ret;
249 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
251 if (!bus && cs < SH_SPI_NUM_CS)
252 return 1;
253 else
254 return 0;
257 void spi_cs_activate(struct spi_slave *slave)
262 void spi_cs_deactivate(struct spi_slave *slave)