board/LEOX/elpt860/elpt860.c

   1 /*
   2 **=====================================================================
   3 **
   4 ** Copyright (C) 2000, 2001, 2002, 2003
   5 ** The LEOX team <team@leox.org>, http://www.leox.org
   6 **
   7 ** LEOX.org is about the development of free hardware and software resources
   8 **   for system on chip.
   9 **
  10 ** Description: U-Boot port on the LEOX's ELPT860 CPU board
  11 ** ~~~~~~~~~~~
  12 **
  13 **=====================================================================
  14 **
  15  * SPDX-License-Identifier:     GPL-2.0+
  16 **
  17 **=====================================================================
  18 */
  19
  20 /*
  21 ** Note 1: In this file, you have to provide the following functions:
  22 ** ------
  23 **              int             board_early_init_f(void)
  24 **              int             checkboard(void)
  25 **              phys_size_t     initdram(int board_type)
  26 ** called from 'board_init_f()' into 'common/board.c'
  27 **
  28 **              void            reset_phy(void)
  29 ** called from 'board_init_r()' into 'common/board.c'
  30 */
  31
  32 #include <common.h>
  33 #include <mpc8xx.h>
  34
  35 /* ------------------------------------------------------------------------- */
  36
  37 static long int dram_size (long int, long int *, long int);
  38
  39 /* ------------------------------------------------------------------------- */
  40
  41 #define _NOT_USED_      0xFFFFFFFF
  42
  43 const uint init_sdram_table[] = {
  44         /*
  45          * Single Read. (Offset 0 in UPMA RAM)
  46          */
  47         0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
  48         0xFFFFFC04,             /* last */
  49         /*
  50          * SDRAM Initialization (offset 5 in UPMA RAM)
  51          *
  52          * This is no UPM entry point. The following definition uses
  53          * the remaining space to establish an initialization
  54          * sequence, which is executed by a RUN command.
  55          *
  56          */
  57         0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,     /* last */
  58         /*
  59          * Burst Read. (Offset 8 in UPMA RAM)
  60          */
  61         0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  62         0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  63         0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
  64         0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
  65         /*
  66          * Single Write. (Offset 18 in UPMA RAM)
  67          */
  68         0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
  69         0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
  70         /*
  71          * Burst Write. (Offset 20 in UPMA RAM)
  72          */
  73         0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  74         0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
  75         0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
  76         0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
  77 };
  78
  79 const uint sdram_table[] = {
  80         /*
  81          * Single Read. (Offset 0 in UPMA RAM)
  82          */
  83         0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
  84         0xFF0FFC00,             /* last */
  85         /*
  86          * SDRAM Initialization (offset 5 in UPMA RAM)
  87          *
  88          * This is no UPM entry point. The following definition uses
  89          * the remaining space to establish an initialization
  90          * sequence, which is executed by a RUN command.
  91          *
  92          */
  93         0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05,     /* last */
  94         /*
  95          * Burst Read. (Offset 8 in UPMA RAM)
  96          */
  97         0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
  98         0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
  99         0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
 100         0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
 101         /*
 102          * Single Write. (Offset 18 in UPMA RAM)
 103          */
 104         0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
 105         0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05,     /* last */
 106         _NOT_USED_,
 107         /*
 108          * Burst Write. (Offset 20 in UPMA RAM)
 109          */
 110         0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
 111         0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
 112         0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
 113         0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
 114         /*
 115          * Refresh  (Offset 30 in UPMA RAM)
 116          */
 117         0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
 118         0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
 119         0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
 120         /*
 121          * Exception. (Offset 3c in UPMA RAM)
 122          */
 123         0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
 124 };
 125
 126 /* ------------------------------------------------------------------------- */
 127
 128 #define CONFIG_SYS_PC4    0x0800
 129
 130 #define CONFIG_SYS_DS1    CONFIG_SYS_PC4
 131
 132 /*
 133  * Very early board init code (fpga boot, etc.)
 134  */
 135 int board_early_init_f (void)
 136 {
 137         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 138
 139         /*
 140          * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
 141          */
 142         immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1;   /* PCDAT (DS1 = 0)                */
 143         immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1;   /* PCPAR (0=general purpose I/O)  */
 144         immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1;    /* PCDIR (I/O: 0=input, 1=output) */
 145
 146         return (0);             /* success */
 147 }
 148
 149 /*
 150  * Check Board Identity:
 151  *
 152  * Test ELPT860 ID string
 153  *
 154  * Return 1 if no second DRAM bank, otherwise returns 0
 155  */
 156
 157 int checkboard (void)
 158 {
 159         char buf[64];
 160         int i = getenv_f("serial#", buf, sizeof(buf));
 161
 162         if ((i < 0) || strncmp(buf, "ELPT860", 7))
 163                 printf ("### No HW ID - assuming ELPT860\n");
 164
 165         return (0);             /* success */
 166 }
 167
 168 /* ------------------------------------------------------------------------- */
 169
 170 phys_size_t initdram (int board_type)
 171 {
 172         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 173         volatile memctl8xx_t *memctl = &immap->im_memctl;
 174         long int size8, size9;
 175         long int size_b0 = 0;
 176
 177         /*
 178          * This sequence initializes SDRAM chips on ELPT860 board
 179          */
 180         upmconfig (UPMA, (uint *) init_sdram_table,
 181                    sizeof (init_sdram_table) / sizeof (uint));
 182
 183         memctl->memc_mptpr = 0x0200;
 184         memctl->memc_mamr = 0x18002111;
 185
 186         memctl->memc_mar = 0x00000088;
 187         memctl->memc_mcr = 0x80002000;  /* CS1: SDRAM bank 0 */
 188
 189         upmconfig (UPMA, (uint *) sdram_table,
 190                    sizeof (sdram_table) / sizeof (uint));
 191
 192         /*
 193          * Preliminary prescaler for refresh (depends on number of
 194          * banks): This value is selected for four cycles every 62.4 us
 195          * with two SDRAM banks or four cycles every 31.2 us with one
 196          * bank. It will be adjusted after memory sizing.
 197          */
 198         memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 199
 200         /*
 201          * The following value is used as an address (i.e. opcode) for
 202          * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
 203          * the port size is 32bit the SDRAM does NOT "see" the lower two
 204          * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
 205          * MICRON SDRAMs:
 206          * ->    0 00 010 0 010
 207          *       |  |   | |   +- Burst Length = 4
 208          *       |  |   | +----- Burst Type   = Sequential
 209          *       |  |   +------- CAS Latency  = 2
 210          *       |  +----------- Operating Mode = Standard
 211          *       +-------------- Write Burst Mode = Programmed Burst Length
 212          */
 213         memctl->memc_mar = 0x00000088;
 214
 215         /*
 216          * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
 217          * preliminary addresses - these have to be modified after the
 218          * SDRAM size has been determined.
 219          */
 220         memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 221         memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 222
 223         memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 224
 225         udelay (200);
 226
 227         /* perform SDRAM initializsation sequence */
 228
 229         memctl->memc_mcr = 0x80002105;  /* CS1: SDRAM bank 0 */
 230         udelay (1);
 231         memctl->memc_mcr = 0x80002230;  /* CS1: SDRAM bank 0 - execute twice */
 232         udelay (1);
 233
 234         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 235
 236         udelay (1000);
 237
 238         /*
 239          * Check Bank 0 Memory Size for re-configuration
 240          *
 241          * try 8 column mode
 242          */
 243         size8 = dram_size (CONFIG_SYS_MAMR_8COL,
 244                            SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 245
 246         udelay (1000);
 247
 248         /*
 249          * try 9 column mode
 250          */
 251         size9 = dram_size (CONFIG_SYS_MAMR_9COL,
 252                            SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 253
 254         if (size8 < size9) {    /* leave configuration at 9 columns       */
 255                 size_b0 = size9;
 256                 /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
 257         } else {                /* back to 8 columns                      */
 258
 259                 size_b0 = size8;
 260                 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 261                 udelay (500);
 262                 /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
 263         }
 264
 265         udelay (1000);
 266
 267         /*
 268          * Adjust refresh rate depending on SDRAM type, both banks
 269          * For types > 128 MBit leave it at the current (fast) rate
 270          */
 271         if (size_b0 < 0x02000000) {
 272                 /* reduce to 15.6 us (62.4 us / quad) */
 273                 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 274                 udelay (1000);
 275         }
 276
 277         /*
 278          * Final mapping: map bigger bank first
 279          */
 280         memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 281         memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 282
 283         {
 284                 unsigned long reg;
 285
 286                 /* adjust refresh rate depending on SDRAM type, one bank */
 287                 reg = memctl->memc_mptpr;
 288                 reg >>= 1;      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 289                 memctl->memc_mptpr = reg;
 290         }
 291
 292         udelay (10000);
 293
 294         return (size_b0);
 295 }
 296
 297 /* ------------------------------------------------------------------------- */
 298
 299 /*
 300  * Check memory range for valid RAM. A simple memory test determines
 301  * the actually available RAM size between addresses `base' and
 302  * `base + maxsize'. Some (not all) hardware errors are detected:
 303  * - short between address lines
 304  * - short between data lines
 305  */
 306
 307 static long int
 308 dram_size (long int mamr_value, long int *base, long int maxsize)
 309 {
 310         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 311         volatile memctl8xx_t *memctl = &immap->im_memctl;
 312
 313         memctl->memc_mamr = mamr_value;
 314
 315         return (get_ram_size (base, maxsize));
 316 }
 317
 318 /* ------------------------------------------------------------------------- */
 319
 320 #define CONFIG_SYS_PA1     0x4000
 321 #define CONFIG_SYS_PA2     0x2000
 322
 323 #define CONFIG_SYS_LBKs    (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)
 324
 325 void reset_phy (void)
 326 {
 327         volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 328
 329         /*
 330          * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
 331          *                                          and no AUI loopback
 332          */
 333         immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs;  /* PADAT (LBK eth 1&2 = 0)        */
 334         immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs;  /* PAPAR (0=general purpose I/O)  */
 335         immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs;   /* PADIR (I/O: 0=input, 1=output) */
 336 }