board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/at91sam9g45_matrix.h>
  12 #include <asm/arch/at91sam9_smc.h>
  13 #include <asm/arch/at91_common.h>
  14 #include <asm/arch/at91_pmc.h>
  15 #include <asm/arch/gpio.h>
  16 #include <asm/arch/clk.h>
  17 #include <lcd.h>
  18 #include <atmel_lcdc.h>
  19 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  20 #include <net.h>
  21 #endif
  22 #include <netdev.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 /* ------------------------------------------------------------------------- */
  27 /*
  28  * Miscelaneous platform dependent initialisations
  29  */
  30
  31 #ifdef CONFIG_CMD_NAND
  32 void at91sam9m10g45ek_nand_hw_init(void)
  33 {
  34         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  35         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  36         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  37         unsigned long csa;
  38
  39         /* Enable CS3 */
  40         csa = readl(&matrix->ebicsa);
  41         csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  42         writel(csa, &matrix->ebicsa);
  43
  44         /* Configure SMC CS3 for NAND/SmartMedia */
  45         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  46                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  47                &smc->cs[3].setup);
  48         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
  49                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
  50                &smc->cs[3].pulse);
  51         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
  52                &smc->cs[3].cycle);
  53         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  54                AT91_SMC_MODE_EXNW_DISABLE |
  55 #ifdef CONFIG_SYS_NAND_DBW_16
  56                AT91_SMC_MODE_DBW_16 |
  57 #else /* CONFIG_SYS_NAND_DBW_8 */
  58                AT91_SMC_MODE_DBW_8 |
  59 #endif
  60                AT91_SMC_MODE_TDF_CYCLE(3),
  61                &smc->cs[3].mode);
  62
  63         writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  64
  65         /* Configure RDY/BSY */
  66         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  67
  68         /* Enable NandFlash */
  69         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  70 }
  71 #endif
  72
  73 #ifdef CONFIG_CMD_USB
  74 static void at91sam9m10g45ek_usb_hw_init(void)
  75 {
  76         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  77
  78         writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
  79
  80         at91_set_gpio_output(AT91_PIN_PD1, 0);
  81         at91_set_gpio_output(AT91_PIN_PD3, 0);
  82 }
  83 #endif
  84
  85 #ifdef CONFIG_MACB
  86 static void at91sam9m10g45ek_macb_hw_init(void)
  87 {
  88         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  89         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  90
  91         /* Enable clock */
  92         writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  93
  94         /*
  95          * Disable pull-up on:
  96          *      RXDV (PA15) => PHY normal mode (not Test mode)
  97          *      ERX0 (PA12) => PHY ADDR0
  98          *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
  99          *
 100          * PHY has internal pull-down
 101          */
 102         writel(pin_to_mask(AT91_PIN_PA15) |
 103                pin_to_mask(AT91_PIN_PA12) |
 104                pin_to_mask(AT91_PIN_PA13),
 105                &pioa->pudr);
 106
 107         at91_phy_reset();
 108
 109         /* Re-enable pull-up */
 110         writel(pin_to_mask(AT91_PIN_PA15) |
 111                pin_to_mask(AT91_PIN_PA12) |
 112                pin_to_mask(AT91_PIN_PA13),
 113                &pioa->puer);
 114
 115         /* And the pins. */
 116         at91_macb_hw_init();
 117 }
 118 #endif
 119
 120 #ifdef CONFIG_LCD
 121
 122 vidinfo_t panel_info = {
 123         vl_col:         480,
 124         vl_row:         272,
 125         vl_clk:         9000000,
 126         vl_sync:        ATMEL_LCDC_INVLINE_NORMAL |
 127                         ATMEL_LCDC_INVFRAME_NORMAL,
 128         vl_bpix:        3,
 129         vl_tft:         1,
 130         vl_hsync_len:   45,
 131         vl_left_margin: 1,
 132         vl_right_margin:1,
 133         vl_vsync_len:   1,
 134         vl_upper_margin:40,
 135         vl_lower_margin:1,
 136         mmio :           ATMEL_BASE_LCDC,
 137 };
 138
 139
 140 void lcd_enable(void)
 141 {
 142         at91_set_A_periph(AT91_PIN_PE6, 1);     /* power up */
 143 }
 144
 145 void lcd_disable(void)
 146 {
 147         at91_set_A_periph(AT91_PIN_PE6, 0);     /* power down */
 148 }
 149
 150 static void at91sam9m10g45ek_lcd_hw_init(void)
 151 {
 152         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 153
 154         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 155         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
 156         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
 157         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
 158         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
 159
 160         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
 161         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
 162         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
 163         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
 164         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
 165         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
 166         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
 167         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
 168         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
 169         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
 170         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
 171         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
 172         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
 173         at91_set_B_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
 174         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
 175         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
 176         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
 177         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
 178         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
 179         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
 180         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
 181         at91_set_B_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
 182         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
 183         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
 184
 185         writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 186
 187         gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 188 }
 189
 190 #ifdef CONFIG_LCD_INFO
 191 #include <nand.h>
 192 #include <version.h>
 193
 194 void lcd_show_board_info(void)
 195 {
 196         ulong dram_size, nand_size;
 197         int i;
 198         char temp[32];
 199
 200         lcd_printf ("%s\n", U_BOOT_VERSION);
 201         lcd_printf ("(C) 2008 ATMEL Corp\n");
 202         lcd_printf ("at91support@atmel.com\n");
 203         lcd_printf ("%s CPU at %s MHz\n",
 204                 ATMEL_CPU_NAME,
 205                 strmhz(temp, get_cpu_clk_rate()));
 206
 207         dram_size = 0;
 208         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 209                 dram_size += gd->bd->bi_dram[i].size;
 210         nand_size = 0;
 211         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 212                 nand_size += nand_info[i].size;
 213         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 214                 dram_size >> 20,
 215                 nand_size >> 20 );
 216 }
 217 #endif /* CONFIG_LCD_INFO */
 218 #endif
 219
 220 int board_early_init_f(void)
 221 {
 222         at91_seriald_hw_init();
 223         return 0;
 224 }
 225
 226 int board_init(void)
 227 {
 228         /* arch number of AT91SAM9M10G45EK-Board */
 229 #ifdef CONFIG_AT91SAM9M10G45EK
 230         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
 231 #elif defined CONFIG_AT91SAM9G45EKES
 232         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
 233 #endif
 234
 235         /* adress of boot parameters */
 236         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 237
 238 #ifdef CONFIG_CMD_NAND
 239         at91sam9m10g45ek_nand_hw_init();
 240 #endif
 241 #ifdef CONFIG_CMD_USB
 242         at91sam9m10g45ek_usb_hw_init();
 243 #endif
 244 #ifdef CONFIG_HAS_DATAFLASH
 245         at91_spi0_hw_init(1 << 0);
 246 #endif
 247 #ifdef CONFIG_ATMEL_SPI
 248         at91_spi0_hw_init(1 << 4);
 249 #endif
 250 #ifdef CONFIG_MACB
 251         at91sam9m10g45ek_macb_hw_init();
 252 #endif
 253 #ifdef CONFIG_LCD
 254         at91sam9m10g45ek_lcd_hw_init();
 255 #endif
 256         return 0;
 257 }
 258
 259 int dram_init(void)
 260 {
 261         gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
 262                                     CONFIG_SYS_SDRAM_SIZE);
 263         return 0;
 264 }
 265
 266 #ifdef CONFIG_RESET_PHY_R
 267 void reset_phy(void)
 268 {
 269 }
 270 #endif
 271
 272 int board_eth_init(bd_t *bis)
 273 {
 274         int rc = 0;
 275 #ifdef CONFIG_MACB
 276         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 277 #endif
 278         return rc;
 279 }
 280
 281 /* SPI chip select control */
 282 #ifdef CONFIG_ATMEL_SPI
 283 #include <spi.h>
 284
 285 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 286 {
 287         return bus == 0 && cs < 2;
 288 }
 289
 290 void spi_cs_activate(struct spi_slave *slave)
 291 {
 292         switch(slave->cs) {
 293                 case 1:
 294                         at91_set_gpio_output(AT91_PIN_PB18, 0);
 295                         break;
 296                 case 0:
 297                 default:
 298                         at91_set_gpio_output(AT91_PIN_PB3, 0);
 299                         break;
 300         }
 301 }
 302
 303 void spi_cs_deactivate(struct spi_slave *slave)
 304 {
 305         switch(slave->cs) {
 306                 case 1:
 307                         at91_set_gpio_output(AT91_PIN_PB18, 1);
 308                         break;
 309                 case 0:
 310                 default:
 311                         at91_set_gpio_output(AT91_PIN_PB3, 1);
 312                 break;
 313         }
 314 }
 315 #endif /* CONFIG_ATMEL_SPI */