board/matrix_vision/mvblm7/fpga.c

   1 /*
   2  * (C) Copyright 2002
   3  * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
   4  * Keith Outwater, keith_outwater@mvis.com.
   5  *
   6  * (C) Copyright 2008
   7  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <ACEX1K.h>
  14 #include <command.h>
  15 #include "fpga.h"
  16 #include "mvblm7.h"
  17
  18 #ifdef FPGA_DEBUG
  19 #define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
  20 #else
  21 #define fpga_debug(fmt, args...)
  22 #endif
  23
  24 Altera_CYC2_Passive_Serial_fns altera_fns = {
  25         fpga_null_fn,
  26         fpga_config_fn,
  27         fpga_status_fn,
  28         fpga_done_fn,
  29         fpga_wr_fn,
  30         fpga_null_fn,
  31         fpga_null_fn,
  32 };
  33
  34 Altera_desc cyclone2 = {
  35         Altera_CYC2,
  36         passive_serial,
  37         Altera_EP2C20_SIZE,
  38         (void *) &altera_fns,
  39         NULL,
  40         0
  41 };
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 int mvblm7_init_fpga(void)
  46 {
  47         fpga_debug("Initialize FPGA interface\n");
  48         fpga_init();
  49         fpga_add(fpga_altera, &cyclone2);
  50         fpga_config_fn(0, 1, 0);
  51         udelay(60);
  52
  53         return 1;
  54 }
  55
  56 int fpga_null_fn(int cookie)
  57 {
  58         return 0;
  59 }
  60
  61 int fpga_config_fn(int assert, int flush, int cookie)
  62 {
  63         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  64         volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
  65         u32 dvo = gpio->dat;
  66
  67         fpga_debug("SET config : %s\n", assert ? "low" : "high");
  68         if (assert)
  69                 dvo |= FPGA_CONFIG;
  70         else
  71                 dvo &= ~FPGA_CONFIG;
  72
  73         if (flush)
  74                 gpio->dat = dvo;
  75
  76         return assert;
  77 }
  78
  79 int fpga_done_fn(int cookie)
  80 {
  81         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  82         volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
  83         int result = 0;
  84
  85         udelay(10);
  86         fpga_debug("CONF_DONE check ... ");
  87         if (gpio->dat & FPGA_CONF_DONE)  {
  88                 fpga_debug("high\n");
  89                 result = 1;
  90         } else
  91                 fpga_debug("low\n");
  92
  93         return result;
  94 }
  95
  96 int fpga_status_fn(int cookie)
  97 {
  98         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  99         volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 100         int result = 0;
 101
 102         fpga_debug("STATUS check ... ");
 103         if (gpio->dat & FPGA_STATUS)  {
 104                 fpga_debug("high\n");
 105                 result = 1;
 106         } else
 107                 fpga_debug("low\n");
 108
 109         return result;
 110 }
 111
 112 int fpga_clk_fn(int assert_clk, int flush, int cookie)
 113 {
 114         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 115         volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 116         u32 dvo = gpio->dat;
 117
 118         fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
 119         if (assert_clk)
 120                 dvo |= FPGA_CCLK;
 121         else
 122                 dvo &= ~FPGA_CCLK;
 123
 124         if (flush)
 125                 gpio->dat = dvo;
 126
 127         return assert_clk;
 128 }
 129
 130 static inline int _write_fpga(u8 val, int dump)
 131 {
 132         volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 133         volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 134         int i;
 135         u32 dvo = gpio->dat;
 136
 137         if (dump)
 138                 fpga_debug("  %02x -> ", val);
 139         for (i = 0; i < 8; i++) {
 140                 dvo &= ~FPGA_CCLK;
 141                 gpio->dat = dvo;
 142                 dvo &= ~FPGA_DIN;
 143                 if (dump)
 144                         fpga_debug("%d ", val&1);
 145                 if (val & 1)
 146                         dvo |= FPGA_DIN;
 147                 gpio->dat = dvo;
 148                 dvo |= FPGA_CCLK;
 149                 gpio->dat = dvo;
 150                 val >>= 1;
 151         }
 152         if (dump)
 153                 fpga_debug("\n");
 154
 155         return 0;
 156 }
 157
 158 int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
 159 {
 160         unsigned char *data = (unsigned char *) buf;
 161         int i;
 162
 163         fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
 164         for (i = 0; i < len; i++)
 165                 _write_fpga(data[i], 0);
 166         fpga_debug("\n");
 167
 168         return FPGA_SUCCESS;
 169 }