board/matrix_vision/mvblm7/mvblm7.c

   1 /*
   2  * Copyright (C) Freescale Semiconductor, Inc. 2006.
   3  *
   4  * (C) Copyright 2008
   5  * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <ioports.h>
  12 #include <mpc83xx.h>
  13 #include <asm/mpc8349_pci.h>
  14 #include <pci.h>
  15 #include <spi.h>
  16 #include <asm/mmu.h>
  17 #if defined(CONFIG_OF_LIBFDT)
  18 #include <libfdt.h>
  19 #endif
  20
  21 #include "../common/mv_common.h"
  22 #include "mvblm7.h"
  23
  24 int fixed_sdram(void)
  25 {
  26         volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  27         u32 msize = 0;
  28         u32 ddr_size;
  29         u32 ddr_size_log2;
  30         char *s = getenv("ddr_size");
  31
  32         msize = CONFIG_SYS_DDR_SIZE;
  33         if (s) {
  34                 u32 env_ddr_size = simple_strtoul(s, NULL, 10);
  35                 if (env_ddr_size == 512)
  36                         msize = 512;
  37         }
  38
  39         for (ddr_size = msize << 20, ddr_size_log2 = 0;
  40              (ddr_size > 1);
  41              ddr_size = ddr_size >> 1, ddr_size_log2++) {
  42                 if (ddr_size & 1)
  43                         return -1;
  44         }
  45         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
  46         im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
  47                 LAWAR_SIZE);
  48
  49         im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
  50         im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  51         im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  52         im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  53         im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  54         im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  55         im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
  56         im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
  57         im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  58         im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
  59         im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  60         im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  61
  62         asm("sync;isync");
  63         udelay(600);
  64
  65         im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  66
  67         asm("sync;isync");
  68         udelay(500);
  69
  70         return msize;
  71 }
  72
  73 phys_size_t initdram(int board_type)
  74 {
  75         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  76         u32 msize = 0;
  77
  78         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  79                 return -1;
  80
  81         im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
  82         msize = fixed_sdram();
  83
  84         /* return total bus RAM size(bytes) */
  85         return msize * 1024 * 1024;
  86 }
  87
  88 int misc_init_r(void)
  89 {
  90         char *s = getenv("reset_env");
  91
  92         if (s) {
  93                 mv_reset_environment();
  94         }
  95
  96         return 0;
  97 }
  98
  99 int checkboard(void)
 100 {
 101         puts("Board: Matrix Vision mvBlueLYNX-M7\n");
 102
 103         return 0;
 104 }
 105
 106 #ifdef CONFIG_HARD_SPI
 107 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 108 {
 109         return bus == 0 && cs == 0;
 110 }
 111
 112 void spi_cs_activate(struct spi_slave *slave)
 113 {
 114         volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 115
 116         iopd->dat &= ~MVBLM7_MMC_CS;
 117 }
 118
 119 void spi_cs_deactivate(struct spi_slave *slave)
 120 {
 121         volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 122
 123         iopd->dat |= ~MVBLM7_MMC_CS;
 124 }
 125 #endif
 126
 127 #if defined(CONFIG_OF_BOARD_SETUP)
 128 void ft_board_setup(void *blob, bd_t *bd)
 129 {
 130         ft_cpu_setup(blob, bd);
 131 #ifdef CONFIG_PCI
 132         ft_pci_setup(blob, bd);
 133 #endif
 134 }
 135
 136 #endif