board/mimc/mimc200/mimc200.c

   1 /*
   2  * Copyright (C) 2006 Atmel Corporation
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <netdev.h>
   8
   9 #include <asm/io.h>
  10 #include <asm/sdram.h>
  11 #include <asm/arch/clk.h>
  12 #include <asm/arch/gpio.h>
  13 #include <asm/arch/hmatrix.h>
  14 #include <asm/arch/mmu.h>
  15 #include <asm/arch/portmux.h>
  16 #include <atmel_lcdc.h>
  17 #include <lcd.h>
  18
  19 #include "../../../arch/avr32/cpu/hsmc3.h"
  20
  21 struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
  22         {
  23                 .virt_pgno      = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
  24                 .nr_pages       = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
  25                 .phys           = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
  26                                         | MMU_VMR_CACHE_NONE,
  27         }, {
  28                 .virt_pgno      = EBI_SRAM_CS2_BASE >> PAGE_SHIFT,
  29                 .nr_pages       = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT,
  30                 .phys           = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT)
  31                                         | MMU_VMR_CACHE_NONE,
  32         }, {
  33                 .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
  34                 .nr_pages       = EBI_SDRAM_SIZE >> PAGE_SHIFT,
  35                 .phys           = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
  36                                         | MMU_VMR_CACHE_WRBACK,
  37         },
  38 };
  39
  40 #if defined(CONFIG_LCD)
  41 /* 480x272x16 @ 72 Hz */
  42 vidinfo_t panel_info = {
  43         .vl_col                 = 480,          /* Number of columns */
  44         .vl_row                 = 272,          /* Number of rows */
  45         .vl_clk                 = 5000000,      /* pixel clock in ps */
  46         .vl_sync                = ATMEL_LCDC_INVCLK_INVERTED |
  47                                   ATMEL_LCDC_INVLINE_INVERTED |
  48                                   ATMEL_LCDC_INVFRAME_INVERTED,
  49         .vl_bpix                = LCD_COLOR16,  /* Bits per pixel, BPP = 2^n */
  50         .vl_tft                 = 1,            /* 0 = passive, 1 = TFT */
  51         .vl_hsync_len           = 42,           /* Length of horizontal sync */
  52         .vl_left_margin         = 1,            /* Time from sync to picture */
  53         .vl_right_margin        = 1,            /* Time from picture to sync */
  54         .vl_vsync_len           = 1,            /* Length of vertical sync */
  55         .vl_upper_margin        = 12,           /* Time from sync to picture */
  56         .vl_lower_margin        = 1,            /* Time from picture to sync */
  57         .mmio                   = LCDC_BASE,    /* Memory mapped registers */
  58 };
  59
  60 void lcd_enable(void)
  61 {
  62 }
  63
  64 void lcd_disable(void)
  65 {
  66 }
  67 #endif
  68
  69 DECLARE_GLOBAL_DATA_PTR;
  70
  71 static const struct sdram_config sdram_config = {
  72         .data_bits      = SDRAM_DATA_16BIT,
  73         .row_bits       = 13,
  74         .col_bits       = 9,
  75         .bank_bits      = 2,
  76         .cas            = 3,
  77         .twr            = 2,
  78         .trc            = 6,
  79         .trp            = 2,
  80         .trcd           = 2,
  81         .tras           = 6,
  82         .txsr           = 6,
  83         /* 15.6 us */
  84         .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
  85 };
  86
  87 int board_early_init_f(void)
  88 {
  89         /* Enable SDRAM in the EBI mux */
  90         hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  91
  92         /* Enable 26 address bits and NCS2 */
  93         portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
  94         portmux_enable_usart1(PORTMUX_DRIVE_MIN);
  95
  96         /* de-assert "force sys reset" pin */
  97         portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
  98                         PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
  99
 100         /* init custom i/o */
 101         /* cpu type inputs */
 102         portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
 103                         PORTMUX_DIR_INPUT);
 104         /* main board type inputs */
 105         portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
 106                         PORTMUX_DIR_INPUT);
 107         /* DEBUG input (use weak pullup) */
 108         portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
 109                         PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
 110
 111         /* are we suppressing the console ? */
 112         if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
 113                 gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
 114
 115         /* reset phys */
 116         portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
 117         portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
 118                         PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
 119
 120         udelay(5000);
 121
 122         /* release phys reset */
 123         gpio_set_value(GPIO_PIN_PC(18), 0);     /* PHY RESET (Release)  */
 124
 125         /* setup Data Flash chip select (NCS2) */
 126         hsmc3_writel(MODE2, 0x20121003);
 127         hsmc3_writel(CYCLE2, 0x000a0009);
 128         hsmc3_writel(PULSE2, 0x0a060806);
 129         hsmc3_writel(SETUP2, 0x00030102);
 130
 131         /* setup FRAM chip select (NCS3) */
 132         hsmc3_writel(MODE3, 0x10120001);
 133         hsmc3_writel(CYCLE3, 0x001e001d);
 134         hsmc3_writel(PULSE3, 0x08040704);
 135         hsmc3_writel(SETUP3, 0x02050204);
 136
 137 #if defined(CONFIG_MACB)
 138         /* init macb0 pins */
 139         portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
 140         portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
 141 #endif
 142
 143 #if defined(CONFIG_MMC)
 144         portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
 145 #endif
 146
 147 #if defined(CONFIG_LCD)
 148         portmux_enable_lcdc(1);
 149 #endif
 150
 151         return 0;
 152 }
 153
 154 phys_size_t initdram(int board_type)
 155 {
 156         unsigned long expected_size;
 157         unsigned long actual_size;
 158         void *sdram_base;
 159
 160         sdram_base = uncached(EBI_SDRAM_BASE);
 161
 162         expected_size = sdram_init(sdram_base, &sdram_config);
 163         actual_size = get_ram_size(sdram_base, expected_size);
 164
 165         if (expected_size != actual_size)
 166                 printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
 167                                 actual_size >> 20, expected_size >> 20);
 168
 169         return actual_size;
 170 }
 171
 172 int board_early_init_r(void)
 173 {
 174         gd->bd->bi_phy_id[0] = 0x01;
 175         gd->bd->bi_phy_id[1] = 0x03;
 176         return 0;
 177 }
 178
 179 int board_postclk_init(void)
 180 {
 181         /* Use GCLK0 as 10MHz output */
 182         gclk_enable_output(0, PORTMUX_DRIVE_LOW);
 183         gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
 184         return 0;
 185 }
 186
 187 /* SPI chip select control */
 188 #ifdef CONFIG_ATMEL_SPI
 189 #include <spi.h>
 190
 191 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 192 {
 193         return (bus == 0) && (cs == 0);
 194 }
 195
 196 void spi_cs_activate(struct spi_slave *slave)
 197 {
 198 }
 199
 200 void spi_cs_deactivate(struct spi_slave *slave)
 201 {
 202 }
 203 #endif /* CONFIG_ATMEL_SPI */
 204
 205 #ifdef CONFIG_CMD_NET
 206 int board_eth_init(bd_t *bi)
 207 {
 208         macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
 209         macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
 210
 211         return 0;
 212 }
 213 #endif