board/ti/ti816x/evm.c

   1 /*
   2  * evm.c
   3  *
   4  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
   5  * Antoine Tenart, <atenart@adeneo-embedded.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <spl.h>
  12 #include <asm/cache.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/ddr_defs.h>
  17 #include <asm/arch/hardware.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/arch/mmc_host_def.h>
  20 #include <asm/arch/mem.h>
  21 #include <asm/arch/mux.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 int board_init(void)
  26 {
  27         gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
  28         return 0;
  29 }
  30
  31 #ifdef CONFIG_SPL_BUILD
  32
  33 static struct module_pin_mux mmc_pin_mux[] = {
  34         { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
  35         { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
  36         { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  37         { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  38         { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  39         { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  40         { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
  41         { -1 },
  42 };
  43
  44 const struct dmm_lisa_map_regs evm_lisa_map_regs = {
  45         .dmm_lisa_map_0 = 0x00000000,
  46         .dmm_lisa_map_1 = 0x00000000,
  47         .dmm_lisa_map_2 = 0x80640300,
  48         .dmm_lisa_map_3 = 0xC0640320,
  49 };
  50
  51 /*
  52  * DDR2 related definitions
  53  */
  54 #ifdef CONFIG_TI816X_EVM_DDR2
  55 static struct ddr_data ddr2_data = {
  56         .datardsratio0          = ((0x40<<10) | (0x40<<0)),
  57         .datawdsratio0          = ((0x4A<<10) | (0x4A<<0)),
  58         .datawiratio0           = ((0x0<<10) | (0x0<<0)),
  59         .datagiratio0           = ((0x0<<10) | (0x0<<0)),
  60         .datafwsratio0          = ((0x13A<<10) | (0x13A<<0)),
  61         .datawrsratio0          = ((0x8A<<10) | (0x8A<<0)),
  62 };
  63
  64 static struct cmd_control ddr2_ctrl = {
  65         .cmd0csratio    = 0x80,
  66         .cmd0iclkout    = 0x00,
  67
  68         .cmd1csratio    = 0x80,
  69         .cmd1iclkout    = 0x00,
  70
  71         .cmd2csratio    = 0x80,
  72         .cmd2iclkout    = 0x00,
  73
  74 };
  75
  76 static struct emif_regs ddr2_emif0_regs = {
  77         .sdram_config           = 0x43801A3A,
  78         .ref_ctrl               = 0x10000C30,
  79         .sdram_tim1             = 0x0AAB15E2,
  80         .sdram_tim2             = 0x423631D2,
  81         .sdram_tim3             = 0x0080032F,
  82         .emif_ddr_phy_ctlr_1    = 0x0, /* depend on cpu rev, set later */
  83 };
  84
  85 static struct emif_regs ddr2_emif1_regs = {
  86         .sdram_config           = 0x43801A3A,
  87         .ref_ctrl               = 0x10000C30,
  88         .sdram_tim1             = 0x0AAB15E2,
  89         .sdram_tim2             = 0x423631D2,
  90         .sdram_tim3             = 0x0080032F,
  91         .emif_ddr_phy_ctlr_1    = 0x0, /* depend on cpu rev, set later */
  92 };
  93 #endif
  94
  95 /*
  96  * DDR3 related definitions
  97  */
  98
  99 #if defined(CONFIG_TI816X_DDR_PLL_400)
 100 #define RD_DQS          0x03B
 101 #define WR_DQS          0x0A6
 102 #define RD_DQS_GATE     0x12A
 103 #define EMIF_SDCFG      0x62A41032
 104 #define EMIF_SDREF      0x10000C30
 105 #define EMIF_TIM1       0x0CCCE524
 106 #define EMIF_TIM2       0x30308023
 107 #define EMIF_TIM3       0x009F82CF
 108 #define EMIF_PHYCFG     0x0000010B
 109 #elif defined(CONFIG_TI816X_DDR_PLL_531)
 110 #define RD_DQS          0x039
 111 #define WR_DQS          0x0B4
 112 #define RD_DQS_GATE     0x13D
 113 #define EMIF_SDCFG      0x62A51832
 114 #define EMIF_SDREF      0x1000102E
 115 #define EMIF_TIM1       0x0EF136AC
 116 #define EMIF_TIM2       0x30408063
 117 #define EMIF_TIM3       0x009F83AF
 118 #define EMIF_PHYCFG     0x0000010C
 119 #elif defined(CONFIG_TI816X_DDR_PLL_675)
 120 #define RD_DQS          0x039
 121 #define WR_DQS          0x091
 122 #define RD_DQS_GATE     0x196
 123 #define EMIF_SDCFG      0x62A63032
 124 #define EMIF_SDREF      0x10001491
 125 #define EMIF_TIM1       0x13358875
 126 #define EMIF_TIM2       0x5051806C
 127 #define EMIF_TIM3       0x009F84AF
 128 #define EMIF_PHYCFG     0x0000010F
 129 #elif defined(CONFIG_TI816X_DDR_PLL_796)
 130 #define RD_DQS          0x035
 131 #define WR_DQS          0x093
 132 #define RD_DQS_GATE     0x1B3
 133 #define EMIF_SDCFG      0x62A73832
 134 #define EMIF_SDREF      0x10001841
 135 #define EMIF_TIM1       0x1779C9FE
 136 #define EMIF_TIM2       0x50608074
 137 #define EMIF_TIM3       0x009F857F
 138 #define EMIF_PHYCFG     0x00000110
 139 #endif
 140
 141 static struct ddr_data ddr3_data = {
 142         .datardsratio0          = ((RD_DQS<<10) | (RD_DQS<<0)),
 143         .datawdsratio0          = ((WR_DQS<<10) | (WR_DQS<<0)),
 144         .datawiratio0           = ((0x20<<10) | 0x20<<0),
 145         .datagiratio0           = ((0x20<<10) | 0x20<<0),
 146         .datafwsratio0          = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
 147         .datawrsratio0          = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
 148 };
 149
 150 static const struct cmd_control ddr3_ctrl = {
 151         .cmd0csratio    = 0x100,
 152         .cmd0iclkout    = 0x001,
 153
 154         .cmd1csratio    = 0x100,
 155         .cmd1iclkout    = 0x001,
 156
 157         .cmd2csratio    = 0x100,
 158         .cmd2iclkout    = 0x001,
 159 };
 160
 161 static const struct emif_regs ddr3_emif0_regs = {
 162         .sdram_config           = EMIF_SDCFG,
 163         .ref_ctrl               = EMIF_SDREF,
 164         .sdram_tim1             = EMIF_TIM1,
 165         .sdram_tim2             = EMIF_TIM2,
 166         .sdram_tim3             = EMIF_TIM3,
 167         .emif_ddr_phy_ctlr_1    = EMIF_PHYCFG,
 168 };
 169
 170 static const struct emif_regs ddr3_emif1_regs = {
 171         .sdram_config           = EMIF_SDCFG,
 172         .ref_ctrl               = EMIF_SDREF,
 173         .sdram_tim1             = EMIF_TIM1,
 174         .sdram_tim2             = EMIF_TIM2,
 175         .sdram_tim3             = EMIF_TIM3,
 176         .emif_ddr_phy_ctlr_1    = EMIF_PHYCFG,
 177 };
 178
 179 void set_uart_mux_conf(void) {}
 180
 181 void set_mux_conf_regs(void)
 182 {
 183         configure_module_pin_mux(mmc_pin_mux);
 184 }
 185
 186 void sdram_init(void)
 187 {
 188         config_dmm(&evm_lisa_map_regs);
 189
 190 #ifdef CONFIG_TI816X_EVM_DDR2
 191         if (CONFIG_TI816X_USE_EMIF0) {
 192                 ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
 193                         (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
 194                 config_ddr(0, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif0_regs,
 195                            0);
 196         }
 197
 198         if (CONFIG_TI816X_USE_EMIF1) {
 199                 ddr2_emif1_regs.emif_ddr_phy_ctlr_1 =
 200                         (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
 201                 config_ddr(1, NULL, &ddr2_data, &ddr2_ctrl, &ddr2_emif1_regs,
 202                            1);
 203         }
 204 #endif
 205
 206 #ifdef CONFIG_TI816X_EVM_DDR3
 207         if (CONFIG_TI816X_USE_EMIF0)
 208                 config_ddr(0, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs,
 209                            0);
 210
 211         if (CONFIG_TI816X_USE_EMIF1)
 212                 config_ddr(1, NULL, &ddr3_data, &ddr3_ctrl, &ddr3_emif1_regs,
 213                            1);
 214 #endif
 215 }
 216 #endif /* CONFIG_SPL_BUILD */