drivers/i2c/ppc4xx_i2c.c

   1 /*
   2  * (C) Copyright 2007-2009
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
   6  *
   7  * (C) Copyright 2001
   8  * Bill Hunter,  Wave 7 Optics, williamhunter@mediaone.net
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/ppc4xx.h>
  15 #include <asm/ppc4xx-i2c.h>
  16 #include <i2c.h>
  17 #include <asm/io.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static inline struct ppc4xx_i2c *ppc4xx_get_i2c(int hwadapnr)
  22 {
  23         unsigned long base;
  24
  25 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  26         defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  27         defined(CONFIG_460EX) || defined(CONFIG_460GT)
  28         base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + (hwadapnr * 0x100);
  29 #elif defined(CONFIG_440) || defined(CONFIG_405EX)
  30 /* all remaining 440 variants */
  31         base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + (hwadapnr * 0x100);
  32 #else
  33 /* all 405 variants */
  34         base = 0xEF600500 + (hwadapnr * 0x100);
  35 #endif
  36         return (struct ppc4xx_i2c *)base;
  37 }
  38
  39 static void _i2c_bus_reset(struct i2c_adapter *adap)
  40 {
  41         struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
  42         int i;
  43         u8 dc;
  44
  45         /* Reset status register */
  46         /* write 1 in SCMP and IRQA to clear these fields */
  47         out_8(&i2c->sts, 0x0A);
  48
  49         /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
  50         out_8(&i2c->extsts, 0x8F);
  51
  52         /* Place chip in the reset state */
  53         out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
  54
  55         /* Check if bus is free */
  56         dc = in_8(&i2c->directcntl);
  57         if (!DIRCTNL_FREE(dc)){
  58                 /* Try to set bus free state */
  59                 out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
  60
  61                 /* Wait until we regain bus control */
  62                 for (i = 0; i < 100; ++i) {
  63                         dc = in_8(&i2c->directcntl);
  64                         if (DIRCTNL_FREE(dc))
  65                                 break;
  66
  67                         /* Toggle SCL line */
  68                         dc ^= IIC_DIRCNTL_SCC;
  69                         out_8(&i2c->directcntl, dc);
  70                         udelay(10);
  71                         dc ^= IIC_DIRCNTL_SCC;
  72                         out_8(&i2c->directcntl, dc);
  73                 }
  74         }
  75
  76         /* Remove reset */
  77         out_8(&i2c->xtcntlss, 0);
  78 }
  79
  80 static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  81 {
  82         struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
  83         int val, divisor;
  84
  85 #ifdef CONFIG_SYS_I2C_INIT_BOARD
  86         /*
  87          * Call board specific i2c bus reset routine before accessing the
  88          * environment, which might be in a chip on that bus. For details
  89          * about this problem see doc/I2C_Edge_Conditions.
  90          */
  91         i2c_init_board();
  92 #endif
  93
  94         /* Handle possible failed I2C state */
  95         /* FIXME: put this into i2c_init_board()? */
  96         _i2c_bus_reset(adap);
  97
  98         /* clear lo master address */
  99         out_8(&i2c->lmadr, 0);
 100
 101         /* clear hi master address */
 102         out_8(&i2c->hmadr, 0);
 103
 104         /* clear lo slave address */
 105         out_8(&i2c->lsadr, 0);
 106
 107         /* clear hi slave address */
 108         out_8(&i2c->hsadr, 0);
 109
 110         /* Clock divide Register */
 111         /* set divisor according to freq_opb */
 112         divisor = (get_OPB_freq() - 1) / 10000000;
 113         if (divisor == 0)
 114                 divisor = 1;
 115         out_8(&i2c->clkdiv, divisor);
 116
 117         /* no interrupts */
 118         out_8(&i2c->intrmsk, 0);
 119
 120         /* clear transfer count */
 121         out_8(&i2c->xfrcnt, 0);
 122
 123         /* clear extended control & stat */
 124         /* write 1 in SRC SRS SWC SWS to clear these fields */
 125         out_8(&i2c->xtcntlss, 0xF0);
 126
 127         /* Mode Control Register
 128            Flush Slave/Master data buffer */
 129         out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
 130
 131         val = in_8(&i2c->mdcntl);
 132
 133         /* Ignore General Call, slave transfers are ignored,
 134          * disable interrupts, exit unknown bus state, enable hold
 135          * SCL 100kHz normaly or FastMode for 400kHz and above
 136          */
 137
 138         val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
 139         if (speed >= 400000)
 140                 val |= IIC_MDCNTL_FSM;
 141         out_8(&i2c->mdcntl, val);
 142
 143         /* clear control reg */
 144         out_8(&i2c->cntl, 0x00);
 145 }
 146
 147 /*
 148  * This code tries to use the features of the 405GP i2c
 149  * controller. It will transfer up to 4 bytes in one pass
 150  * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
 151  * is possible to do out16(lhz) transfers.
 152  *
 153  * cmd_type is 0 for write 1 for read.
 154  *
 155  * addr_len can take any value from 0-255, it is only limited
 156  * by the char, we could make it larger if needed. If it is
 157  * 0 we skip the address write cycle.
 158  *
 159  * Typical case is a Write of an addr followd by a Read. The
 160  * IBM FAQ does not cover this. On the last byte of the write
 161  * we don't set the creg CHT bit, and on the first bytes of the
 162  * read we set the RPST bit.
 163  *
 164  * It does not support address only transfers, there must be
 165  * a data part. If you want to write the address yourself, put
 166  * it in the data pointer.
 167  *
 168  * It does not support transfer to/from address 0.
 169  *
 170  * It does not check XFRCNT.
 171  */
 172 static int _i2c_transfer(struct i2c_adapter *adap,
 173                         unsigned char cmd_type,
 174                         unsigned char chip,
 175                         unsigned char addr[],
 176                         unsigned char addr_len,
 177                         unsigned char data[],
 178                         unsigned short data_len)
 179 {
 180         struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
 181         u8 *ptr;
 182         int reading;
 183         int tran, cnt;
 184         int result;
 185         int status;
 186         int i;
 187         u8 creg;
 188
 189         if (data == 0 || data_len == 0) {
 190                 /* Don't support data transfer of no length or to address 0 */
 191                 printf( "i2c_transfer: bad call\n" );
 192                 return IIC_NOK;
 193         }
 194         if (addr && addr_len) {
 195                 ptr = addr;
 196                 cnt = addr_len;
 197                 reading = 0;
 198         } else {
 199                 ptr = data;
 200                 cnt = data_len;
 201                 reading = cmd_type;
 202         }
 203
 204         /* Clear Stop Complete Bit */
 205         out_8(&i2c->sts, IIC_STS_SCMP);
 206
 207         /* Check init */
 208         i = 10;
 209         do {
 210                 /* Get status */
 211                 status = in_8(&i2c->sts);
 212                 i--;
 213         } while ((status & IIC_STS_PT) && (i > 0));
 214
 215         if (status & IIC_STS_PT) {
 216                 result = IIC_NOK_TOUT;
 217                 return(result);
 218         }
 219
 220         /* flush the Master/Slave Databuffers */
 221         out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
 222               IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
 223
 224         /* need to wait 4 OPB clocks? code below should take that long */
 225
 226         /* 7-bit adressing */
 227         out_8(&i2c->hmadr, 0);
 228         out_8(&i2c->lmadr, chip);
 229
 230         tran = 0;
 231         result = IIC_OK;
 232         creg = 0;
 233
 234         while (tran != cnt && (result == IIC_OK)) {
 235                 int  bc,j;
 236
 237                 /*
 238                  * Control register =
 239                  * Normal transfer, 7-bits adressing, Transfer up to
 240                  * bc bytes, Normal start, Transfer is a sequence of transfers
 241                  */
 242                 creg |= IIC_CNTL_PT;
 243
 244                 bc = (cnt - tran) > 4 ? 4 : cnt - tran;
 245                 creg |= (bc - 1) << 4;
 246                 /* if the real cmd type is write continue trans */
 247                 if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
 248                         creg |= IIC_CNTL_CHT;
 249
 250                 if (reading) {
 251                         creg |= IIC_CNTL_READ;
 252                 } else {
 253                         for(j = 0; j < bc; j++) {
 254                                 /* Set buffer */
 255                                 out_8(&i2c->mdbuf, ptr[tran + j]);
 256                         }
 257                 }
 258                 out_8(&i2c->cntl, creg);
 259
 260                 /*
 261                  * Transfer is in progress
 262                  * we have to wait for upto 5 bytes of data
 263                  * 1 byte chip address+r/w bit then bc bytes
 264                  * of data.
 265                  * udelay(10) is 1 bit time at 100khz
 266                  * Doubled for slop. 20 is too small.
 267                  */
 268                 i = 2 * 5 * 8;
 269                 do {
 270                         /* Get status */
 271                         status = in_8(&i2c->sts);
 272                         udelay(10);
 273                         i--;
 274                 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
 275                          (i > 0));
 276
 277                 if (status & IIC_STS_ERR) {
 278                         result = IIC_NOK;
 279                         status = in_8(&i2c->extsts);
 280                         /* Lost arbitration? */
 281                         if (status & IIC_EXTSTS_LA)
 282                                 result = IIC_NOK_LA;
 283                         /* Incomplete transfer? */
 284                         if (status & IIC_EXTSTS_ICT)
 285                                 result = IIC_NOK_ICT;
 286                         /* Transfer aborted? */
 287                         if (status & IIC_EXTSTS_XFRA)
 288                                 result = IIC_NOK_XFRA;
 289                 } else if ( status & IIC_STS_PT) {
 290                         result = IIC_NOK_TOUT;
 291                 }
 292
 293                 /* Command is reading => get buffer */
 294                 if ((reading) && (result == IIC_OK)) {
 295                         /* Are there data in buffer */
 296                         if (status & IIC_STS_MDBS) {
 297                                 /*
 298                                  * even if we have data we have to wait 4OPB
 299                                  * clocks for it to hit the front of the FIFO,
 300                                  * after that we can just read. We should check
 301                                  * XFCNT here and if the FIFO is full there is
 302                                  * no need to wait.
 303                                  */
 304                                 udelay(1);
 305                                 for (j = 0; j < bc; j++)
 306                                         ptr[tran + j] = in_8(&i2c->mdbuf);
 307                         } else
 308                                 result = IIC_NOK_DATA;
 309                 }
 310                 creg = 0;
 311                 tran += bc;
 312                 if (ptr == addr && tran == cnt) {
 313                         ptr = data;
 314                         cnt = data_len;
 315                         tran = 0;
 316                         reading = cmd_type;
 317                         if (reading)
 318                                 creg = IIC_CNTL_RPST;
 319                 }
 320         }
 321         return result;
 322 }
 323
 324 static int ppc4xx_i2c_probe(struct i2c_adapter *adap, uchar chip)
 325 {
 326         uchar buf[1];
 327
 328         buf[0] = 0;
 329
 330         /*
 331          * What is needed is to send the chip address and verify that the
 332          * address was <ACK>ed (i.e. there was a chip at that address which
 333          * drove the data line low).
 334          */
 335         return (_i2c_transfer(adap, 1, chip << 1, 0, 0, buf, 1) != 0);
 336 }
 337
 338 static int ppc4xx_i2c_transfer(struct i2c_adapter *adap, uchar chip, uint addr,
 339                                int alen, uchar *buffer, int len, int read)
 340 {
 341         uchar xaddr[4];
 342         int ret;
 343
 344         if (alen > 4) {
 345                 printf("I2C: addr len %d not supported\n", alen);
 346                 return 1;
 347         }
 348
 349         if (alen > 0) {
 350                 xaddr[0] = (addr >> 24) & 0xFF;
 351                 xaddr[1] = (addr >> 16) & 0xFF;
 352                 xaddr[2] = (addr >> 8) & 0xFF;
 353                 xaddr[3] = addr & 0xFF;
 354         }
 355
 356
 357 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 358         /*
 359          * EEPROM chips that implement "address overflow" are ones
 360          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 361          * address and the extra bits end up in the "chip address"
 362          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 363          * four 256 byte chips.
 364          *
 365          * Note that we consider the length of the address field to
 366          * still be one byte because the extra address bits are
 367          * hidden in the chip address.
 368          */
 369         if (alen > 0)
 370                 chip |= ((addr >> (alen * 8)) &
 371                          CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 372 #endif
 373         ret = _i2c_transfer(adap, read, chip << 1, &xaddr[4 - alen], alen,
 374                             buffer, len);
 375         if (ret) {
 376                 printf("I2C %s: failed %d\n", read ? "read" : "write", ret);
 377                 return 1;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static int ppc4xx_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 384                            int alen, uchar *buffer, int len)
 385 {
 386         return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 1);
 387 }
 388
 389 static int ppc4xx_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 390                             int alen, uchar *buffer, int len)
 391 {
 392         return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
 393 }
 394
 395 static unsigned int ppc4xx_i2c_set_bus_speed(struct i2c_adapter *adap,
 396                                              unsigned int speed)
 397 {
 398         if (speed != adap->speed)
 399                 return -1;
 400         return speed;
 401 }
 402
 403 /*
 404  * Register ppc4xx i2c adapters
 405  */
 406 #ifdef CONFIG_SYS_I2C_PPC4XX_CH0
 407 U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_0, ppc4xx_i2c_init, ppc4xx_i2c_probe,
 408                          ppc4xx_i2c_read, ppc4xx_i2c_write,
 409                          ppc4xx_i2c_set_bus_speed,
 410                          CONFIG_SYS_I2C_PPC4XX_SPEED_0,
 411                          CONFIG_SYS_I2C_PPC4XX_SLAVE_0, 0)
 412 #endif
 413 #ifdef CONFIG_SYS_I2C_PPC4XX_CH1
 414 U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_1, ppc4xx_i2c_init, ppc4xx_i2c_probe,
 415                          ppc4xx_i2c_read, ppc4xx_i2c_write,
 416                          ppc4xx_i2c_set_bus_speed,
 417                          CONFIG_SYS_I2C_PPC4XX_SPEED_1,
 418                          CONFIG_SYS_I2C_PPC4XX_SLAVE_1, 1)
 419 #endif