drivers/usb/musb/musb_core.h

   1 /******************************************************************
   2  * Copyright 2008 Mentor Graphics Corporation
   3  * Copyright (C) 2008 by Texas Instruments
   4  *
   5  * This file is part of the Inventra Controller Driver for Linux.
   6  *
   7  * The Inventra Controller Driver for Linux is free software; you
   8  * can redistribute it and/or modify it under the terms of the GNU
   9  * General Public License version 2 as published by the Free Software
  10  * Foundation.
  11  *
  12  * The Inventra Controller Driver for Linux is distributed in
  13  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  14  * without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16  * License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with The Inventra Controller Driver for Linux ; if not,
  20  * write to the Free Software Foundation, Inc., 59 Temple Place,
  21  * Suite 330, Boston, MA  02111-1307  USA
  22  *
  23  * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION
  24  * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE
  25  * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS
  26  * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER.
  27  * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES
  28  * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NON-INFRINGEMENT.  MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT
  30  * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR
  31  * GRAPHICS SUPPORT CUSTOMER.
  32  ******************************************************************/
  33
  34 #ifndef __MUSB_HDRC_DEFS_H__
  35 #define __MUSB_HDRC_DEFS_H__
  36
  37 #include <usb_defs.h>
  38 #include <asm/io.h>
  39
  40 #ifdef CONFIG_USB_BLACKFIN
  41 # include "blackfin_usb.h"
  42 #endif
  43
  44 #define MUSB_EP0_FIFOSIZE       64      /* This is non-configurable */
  45
  46 /* EP0 */
  47 struct musb_ep0_regs {
  48         u16     reserved4;
  49         u16     csr0;
  50         u16     reserved5;
  51         u16     reserved6;
  52         u16     count0;
  53         u8      host_type0;
  54         u8      host_naklimit0;
  55         u8      reserved7;
  56         u8      reserved8;
  57         u8      reserved9;
  58         u8      configdata;
  59 };
  60
  61 /* EP 1-15 */
  62 struct musb_epN_regs {
  63         u16     txmaxp;
  64         u16     txcsr;
  65         u16     rxmaxp;
  66         u16     rxcsr;
  67         u16     rxcount;
  68         u8      txtype;
  69         u8      txinterval;
  70         u8      rxtype;
  71         u8      rxinterval;
  72         u8      reserved0;
  73         u8      fifosize;
  74 };
  75
  76 /* Mentor USB core register overlay structure */
  77 #ifndef musb_regs
  78 struct musb_regs {
  79         /* common registers */
  80         u8      faddr;
  81         u8      power;
  82         u16     intrtx;
  83         u16     intrrx;
  84         u16     intrtxe;
  85         u16     intrrxe;
  86         u8      intrusb;
  87         u8      intrusbe;
  88         u16     frame;
  89         u8      index;
  90         u8      testmode;
  91         /* indexed registers */
  92         u16     txmaxp;
  93         u16     txcsr;
  94         u16     rxmaxp;
  95         u16     rxcsr;
  96         u16     rxcount;
  97         u8      txtype;
  98         u8      txinterval;
  99         u8      rxtype;
 100         u8      rxinterval;
 101         u8      reserved0;
 102         u8      fifosize;
 103         /* fifo */
 104         u32     fifox[16];
 105         /* OTG, dynamic FIFO, version & vendor registers */
 106         u8      devctl;
 107         u8      reserved1;
 108         u8      txfifosz;
 109         u8      rxfifosz;
 110         u16     txfifoadd;
 111         u16     rxfifoadd;
 112         u32     vcontrol;
 113         u16     hwvers;
 114         u16     reserved2a[1];
 115         u8      ulpi_busctl;
 116         u8      reserved2b[1];
 117         u16     reserved2[3];
 118         u8      epinfo;
 119         u8      raminfo;
 120         u8      linkinfo;
 121         u8      vplen;
 122         u8      hseof1;
 123         u8      fseof1;
 124         u8      lseof1;
 125         u8      reserved3;
 126         /* target address registers */
 127         struct musb_tar_regs {
 128                 u8      txfuncaddr;
 129                 u8      reserved0;
 130                 u8      txhubaddr;
 131                 u8      txhubport;
 132                 u8      rxfuncaddr;
 133                 u8      reserved1;
 134                 u8      rxhubaddr;
 135                 u8      rxhubport;
 136         } tar[16];
 137         /*
 138          * endpoint registers
 139          * ep0 elements are valid when array index is 0
 140          * otherwise epN is valid
 141          */
 142         union musb_ep_regs {
 143                 struct musb_ep0_regs ep0;
 144                 struct musb_epN_regs epN;
 145         } ep[16];
 146
 147 } __attribute__((packed));
 148 #endif
 149
 150 /*
 151  * MUSB Register bits
 152  */
 153
 154 /* POWER */
 155 #define MUSB_POWER_ISOUPDATE    0x80
 156 #define MUSB_POWER_SOFTCONN     0x40
 157 #define MUSB_POWER_HSENAB       0x20
 158 #define MUSB_POWER_HSMODE       0x10
 159 #define MUSB_POWER_RESET        0x08
 160 #define MUSB_POWER_RESUME       0x04
 161 #define MUSB_POWER_SUSPENDM     0x02
 162 #define MUSB_POWER_ENSUSPEND    0x01
 163 #define MUSB_POWER_HSMODE_SHIFT 4
 164
 165 /* INTRUSB */
 166 #define MUSB_INTR_SUSPEND       0x01
 167 #define MUSB_INTR_RESUME        0x02
 168 #define MUSB_INTR_RESET         0x04
 169 #define MUSB_INTR_BABBLE        0x04
 170 #define MUSB_INTR_SOF           0x08
 171 #define MUSB_INTR_CONNECT       0x10
 172 #define MUSB_INTR_DISCONNECT    0x20
 173 #define MUSB_INTR_SESSREQ       0x40
 174 #define MUSB_INTR_VBUSERROR     0x80    /* For SESSION end */
 175
 176 /* DEVCTL */
 177 #define MUSB_DEVCTL_BDEVICE     0x80
 178 #define MUSB_DEVCTL_FSDEV       0x40
 179 #define MUSB_DEVCTL_LSDEV       0x20
 180 #define MUSB_DEVCTL_VBUS        0x18
 181 #define MUSB_DEVCTL_VBUS_SHIFT  3
 182 #define MUSB_DEVCTL_HM          0x04
 183 #define MUSB_DEVCTL_HR          0x02
 184 #define MUSB_DEVCTL_SESSION     0x01
 185
 186 /* ULPI VBUSCONTROL */
 187 #define ULPI_USE_EXTVBUS        0x01
 188 #define ULPI_USE_EXTVBUSIND     0x02
 189
 190 /* TESTMODE */
 191 #define MUSB_TEST_FORCE_HOST    0x80
 192 #define MUSB_TEST_FIFO_ACCESS   0x40
 193 #define MUSB_TEST_FORCE_FS      0x20
 194 #define MUSB_TEST_FORCE_HS      0x10
 195 #define MUSB_TEST_PACKET        0x08
 196 #define MUSB_TEST_K             0x04
 197 #define MUSB_TEST_J             0x02
 198 #define MUSB_TEST_SE0_NAK       0x01
 199
 200 /* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */
 201 #define MUSB_FIFOSZ_DPB         0x10
 202 /* Allocation size (8, 16, 32, ... 4096) */
 203 #define MUSB_FIFOSZ_SIZE        0x0f
 204
 205 /* CSR0 */
 206 #define MUSB_CSR0_FLUSHFIFO     0x0100
 207 #define MUSB_CSR0_TXPKTRDY      0x0002
 208 #define MUSB_CSR0_RXPKTRDY      0x0001
 209
 210 /* CSR0 in Peripheral mode */
 211 #define MUSB_CSR0_P_SVDSETUPEND 0x0080
 212 #define MUSB_CSR0_P_SVDRXPKTRDY 0x0040
 213 #define MUSB_CSR0_P_SENDSTALL   0x0020
 214 #define MUSB_CSR0_P_SETUPEND    0x0010
 215 #define MUSB_CSR0_P_DATAEND     0x0008
 216 #define MUSB_CSR0_P_SENTSTALL   0x0004
 217
 218 /* CSR0 in Host mode */
 219 #define MUSB_CSR0_H_DIS_PING            0x0800
 220 #define MUSB_CSR0_H_WR_DATATOGGLE       0x0400  /* Set to allow setting: */
 221 #define MUSB_CSR0_H_DATATOGGLE          0x0200  /* Data toggle control */
 222 #define MUSB_CSR0_H_NAKTIMEOUT          0x0080
 223 #define MUSB_CSR0_H_STATUSPKT           0x0040
 224 #define MUSB_CSR0_H_REQPKT              0x0020
 225 #define MUSB_CSR0_H_ERROR               0x0010
 226 #define MUSB_CSR0_H_SETUPPKT            0x0008
 227 #define MUSB_CSR0_H_RXSTALL             0x0004
 228
 229 /* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */
 230 #define MUSB_CSR0_P_WZC_BITS    \
 231         (MUSB_CSR0_P_SENTSTALL)
 232 #define MUSB_CSR0_H_WZC_BITS    \
 233         (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \
 234         | MUSB_CSR0_RXPKTRDY)
 235
 236 /* TxType/RxType */
 237 #define MUSB_TYPE_SPEED         0xc0
 238 #define MUSB_TYPE_SPEED_SHIFT   6
 239 #define MUSB_TYPE_SPEED_HIGH    1
 240 #define MUSB_TYPE_SPEED_FULL    2
 241 #define MUSB_TYPE_SPEED_LOW     3
 242 #define MUSB_TYPE_PROTO         0x30    /* Implicitly zero for ep0 */
 243 #define MUSB_TYPE_PROTO_SHIFT   4
 244 #define MUSB_TYPE_REMOTE_END    0xf     /* Implicitly zero for ep0 */
 245 #define MUSB_TYPE_PROTO_BULK    2
 246 #define MUSB_TYPE_PROTO_INTR    3
 247
 248 /* CONFIGDATA */
 249 #define MUSB_CONFIGDATA_MPRXE           0x80    /* Auto bulk pkt combining */
 250 #define MUSB_CONFIGDATA_MPTXE           0x40    /* Auto bulk pkt splitting */
 251 #define MUSB_CONFIGDATA_BIGENDIAN       0x20
 252 #define MUSB_CONFIGDATA_HBRXE           0x10    /* HB-ISO for RX */
 253 #define MUSB_CONFIGDATA_HBTXE           0x08    /* HB-ISO for TX */
 254 #define MUSB_CONFIGDATA_DYNFIFO         0x04    /* Dynamic FIFO sizing */
 255 #define MUSB_CONFIGDATA_SOFTCONE        0x02    /* SoftConnect */
 256 #define MUSB_CONFIGDATA_UTMIDW          0x01    /* Data width 0/1 => 8/16bits */
 257
 258 /* TXCSR in Peripheral and Host mode */
 259 #define MUSB_TXCSR_AUTOSET              0x8000
 260 #define MUSB_TXCSR_MODE                 0x2000
 261 #define MUSB_TXCSR_DMAENAB              0x1000
 262 #define MUSB_TXCSR_FRCDATATOG           0x0800
 263 #define MUSB_TXCSR_DMAMODE              0x0400
 264 #define MUSB_TXCSR_CLRDATATOG           0x0040
 265 #define MUSB_TXCSR_FLUSHFIFO            0x0008
 266 #define MUSB_TXCSR_FIFONOTEMPTY         0x0002
 267 #define MUSB_TXCSR_TXPKTRDY             0x0001
 268
 269 /* TXCSR in Peripheral mode */
 270 #define MUSB_TXCSR_P_ISO                0x4000
 271 #define MUSB_TXCSR_P_INCOMPTX           0x0080
 272 #define MUSB_TXCSR_P_SENTSTALL          0x0020
 273 #define MUSB_TXCSR_P_SENDSTALL          0x0010
 274 #define MUSB_TXCSR_P_UNDERRUN           0x0004
 275
 276 /* TXCSR in Host mode */
 277 #define MUSB_TXCSR_H_WR_DATATOGGLE      0x0200
 278 #define MUSB_TXCSR_H_DATATOGGLE         0x0100
 279 #define MUSB_TXCSR_H_NAKTIMEOUT         0x0080
 280 #define MUSB_TXCSR_H_RXSTALL            0x0020
 281 #define MUSB_TXCSR_H_ERROR              0x0004
 282 #define MUSB_TXCSR_H_DATATOGGLE_SHIFT   8
 283
 284 /* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 285 #define MUSB_TXCSR_P_WZC_BITS   \
 286         (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \
 287         | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY)
 288 #define MUSB_TXCSR_H_WZC_BITS   \
 289         (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \
 290         | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY)
 291
 292 /* RXCSR in Peripheral and Host mode */
 293 #define MUSB_RXCSR_AUTOCLEAR            0x8000
 294 #define MUSB_RXCSR_DMAENAB              0x2000
 295 #define MUSB_RXCSR_DISNYET              0x1000
 296 #define MUSB_RXCSR_PID_ERR              0x1000
 297 #define MUSB_RXCSR_DMAMODE              0x0800
 298 #define MUSB_RXCSR_INCOMPRX             0x0100
 299 #define MUSB_RXCSR_CLRDATATOG           0x0080
 300 #define MUSB_RXCSR_FLUSHFIFO            0x0010
 301 #define MUSB_RXCSR_DATAERROR            0x0008
 302 #define MUSB_RXCSR_FIFOFULL             0x0002
 303 #define MUSB_RXCSR_RXPKTRDY             0x0001
 304
 305 /* RXCSR in Peripheral mode */
 306 #define MUSB_RXCSR_P_ISO                0x4000
 307 #define MUSB_RXCSR_P_SENTSTALL          0x0040
 308 #define MUSB_RXCSR_P_SENDSTALL          0x0020
 309 #define MUSB_RXCSR_P_OVERRUN            0x0004
 310
 311 /* RXCSR in Host mode */
 312 #define MUSB_RXCSR_H_AUTOREQ            0x4000
 313 #define MUSB_RXCSR_H_WR_DATATOGGLE      0x0400
 314 #define MUSB_RXCSR_H_DATATOGGLE         0x0200
 315 #define MUSB_RXCSR_H_RXSTALL            0x0040
 316 #define MUSB_RXCSR_H_REQPKT             0x0020
 317 #define MUSB_RXCSR_H_ERROR              0x0004
 318 #define MUSB_S_RXCSR_H_DATATOGGLE       9
 319
 320 /* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */
 321 #define MUSB_RXCSR_P_WZC_BITS   \
 322         (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \
 323         | MUSB_RXCSR_RXPKTRDY)
 324 #define MUSB_RXCSR_H_WZC_BITS   \
 325         (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \
 326         | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY)
 327
 328 /* HUBADDR */
 329 #define MUSB_HUBADDR_MULTI_TT           0x80
 330
 331 /* Endpoint configuration information. Note: The value of endpoint fifo size
 332  * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other
 333  * values are not supported
 334  */
 335 struct musb_epinfo {
 336         u8      epnum;  /* endpoint number      */
 337         u8      epdir;  /* endpoint direction   */
 338         u16     epsize; /* endpoint FIFO size   */
 339 };
 340
 341 /*
 342  * Platform specific MUSB configuration. Any platform using the musb
 343  * functionality should create one instance of this structure in the
 344  * platform specific file.
 345  */
 346 struct musb_config {
 347         struct  musb_regs       *regs;
 348         u32                     timeout;
 349         u8                      musb_speed;
 350         u8                      extvbus;
 351 };
 352
 353 /* externally defined data */
 354 extern struct musb_config       musb_cfg;
 355 extern struct musb_regs         *musbr;
 356
 357 /* exported functions */
 358 extern void musb_start(void);
 359 extern void musb_configure_ep(const struct musb_epinfo *epinfo, u8 cnt);
 360 extern void write_fifo(u8 ep, u32 length, void *fifo_data);
 361 extern void read_fifo(u8 ep, u32 length, void *fifo_data);
 362
 363 #if defined(CONFIG_USB_BLACKFIN)
 364 /* Every USB register is accessed as a 16-bit even if the value itself
 365  * is only 8-bits in size.  Fun stuff.
 366  */
 367 # undef  readb
 368 # define readb(addr)     (u8)bfin_read16(addr)
 369 # undef  writeb
 370 # define writeb(b, addr) bfin_write16(addr, b)
 371 # undef MUSB_TXCSR_MODE /* not supported */
 372 # define MUSB_TXCSR_MODE 0
 373 /*
 374  * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY.
 375  * However, it has no ULPI support - so there are no registers at all.
 376  * That means accesses to ULPI_BUSCONTROL have to be abstracted away.
 377  */
 378 static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
 379 {
 380         return 0;
 381 }
 382 static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
 383 {}
 384 #else
 385 static inline u8 musb_read_ulpi_buscontrol(struct musb_regs *musbr)
 386 {
 387         return readb(&musbr->ulpi_busctl);
 388 }
 389 static inline void musb_write_ulpi_buscontrol(struct musb_regs *musbr, u8 val)
 390 {
 391         writeb(val, &musbr->ulpi_busctl);
 392 }
 393 #endif
 394
 395 #endif  /* __MUSB_HDRC_DEFS_H__ */