board/RRvision/RRvision.c

   1 /*
   2  * (C) Copyright 2001-2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <mpc8xx.h>
  10
  11 /* ------------------------------------------------------------------------- */
  12
  13 static long int dram_size (long int, long int *, long int);
  14
  15 /* ------------------------------------------------------------------------- */
  16
  17 #define _NOT_USED_      0xFFFFFFFF
  18
  19 const uint sdram_table[] =
  20 {
  21         /*
  22          * Single Read. (Offset 0 in UPMA RAM)
  23          */
  24         0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
  25         0x1FF77C47, /* last */
  26         /*
  27          * SDRAM Initialization (offset 5 in UPMA RAM)
  28          *
  29          * This is no UPM entry point. The following definition uses
  30          * the remaining space to establish an initialization
  31          * sequence, which is executed by a RUN command.
  32          *
  33          */
  34                     0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
  35         /*
  36          * Burst Read. (Offset 8 in UPMA RAM)
  37          */
  38         0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
  39         0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
  40         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  41         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  42         /*
  43          * Single Write. (Offset 18 in UPMA RAM)
  44          */
  45         0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
  46         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  47         /*
  48          * Burst Write. (Offset 20 in UPMA RAM)
  49          */
  50         0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
  51         0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
  52                                             _NOT_USED_,
  53         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  54         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  55         /*
  56          * Refresh  (Offset 30 in UPMA RAM)
  57          */
  58         0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
  59         0xFFFFFC84, 0xFFFFFC07, /* last */
  60                                 _NOT_USED_, _NOT_USED_,
  61         _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
  62         /*
  63          * Exception. (Offset 3c in UPMA RAM)
  64          */
  65         0x7FFFFC07, /* last */
  66                     _NOT_USED_, _NOT_USED_, _NOT_USED_,
  67 };
  68
  69 /* ------------------------------------------------------------------------- */
  70
  71
  72 /*
  73  * Check Board Identity:
  74  *
  75  * Always return 1 (no second DRAM bank).
  76  */
  77
  78 int checkboard (void)
  79 {
  80         char buf[64];
  81         int i;
  82         int l = getenv_f("serial#", buf, sizeof(buf));
  83
  84         puts ("Board: RRvision ");
  85
  86         for (i=0; i < l; ++i) {
  87                 if (buf[i] == ' ')
  88                         break;
  89                 putc (buf[i]);
  90         }
  91
  92         putc ('\n');
  93
  94         return (0);
  95 }
  96
  97 /* ------------------------------------------------------------------------- */
  98
  99 phys_size_t initdram (int board_type)
 100 {
 101         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 102         volatile memctl8xx_t *memctl = &immap->im_memctl;
 103         unsigned long reg;
 104         long int size8, size9;
 105         long int size = 0;
 106
 107         upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table) / sizeof(uint));
 108
 109         /*
 110          * Preliminary prescaler for refresh (depends on number of
 111          * banks): This value is selected for four cycles every 62.4 us
 112          * with two SDRAM banks or four cycles every 31.2 us with one
 113          * bank. It will be adjusted after memory sizing.
 114          */
 115         memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 116
 117         memctl->memc_mar = 0x00000088;
 118
 119         /*
 120          * Map controller bank 1 the SDRAM bank 2 at physical address 0.
 121          */
 122         memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM;
 123         memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM;
 124
 125         memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 126
 127         udelay (200);
 128
 129         /* perform SDRAM initializsation sequence */
 130
 131         memctl->memc_mcr = 0x80002105;  /* SDRAM bank 0 */
 132         udelay (1);
 133         memctl->memc_mcr = 0x80002230;  /* SDRAM bank 0 - execute twice */
 134         udelay (1);
 135
 136         memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
 137
 138         udelay (1000);
 139
 140         /*
 141          * Check Bank 0 Memory Size
 142          *
 143          * try 8 column mode
 144          */
 145         size8 = dram_size (CONFIG_SYS_MAMR_8COL,
 146                            SDRAM_BASE2_PRELIM,
 147                            SDRAM_MAX_SIZE);
 148
 149         udelay (1000);
 150
 151         /*
 152          * try 9 column mode
 153          */
 154         size9 = dram_size (CONFIG_SYS_MAMR_9COL,
 155                            SDRAM_BASE2_PRELIM,
 156                            SDRAM_MAX_SIZE);
 157
 158         if (size8 < size9) {            /* leave configuration at 9 columns */
 159                 size = size9;
 160 /*              debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);  */
 161         } else {                        /* back to 8 columns            */
 162                 size = size8;
 163                 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 164                 udelay (500);
 165 /*              debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);  */
 166         }
 167
 168         udelay (1000);
 169
 170         /*
 171          * Adjust refresh rate depending on SDRAM type
 172          * For types > 128 MBit leave it at the current (fast) rate
 173          */
 174         if (size < 0x02000000) {
 175                 /* reduce to 15.6 us (62.4 us / quad) */
 176                 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 177                 udelay (1000);
 178         }
 179
 180         /*
 181          * Final mapping
 182          */
 183         memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 184         memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 185
 186         /*
 187          * No bank 1
 188          *
 189          * invalidate bank
 190          */
 191         memctl->memc_br3 = 0;
 192
 193         /* adjust refresh rate depending on SDRAM type, one bank */
 194         reg = memctl->memc_mptpr;
 195         reg >>= 1;                      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 196         memctl->memc_mptpr = reg;
 197
 198         udelay (10000);
 199
 200         return (size);
 201 }
 202
 203 /* ------------------------------------------------------------------------- */
 204
 205 /*
 206  * Check memory range for valid RAM. A simple memory test determines
 207  * the actually available RAM size between addresses `base' and
 208  * `base + maxsize'. Some (not all) hardware errors are detected:
 209  * - short between address lines
 210  * - short between data lines
 211  */
 212
 213 static long int dram_size (long int mamr_value, long int *base,
 214                                                    long int maxsize)
 215 {
 216         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 217         volatile memctl8xx_t *memctl = &immap->im_memctl;
 218
 219         memctl->memc_mamr = mamr_value;
 220
 221         return (get_ram_size(base, maxsize));
 222 }