board/evb64260/evb64260.c

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * evb64260.c - main board support/init for the Galileo Eval board.
  10  */
  11
  12 #include <common.h>
  13 #include <74xx_7xx.h>
  14 #include <galileo/memory.h>
  15 #include <galileo/pci.h>
  16 #include <galileo/gt64260R.h>
  17 #include <net.h>
  18 #include <netdev.h>
  19 #include <linux/compiler.h>
  20
  21 #include <asm/io.h>
  22 #include "eth.h"
  23 #include "mpsc.h"
  24 #include "i2c.h"
  25 #include "64260.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_ZUMA_V2
  30 extern void zuma_mbox_init(void);
  31 #endif
  32
  33 #undef  DEBUG
  34 #define MAP_PCI
  35
  36 #ifdef DEBUG
  37 #define DP(x) x
  38 #else
  39 #define DP(x)
  40 #endif
  41
  42 /* ------------------------------------------------------------------------- */
  43
  44 /* this is the current GT register space location */
  45 /* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
  46
  47 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  48  * to the "final" value. This means that any debug_led calls before
  49  * board_early_init_f wont work right (like in cpu_init_f).
  50  * See also my_remap_gt_regs below. (NTL)
  51  */
  52
  53 unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
  54
  55 /* ------------------------------------------------------------------------- */
  56
  57 /*
  58  * This is a version of the GT register space remapping function that
  59  * doesn't touch globals (meaning, it's ok to run from flash.)
  60  *
  61  * Unfortunately, this has the side effect that a writable
  62  * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
  63  */
  64
  65 void
  66 my_remap_gt_regs(u32 cur_loc, u32 new_loc)
  67 {
  68         u32 temp;
  69
  70         /* check and see if it's already moved */
  71         temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
  72         if ((temp & 0xffff) == new_loc >> 20)
  73                 return;
  74
  75         temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
  76                 0xffff0000) | (new_loc >> 20);
  77
  78         out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
  79
  80         while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
  81 }
  82
  83 static void
  84 gt_pci_config(void)
  85 {
  86         /* move PCI stuff out of the way - NTL */
  87         /* map PCI Host 0 */
  88         pciMapSpace(PCI_HOST0, PCI_REGION0, CONFIG_SYS_PCI0_0_MEM_SPACE,
  89                 CONFIG_SYS_PCI0_0_MEM_SPACE, CONFIG_SYS_PCI0_MEM_SIZE);
  90
  91         pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0);
  92         pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0);
  93         pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0);
  94
  95         pciMapSpace(PCI_HOST0, PCI_IO, CONFIG_SYS_PCI0_IO_SPACE_PCI,
  96                 CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE);
  97
  98         /* map PCI Host 1 */
  99         pciMapSpace(PCI_HOST1, PCI_REGION0, CONFIG_SYS_PCI1_0_MEM_SPACE,
 100                 CONFIG_SYS_PCI1_0_MEM_SPACE, CONFIG_SYS_PCI1_MEM_SIZE);
 101
 102         pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0);
 103         pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0);
 104         pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0);
 105
 106         pciMapSpace(PCI_HOST1, PCI_IO, CONFIG_SYS_PCI1_IO_SPACE_PCI,
 107                 CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE);
 108
 109         /* PCI interface settings */
 110         GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
 111         GT_REG_WRITE(PCI_1TIMEOUT_RETRY, 0xffff);
 112         GT_REG_WRITE(PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
 113         GT_REG_WRITE(PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffff80e);
 114
 115
 116 }
 117
 118 /* Setup CPU interface paramaters */
 119 static void
 120 gt_cpu_config(void)
 121 {
 122         cpu_t cpu = get_cpu_type();
 123         ulong tmp;
 124
 125         /* cpu configuration register */
 126         tmp = GTREGREAD(CPU_CONFIGURATION);
 127
 128         /* set the AACK delay bit
 129          * see Res#14 */
 130         tmp |= CPU_CONF_AACK_DELAY;
 131         tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */
 132
 133         /* Galileo claims this is necessary for all busses >= 100 MHz */
 134         tmp |= CPU_CONF_FAST_CLK;
 135
 136         if (cpu == CPU_750CX) {
 137                 tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */
 138                 tmp &= ~CPU_CONF_AP_VALID;
 139         } else {
 140                 tmp |= CPU_CONF_DP_VALID;
 141                 tmp |= CPU_CONF_AP_VALID;
 142         }
 143
 144         /* this only works with the MPX bus */
 145         tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */
 146         tmp |= CPU_CONF_PIPELINE;
 147         tmp |= CPU_CONF_TA_DELAY;
 148
 149         GT_REG_WRITE(CPU_CONFIGURATION, tmp);
 150
 151         /* CPU master control register */
 152         tmp = GTREGREAD(CPU_MASTER_CONTROL);
 153
 154         tmp |= CPU_MAST_CTL_ARB_EN;
 155
 156         if ((cpu == CPU_7400) ||
 157             (cpu == CPU_7410) ||
 158             (cpu == CPU_7450)) {
 159
 160                 tmp |= CPU_MAST_CTL_CLEAN_BLK;
 161                 tmp |= CPU_MAST_CTL_FLUSH_BLK;
 162
 163         } else {
 164                 /* cleanblock must be cleared for CPUs
 165                  * that do not support this command
 166                  * see Res#1 */
 167                 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
 168                 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
 169         }
 170         GT_REG_WRITE(CPU_MASTER_CONTROL, tmp);
 171 }
 172
 173 /*
 174  * board_early_init_f.
 175  *
 176  * set up gal. device mappings, etc.
 177  */
 178 int board_early_init_f (void)
 179 {
 180         uchar sram_boot = 0;
 181
 182         /*
 183          * set up the GT the way the kernel wants it
 184          * the call to move the GT register space will obviously
 185          * fail if it has already been done, but we're going to assume
 186          * that if it's not at the power-on location, it's where we put
 187          * it last time. (huber)
 188          */
 189         my_remap_gt_regs(CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 190
 191         gt_pci_config();
 192
 193         /* mask all external interrupt sources */
 194         GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
 195         GT_REG_WRITE(CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
 196         GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
 197         GT_REG_WRITE(PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
 198         GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
 199         GT_REG_WRITE(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
 200         GT_REG_WRITE(CPU_INT_0_MASK, 0);
 201         GT_REG_WRITE(CPU_INT_1_MASK, 0);
 202         GT_REG_WRITE(CPU_INT_2_MASK, 0);
 203         GT_REG_WRITE(CPU_INT_3_MASK, 0);
 204
 205         /* now, onto the configuration */
 206         GT_REG_WRITE(SDRAM_CONFIGURATION, CONFIG_SYS_SDRAM_CONFIG);
 207
 208         /* ----- DEVICE BUS SETTINGS ------ */
 209
 210         /*
 211          * EVB
 212          * 0 - SRAM
 213          * 1 - RTC
 214          * 2 - UART
 215          * 3 - Flash
 216          * boot - BootCS
 217          *
 218          * Zuma
 219          * 0 - Flash
 220          * boot - BootCS
 221          */
 222
 223         /*
 224          * the dual 7450 module requires burst access to the boot
 225          * device, so the serial rom copies the boot device to the
 226          * on-board sram on the eval board, and updates the correct
 227          * registers to boot from the sram. (device0)
 228          */
 229 #if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
 230         /* Zuma has no SRAM */
 231         sram_boot = 0;
 232 #else
 233         if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CONFIG_SYS_MONITOR_BASE)
 234                 sram_boot = 1;
 235 #endif
 236
 237                 memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
 238
 239         memoryMapDeviceSpace(DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
 240         memoryMapDeviceSpace(DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
 241         memoryMapDeviceSpace(DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
 242
 243         /* configure device timing */
 244 #ifdef CONFIG_SYS_DEV0_PAR
 245         if (!sram_boot)
 246                 GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
 247 #endif
 248
 249 #ifdef CONFIG_SYS_DEV1_PAR
 250         GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
 251 #endif
 252 #ifdef CONFIG_SYS_DEV2_PAR
 253         GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
 254 #endif
 255
 256 #ifdef CONFIG_EVB64260
 257 #ifdef CONFIG_SYS_32BIT_BOOT_PAR
 258         /* detect if we are booting from the 32 bit flash */
 259         if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 260                 /* 32 bit boot flash */
 261                 GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 262                 GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
 263         } else {
 264                 /* 8 bit boot flash */
 265                 GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
 266                 GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 267         }
 268 #else
 269         /* 8 bit boot flash only */
 270         GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 271 #endif
 272 #else /* CONFIG_EVB64260 not defined */
 273                 /* We are booting from 16-bit flash.
 274                  */
 275         GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_16BIT_BOOT_PAR);
 276 #endif
 277
 278         gt_cpu_config();
 279
 280         /* MPP setup */
 281         GT_REG_WRITE(MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
 282         GT_REG_WRITE(MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
 283         GT_REG_WRITE(MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
 284         GT_REG_WRITE(MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 285
 286         GT_REG_WRITE(GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
 287         GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CONFIG_SYS_SERIAL_PORT_MUX);
 288
 289         return 0;
 290 }
 291
 292 /* various things to do after relocation */
 293
 294 int misc_init_r (void)
 295 {
 296         icache_enable();
 297 #ifdef CONFIG_SYS_L2
 298         l2cache_enable();
 299 #endif
 300
 301 #ifdef CONFIG_MPSC
 302         mpsc_init2();
 303 #endif
 304
 305 #ifdef CONFIG_ZUMA_V2
 306         zuma_mbox_init();
 307 #endif
 308         return (0);
 309 }
 310
 311 void
 312 after_reloc(ulong dest_addr)
 313 {
 314         /* check to see if we booted from the sram.  If so, move things
 315          * back to the way they should be. (we're running from main
 316          * memory at this point now */
 317
 318         if (memoryGetDeviceBaseAddress(DEVICE0) == CONFIG_SYS_MONITOR_BASE) {
 319                 memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
 320                 memoryMapDeviceSpace(BOOT_DEVICE, CONFIG_SYS_FLASH_BASE, _1M);
 321         }
 322
 323         /* now, jump to the main U-Boot board init code */
 324         board_init_r ((gd_t *)gd, dest_addr);
 325
 326         /* NOTREACHED */
 327 }
 328
 329 /* ------------------------------------------------------------------------- */
 330
 331 /*
 332  * Check Board Identity:
 333  */
 334
 335 int
 336 checkboard (void)
 337 {
 338         puts ("Board: " CONFIG_SYS_BOARD_NAME "\n");
 339         return (0);
 340 }
 341
 342 /* utility functions */
 343 void
 344 debug_led(int led, int mode)
 345 {
 346 #if !defined(CONFIG_ZUMA_V2) && !defined(CONFIG_P3G4)
 347         volatile int *addr = NULL;
 348         __maybe_unused int dummy;
 349
 350         if (mode == 1) {
 351                 switch (led) {
 352                 case 0:
 353                         addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x08000);
 354                         break;
 355
 356                 case 1:
 357                         addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x0c000);
 358                         break;
 359
 360                 case 2:
 361                         addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x10000);
 362                         break;
 363                 }
 364         } else if (mode == 0) {
 365                 switch (led) {
 366                 case 0:
 367                         addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x14000);
 368                         break;
 369
 370                 case 1:
 371                         addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x18000);
 372                         break;
 373
 374                 case 2:
 375                         addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x1c000);
 376                         break;
 377                 }
 378         }
 379         WRITE_CHAR(addr, 0);
 380         dummy = *addr;
 381 #endif /* CONFIG_ZUMA_V2 */
 382 }
 383
 384 void
 385 display_mem_map(void)
 386 {
 387     int i,j;
 388     unsigned int base,size,width;
 389     /* SDRAM */
 390     printf("SDRAM\n");
 391     for(i=0;i<=BANK3;i++) {
 392         base = memoryGetBankBaseAddress(i);
 393         size = memoryGetBankSize(i);
 394         if(size !=0)
 395         {
 396             printf("BANK%d: base - 0x%08x\tsize - %dM bytes\n",i,base,size>>20);
 397         }
 398     }
 399
 400     /* CPU's PCI windows */
 401     for(i=0;i<=PCI_HOST1;i++) {
 402         printf("\nCPU's PCI %d windows\n", i);
 403         base=pciGetSpaceBase(i,PCI_IO);
 404         size=pciGetSpaceSize(i,PCI_IO);
 405         printf("      IO: base - 0x%08x\tsize - %dM bytes\n",base,size>>20);
 406         for(j=0;j<=PCI_REGION3;j++) {
 407             base = pciGetSpaceBase(i,j);
 408             size = pciGetSpaceSize(i,j);
 409             printf("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n",j,base,
 410                     size>>20);
 411         }
 412     }
 413
 414     /* Devices */
 415     printf("\nDEVICES\n");
 416         for(i=0;i<=DEVICE3;i++) {
 417         base = memoryGetDeviceBaseAddress(i);
 418         size = memoryGetDeviceSize(i);
 419         width= memoryGetDeviceWidth(i) * 8;
 420         printf("DEV %d:  base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
 421                i, base, size>>20, width);
 422     }
 423
 424     /* Bootrom */
 425     base = memoryGetDeviceBaseAddress(BOOT_DEVICE); /* Boot */
 426     size = memoryGetDeviceSize(BOOT_DEVICE);
 427     width= memoryGetDeviceWidth(BOOT_DEVICE) * 8;
 428     printf(" BOOT:  base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
 429            base, size>>20, width);
 430 }
 431
 432 int board_eth_init(bd_t *bis)
 433 {
 434         gt6426x_eth_initialize(bis);
 435         return 0;
 436 }