board/nvidia/venice2/as3722_init.c

   1 /*
   2  * (C) Copyright 2013
   3  * NVIDIA Corporation <www.nvidia.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch-tegra/tegra_i2c.h>
  11 #include "as3722_init.h"
  12
  13 /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
  14
  15 void tegra_i2c_ll_write_addr(uint addr, uint config)
  16 {
  17         struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  18
  19         writel(addr, &reg->cmd_addr0);
  20         writel(config, &reg->cnfg);
  21 }
  22
  23 void tegra_i2c_ll_write_data(uint data, uint config)
  24 {
  25         struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  26
  27         writel(data, &reg->cmd_data1);
  28         writel(config, &reg->cnfg);
  29 }
  30
  31 void pmic_enable_cpu_vdd(void)
  32 {
  33         debug("%s entry\n", __func__);
  34
  35         /* Don't need to set up VDD_CORE - already done - by OTP */
  36
  37         debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
  38         /*
  39          * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
  40          * First set VDD to 1.0V, then enable the VDD regulator.
  41          */
  42         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  43         tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
  44         /*
  45          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  46          * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
  47          */
  48         udelay(10 * 1000);
  49
  50         debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
  51         /*
  52          * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
  53          * First set VDD to 1.0V, then enable the VDD regulator.
  54          */
  55         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  56         tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  57         /*
  58          * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  59          * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
  60          */
  61         udelay(10 * 1000);
  62
  63         debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
  64         /*
  65          * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
  66          * First set VDD to 1.2V, then enable the VDD regulator.
  67          */
  68         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  69         tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
  70         /*
  71          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  72          * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
  73          */
  74         udelay(10 * 1000);
  75
  76         debug("%s: Set VDD_SDMMC to 3.3V via AS3722 reg 0x16/4E\n", __func__);
  77         /*
  78          * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
  79          * First set it to bypass 3.3V straight thru, then enable the regulator
  80          *
  81          * NOTE: We do this early because doing it later seems to hose the CPU
  82          * power rail/partition startup. Need to debug.
  83          */
  84         tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  85         tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  86         /*
  87          * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  88          * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
  89          */
  90         udelay(10 * 1000);
  91 }