board/ti/sdp3430/sdp.c

   1 /*
   2  * (C) Copyright 2004-2009
   3  * Texas Instruments Incorporated, <www.ti.com>
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8 #include <common.h>
   9 #include <netdev.h>
  10 #include <twl4030.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/mmc_host_def.h>
  13 #include <asm/arch/mux.h>
  14 #include <asm/arch/mem.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/mach-types.h>
  17 #include "sdp.h"
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 const omap3_sysinfo sysinfo = {
  22         DDR_DISCRETE,
  23         "OMAP3 SDP3430 board",
  24 #if defined(CONFIG_ENV_IS_IN_ONENAND)
  25         "OneNAND",
  26 #elif defined(CONFIG_ENV_IS_IN_NAND)
  27         "NAND",
  28 #else
  29         "NOR",
  30 #endif
  31 };
  32
  33 /* Timing definitions for GPMC controller for Sibley NOR */
  34 static const u32 gpmc_sdp_nor[] = {
  35     SDP3430_NOR_GPMC_CONF1,
  36     SDP3430_NOR_GPMC_CONF2,
  37     SDP3430_NOR_GPMC_CONF3,
  38     SDP3430_NOR_GPMC_CONF4,
  39     SDP3430_NOR_GPMC_CONF5,
  40     SDP3430_NOR_GPMC_CONF6,
  41     /*CONF7- computed as params */
  42 };
  43
  44 /*
  45  * Timing definitions for GPMC controller for Debug Board
  46  * Debug board contains access to ethernet and DIP Switch setting
  47  * information etc.
  48  */
  49 static const u32 gpmc_sdp_debug[] = {
  50     SDP3430_DEBUG_GPMC_CONF1,
  51     SDP3430_DEBUG_GPMC_CONF2,
  52     SDP3430_DEBUG_GPMC_CONF3,
  53     SDP3430_DEBUG_GPMC_CONF4,
  54     SDP3430_DEBUG_GPMC_CONF5,
  55     SDP3430_DEBUG_GPMC_CONF6,
  56     /*CONF7- computed as params */
  57 };
  58
  59 /* Timing defintions for GPMC OneNAND */
  60 static const u32 gpmc_sdp_onenand[] = {
  61     SDP3430_ONENAND_GPMC_CONF1,
  62     SDP3430_ONENAND_GPMC_CONF2,
  63     SDP3430_ONENAND_GPMC_CONF3,
  64     SDP3430_ONENAND_GPMC_CONF4,
  65     SDP3430_ONENAND_GPMC_CONF5,
  66     SDP3430_ONENAND_GPMC_CONF6,
  67     /*CONF7- computed as params */
  68 };
  69
  70 /* GPMC definitions for GPMC NAND */
  71 static const u32 gpmc_sdp_nand[] = {
  72     SDP3430_NAND_GPMC_CONF1,
  73     SDP3430_NAND_GPMC_CONF2,
  74     SDP3430_NAND_GPMC_CONF3,
  75     SDP3430_NAND_GPMC_CONF4,
  76     SDP3430_NAND_GPMC_CONF5,
  77     SDP3430_NAND_GPMC_CONF6,
  78     /*CONF7- computed as params */
  79 };
  80
  81 /* gpmc_cfg is initialized by gpmc_init and we use it here */
  82 extern struct gpmc *gpmc_cfg;
  83
  84 /**
  85  * @brief board_init - gpmc and basic setup as phase1 of boot sequence
  86  *
  87  * @return 0
  88  */
  89 int board_init(void)
  90 {
  91         gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  92         /* TODO: Dynamically pop out CS mapping and program accordingly */
  93         /* Configure devices for default ON ON ON settings */
  94         enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0],
  95                         CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M);
  96         enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000,
  97                         GPMC_SIZE_16M);
  98         enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000,
  99                         GPMC_SIZE_16M);
 100         enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE,
 101                         GPMC_SIZE_16M);
 102         /* board id for Linux */
 103         gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP;
 104         /* boot param addr */
 105         gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 106
 107         return 0;
 108 }
 109
 110 #define LAN_RESET_REGISTER      (CONFIG_LAN91C96_BASE + 0x01c)
 111 #define ETH_CONTROL_REG         (CONFIG_LAN91C96_BASE + 0x30b)
 112
 113 /**
 114  * @brief board_eth_init Take the Ethernet controller out of reset and wait
 115  * for the EEPROM load to complete.
 116  */
 117 int board_eth_init(bd_t *bis)
 118 {
 119         int rc = 0;
 120 #ifdef CONFIG_LAN91C96
 121         int cnt = 20;
 122
 123         writew(0x0, LAN_RESET_REGISTER);
 124         do {
 125                 writew(0x1, LAN_RESET_REGISTER);
 126                 udelay(100);
 127                 if (cnt == 0)
 128                         goto reset_err_out;
 129                 --cnt;
 130         } while (readw(LAN_RESET_REGISTER) != 0x1);
 131
 132         cnt = 20;
 133
 134         do {
 135                 writew(0x0, LAN_RESET_REGISTER);
 136                 udelay(100);
 137                 if (cnt == 0)
 138                         goto reset_err_out;
 139                 --cnt;
 140         } while (readw(LAN_RESET_REGISTER) != 0x0000);
 141         udelay(1000);
 142
 143         writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG);
 144         udelay(1000);
 145         rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
 146 reset_err_out:
 147
 148 #endif
 149         return rc;
 150 }
 151
 152 /**
 153  * @brief misc_init_r - Configure SDP board specific configurations
 154  * such as power configurations, ethernet initialization as phase2 of
 155  * boot sequence
 156  *
 157  * @return 0
 158  */
 159 int misc_init_r(void)
 160 {
 161         /* Partial setup:
 162          *   VAUX3 - 2.8V for DVI
 163          *   VPLL1 - 1.8V
 164          *   VDAC  - 1.8V
 165          * and turns on LEDA/LEDB (not needed ... NOP?)
 166          */
 167         twl4030_power_init();
 168
 169         /* FIXME finish setup:
 170          *   VAUX1 - 2.8V for mainboard I/O
 171          *   VAUX2 - 2.8V for camera
 172          *   VAUX4 - 1.8V for OMAP3 CSI
 173          *   VMMC1 - 3.15V (init, variable) for MMC1
 174          *   VMMC2 - 1.85V for MMC2
 175          *   VSIM  - off (init, variable) for MMC1.DAT[3..7], SIM
 176          *   VPLL2 - 1.8V
 177          */
 178
 179         return 0;
 180 }
 181
 182 /**
 183  * @brief set_muxconf_regs Setting up the configuration Mux registers
 184  * specific to the hardware. Many pins need to be moved from protect
 185  * to primary mode.
 186  */
 187 void set_muxconf_regs(void)
 188 {
 189         /* platform specific muxes */
 190         MUX_SDP3430();
 191 }
 192
 193 #ifdef CONFIG_GENERIC_MMC
 194 int board_mmc_init(bd_t *bis)
 195 {
 196         return omap_mmc_init(0, 0, 0, -1, -1);
 197 }
 198 #endif