drivers/ddr/fsl/mpc85xx_ddr_gen1.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <fsl_ddr_sdram.h>
  12
  13 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  14 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  15 #endif
  16
  17 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  18                              unsigned int ctrl_num, int step)
  19 {
  20         unsigned int i;
  21         struct ccsr_ddr __iomem *ddr =
  22                 (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
  23
  24         if (ctrl_num != 0) {
  25                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  26                 return;
  27         }
  28
  29         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  30                 if (i == 0) {
  31                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  32                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  33
  34                 } else if (i == 1) {
  35                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  36                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  37
  38                 } else if (i == 2) {
  39                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  40                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  41
  42                 } else if (i == 3) {
  43                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  44                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  45                 }
  46         }
  47
  48         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  49         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  50         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  51         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  52 #if defined(CONFIG_MPC8555) || defined(CONFIG_MPC8541)
  53         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  54 #endif
  55
  56         /*
  57          * 200 painful micro-seconds must elapse between
  58          * the DDR clock setup and the DDR config enable.
  59          */
  60         udelay(200);
  61         asm volatile("sync;isync");
  62
  63         out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg);
  64
  65         asm("sync;isync;msync");
  66         udelay(500);
  67 }
  68
  69 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  70 /*
  71  * Initialize all of memory for ECC, then enable errors.
  72  */
  73
  74 void
  75 ddr_enable_ecc(unsigned int dram_size)
  76 {
  77         struct ccsr_ddr __iomem *ddr =
  78                 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
  79
  80         dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
  81
  82         /*
  83          * Enable errors for ECC.
  84          */
  85         debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
  86         ddr->err_disable = 0x00000000;
  87         asm("sync;isync;msync");
  88         debug("DMA DDR: err_disable = 0x%08x\n", ddr->err_disable);
  89 }
  90
  91 #endif  /* CONFIG_DDR_ECC  && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */