| blob | d3aee4e9eab211a0177b4c42b283e789024d9614 |
1 '\" te
2 .\" Copyright (c) 2005 Innovative Computing Labs Computer Science Department, University of Tennessee, Knoxville, TN. All Rights Reserved.
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8 .\" license conforms to the BSD License template.
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10 .TH GENERIC_EVENTS 3CPC "Oct 8, 2008"
11 .SH NAME
12 generic_events \- generic performance counter events
13 .SH DESCRIPTION
14 .sp
15 .LP
16 The Solaris \fBcpc\fR(3CPC) subsystem implements a number of predefined,
17 generic performance counter events. Each generic event maps onto a single
18 platform specific event and one or more optional attributes. Each hardware
19 platform only need support a subset of the total set of generic events.
20 .sp
21 .LP
22 The defined generic events are:
23 .sp
24 .ne 2
25 .na
26 \fB\fBPAPI_br_cn\fR\fR
27 .ad
28 .RS 16n
29 Conditional branch instructions
30 .RE
32 .sp
33 .ne 2
34 .na
35 \fB\fBPAPI_br_ins\fR\fR
36 .ad
37 .RS 16n
38 Branch instructions taken
39 .RE
41 .sp
42 .ne 2
43 .na
44 \fB\fBPAPI_br_msp\fR\fR
45 .ad
46 .RS 16n
47 Conditional branch instructions mispredicted
48 .RE
50 .sp
51 .ne 2
52 .na
53 \fB\fBPAPI_br_ntk\fR\fR
54 .ad
55 .RS 16n
56 Conditional branch instructions not taken
57 .RE
59 .sp
60 .ne 2
61 .na
62 \fB\fBPAPI_br_prc\fR\fR
63 .ad
64 .RS 16n
65 Conditional branch instructions correctly predicted
66 .RE
68 .sp
69 .ne 2
70 .na
71 \fB\fBPAPI_br_ucn\fR\fR
72 .ad
73 .RS 16n
74 Unconditional branch instructions
75 .RE
77 .sp
78 .ne 2
79 .na
80 \fB\fBPAPI_bru_idl\fR\fR
81 .ad
82 .RS 16n
83 Cycles branch units are idle
84 .RE
86 .sp
87 .ne 2
88 .na
89 \fB\fBPAPI_btac_m\fR\fR
90 .ad
91 .RS 16n
92 Branch target address cache misses
93 .RE
95 .sp
96 .ne 2
97 .na
98 \fB\fBPAPI_ca_cln\fR\fR
99 .ad
100 .RS 16n
101 Requests for exclusive access to clean cache line
102 .RE
104 .sp
105 .ne 2
106 .na
107 \fB\fBPAPI_ca_inv\fR\fR
108 .ad
109 .RS 16n
110 Requests for cache invalidation
111 .RE
113 .sp
114 .ne 2
115 .na
116 \fB\fBPAPI_ca_itv\fR\fR
117 .ad
118 .RS 16n
119 Requests for cache line intervention
120 .RE
122 .sp
123 .ne 2
124 .na
125 \fB\fBPAPI_ca_shr\fR\fR
126 .ad
127 .RS 16n
128 Request for exclusive access to shared cache line
129 .RE
131 .sp
132 .ne 2
133 .na
134 \fB\fBPAPI_ca_snp\fR\fR
135 .ad
136 .RS 16n
137 Request for cache snoop
138 .RE
140 .sp
141 .ne 2
142 .na
143 \fB\fBPAPI_csr_fal\fR\fR
144 .ad
145 .RS 16n
146 Failed conditional store instructions
147 .RE
149 .sp
150 .ne 2
151 .na
152 \fB\fBPAPI_csr_suc\fR\fR
153 .ad
154 .RS 16n
155 Successful conditional store instructions
156 .RE
158 .sp
159 .ne 2
160 .na
161 \fB\fBPAPI_csr_tot\fR\fR
162 .ad
163 .RS 16n
164 Total conditional store instructions
165 .RE
167 .sp
168 .ne 2
169 .na
170 \fB\fBPAPI_fad_ins\fR\fR
171 .ad
172 .RS 16n
173 Floating point add instructions
174 .RE
176 .sp
177 .ne 2
178 .na
179 \fB\fBPAPI_fdv_ins\fR\fR
180 .ad
181 .RS 16n
182 Floating point divide instructions
183 .RE
185 .sp
186 .ne 2
187 .na
188 \fB\fBPAPI_fma_ins\fR\fR
189 .ad
190 .RS 16n
191 Floating point multiply and add instructions
192 .RE
194 .sp
195 .ne 2
196 .na
197 \fB\fBPAPI_fml_ins\fR\fR
198 .ad
199 .RS 16n
200 Floating point multiply instructions
201 .RE
203 .sp
204 .ne 2
205 .na
206 \fB\fBPAPI_fnv_ins\fR\fR
207 .ad
208 .RS 16n
209 Floating point inverse instructions
210 .RE
212 .sp
213 .ne 2
214 .na
215 \fB\fBPAPI_fp_ops\fR\fR
216 .ad
217 .RS 16n
218 Floating point operations
219 .RE
221 .sp
222 .ne 2
223 .na
224 \fB\fBPAPI_fp_stal\fR\fR
225 .ad
226 .RS 16n
227 Cycles the floating point unit stalled
228 .RE
230 .sp
231 .ne 2
232 .na
233 \fB\fBPAPI_fpu_idl\fR\fR
234 .ad
235 .RS 16n
236 Cycles the floating point units are idle
237 .RE
239 .sp
240 .ne 2
241 .na
242 \fB\fBPAPI_fsq_ins\fR\fR
243 .ad
244 .RS 16n
245 Floating point sqrt instructions
246 .RE
248 .sp
249 .ne 2
250 .na
251 \fB\fBPAPI_ful_ccy\fR\fR
252 .ad
253 .RS 16n
254 Cycles with maximum instructions completed
255 .RE
257 .sp
258 .ne 2
259 .na
260 \fB\fBPAPI_ful_icy\fR\fR
261 .ad
262 .RS 16n
263 Cycles with maximum instruction issue
264 .RE
266 .sp
267 .ne 2
268 .na
269 \fB\fBPAPI_fxu_idl\fR\fR
270 .ad
271 .RS 16n
272 Cycles when units are idle
273 .RE
275 .sp
276 .ne 2
277 .na
278 \fB\fBPAPI_hw_int\fR\fR
279 .ad
280 .RS 16n
281 Hardware interrupts
282 .RE
284 .sp
285 .ne 2
286 .na
287 \fB\fBPAPI_int_ins\fR\fR
288 .ad
289 .RS 16n
290 Integer instructions
291 .RE
293 .sp
294 .ne 2
295 .na
296 \fB\fBPAPI_tot_cyc\fR\fR
297 .ad
298 .RS 16n
299 Total cycles
300 .RE
302 .sp
303 .ne 2
304 .na
305 \fB\fBPAPI_tot_iis\fR\fR
306 .ad
307 .RS 16n
308 Instructions issued
309 .RE
311 .sp
312 .ne 2
313 .na
314 \fB\fBPAPI_tot_ins\fR\fR
315 .ad
316 .RS 16n
317 Instructions completed
318 .RE
320 .sp
321 .ne 2
322 .na
323 \fB\fBPAPI_vec_ins\fR\fR
324 .ad
325 .RS 16n
326 VectorSIMD instructions
327 .RE
329 .sp
330 .ne 2
331 .na
332 \fB\fBPAPI_l1_dca\fR\fR
333 .ad
334 .RS 16n
335 Level 1 data cache accesses
336 .RE
338 .sp
339 .ne 2
340 .na
341 \fB\fBPAPI_l1_dch\fR\fR
342 .ad
343 .RS 16n
344 Level 1 data cache hits
345 .RE
347 .sp
348 .ne 2
349 .na
350 \fB\fBPAPI_l1_dcm\fR\fR
351 .ad
352 .RS 16n
353 Level 1 data cache misses
354 .RE
356 .sp
357 .ne 2
358 .na
359 \fB\fBPAPI_l1_dcr\fR\fR
360 .ad
361 .RS 16n
362 Level 1 data cache reads
363 .RE
365 .sp
366 .ne 2
367 .na
368 \fB\fBPAPI_l1_dcw\fR\fR
369 .ad
370 .RS 16n
371 Level 1 data cache writes
372 .RE
374 .sp
375 .ne 2
376 .na
377 \fB\fBPAPI_l1_ica\fR\fR
378 .ad
379 .RS 16n
380 Level 1 instruction cache accesses
381 .RE
383 .sp
384 .ne 2
385 .na
386 \fB\fBPAPI_l1_ich\fR\fR
387 .ad
388 .RS 16n
389 Level 1 instruction cache hits
390 .RE
392 .sp
393 .ne 2
394 .na
395 \fB\fBPAPI_l1_icm\fR\fR
396 .ad
397 .RS 16n
398 Level 1 instruction cache misses
399 .RE
401 .sp
402 .ne 2
403 .na
404 \fB\fBPAPI_l1_icr\fR\fR
405 .ad
406 .RS 16n
407 Level 1 instruction cache reads
408 .RE
410 .sp
411 .ne 2
412 .na
413 \fB\fBPAPI_l1_icw\fR\fR
414 .ad
415 .RS 16n
416 Level 1 instruction cache writes
417 .RE
419 .sp
420 .ne 2
421 .na
422 \fB\fBPAPI_l1_ldm\fR\fR
423 .ad
424 .RS 16n
425 Level 1 cache load misses
426 .RE
428 .sp
429 .ne 2
430 .na
431 \fB\fBPAPI_l1_stm\fR\fR
432 .ad
433 .RS 16n
434 Level 1 cache store misses
435 .RE
437 .sp
438 .ne 2
439 .na
440 \fB\fBPAPI_l1_tca\fR\fR
441 .ad
442 .RS 16n
443 Level 1 cache accesses
444 .RE
446 .sp
447 .ne 2
448 .na
449 \fB\fBPAPI_l1_tch\fR\fR
450 .ad
451 .RS 16n
452 Level 1 cache hits
453 .RE
455 .sp
456 .ne 2
457 .na
458 \fB\fBPAPI_l1_tcm\fR\fR
459 .ad
460 .RS 16n
461 Level 1 cache misses
462 .RE
464 .sp
465 .ne 2
466 .na
467 \fB\fBPAPI_l1_tcr\fR\fR
468 .ad
469 .RS 16n
470 Level 1 cache reads
471 .RE
473 .sp
474 .ne 2
475 .na
476 \fB\fBPAPI_l1_tcw\fR\fR
477 .ad
478 .RS 16n
479 Level 1 cache writes
480 .RE
482 .sp
483 .ne 2
484 .na
485 \fB\fBPAPI_l2_dca\fR\fR
486 .ad
487 .RS 16n
488 Level 2 data cache accesses
489 .RE
491 .sp
492 .ne 2
493 .na
494 \fB\fBPAPI_l2_dch\fR\fR
495 .ad
496 .RS 16n
497 Level 2 data cache hits
498 .RE
500 .sp
501 .ne 2
502 .na
503 \fB\fBPAPI_l2_dcm\fR\fR
504 .ad
505 .RS 16n
506 Level 2 data cache misses
507 .RE
509 .sp
510 .ne 2
511 .na
512 \fB\fBPAPI_l2_dcr\fR\fR
513 .ad
514 .RS 16n
515 Level 2 data cache reads
516 .RE
518 .sp
519 .ne 2
520 .na
521 \fB\fBPAPI_l2_dcw\fR\fR
522 .ad
523 .RS 16n
524 Level 2 data cache writes
525 .RE
527 .sp
528 .ne 2
529 .na
530 \fB\fBPAPI_l2_ica\fR\fR
531 .ad
532 .RS 16n
533 Level 2 instruction cache accesses
534 .RE
536 .sp
537 .ne 2
538 .na
539 \fB\fBPAPI_l2_ich\fR\fR
540 .ad
541 .RS 16n
542 Level 2 instruction cache hits
543 .RE
545 .sp
546 .ne 2
547 .na
548 \fB\fBPAPI_l2_icm\fR\fR
549 .ad
550 .RS 16n
551 Level 2 instruction cache misses
552 .RE
554 .sp
555 .ne 2
556 .na
557 \fB\fBPAPI_l2_icr\fR\fR
558 .ad
559 .RS 16n
560 Level 2 instruction cache reads
561 .RE
563 .sp
564 .ne 2
565 .na
566 \fB\fBPAPI_l2_icw\fR\fR
567 .ad
568 .RS 16n
569 Level 2 instruction cache writes
570 .RE
572 .sp
573 .ne 2
574 .na
575 \fB\fBPAPI_l2_ldm\fR\fR
576 .ad
577 .RS 16n
578 Level 2 cache load misses
579 .RE
581 .sp
582 .ne 2
583 .na
584 \fB\fBPAPI_l2_stm\fR\fR
585 .ad
586 .RS 16n
587 Level 2 cache store misses
588 .RE
590 .sp
591 .ne 2
592 .na
593 \fB\fBPAPI_l2_tca\fR\fR
594 .ad
595 .RS 16n
596 Level 2 cache accesses
597 .RE
599 .sp
600 .ne 2
601 .na
602 \fB\fBPAPI_l2_tch\fR\fR
603 .ad
604 .RS 16n
605 Level 2 cache hits
606 .RE
608 .sp
609 .ne 2
610 .na
611 \fB\fBPAPI_l2_tcm\fR\fR
612 .ad
613 .RS 16n
614 Level 2 cache misses
615 .RE
617 .sp
618 .ne 2
619 .na
620 \fB\fBPAPI_l2_tcr\fR\fR
621 .ad
622 .RS 16n
623 Level 2 cache reads
624 .RE
626 .sp
627 .ne 2
628 .na
629 \fB\fBPAPI_l2_tcw\fR\fR
630 .ad
631 .RS 16n
632 Level 2 cache writes
633 .RE
635 .sp
636 .ne 2
637 .na
638 \fB\fBPAPI_l3_dca\fR\fR
639 .ad
640 .RS 16n
641 Level 3 data cache accesses
642 .RE
644 .sp
645 .ne 2
646 .na
647 \fB\fBPAPI_l3_dch\fR\fR
648 .ad
649 .RS 16n
650 Level 3 data cache hits
651 .RE
653 .sp
654 .ne 2
655 .na
656 \fB\fBPAPI_l3_dcm\fR\fR
657 .ad
658 .RS 16n
659 Level 3 data cache misses
660 .RE
662 .sp
663 .ne 2
664 .na
665 \fB\fBPAPI_l3_dcr\fR\fR
666 .ad
667 .RS 16n
668 Level 3 data cache reads
669 .RE
671 .sp
672 .ne 2
673 .na
674 \fB\fBPAPI_l3_dcw\fR\fR
675 .ad
676 .RS 16n
677 Level 3 data cache writes
678 .RE
680 .sp
681 .ne 2
682 .na
683 \fB\fBPAPI_l3_ica\fR\fR
684 .ad
685 .RS 16n
686 Level 3 instruction cache accesses
687 .RE
689 .sp
690 .ne 2
691 .na
692 \fB\fBPAPI_l3_ich\fR\fR
693 .ad
694 .RS 16n
695 Level 3 instruction cache hits
696 .RE
698 .sp
699 .ne 2
700 .na
701 \fB\fBPAPI_l3_icm\fR\fR
702 .ad
703 .RS 16n
704 Level 3 instruction cache misses
705 .RE
707 .sp
708 .ne 2
709 .na
710 \fB\fBPAPI_l3_icr\fR\fR
711 .ad
712 .RS 16n
713 Level 3 instruction cache reads
714 .RE
716 .sp
717 .ne 2
718 .na
719 \fB\fBPAPI_l3_icw\fR\fR
720 .ad
721 .RS 16n
722 Level 3 instruction cache writes
723 .RE
725 .sp
726 .ne 2
727 .na
728 \fB\fBPAPI_l3_ldm\fR\fR
729 .ad
730 .RS 16n
731 Level 3 cache load misses
732 .RE
734 .sp
735 .ne 2
736 .na
737 \fB\fBPAPI_l3_stm\fR\fR
738 .ad
739 .RS 16n
740 Level 3 cache store misses
741 .RE
743 .sp
744 .ne 2
745 .na
746 \fB\fBPAPI_l3_tca\fR\fR
747 .ad
748 .RS 16n
749 Level 3 cache accesses
750 .RE
752 .sp
753 .ne 2
754 .na
755 \fB\fBPAPI_l3_tch\fR\fR
756 .ad
757 .RS 16n
758 Level 3 cache hits
759 .RE
761 .sp
762 .ne 2
763 .na
764 \fB\fBPAPI_l3_tcm\fR\fR
765 .ad
766 .RS 16n
767 Level 3 cache misses
768 .RE
770 .sp
771 .ne 2
772 .na
773 \fB\fBPAPI_l3_tcr\fR\fR
774 .ad
775 .RS 16n
776 Level 3 cache reads
777 .RE
779 .sp
780 .ne 2
781 .na
782 \fB\fBPAPI_l3_tcw\fR\fR
783 .ad
784 .RS 16n
785 Level 3 cache writes
786 .RE
788 .sp
789 .ne 2
790 .na
791 \fB\fBPAPI_ld_ins\fR\fR
792 .ad
793 .RS 16n
794 Load Instructions
795 .RE
797 .sp
798 .ne 2
799 .na
800 \fB\fBPAPI_lst_ins\fR\fR
801 .ad
802 .RS 16n
803 Loadstore Instructions
804 .RE
806 .sp
807 .ne 2
808 .na
809 \fB\fBPAPI_lsu_idl\fR\fR
810 .ad
811 .RS 16n
812 Cycles load store units are idle
813 .RE
815 .sp
816 .ne 2
817 .na
818 \fB\fBPAPI_mem_rcy\fR\fR
819 .ad
820 .RS 16n
821 Cycles stalled waiting for memory reads
822 .RE
824 .sp
825 .ne 2
826 .na
827 \fB\fBPAPI_mem_scy\fR\fR
828 .ad
829 .RS 16n
830 Cycles stalled waiting for memory accesses
831 .RE
833 .sp
834 .ne 2
835 .na
836 \fB\fBPAPI_mem_wcy\fR\fR
837 .ad
838 .RS 16n
839 Cycles stalled waiting for memory writes
840 .RE
842 .sp
843 .ne 2
844 .na
845 \fB\fBPAPI_prf_dm\fR\fR
846 .ad
847 .RS 16n
848 Data prefetch cache misses
849 .RE
851 .sp
852 .ne 2
853 .na
854 \fB\fBPAPI_res_stl\fR\fR
855 .ad
856 .RS 16n
857 Cycles stalled on any resource
858 .RE
860 .sp
861 .ne 2
862 .na
863 \fB\fBPAPI_sr_ins\fR\fR
864 .ad
865 .RS 16n
866 Store Instructions
867 .RE
869 .sp
870 .ne 2
871 .na
872 \fB\fBPAPI_stl_ccy\fR\fR
873 .ad
874 .RS 16n
875 Cycles with no instructions completed
876 .RE
878 .sp
879 .ne 2
880 .na
881 \fB\fBPAPI_syc_ins\fR\fR
882 .ad
883 .RS 16n
884 Synchronization instructions completed
885 .RE
887 .sp
888 .ne 2
889 .na
890 \fB\fBPAPI_tlb_dm\fR\fR
891 .ad
892 .RS 16n
893 Data TLB misses
894 .RE
896 .sp
897 .ne 2
898 .na
899 \fB\fBPAPI_tlb_im\fR\fR
900 .ad
901 .RS 16n
902 Instruction TLB misses
903 .RE
905 .sp
906 .ne 2
907 .na
908 \fB\fBPAPI_tlb_sd\fR\fR
909 .ad
910 .RS 16n
911 TLB shootdowns
912 .RE
914 .sp
915 .ne 2
916 .na
917 \fB\fBPAPI_tlb_tl\fR\fR
918 .ad
919 .RS 16n
920 Total TLB misses
921 .RE
923 .sp
924 .LP
925 The tables below define mappings of generic events to platform events and any
926 associated attribute for all supported platforms.
927 .SS "AMD Opteron Family 0xF Processor"
928 .sp
930 .sp
931 .TS
932 c c c
933 l l l .
934 Generic Event Platform Event Unit Mask
935 _
936 \fBPAPI_br_ins\fR \fBFR_retired_branches_w_excp_intr\fR 0x0
937 \fBPAPI_br_msp\fR \fBFR_retired_branches_mispred\fR 0x0
938 \fBPAPI_br_tkn\fR \fBFR_retired_taken_branches\fR 0x0
939 \fBPAPI_fp_ops\fR \fBFP_dispatched_fpu_ops\fR 0x3
940 \fBPAPI_fad_ins\fR \fBFP_dispatched_fpu_ops\fR 0x1
941 \fBPAPI_fml_ins\fR \fBFP_dispatched_fpu_ops\fR 0x2
942 \fBPAPI_fpu_idl\fR \fBFP_cycles_no_fpu_ops_retired\fR 0x0
943 \fBPAPI_tot_cyc\fR \fBBU_cpu_clk_unhalted\fR 0x0
944 \fBPAPI_tot_ins\fR \fBFR_retired_x86_instr_w_excp_intr\fR 0x0
945 \fBPAPI_l1_dca\fR \fBDC_access\fR 0x0
946 \fBPAPI_l1_dcm\fR \fBDC_miss\fR 0x0
947 \fBPAPI_l1_ldm\fR \fBDC_refill_from_L2\fR 0xe
948 \fBPAPI_l1_stm\fR \fBDC_refill_from_L2\fR 0x10
949 \fBPAPI_l1_ica\fR \fBIC_fetch\fR 0x0
950 \fBPAPI_l1_icm\fR \fBIC_miss\fR 0x0
951 \fBPAPI_l1_icr\fR \fBIC_fetch\fR 0x0
952 \fBPAPI_l2_dch\fR \fBDC_refill_from_L2\fR 0x1e
953 \fBPAPI_l2_dcm\fR \fBDC_refill_from_system\fR 0x1e
954 \fBPAPI_l2_dcr\fR \fBDC_refill_from_L2\fR 0xe
955 \fBPAPI_l2_dcw\fR \fBDC_refill_from_L2\fR 0x10
956 \fBPAPI_l2_ich\fR \fBIC_refill_from_L2\fR 0x0
957 \fBPAPI_l2_icm\fR \fBIC_refill_from_system\fR 0x0
958 \fBPAPI_l2_ldm\fR \fBDC_refill_from_system\fR 0xe
959 \fBPAPI_l2_stm\fR \fBDC_refill_from_system\fR 0x10
960 \fBPAPI_res_stl\fR \fBFR_dispatch_stalls\fR 0x0
961 \fBPAPI_stl_icy\fR \fBFR_nothing_to_dispatch\fR 0x0
962 \fBPAPI_hw_int\fR \fBFR_taken_hardware_intrs\fR 0x0
963 \fBPAPI_tlb_dm\fR \fBDC_dtlb_L1_miss_L2_miss\fR 0x0
964 \fBPAPI_tlb_im\fR \fBIC_itlb_L1_miss_L2_miss\fR 0x0
965 \fBPAPI_fp_ins\fR \fBFR_retired_fpu_instr\fR 0xd
966 \fBPAPI_vec_ins\fR \fBFR_retired_fpu_instr\fR 0x4
967 .TE
969 .SS "AMD Opteron Family 0x10 Processors"
970 .sp
972 .sp
973 .TS
974 c c c
975 l l l .
976 Generic Event Platform Event Event Mask
977 _
978 \fBPAPI_br_ins\fR \fBFR_retired_branches_w_excp_intr\fR 0x0
979 \fBPAPI_br_msp\fR \fBFR_retired_branches_mispred\fR 0x0
980 \fBPAPI_br_tkn\fR \fBFR_retired_taken_branches\fR 0x0
981 \fBPAPI_fp_ops\fR \fBFP_dispatched_fpu_ops\fR 0x3
982 \fBPAPI_fad_ins\fR \fBFP_dispatched_fpu_ops\fR 0x1
983 \fBPAPI_fml_ins\fR \fBFP_dispatched_fpu_ops\fR 0x2
984 \fBPAPI_fpu_idl\fR \fBFP_cycles_no_fpu_ops_retired\fR 0x0
985 \fBPAPI_tot_cyc\fR \fBBU_cpu_clk_unhalted\fR 0x0
986 \fBPAPI_tot_ins\fR \fBFR_retired_x86_instr_w_excp_intr\fR 0x0
987 \fBPAPI_l1_dca\fR \fBDC_access\fR 0x0
988 \fBPAPI_l1_dcm\fR \fBDC_miss\fR 0x0
989 \fBPAPI_l1_ldm\fR \fBDC_refill_from_L2\fR 0xe
990 \fBPAPI_l1_stm\fR \fBDC_refill_from_L2\fR 0x10
991 \fBPAPI_l1_ica\fR \fBIC_fetch\fR 0x0
992 \fBPAPI_l1_icm\fR \fBIC_miss\fR 0x0
993 \fBPAPI_l1_icr\fR \fBIC_fetch\fR 0x0
994 \fBPAPI_l2_dch\fR \fBDC_refill_from_L2\fR 0x1e
995 \fBPAPI_l2_dcm\fR \fBDC_refill_from_system\fR 0x1e
996 \fBPAPI_l2_dcr\fR \fBDC_refill_from_L2\fR 0xe
997 \fBPAPI_l2_dcw\fR \fBDC_refill_from_L2\fR 0x10
998 \fBPAPI_l2_ich\fR \fBIC_refill_from_L2\fR 0x0
999 \fBPAPI_l2_icm\fR \fBIC_refill_from_system\fR 0x0
1000 \fBPAPI_l2_ldm\fR \fBDC_refill_from_system\fR 0xe
1001 \fBPAPI_l2_stm\fR \fBDC_refill_from_system\fR 0x10
1002 \fBPAPI_res_stl\fR \fBFR_dispatch_stalls\fR 0x0
1003 \fBPAPI_stl_icy\fR \fBFR_nothing_to_dispatch\fR 0x0
1004 \fBPAPI_hw_int\fR \fBFR_taken_hardware_intrs\fR 0x0
1005 \fBPAPI_tlb_dm\fR \fBDC_dtlb_L1_miss_L2_miss\fR 0x7
1006 \fBPAPI_tlb_im\fR \fBIC_itlb_L1_miss_L2_miss\fR 0x3
1007 \fBPAPI_fp_ins\fR \fBFR_retired_fpu_instr\fR 0xd
1008 \fBPAPI_vec_ins\fR \fBFR_retired_fpu_instr\fR 0x4
1009 \fBPAPI_l3_dcr\fR \fBL3_read_req\fR 0xf1
1010 \fBPAPI_l3_icr\fR \fBL3_read_req\fR 0xf2
1011 \fBPAPI_l3_tcr\fR \fBL3_read_req\fR 0xf7
1012 \fBPAPI_l3_stm\fR \fBL3_miss\fR 0xf4
1013 \fBPAPI_l3_ldm\fR \fBL3_miss\fR 0xf3
1014 \fBPAPI_l3_tcm\fR \fBL3_miss\fR 0xf7
1015 .TE
1017 .SS "Intel Pentium IV Processor"
1018 .sp
1020 .sp
1021 .TS
1022 c c c
1023 l l l .
1024 Generic Event Platform Event Event Mask
1025 _
1026 \fBPAPI_br_msp\fR \fBbranch_retired\fR 0xa
1027 \fBPAPI_br_ins\fR \fBbranch_retired\fR 0xf
1028 \fBPAPI_br_tkn\fR \fBbranch_retired\fR 0xc
1029 \fBPAPI_br_ntk\fR \fBbranch_retired\fR 0x3
1030 \fBPAPI_br_prc\fR \fBbranch_retired\fR 0x5
1031 \fBPAPI_tot_ins\fR \fBinstr_retired\fR 0x3
1032 \fBPAPI_tot_cyc\fR \fBglobal_power_events\fR 0x1
1033 \fBPAPI_tlb_dm\fR \fBpage_walk_type\fR 0x1
1034 \fBPAPI_tlb_im\fR \fBpage_walk_type\fR 0x2
1035 \fBPAPI_tlb_tm\fR \fBpage_walk_type\fR 0x3
1036 \fBPAPI_l2_ldm\fR \fBBSQ_cache_reference\fR 0x100
1037 \fBPAPI_l2_stm\fR \fBBSQ_cache_reference\fR 0x400
1038 \fBPAPI_l2_tcm\fR \fBBSQ_cache_reference\fR 0x500
1039 .TE
1041 .SS "Intel Pentium Pro/II/III Processor"
1042 .sp
1044 .sp
1045 .TS
1046 c c c
1047 l l l .
1048 Generic Event Platform Event Event Mask
1049 _
1050 \fBPAPI_ca_shr\fR \fBl2_ifetch\fR 0xf
1051 \fBPAPI_ca_cln\fR \fBbus_tran_rfo\fR 0x0
1052 \fBPAPI_ca_itv\fR \fBbus_tran_inval\fR 0x0
1053 \fBPAPI_tlb_im\fR \fBitlb_miss\fR 0x0
1054 \fBPAPI_btac_m\fR \fBbtb_misses\fR 0x0
1055 \fBPAPI_hw_int\fR \fBhw_int_rx\fR 0x0
1056 \fBPAPI_br_cn\fR \fBbr_inst_retired\fR 0x0
1057 \fBPAPI_br_tkn\fR \fBbr_taken_retired\fR 0x0
1058 \fBPAPI_br_msp\fR \fBbr_miss_pred_taken_ret\fR 0x0
1059 \fBPAPI_br_ins\fR \fBbr_inst_retired\fR 0x0
1060 \fBPAPI_res_stl\fR \fBresource_stalls\fR 0x0
1061 \fBPAPI_tot_iis\fR \fBinst_decoder\fR 0x0
1062 \fBPAPI_tot_ins\fR \fBinst_retired\fR 0x0
1063 \fBPAPI_tot_cyc\fR \fBcpu_clk_unhalted\fR 0x0
1064 \fBPAPI_l1_dcm\fR \fBdcu_lines_in\fR 0x0
1065 \fBPAPI_l1_icm\fR \fBl2_ifetch\fR 0xf
1066 \fBPAPI_l1_tcm\fR \fBl2_rqsts\fR 0xf
1067 \fBPAPI_l1_dca\fR \fBdata_mem_refs\fR 0x0
1068 \fBPAPI_l1_ldm\fR \fBl2_ld\fR 0xf
1069 \fBPAPI_l1_stm\fR \fBl2_st\fR 0xf
1070 \fBPAPI_l2_icm\fR \fBbus_tran_ifetch\fR 0x0
1071 \fBPAPI_l2_dcr\fR \fBl2_ld\fR 0xf
1072 \fBPAPI_l2_dcw\fR \fBl2_st\fR 0xf
1073 \fBPAPI_l2_tcm\fR \fBl2_lines_in\fR 0x0
1074 \fBPAPI_l2_tca\fR \fBl2_rqsts\fR 0xf
1075 \fBPAPI_l2_tcw\fR \fBl2_st\fR 0xf
1076 \fBPAPI_l2_stm\fR \fBl2_m_lines_inm\fR 0x0
1077 \fBPAPI_fp_ins\fR \fBflops\fR 0x0
1078 \fBPAPI_fp_ops\fR \fBflops\fR 0x0
1079 \fBPAPI_fml_ins\fR \fBmul\fR 0x0
1080 \fBPAPI_fdv_ins\fR \fBdiv\fR 0x0
1081 .TE
1083 .SS "UltraSPARC I/II Processor"
1084 .sp
1086 .sp
1087 .TS
1088 c c
1089 l l .
1090 Generic Event Platform Event
1091 _
1092 \fBPAPI_tot_cyc\fR \fBCycle_cnt\fR
1093 \fBPAPI_tot_ins\fR \fBInstr_cnt\fR
1094 \fBPAPI_tot_iis\fR \fBInstr_cnt\fR
1095 \fBPAPI_l1_dcr\fR \fBDC_rd\fR
1096 \fBPAPI_l1_dcw\fR \fBDC_wr\fR
1097 \fBPAPI_l1_ica\fR \fBIC_ref\fR
1098 \fBPAPI_l1_ich\fR \fBIC_hit\fR
1099 \fBPAPI_l2_tca\fR \fBEC_ref\fR
1100 \fBPAPI_l2_dch\fR \fBEC_rd_hit\fR
1101 \fBPAPI_l2_tch\fR \fBEC_hit\fR
1102 \fBPAPI_l2_ich\fR \fBEC_ic_hit\fR
1103 \fBPAPI_ca_inv\fR \fBEC_snoop_inv\fR
1104 \fBPAPI_br_msp\fR \fBDispatch0_mispred\fR
1105 \fBPAPI_ca_snp\fR \fBEC_snoop_cb\fR
1106 .TE
1108 .SS "UltraSPARC III/IIIi/IV Processor"
1109 .sp
1111 .sp
1112 .TS
1113 c c
1114 l l .
1115 Generic Event Platform Event
1116 _
1117 \fBPAPI_tot_cyc\fR \fBCycle_cnt\fR
1118 \fBPAPI_tot_ins\fR \fBInstr_cnt\fR
1119 \fBPAPI_tot_iis\fR \fBInstr_cnt\fR
1120 \fBPAPI_fma_ins\fR \fBFA_pipe_completion\fR
1121 \fBPAPI_fml_ins\fR \fBFM_pipe_completion\fR
1122 \fBPAPI_l1_dcr\fR \fBDC_rd\fR
1123 \fBPAPI_l1_dcw\fR \fBDC_wr\fR
1124 \fBPAPI_l1_ica\fR \fBIC_ref\fR
1125 \fBPAPI_l1_icm\fR \fBIC_miss\fR
1126 \fBPAPI_l2_tca\fR \fBEC_ref\fR
1127 \fBPAPI_l2_ldm\fR \fBEC_rd_miss\fR
1128 \fBPAPI_l2_tcm\fR \fBEC_misses\fR
1129 \fBPAPI_l2_icm\fR \fBEC_ic_miss\fR
1130 \fBPAPI_tlb_dm\fR \fBDTLB_miss\fR
1131 \fBPAPI_tlb_im\fR \fBITLB_miss\fR
1132 \fBPAPI_br_ntk\fR \fBIU_Stat_Br_count_untaken\fR
1133 \fBPAPI_br_msp\fR \fBDispatch0_mispred\fR
1134 \fBPAPI_br_tkn\fR \fBIU_Stat_Br_count_taken\fR
1135 \fBPAPI_ca_inv\fR \fBEC_snoop_inv\fR
1136 \fBPAPI_ca_snp\fR \fBEC_snoop_cb\fR
1137 .TE
1139 .SS "UltraSPARC IV+ Processor"
1140 .sp
1142 .sp
1143 .TS
1144 c c
1145 l l .
1146 Generic Event Platform Event
1147 _
1148 \fBPAPI_tot_cyc\fR \fBCycle_cnt\fR
1149 \fBPAPI_tot_ins\fR \fBInstr_cnt\fR
1150 \fBPAPI_tot_iis\fR \fBInstr_cnt\fR
1151 \fBPAPI_fma_ins\fR \fBFA_pipe_completion\fR
1152 \fBPAPI_fml_ins\fR \fBFM_pipe_completion\fR
1153 \fBPAPI_l1_dcr\fR \fBDC_rd\fR
1154 \fBPAPI_l1_stm\fR \fBDC_wr_miss\fR
1155 \fBPAPI_l1_ica\fR \fBIC_ref\fR
1156 \fBPAPI_l1_icm\fR \fBIC_L2_req\fR
1157 \fBPAPI_l1_ldm\fR \fBDC_rd_miss\fR
1158 \fBPAPI_l1_dcw\fR \fBDC_wr\fR
1159 \fBPAPI_l2_tca\fR \fBL2_ref\fR
1160 \fBPAPI_l2_ldm\fR \fBL2_rd_miss\fR
1161 \fBPAPI_l2_icm\fR \fBL2_IC_miss\fR
1162 \fBPAPI_l2_stm\fR \fBL2_write_miss\fR
1163 \fBPAPI_l2_tcm\fR \fBL2_miss\fR
1164 \fBPAPI_l3_tcm\fR \fBL3_miss\fR
1165 \fBPAPI_l3_icm\fR \fBL3_IC_miss\fR
1166 \fBPAPI_l3_ldm\fR \fBL3_rd_miss\fR
1167 \fBPAPI_tlb_im\fR \fBITLB_miss\fR
1168 \fBPAPI_tlb_dm\fR \fBDTLB_miss\fR
1169 \fBPAPI_br_tkn\fR \fBIU_stat_br_count_taken\fR
1170 \fBPAPI_br_ntk\fR \fBIU_stat_br_count_untaken\fR
1171 .TE
1173 .SS "Niagara T1 Processor"
1174 .sp
1176 .sp
1177 .TS
1178 c c
1179 l l .
1180 Generic Event Platform Event
1181 _
1182 \fBPAPI_tot_cyc\fR \fBCycle_cnt\fR
1183 \fBPAPI_l2_icm\fR \fBL2_imiss\fR
1184 \fBPAPI_l2_ldm\fR \fBL2_dmiss_ld\fR
1185 \fBPAPI_fp_ops\fR \fBFP_instr_cnt\fR
1186 \fBPAPI_l1_icm\fR \fBIC_miss\fR
1187 \fBPAPI_l1_dcm\fR \fBDC_miss\fR
1188 \fBPAPI_tlb_im\fR \fBITLB_miss\fR
1189 \fBPAPI_tlb_dm\fR \fBDTLB_miss\fR
1190 .TE
1192 .SS "Niagara T2 Processor"
1193 .sp
1195 .sp
1196 .TS
1197 c c
1198 l l .
1199 Generic Event Platform Event
1200 _
1201 \fBPAPI_tot_ins\fR \fBInstr_cnt\fR
1202 \fBPAPI_l1_dcm\fR \fBDC_miss\fR
1203 \fBPAPI_l1_icm\fR \fBIC_miss\fR
1204 \fBPAPI_l2_icm\fR \fBL2_imiss\fR
1205 \fBPAPI_l2_ldm\fR \fBL2_dmiss_ld\fR
1206 \fBPAPI_tlb_dm\fR \fBDTLB_miss\fR
1207 \fBPAPI_tlb_im\fR \fBITLB_miss\fR
1208 \fBPAPI_tlb_tm\fR \fBTLB_miss\fR
1209 \fBPAPI_br_tkn\fR \fBBr_taken\fR
1210 \fBPAPI_br_ins\fR \fBBr_completed\fR
1211 \fBPAPI_ld_ins\fR \fBInstr_ld\fR
1212 \fBPAPI_sr_ins\fR \fBInstr_st\fR
1213 .TE
1215 .SS "SPARC64 VI/VII Processor"
1216 .sp
1218 .sp
1219 .TS
1220 c c
1221 l l .
1222 Generic Event Platform Event
1223 _
1224 \fBPAPI_tot_cyc\fR \fBcycle_counts\fR
1225 \fBPAPI_tot_ins\fR \fBinstruction_counts\fR
1226 \fBPAPI_br_tkn\fR \fBbranch_instructions\fR
1227 \fBPAPI_fp_ops\fR \fBfloating_instructions\fR
1228 \fBPAPI_fma_ins\fR \fBimpdep2_instructions\fR
1229 \fBPAPI_l1_dcm\fR \fBop_r_iu_req_mi_go\fR
1230 \fBPAPI_l1_icm\fR \fBif_r_iu_req_mi_go\fR
1231 \fBPAPI_tlb_dm\fR \fBtrap_DMMU_miss\fR
1232 \fBPAPI_tlb_im\fR \fBtrap_IMMU_miss\fR
1233 .TE
1235 .SH ATTRIBUTES
1236 .sp
1237 .LP
1238 See \fBattributes\fR(5) for descriptions of the following attributes:
1239 .sp
1241 .sp
1242 .TS
1243 box;
1244 c | c
1245 l | l .
1246 ATTRIBUTE TYPE ATTRIBUTE VALUE
1247 _
1248 Interface Stability Volatile
1249 .TE
1251 .SH SEE ALSO
1252 .sp
1253 .LP
1254 \fBcpc\fR(3CPC), \fBattributes\fR(5)
1255 .SH NOTES
1256 .sp
1257 .LP
1258 Generic names prefixed with "PAPI_" are taken from the University of
1259 Tennessee's PAPI project, http://icl.cs.utk.edu/papi\&.