2 * Solaris DLPI driver for ethernet cards based on the ADMtek Centaur
4 * Copyright (c) 2007 by Garrett D'Amore <garrett@damore.org>.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the author nor the names of any co-contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS''
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
33 * Use is subject to license terms.
44 * Registers and values are here, becuase they can be exported to userland
45 * via the AFEIOC_GETCSR and friends ioctls. These are private to this
46 * driver and the bundled diagnostic utility, and should not be used by
47 * end user application programs.
51 * AFE register definitions.
53 /* PCI configuration registers */
54 #define PCI_VID 0x00 /* Loaded vendor ID */
55 #define PCI_DID 0x02 /* Loaded device ID */
56 #define PCI_CMD 0x04 /* Configuration command register */
57 #define PCI_STAT 0x06 /* Configuration status register */
58 #define PCI_RID 0x08 /* Revision ID */
59 #define PCI_CLS 0x0c /* Cache line size */
60 #define PCI_SVID 0x2c /* Subsystem vendor ID */
61 #define PCI_SSID 0x2e /* Subsystem ID */
62 #define PCI_MINGNT 0x3e /* Minimum Grant */
63 #define PCI_MAXLAT 0x3f /* Maximum latency */
64 #define PCI_SIG 0x80 /* Signature of AN983 */
65 #define PCI_PMR0 0xc0 /* Power Management Register 0 */
66 #define PCI_PMR1 0xc4 /* Power Management Register 1 */
69 * Bits for PCI command register.
71 #define PCI_CMD_MWIE 0x0010 /* memory write-invalidate enable */
72 #define PCI_CMD_BME 0x0004 /* bus master enable */
73 #define PCI_CMD_MAE 0x0002 /* memory access enable */
74 #define PCI_CMD_IOE 0x0001 /* I/O access enable */
77 * Signature values for PCI_SIG
79 #define SIG_AN983 0x09811317
80 #define SIG_AN985 0x09851317
81 #define SIG_ADM9511 0x69851317
83 /* Ordinary control/status registers */
84 #define CSR_PAR 0x00 /* PCI access register */
85 #define CSR_TDR 0x08 /* Transmit demand register */
86 #define CSR_RDR 0x10 /* Receive demand register */
87 #define CSR_RDB 0x18 /* Receive descriptor base address */
88 #define CSR_TDB 0x20 /* Transmit descriptor base address */
89 #define CSR_SR 0x28 /* Status register */
90 #define CSR_NAR 0x30 /* Network access register */
91 #define CSR_IER 0x38 /* Interrupt enable register */
92 #define CSR_LPC 0x40 /* Lost packet counter */
93 #define CSR_SPR 0x48 /* Serial port register */
94 #define CSR_TIMER 0x58 /* Timer */
95 #define CSR_SR2 0x80 /* Status register 2 */
96 #define CSR_IER2 0x84 /* Interrupt enable register 2 */
97 #define CSR_CR 0x88 /* Command register */
98 #define CSR_PMCSR 0x90 /* Power Management Command and Status */
99 #define CSR_PAR0 0xa4 /* Physical address register 0 */
100 #define CSR_PAR1 0xa8 /* Physical address register 1 */
101 #define CSR_MAR0 0xac /* Multicast address hash table register 0 */
102 #define CSR_MAR1 0xb0 /* Multicast address hash table register 1 */
103 #define CSR_BMCR 0xb4 /* PHY BMCR (comet only) */
104 #define CSR_BMSR 0xb8 /* PHY BMSR (comet only) */
105 #define CSR_PHYIDR1 0xbc /* PHY PHYIDR1 (comet only) */
106 #define CSR_PHYIDR2 0xc0 /* PHY PHYIDR2 (comet only) */
107 #define CSR_ANAR 0xc4 /* PHY ANAR (comet only) */
108 #define CSR_ANLPAR 0xc8 /* PHY ANLPAR (comet only) */
109 #define CSR_ANER 0xcc /* PHY ANER (comet only) */
110 #define CSR_XMC 0xd0 /* XCVR mode control (comet only) */
111 #define CSR_XCIIS 0xd4 /* XCVR config info/int status (comet only) */
112 #define CSR_XIE 0xd8 /* XCVR interupt enable (comet only) */
113 #define CSR_OPM 0xfc /* Opmode register (centaur only) */
116 * Bits for PCI access register.
118 #define PAR_RESET 0x00000001U /* Reset the entire chip */
119 #define PAR_MWIE 0x01000000U /* PCI memory-write-invalidate */
120 #define PAR_MRLE 0x00800000U /* PCI memory-read-line */
121 #define PAR_MRME 0x00200000U /* PCI memory-read-multiple */
122 #define PAR_TXHIPRI 0x00000002U /* Transmit higher priority */
123 #define PAR_DESCSKIP 0x0000007cU /* Descriptor skip length in DW */
124 #define PAR_BIGENDIAN 0x00000080U /* Use big endian data buffers */
125 #define PAR_TXAUTOPOLL 0x00060000U /* Programmable TX autopoll interval */
126 #define PAR_RXFIFO_100 0x00009000U /* RX FIFO control, Centaur only */
127 #define PAR_RXFIFO_10 0x00002800U /* RX FIFO control, Centaur only */
128 #define PAR_CALIGN_NONE 0x00000000U /* No cache alignment, Comet */
129 #define PAR_CALIGN_8 0x00004000U /* 8 DW cache alignment, Comet */
130 #define PAR_CALIGN_16 0x00008000U /* 16 DW cache alignment, Comet */
131 #define PAR_CALIGN_32 0x0000c000U /* 32 DW cache alignment, Comet */
132 #define PAR_BURSTLEN 0x00003F00U /* Programmable burst length, Comet */
133 #define PAR_BURSTUNL 0x00000000U /* Unlimited burst length, Comet */
134 #define PAR_BURST_1 0x00000100U /* 1 DW burst length, Comet */
135 #define PAR_BURST_2 0x00000200U /* 2 DW burst length, Comet */
136 #define PAR_BURST_4 0x00000400U /* 4 DW burst length, Comet */
137 #define PAR_BURST_8 0x00000800U /* 8 DW burst length, Comet */
138 #define PAR_BURST_16 0x00001000U /* 16 DW burst length, Comet */
139 #define PAR_BURST_32 0x00002000U /* 32 DW burst length, Comet */
142 * Bits for status register.
144 #define SR_BERR_TYPE 0x03800000U /* bus error type */
145 #define SR_BERR_PARITY 0x00000000U /* parity error */
146 #define SR_BERR_TARGET_ABORT 0x01000000U /* target abort */
147 #define SR_BERR_MASTER_ABORT 0x00800000U /* master abort */
148 #define SR_TX_STATE 0x00700000U /* transmit state */
149 #define SR_RX_STATE 0x000E0000U /* receive state */
152 * Interrupts. These are in IER2 and SR2. Some of them also appear
153 * in SR and IER, but we only use the ADMtek specific IER2 and SR2.
155 #define INT_TXEARLY 0x80000000U /* transmit early interrupt */
156 #define INT_RXEARLY 0x40000000U /* receive early interrupt */
157 #define INT_LINKCHG 0x20000000U /* link status changed */
158 #define INT_TXDEFER 0x10000000U /* transmit defer interrupt */
159 #define INT_PAUSE 0x04000000U /* pause frame received */
160 #define INT_NORMAL 0x00010000U /* normal interrupt */
161 #define INT_ABNORMAL 0x00008000U /* abnormal interrupt */
162 #define INT_BUSERR 0x00002000U /* fatal bus error */
163 #define INT_TIMER 0x00000800U /* onboard timer */
164 #define INT_RXJABBER 0x00000200U /* receive watchdog */
165 #define INT_RXSTOPPED 0x00000100U /* receive stopped */
166 #define INT_RXNOBUF 0x00000080U /* no rcv descriptor */
167 #define INT_RXOK 0x00000040U /* receive complete */
168 #define INT_TXUNDERFLOW 0x00000020U /* transmit underflow */
169 #define INT_TXJABBER 0x00000008U /* transmit jabber timeout */
170 #define INT_TXNOBUF 0x00000004U /* no xmt descriptor */
171 #define INT_TXSTOPPED 0x00000002U /* transmit stopped */
172 #define INT_TXOK 0x00000001U /* transmit ok interrupt */
174 #define INT_NONE 0x00000000U /* no interrupts */
175 #define INT_ALL 0xf401abefU /* all interrupts */
176 #define INT_WANTED (INT_NORMAL | INT_ABNORMAL | \
177 INT_BUSERR | INT_RXJABBER | \
178 INT_RXOK | INT_RXNOBUF | \
179 INT_TIMER | INT_LINKCHG | \
180 INT_RXSTOPPED | INT_TXSTOPPED | \
181 INT_TXUNDERFLOW | INT_TXJABBER)
184 * Bits for network access register.
186 #define NAR_TX_ENABLE 0x00002000U /* Enable transmit */
187 #define NAR_RX_MULTI 0x00000080U /* Receive all multicast packets */
188 #define NAR_RX_PROMISC 0x00000040U /* Receive any good packet */
189 #define NAR_RX_BAD 0x00000008U /* Pass bad packets */
190 #define NAR_RX_ENABLE 0x00000002U /* Enable receive */
191 #define NAR_TR 0x0000c000U /* Transmit threshold mask */
192 #define NAR_TR_72 0x00000000U /* 72 B (128 @ 100Mbps) tx thresh */
193 #define NAR_TR_96 0x00004000U /* 96 B (256 @ 100Mbps) tx thresh */
194 #define NAR_TR_128 0x00008000U /* 128 B (512 @ 100Mbps) tx thresh */
195 #define NAR_TR_160 0x0000c000U /* 160 B (1K @ 100Mbsp) tx thresh */
196 #define NAR_SF 0x00200000U /* store and forward */
197 #define NAR_HBD 0x00080000U /* Disable SQE heartbeat */
198 #define NAR_FCOLL 0x00001000U /* force collision */
199 #define NAR_MODE 0x00000c00U /* mode (loopback, etc.) */
200 #define NAR_MACLOOP 0x00000400U /* mac loop back */
203 * Bits for lost packet counter.
205 #define LPC_COUNT 0x0000FFFFU /* Count of missed frames */
206 #define LPC_OFLOW 0x00010000U /* Counter overflow bit */
209 * Bits for CSR_SPR (MII and SROM access)
211 #define SPR_MII_DIN 0x00080000U /* MII data input */
212 #define SPR_MII_CTRL 0x00040000U /* MII management control, 1=read */
213 #define SPR_MII_DOUT 0x00020000U /* MII data output */
214 #define SPR_MII_CLOCK 0x00010000U /* MII data clock */
215 #define SPR_SROM_READ 0x00004000U /* Serial EEPROM read control */
216 #define SPR_SROM_WRITE 0x00002000U /* Serial EEPROM write control */
217 #define SPR_SROM_SEL 0x00000800U /* Serial EEPROM select */
218 #define SPR_SROM_DOUT 0x00000008U /* Serial EEPROM data out */
219 #define SPR_SROM_DIN 0x00000004U /* Serial EEPROM data in */
220 #define SPR_SROM_CLOCK 0x00000002U /* Serial EEPROM clock */
221 #define SPR_SROM_CHIP 0x00000001U /* Serial EEPROM chip select */
222 #define SROM_ENADDR 0x4 /* Offset of ethernet address */
223 #define SROM_READCMD 0x6 /* command to read SROM */
228 #define TIMER_LOOP 0x00010000U /* continuous operating mode */
229 #define TIMER_USEC 204 /* usecs per timer count */
234 #define CR_PAUSE 0x00000020U /* enable pause flow control */
235 #define CR_TXURAUTOR 0x00000001U /* transmit underrun auto recovery */
238 * Bits for XMC (Comet specific)
240 #define XMC_LDIS 0x0800 /* long distance 10Base-T cable */
243 * Bits for XCIIS (Comet specific)
245 #define XCIIS_SPEED 0x0200 /* 100 Mbps mode */
246 #define XCIIS_DUPLEX 0x0100 /* full duplex mode */
247 #define XCIIS_FLOWCTL 0x0080 /* flow control support */
248 #define XCIIS_ANC 0x0040 /* autonegotiation complete */
249 #define XCIIS_RF 0x0020 /* remote fault detected */
250 #define XCIIS_LFAIL 0x0010 /* link fail */
251 #define XCIIS_ANLPAR 0x0008 /* anar received from link partner */
252 #define XCIIS_PDF 0x0004 /* parallel detection fault */
253 #define XCIIS_ANPR 0x0002 /* autoneg. page received */
254 #define XCIIS_REF 0x0001 /* receive error counter full */
257 * Bits for XIE (Comet specific)
259 #define XIE_ANCE 0x0040 /* aneg complete interrupt enable */
260 #define XIE_RFE 0x0020 /* remote fault interrupt enable */
261 #define XIE_LDE 0x0010 /* link fail interrupt enable */
262 #define XIE_ANAE 0x0008 /* aneg. ack. interrupt enable */
263 #define XIE_PDFE 0x0004 /* parallel det. fault int. enable */
264 #define XIE_ANPE 0x0002 /* autoneg. page rec'd int. enable */
265 #define XIE_REFE 0x0001 /* receive error full int. enable */
268 * Centaur 1.1 extensions to MII.
270 #define PHY_PILR 0x10 /* an983b 1.1 - polarity/int lvl */
271 #define PHY_MCR 0x15 /* an983b 1.1 - mode control */
273 #define PILR_NOSQE 0x0800 /* disable 10BaseT SQE */
274 #define MCR_FIBER 0x0001 /* enable fiber */
277 * Bits for Opmode (Centaur specific)
279 #define OPM_SPEED 0x80000000U /* 100 Mbps */
280 #define OPM_DUPLEX 0x40000000U /* full duplex */
281 #define OPM_LINK 0x20000000U /* link up? */
282 #define OPM_MODE 0x00000007U /* mode mask */
283 #define OPM_INTPHY 0x00000007U /* single chip mode, internal PHY */
284 #define OPM_MACONLY 0x00000004U /* MAC ony mode, external PHY */
288 * Put exported kernel interfaces here. (There should be none.)
