usr/src/uts/common/io/atge/atge_l1_reg.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  * Copyright (c) 2012 Gary Mills
  25  */
  26
  27 #ifndef _ATGE_L1_REG_H
  28 #define _ATGE_L1_REG_H
  29
  30 #ifdef __cplusplus
  31         extern "C" {
  32 #endif
  33
  34 #pragma pack(1)
  35 typedef struct  l1_cmb {
  36         uint32_t        intr_status;
  37         uint32_t        rx_prod_cons;
  38         uint32_t        tx_prod_cons;
  39 } l1_cmb_t;
  40
  41 typedef struct  l1_rx_desc {
  42         uint64_t        addr;
  43         uint32_t        len;
  44 } l1_rx_desc_t;
  45
  46 typedef struct  l1_rx_rdesc {
  47         uint32_t        index;
  48         uint32_t        len;
  49         uint32_t        flags;
  50         uint32_t        vtags;
  51 } l1_rx_rdesc_t;
  52
  53 /*
  54  * Statistics counters collected by the MAC
  55  */
  56 typedef struct l1_smb {
  57         /* Rx stats. */
  58         uint32_t rx_frames;
  59         uint32_t rx_bcast_frames;
  60         uint32_t rx_mcast_frames;
  61         uint32_t rx_pause_frames;
  62         uint32_t rx_control_frames;
  63         uint32_t rx_crcerrs;
  64         uint32_t rx_lenerrs;
  65         uint32_t rx_bytes;
  66         uint32_t rx_runts;
  67         uint32_t rx_fragments;
  68         uint32_t rx_pkts_64;
  69         uint32_t rx_pkts_65_127;
  70         uint32_t rx_pkts_128_255;
  71         uint32_t rx_pkts_256_511;
  72         uint32_t rx_pkts_512_1023;
  73         uint32_t rx_pkts_1024_1518;
  74         uint32_t rx_pkts_1519_max;
  75         uint32_t rx_pkts_truncated;
  76         uint32_t rx_fifo_oflows;
  77         uint32_t rx_desc_oflows;
  78         uint32_t rx_alignerrs;
  79         uint32_t rx_bcast_bytes;
  80         uint32_t rx_mcast_bytes;
  81         uint32_t rx_pkts_filtered;
  82         /* Tx stats. */
  83         uint32_t tx_frames;
  84         uint32_t tx_bcast_frames;
  85         uint32_t tx_mcast_frames;
  86         uint32_t tx_pause_frames;
  87         uint32_t tx_excess_defer;
  88         uint32_t tx_control_frames;
  89         uint32_t tx_deferred;
  90         uint32_t tx_bytes;
  91         uint32_t tx_pkts_64;
  92         uint32_t tx_pkts_65_127;
  93         uint32_t tx_pkts_128_255;
  94         uint32_t tx_pkts_256_511;
  95         uint32_t tx_pkts_512_1023;
  96         uint32_t tx_pkts_1024_1518;
  97         uint32_t tx_pkts_1519_max;
  98         uint32_t tx_single_colls;
  99         uint32_t tx_multi_colls;
 100         uint32_t tx_late_colls;
 101         uint32_t tx_excess_colls;
 102         uint32_t tx_underrun;
 103         uint32_t tx_desc_underrun;
 104         uint32_t tx_lenerrs;
 105         uint32_t tx_pkts_truncated;
 106         uint32_t tx_bcast_bytes;
 107         uint32_t tx_mcast_bytes;
 108         uint32_t updated;
 109 } atge_l1_smb_t;
 110 #pragma pack()
 111
 112 #define L1_RX_RING_CNT          256
 113 #define L1_RR_RING_CNT          (ATGE_TX_RING_CNT + L1_RX_RING_CNT)
 114
 115 #define L1_RING_ALIGN           16
 116 #define L1_TX_RING_ALIGN        16
 117 #define L1_RX_RING_ALIGN        16
 118 #define L1_RR_RING_ALIGN        16
 119 #define L1_CMB_ALIGN            16
 120 #define L1_SMB_ALIGN            16
 121
 122 #define L1_CMB_BLOCK_SZ sizeof (struct l1_cmb)
 123 #define L1_SMB_BLOCK_SZ sizeof (struct l1_smb)
 124
 125 #define L1_RX_RING_SZ           \
 126         (sizeof (struct l1_rx_desc) * L1_RX_RING_CNT)
 127
 128 #define L1_RR_RING_SZ           \
 129         (sizeof (struct l1_rx_rdesc) * L1_RR_RING_CNT)
 130
 131 /*
 132  * For RX
 133  */
 134 #define L1_RRD_CONS_SHIFT               16
 135 #define L1_RRD_NSEGS_MASK               0x000000FF
 136 #define L1_RRD_CONS_MASK                0xFFFF0000
 137 #define L1_RRD_NSEGS_SHIFT              0
 138 #define L1_RRD_LEN_MASK                 0xFFFF0000
 139 #define L1_RRD_CSUM_MASK                0x0000FFFF
 140 #define L1_RRD_CSUM_SHIFT               0
 141 #define L1_RRD_LEN_SHIFT                16
 142 #define L1_RRD_ETHERNET                 0x00000080
 143 #define L1_RRD_VLAN                     0x00000100
 144 #define L1_RRD_ERROR                    0x00000200
 145 #define L1_RRD_IPV4                     0x00000400
 146 #define L1_RRD_UDP                      0x00000800
 147 #define L1_RRD_TCP                      0x00001000
 148 #define L1_RRD_BCAST                    0x00002000
 149 #define L1_RRD_MCAST                    0x00004000
 150 #define L1_RRD_PAUSE                    0x00008000
 151 #define L1_RRD_CRC                      0x00010000
 152 #define L1_RRD_CODE                     0x00020000
 153 #define L1_RRD_DRIBBLE                  0x00040000
 154 #define L1_RRD_RUNT                     0x00080000
 155 #define L1_RRD_OFLOW                    0x00100000
 156 #define L1_RRD_TRUNC                    0x00200000
 157 #define L1_RRD_IPCSUM_NOK               0x00400000
 158 #define L1_RRD_TCP_UDPCSUM_NOK          0x00800000
 159 #define L1_RRD_LENGTH_NOK               0x01000000
 160 #define L1_RRD_DES_ADDR_FILTERED        0x02000000
 161 #define RRD_PROD_MASK                   0x0000FFFF
 162 #define TPD_CONS_MASK                   0xFFFF0000
 163 #define TPD_CONS_SHIFT                  16
 164 #define CMB_UPDATED                     0x00000001
 165 #define RRD_PROD_SHIFT                  0
 166
 167 /*
 168  * All descriptors and CMB/SMB share the same high address.
 169  */
 170 #define L1_DESC_ADDR_HI 0x1540
 171 #define L1_DESC_RD_ADDR_LO      0x1544
 172 #define L1_DESC_RRD_ADDR_LO     0x1548
 173 #define L1_DESC_TPD_ADDR_LO     0x154C
 174 #define L1_DESC_CMB_ADDR_LO     0x1550
 175 #define L1_DESC_SMB_ADDR_LO     0x1554
 176 #define L1_DESC_RRD_RD_CNT      0x1558
 177 #define DESC_RRD_CNT_SHIFT      16
 178 #define DESC_RRD_CNT_MASK       0x07FF0000
 179 #define DESC_RD_CNT_SHIFT       0
 180 #define DESC_RD_CNT_MASK        0x000007FF
 181
 182 /*
 183  * PHY registers.
 184  */
 185 #define PHY_CDTS_STAT_OK        0x0000
 186 #define PHY_CDTS_STAT_SHORT     0x0100
 187 #define PHY_CDTS_STAT_OPEN      0x0200
 188 #define PHY_CDTS_STAT_INVAL     0x0300
 189 #define PHY_CDTS_STAT_MASK      0x0300
 190
 191 /*
 192  * DMA CFG registers (L1 specific)
 193  */
 194 #define DMA_CFG_RD_ENB          0x00000400
 195 #define DMA_CFG_WR_ENB          0x00000800
 196 #define DMA_CFG_RD_BURST_MASK   0x07
 197 #define DMA_CFG_RD_BURST_SHIFT  4
 198 #define DMA_CFG_WR_BURST_MASK   0x07
 199 #define DMA_CFG_WR_BURST_SHIFT  7
 200
 201 #define L1_RD_LEN_MASK          0x0000FFFF
 202 #define L1_RD_LEN_SHIFT 0
 203
 204 #define L1_SRAM_RD_ADDR         0x1500
 205 #define L1_SRAM_RD_LEN                  0x1504
 206 #define L1_SRAM_RRD_ADDR                0x1508
 207 #define L1_SRAM_RRD_LEN         0x150C
 208 #define L1_SRAM_TPD_ADDR                0x1510
 209 #define L1_SRAM_TPD_LEN         0x1514
 210 #define L1_SRAM_TRD_ADDR                0x1518
 211 #define L1_SRAM_TRD_LEN         0x151C
 212 #define L1_SRAM_RX_FIFO_ADDR            0x1520
 213 #define L1_SRAM_RX_FIFO_LEN             0x1524
 214 #define L1_SRAM_TX_FIFO_ADDR            0x1528
 215 #define L1_SRAM_TX_FIFO_LEN             0x152C
 216
 217 #define RXQ_CFG_RD_BURST_MASK           0x000000FF
 218 #define RXQ_CFG_RRD_BURST_THRESH_MASK   0x0000FF00
 219 #define RXQ_CFG_RD_PREF_MIN_IPG_MASK    0x001F0000
 220 #define RXQ_CFG_RD_BURST_SHIFT          0
 221 #define RXQ_CFG_RD_BURST_DEFAULT        8
 222 #define RXQ_CFG_RRD_BURST_THRESH_SHIFT  8
 223 #define RXQ_CFG_RRD_BURST_THRESH_DEFAULT 8
 224 #define RXQ_CFG_RD_PREF_MIN_IPG_SHIFT   16
 225 #define RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT 1
 226
 227 #define TXQ_CFG_TPD_FETCH_THRESH_MASK   0x00003F00
 228 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT  8
 229 #define TXQ_CFG_TPD_FETCH_DEFAULT       16
 230
 231 #define L1_TX_JUMBO_TPD_TH_IPG          0x1584
 232 #define TX_JUMBO_TPD_TH_MASK            0x000007FF
 233 #define TX_JUMBO_TPD_IPG_MASK           0x001F0000
 234 #define TX_JUMBO_TPD_TH_SHIFT           0
 235 #define TX_JUMBO_TPD_IPG_SHIFT          16
 236 #define TX_JUMBO_TPD_IPG_DEFAULT        1
 237
 238 /* CMB DMA Write Threshold Register */
 239 #define L1_CMB_WR_THRESH                0x15D4
 240 #define CMB_WR_THRESH_RRD_MASK          0x000007FF
 241 #define CMB_WR_THRESH_TPD_MASK          0x07FF0000
 242 #define CMB_WR_THRESH_RRD_SHIFT         0
 243 #define CMB_WR_THRESH_RRD_DEFAULT       4
 244 #define CMB_WR_THRESH_TPD_SHIFT         16
 245 #define CMB_WR_THRESH_TPD_DEFAULT       4
 246
 247 /* SMB auto DMA timer register */
 248 #define L1_SMB_TIMER                    0x15E4
 249
 250 #define L1_CSMB_CTRL                    0x15D0
 251 #define CSMB_CTRL_CMB_KICK              0x00000001
 252 #define CSMB_CTRL_SMB_KICK              0x00000002
 253 #define CSMB_CTRL_CMB_ENB               0x00000004
 254 #define CSMB_CTRL_SMB_ENB               0x00000008
 255
 256 #define INTR_RX_DMA                     0x00080000
 257 #define INTR_CMB_RX                     0x00100000
 258 #define INTR_CMB_TX                     0x00200000
 259 #define INTR_DIS_SMB                    0x20000000
 260
 261 #define L1_INTRS        \
 262         (INTR_SMB | INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |   \
 263         INTR_CMB_TX | INTR_CMB_RX | INTR_RX_FIFO_OFLOW | INTR_TX_FIFO_UNDERRUN)
 264
 265 #define L1_RXQ_RRD_PAUSE_THRESH 0x15AC
 266 #define RXQ_RRD_PAUSE_THRESH_HI_MASK    0x00000FFF
 267 #define RXQ_RRD_PAUSE_THRESH_LO_MASK    0x0FFF0000
 268 #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT   0
 269 #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT   16
 270
 271 /* RX/TX count-down timer to trigger CMB-write. */
 272 #define L1_CMB_WR_TIMER                 0x15D8
 273 #define CMB_WR_TIMER_RX_MASK            0x0000FFFF
 274 #define CMB_WR_TIMER_TX_MASK            0xFFFF0000
 275 #define CMB_WR_TIMER_RX_SHIFT           0
 276 #define CMB_WR_TIMER_TX_SHIFT           16
 277
 278 /*
 279  * Useful macros.
 280  */
 281 #define L1_RX_NSEGS(x)  \
 282         (((x) & L1_RRD_NSEGS_MASK) >> L1_RRD_NSEGS_SHIFT)
 283 #define L1_RX_CONS(x)   \
 284         (((x) & L1_RRD_CONS_MASK) >> L1_RRD_CONS_SHIFT)
 285 #define L1_RX_CSUM(x)   \
 286         (((x) & L1_RRD_CSUM_MASK) >> L1_RRD_CSUM_SHIFT)
 287 #define L1_RX_BYTES(x)  \
 288         (((x) & L1_RRD_LEN_MASK) >> L1_RRD_LEN_SHIFT)
 289
 290
 291 #ifdef __cplusplus
 292 }
 293 #endif
 294
 295 #endif  /* _ATGE_L1_REG_H */