usr/src/uts/common/io/atge/atge_l1c_reg.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 2012 Gary Mills
  23  *
  24  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  25  * Use is subject to license terms.
  26  */
  27 /*
  28  * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
  29  * All rights reserved.
  30  *
  31  * Redistribution and use in source and binary forms, with or without
  32  * modification, are permitted provided that the following conditions
  33  * are met:
  34  * 1. Redistributions of source code must retain the above copyright
  35  *    notice unmodified, this list of conditions, and the following
  36  *    disclaimer.
  37  * 2. Redistributions in binary form must reproduce the above copyright
  38  *    notice, this list of conditions and the following disclaimer in the
  39  *    documentation and/or other materials provided with the distribution.
  40  *
  41  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  42  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  43  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  44  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  45  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  46  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  47  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  48  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  49  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  50  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  51  * SUCH DAMAGE.
  52  */
  53
  54 #ifndef _ATGE_L1C_REG_H
  55 #define _ATGE_L1C_REG_H
  56
  57 #ifdef __cplusplus
  58         extern "C" {
  59 #endif
  60
  61 #pragma pack(1)
  62 typedef struct  l1c_cmb {
  63         uint32_t        intr_status;
  64         uint32_t        rx_prod_cons;
  65         uint32_t        tx_prod_cons;
  66 } l1c_cmb_t;
  67
  68 typedef struct  l1c_rx_desc {
  69         uint64_t        addr;
  70         /* No length field. */
  71 } l1c_rx_desc_t;
  72
  73 typedef struct  l1c_rx_rdesc {
  74         uint32_t        rdinfo; /* word 0 */
  75         uint32_t        rss;    /* word 1 */
  76         uint32_t        vtag;   /* word 2 */
  77         uint32_t        status; /* word 3 */
  78 } l1c_rx_rdesc_t;
  79
  80 /*
  81  * Statistics counters collected by the MAC
  82  */
  83 typedef struct l1c_smb {
  84         /* Rx stats. */
  85         uint32_t rx_frames;
  86         uint32_t rx_bcast_frames;
  87         uint32_t rx_mcast_frames;
  88         uint32_t rx_pause_frames;
  89         uint32_t rx_control_frames;
  90         uint32_t rx_crcerrs;
  91         uint32_t rx_lenerrs;
  92         uint32_t rx_bytes;
  93         uint32_t rx_runts;
  94         uint32_t rx_fragments;
  95         uint32_t rx_pkts_64;
  96         uint32_t rx_pkts_65_127;
  97         uint32_t rx_pkts_128_255;
  98         uint32_t rx_pkts_256_511;
  99         uint32_t rx_pkts_512_1023;
 100         uint32_t rx_pkts_1024_1518;
 101         uint32_t rx_pkts_1519_max;
 102         uint32_t rx_pkts_truncated;
 103         uint32_t rx_fifo_oflows;
 104         uint32_t rx_desc_oflows;
 105         uint32_t rx_alignerrs;
 106         uint32_t rx_bcast_bytes;
 107         uint32_t rx_mcast_bytes;
 108         uint32_t rx_pkts_filtered;
 109         /* Tx stats. */
 110         uint32_t tx_frames;
 111         uint32_t tx_bcast_frames;
 112         uint32_t tx_mcast_frames;
 113         uint32_t tx_pause_frames;
 114         uint32_t tx_excess_defer;
 115         uint32_t tx_control_frames;
 116         uint32_t tx_deferred;
 117         uint32_t tx_bytes;
 118         uint32_t tx_pkts_64;
 119         uint32_t tx_pkts_65_127;
 120         uint32_t tx_pkts_128_255;
 121         uint32_t tx_pkts_256_511;
 122         uint32_t tx_pkts_512_1023;
 123         uint32_t tx_pkts_1024_1518;
 124         uint32_t tx_pkts_1519_max;
 125         uint32_t tx_single_colls;
 126         uint32_t tx_multi_colls;
 127         uint32_t tx_late_colls;
 128         uint32_t tx_excess_colls;
 129         uint32_t tx_underrun;
 130         uint32_t tx_desc_underrun;
 131         uint32_t tx_lenerrs;
 132         uint32_t tx_pkts_truncated;
 133         uint32_t tx_bcast_bytes;
 134         uint32_t tx_mcast_bytes;
 135         uint32_t updated;
 136 } atge_l1c_smb_t;
 137 #pragma pack()
 138
 139 #define L1C_RX_RING_CNT         256
 140 #define L1C_RR_RING_CNT         L1C_RX_RING_CNT
 141 #define L1C_HEADROOM            6  /* Must be divisible by 2, but not 4. */
 142
 143 #define L1C_RING_ALIGN          16
 144 #define L1C_TX_RING_ALIGN       16
 145 #define L1C_RX_RING_ALIGN       16
 146 #define L1C_RR_RING_ALIGN       16
 147 #define L1C_CMB_ALIGN           16
 148 #define L1C_SMB_ALIGN           16
 149
 150 #define L1C_CMB_BLOCK_SZ        sizeof (struct l1c_cmb)
 151 #define L1C_SMB_BLOCK_SZ        sizeof (struct l1c_smb)
 152
 153 #define L1C_RX_RING_SZ          \
 154         (sizeof (struct l1c_rx_desc) * L1C_RX_RING_CNT)
 155
 156 #define L1C_RR_RING_SZ          \
 157         (sizeof (struct l1c_rx_rdesc) * L1C_RR_RING_CNT)
 158
 159 /*
 160  * For RX
 161  */
 162 /* word 0 */
 163 #define L1C_RRD_CSUM_MASK               0x0000FFFF
 164 #define L1C_RRD_RD_CNT_MASK             0x000F0000
 165 #define L1C_RRD_RD_IDX_MASK             0xFFF00000
 166 #define L1C_RRD_CSUM_SHIFT              0
 167 #define L1C_RRD_RD_CNT_SHIFT            16
 168 #define L1C_RRD_RD_IDX_SHIFT            20
 169 #define L1C_RRD_CSUM(x)                 \
 170         (((x) & L1C_RRD_CSUM_MASK) >> L1C_RRD_CSUM_SHIFT)
 171 #define L1C_RRD_RD_CNT(x)                       \
 172         (((x) & L1C_RRD_RD_CNT_MASK) >> L1C_RRD_RD_CNT_SHIFT)
 173 #define L1C_RRD_RD_IDX(x)                       \
 174         (((x) & L1C_RRD_RD_IDX_MASK) >> L1C_RRD_RD_IDX_SHIFT)
 175
 176 /* word 2 */
 177 #define L1C_RRD_VLAN_MASK               0x0000FFFF
 178 #define L1C_RRD_HEAD_LEN_MASK           0x00FF0000
 179 #define L1C_RRD_HDS_MASK                0x03000000
 180 #define L1C_RRD_HDS_NONE                0x00000000
 181 #define L1C_RRD_HDS_HEAD                0x01000000
 182 #define L1C_RRD_HDS_DATA                0x02000000
 183 #define L1C_RRD_CPU_MASK                0x0C000000
 184 #define L1C_RRD_HASH_FLAG_MASK          0xF0000000
 185 #define L1C_RRD_VLAN_SHIFT              0
 186 #define L1C_RRD_HEAD_LEN_SHIFT          16
 187 #define L1C_RRD_HDS_SHIFT               24
 188 #define L1C_RRD_CPU_SHIFT               26
 189 #define L1C_RRD_HASH_FLAG_SHIFT         28
 190 #define L1C_RRD_VLAN(x)                 \
 191         (((x) & L1C_RRD_VLAN_MASK) >> L1C_RRD_VLAN_SHIFT)
 192 #define L1C_RRD_HEAD_LEN(x)                     \
 193         (((x) & L1C_RRD_HEAD_LEN_MASK) >> L1C_RRD_HEAD_LEN_SHIFT)
 194 #define L1C_RRD_CPU(x)                  \
 195         (((x) & L1C_RRD_CPU_MASK) >> L1C_RRD_CPU_SHIFT)
 196
 197         /* word3 */
 198 #define L1C_RRD_LEN_MASK                0x00003FFF
 199 #define L1C_RRD_LEN_SHIFT               0
 200 #define L1C_RRD_TCP_UDPCSUM_NOK         0x00004000
 201 #define L1C_RRD_IPCSUM_NOK              0x00008000
 202 #define L1C_RRD_VLAN_TAG                0x00010000
 203 #define L1C_RRD_PROTO_MASK              0x000E0000
 204 #define L1C_RRD_PROTO_IPV4              0x00020000
 205 #define L1C_RRD_PROTO_IPV6              0x000C0000
 206 #define L1C_RRD_ERR_SUM                 0x00100000
 207 #define L1C_RRD_ERR_CRC                 0x00200000
 208 #define L1C_RRD_ERR_ALIGN               0x00400000
 209 #define L1C_RRD_ERR_TRUNC               0x00800000
 210 #define L1C_RRD_ERR_RUNT                0x01000000
 211 #define L1C_RRD_ERR_ICMP                0x02000000
 212 #define L1C_RRD_BCAST                   0x04000000
 213 #define L1C_RRD_MCAST                   0x08000000
 214 #define L1C_RRD_SNAP_LLC                0x10000000
 215 #define L1C_RRD_ETHER                   0x00000000
 216 #define L1C_RRD_FIFO_FULL               0x20000000
 217 #define L1C_RRD_ERR_LENGTH              0x40000000
 218 #define L1C_RRD_VALID                   0x80000000
 219 #define L1C_RRD_BYTES(x)                        \
 220         (((x) & L1C_RRD_LEN_MASK) >> L1C_RRD_LEN_SHIFT)
 221 #define L1C_RRD_IPV4(x)                 \
 222         (((x) & L1C_RRD_PROTO_MASK) == L1C_RRD_PROTO_IPV4)
 223
 224 #define RRD_PROD_MASK                   0x0000FFFF
 225 #define TPD_CONS_MASK                   0xFFFF0000
 226 #define TPD_CONS_SHIFT                  16
 227 #define CMB_UPDATED                     0x00000001
 228 #define RRD_PROD_SHIFT                  0
 229
 230 #pragma pack(1)
 231 typedef struct l1c_tx_desc {
 232         uint32_t len;
 233 #define L1C_TD_BUFLEN_MASK              0x00003FFF
 234 #define L1C_TD_VLAN_MASK                0xFFFF0000
 235 #define L1C_TD_BUFLEN_SHIFT             0
 236 #define L1C_TX_BYTES(x)                 \
 237         (((x) << L1C_TD_BUFLEN_SHIFT) & L1C_TD_BUFLEN_MASK)
 238 #define L1C_TD_VLAN_SHIFT               16
 239
 240         uint32_t flags;
 241 #define L1C_TD_L4HDR_OFFSET_MASK        0x000000FF      /* byte unit */
 242 #define L1C_TD_TCPHDR_OFFSET_MASK       0x000000FF      /* byte unit */
 243 #define L1C_TD_PLOAD_OFFSET_MASK        0x000000FF      /* 2 bytes unit */
 244 #define L1C_TD_CUSTOM_CSUM              0x00000100
 245 #define L1C_TD_IPCSUM                   0x00000200
 246 #define L1C_TD_TCPCSUM                  0x00000400
 247 #define L1C_TD_UDPCSUM                  0x00000800
 248 #define L1C_TD_TSO                      0x00001000
 249 #define L1C_TD_TSO_DESCV1               0x00000000
 250 #define L1C_TD_TSO_DESCV2               0x00002000
 251 #define L1C_TD_CON_VLAN_TAG             0x00004000
 252 #define L1C_TD_INS_VLAN_TAG             0x00008000
 253 #define L1C_TD_IPV4_DESCV2              0x00010000
 254 #define L1C_TD_LLC_SNAP                 0x00020000
 255 #define L1C_TD_ETHERNET                 0x00000000
 256 #define L1C_TD_CUSTOM_CSUM_OFFSET_MASK  0x03FC0000      /* 2 bytes unit */
 257 #define L1C_TD_CUSTOM_CSUM_EVEN_PAD     0x40000000
 258 #define L1C_TD_MSS_MASK                 0x7FFC0000
 259 #define L1C_TD_EOP                      0x80000000
 260 #define L1C_TD_L4HDR_OFFSET_SHIFT       0
 261 #define L1C_TD_TCPHDR_OFFSET_SHIFT      0
 262 #define L1C_TD_PLOAD_OFFSET_SHIFT       0
 263 #define L1C_TD_CUSTOM_CSUM_OFFSET_SHIFT 18
 264 #define L1C_TD_MSS_SHIFT                18
 265
 266         uint64_t addr;
 267 } l1c_tx_desc_t;
 268 #pragma pack()
 269
 270 /*
 271  * All descriptors and CMB/SMB share the same high address.
 272  */
 273
 274 /* From Freebsd if_alcreg.h */
 275 #define L1C_RSS_IDT_TABLE0              0x14E0
 276
 277 #define L1C_RX_BASE_ADDR_HI             0x1540
 278
 279 #define L1C_TX_BASE_ADDR_HI             0x1544
 280
 281 #define L1C_SMB_BASE_ADDR_HI            0x1548
 282
 283 #define L1C_SMB_BASE_ADDR_LO            0x154C
 284
 285 #define L1C_RD0_HEAD_ADDR_LO            0x1550
 286
 287 #define L1C_RD1_HEAD_ADDR_LO            0x1554
 288
 289 #define L1C_RD2_HEAD_ADDR_LO            0x1558
 290
 291 #define L1C_RD3_HEAD_ADDR_LO            0x155C
 292
 293 #define L1C_RD_RING_CNT                 0x1560
 294 #define RD_RING_CNT_MASK                0x00000FFF
 295 #define RD_RING_CNT_SHIFT               0
 296
 297 #define L1C_RX_BUF_SIZE                 0x1564
 298 #define RX_BUF_SIZE_MASK                0x0000FFFF
 299 /*
 300  * If larger buffer size than 1536 is specified the controller
 301  * will be locked up. This is hardware limitation.
 302  */
 303 #define RX_BUF_SIZE_MAX                 1536
 304
 305 #define L1C_RRD0_HEAD_ADDR_LO           0x1568
 306
 307 #define L1C_RRD1_HEAD_ADDR_LO           0x156C
 308
 309 #define L1C_RRD2_HEAD_ADDR_LO           0x1570
 310
 311 #define L1C_RRD3_HEAD_ADDR_LO           0x1574
 312
 313 #define L1C_RRD_RING_CNT                0x1578
 314 #define RRD_RING_CNT_MASK               0x00000FFF
 315 #define RRD_RING_CNT_SHIFT              0
 316
 317 #define L1C_TDH_HEAD_ADDR_LO            0x157C
 318
 319 #define L1C_TDL_HEAD_ADDR_LO            0x1580
 320
 321 #define L1C_TD_RING_CNT                 0x1584
 322 #define TD_RING_CNT_MASK                0x0000FFFF
 323 #define TD_RING_CNT_SHIFT               0
 324
 325 #define L1C_CMB_BASE_ADDR_LO            0x1588
 326
 327 #define L1C_RXQ_CFG                     0x15A0
 328 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK      0x00000003
 329 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE      0x00000000
 330 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M        0x00000001
 331 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M       0x00000002
 332 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M      0x00000003
 333
 334 #define L1C_RSS_CPU                     0x15B8
 335
 336 /* End of Freebsd if_alcreg.h */
 337
 338 /*
 339  * PHY registers.
 340  */
 341 #define PHY_CDTS_STAT_OK        0x0000
 342 #define PHY_CDTS_STAT_SHORT     0x0100
 343 #define PHY_CDTS_STAT_OPEN      0x0200
 344 #define PHY_CDTS_STAT_INVAL     0x0300
 345 #define PHY_CDTS_STAT_MASK      0x0300
 346
 347 /*
 348  * MAC CFG registers (L1C specific)
 349  */
 350 #define L1C_CFG_SINGLE_PAUSE_ENB        0x10000000
 351
 352 /*
 353  * DMA CFG registers (L1C specific)
 354  */
 355 #define DMA_CFG_RD_ENB                  0x00000400
 356 #define DMA_CFG_WR_ENB                  0x00000800
 357 #define DMA_CFG_RD_BURST_MASK           0x07
 358 #define DMA_CFG_RD_BURST_SHIFT          4
 359 #define DMA_CFG_WR_BURST_MASK           0x07
 360 #define DMA_CFG_WR_BURST_SHIFT          7
 361 #define DMA_CFG_SMB_DIS                 0x01000000
 362
 363 #define L1C_RD_LEN_MASK                 0x0000FFFF
 364 #define L1C_RD_LEN_SHIFT                0
 365
 366 #define L1C_SRAM_RD_ADDR                0x1500
 367 #define L1C_SRAM_RD_LEN                 0x1504
 368 #define L1C_SRAM_RRD_ADDR               0x1508
 369 #define L1C_SRAM_RRD_LEN                0x150C
 370 #define L1C_SRAM_TPD_ADDR               0x1510
 371 #define L1C_SRAM_TPD_LEN                0x1514
 372 #define L1C_SRAM_TRD_ADDR               0x1518
 373 #define L1C_SRAM_TRD_LEN                0x151C
 374 #define L1C_SRAM_RX_FIFO_ADDR           0x1520
 375 #define L1C_SRAM_RX_FIFO_LEN            0x1524
 376 #define L1C_SRAM_TX_FIFO_ADDR           0x1528
 377 #define L1C_SRAM_TX_FIFO_LEN            0x152C
 378
 379 #define L1C_RXQ_CFG_RD_BURST_MASK       0x03f00000
 380 #define L1C_RXQ_CFG_RD_BURST_SHIFT      20
 381
 382 #define L1C_TXQ_CFG                     0x1590
 383 #define TXQ_CFG_TPD_FETCH_THRESH_MASK   0x00003F00
 384 #define L1C_TXQ_CFG_TPD_BURST_DEFAULT   5
 385 #define TXQ_CFG_TPD_FETCH_THRESH_SHIFT  8
 386 #define TXQ_CFG_TPD_FETCH_DEFAULT       16
 387
 388 #define L1C_TXF_WATER_MARK              0x1598  /* 8 bytes unit */
 389 #define TXF_WATER_MARK_HI_MASK          0x00000FFF
 390 #define TXF_WATER_MARK_LO_MASK          0x0FFF0000
 391 #define TXF_WATER_MARK_BURST_ENB        0x80000000
 392 #define TXF_WATER_MARK_LO_SHIFT         0
 393 #define TXF_WATER_MARK_HI_SHIFT         16
 394
 395 #define L1C_RD_DMA_CFG                  0x15AC
 396 #define RD_DMA_CFG_THRESH_MASK          0x00000FFF      /* 8 bytes unit */
 397 #define RD_DMA_CFG_TIMER_MASK           0xFFFF0000
 398 #define RD_DMA_CFG_THRESH_SHIFT         0
 399 #define RD_DMA_CFG_TIMER_SHIFT          16
 400 #define RD_DMA_CFG_THRESH_DEFAULT       0x100
 401 #define RD_DMA_CFG_TIMER_DEFAULT        0
 402 #define RD_DMA_CFG_TICK_USECS           8
 403 #define L1C_RD_DMA_CFG_USECS(x)         ((x) / RD_DMA_CFG_TICK_USECS)
 404
 405 /* CMB DMA Write Threshold Register */
 406 #define L1C_CMB_WR_THRESH               0x15D4
 407 #define CMB_WR_THRESH_RRD_MASK          0x000007FF
 408 #define CMB_WR_THRESH_TPD_MASK          0x07FF0000
 409 #define CMB_WR_THRESH_RRD_SHIFT         0
 410 #define CMB_WR_THRESH_RRD_DEFAULT       4
 411 #define CMB_WR_THRESH_TPD_SHIFT         16
 412 #define CMB_WR_THRESH_TPD_DEFAULT       4
 413
 414 /* SMB auto DMA timer register */
 415 #define L1C_SMB_TIMER                   0x15E4
 416
 417 #define L1C_CSMB_CTRL                   0x15D0
 418 #define CSMB_CTRL_CMB_KICK              0x00000001
 419 #define CSMB_CTRL_SMB_KICK              0x00000002
 420 #define CSMB_CTRL_CMB_ENB               0x00000004
 421 #define CSMB_CTRL_SMB_ENB               0x00000008
 422
 423 /* From Freebsd if_alcreg.h */
 424 #define L1C_INTR_SMB                    0x00000001
 425 #define L1C_INTR_TIMER                  0x00000002
 426 #define L1C_INTR_MANUAL_TIMER           0x00000004
 427 #define L1C_INTR_RX_FIFO_OFLOW          0x00000008
 428 #define L1C_INTR_RD0_UNDERRUN           0x00000010
 429 #define L1C_INTR_RD1_UNDERRUN           0x00000020
 430 #define L1C_INTR_RD2_UNDERRUN           0x00000040
 431 #define L1C_INTR_RD3_UNDERRUN           0x00000080
 432 #define L1C_INTR_TX_FIFO_UNDERRUN       0x00000100
 433 #define L1C_INTR_DMA_RD_TO_RST          0x00000200
 434 #define L1C_INTR_DMA_WR_TO_RST          0x00000400
 435 #define L1C_INTR_TX_CREDIT              0x00000800
 436 #define L1C_INTR_GPHY                   0x00001000
 437 #define L1C_INTR_GPHY_LOW_PW            0x00002000
 438 #define L1C_INTR_TXQ_TO_RST             0x00004000
 439 #define L1C_INTR_TX_PKT                 0x00008000
 440 #define L1C_INTR_RX_PKT0                0x00010000
 441 #define L1C_INTR_RX_PKT1                0x00020000
 442 #define L1C_INTR_RX_PKT2                0x00040000
 443 #define L1C_INTR_RX_PKT3                0x00080000
 444 #define L1C_INTR_MAC_RX                 0x00100000
 445 #define L1C_INTR_MAC_TX                 0x00200000
 446 #define L1C_INTR_UNDERRUN               0x00400000
 447 #define L1C_INTR_FRAME_ERROR            0x00800000
 448 #define L1C_INTR_FRAME_OK               0x01000000
 449 #define L1C_INTR_CSUM_ERROR             0x02000000
 450 #define L1C_INTR_PHY_LINK_DOWN          0x04000000
 451 #define L1C_INTR_DIS_INT                0x80000000
 452
 453 #define L1C_INTR_RX_PKT                 L1C_INTR_RX_PKT0
 454 #define L1C_INTR_RD_UNDERRUN            L1C_INTR_RD0_UNDERRUN
 455
 456 #define L1C_INTRS                               \
 457         (L1C_INTR_DMA_RD_TO_RST | L1C_INTR_DMA_WR_TO_RST | \
 458         L1C_INTR_TXQ_TO_RST| L1C_INTR_RX_PKT | L1C_INTR_TX_PKT | \
 459         L1C_INTR_RX_FIFO_OFLOW | L1C_INTR_RD_UNDERRUN | \
 460         L1C_INTR_TX_FIFO_UNDERRUN)
 461
 462 #define L1C_RXQ_RRD_PAUSE_THRESH        0x15AC
 463 #define RXQ_RRD_PAUSE_THRESH_HI_MASK    0x00000FFF
 464 #define RXQ_RRD_PAUSE_THRESH_LO_MASK    0x0FFF0000
 465 #define RXQ_RRD_PAUSE_THRESH_HI_SHIFT   0
 466 #define RXQ_RRD_PAUSE_THRESH_LO_SHIFT   16
 467
 468 /* RX/TX count-down timer to trigger CMB-write. */
 469 #define L1C_CMB_WR_TIMER                        0x15D8
 470 #define CMB_WR_TIMER_RX_MASK            0x0000FFFF
 471 #define CMB_WR_TIMER_TX_MASK            0xFFFF0000
 472 #define CMB_WR_TIMER_RX_SHIFT           0
 473 #define CMB_WR_TIMER_TX_SHIFT           16
 474
 475 /*
 476  * Useful macros.
 477  */
 478 #define L1C_RX_NSEGS(x) \
 479         (((x) & L1C_RRD_NSEGS_MASK) >> L1C_RRD_NSEGS_SHIFT)
 480 #define L1C_RX_CONS(x)  \
 481         (((x) & L1C_RRD_CONS_MASK) >> L1C_RRD_CONS_SHIFT)
 482 #define L1C_RX_CSUM(x)  \
 483         (((x) & L1C_RRD_CSUM_MASK) >> L1C_RRD_CSUM_SHIFT)
 484 #define L1C_RX_BYTES(x) \
 485         (((x) & L1C_RRD_LEN_MASK) >> L1C_RRD_LEN_SHIFT)
 486
 487
 488 #ifdef __cplusplus
 489 }
 490 #endif
 491
 492 #endif  /* _ATGE_L1C_REG_H */