usr/src/uts/common/io/atge/atge_l1e_reg.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (c) 2012 Gary Mills
  23  *
  24  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  25  * Use is subject to license terms.
  26  */
  27
  28 #ifndef _ATGE_L1E_REG_H
  29 #define _ATGE_L1E_REG_H
  30
  31 #ifdef __cplusplus
  32         extern "C" {
  33 #endif
  34
  35 /*
  36  * Number of RX Rings (or pages) we use.
  37  */
  38 #define L1E_RX_PAGES            2
  39
  40 #pragma pack(1)
  41 typedef struct  rx_rs   {
  42         uint32_t        seqno;
  43         uint32_t        length;
  44         uint32_t        flags;
  45         uint32_t        vtags;
  46 } rx_rs_t;
  47
  48 typedef struct  rx_cmb {
  49         uint32_t        cmb[L1E_RX_PAGES];
  50 } rx_cmb_t;
  51 #pragma pack()
  52
  53 /* Master configuration */
  54 #define L1E_MASTER_CFG                  0x1400
  55 #define L1E_MASTER_RESET                0x00000001
  56 #define L1E_MASTER_MTIMER_ENB           0x00000002
  57 #define L1E_MASTER_IM_TX_TIMER_ENB      0x00000004
  58 #define L1E_MASTER_MANUAL_INT_ENB       0x00000008
  59 #define L1E_MASTER_IM_RX_TIMER_ENB      0x00000020
  60 #define L1E_MASTER_CHIP_REV_MASK        0x00FF0000
  61 #define L1E_MASTER_CHIP_ID_MASK         0xFF000000
  62 #define L1E_MASTER_CHIP_REV_SHIFT       16
  63 #define L1E_MASTER_CHIP_ID_SHIFT        24
  64
  65
  66 /*
  67  * DMA CFG registers (L1E specific).
  68  */
  69 #define DMA_CFG_RD_REQ_PRI              0x00000400
  70 #define DMA_CFG_TXCMB_ENB               0x00100000
  71 #define DMA_CFG_RD_BURST_MASK           0x07
  72 #define DMA_CFG_RD_BURST_SHIFT          4
  73 #define DMA_CFG_WR_BURST_MASK           0x07
  74 #define DMA_CFG_WR_BURST_SHIFT          7
  75
  76 #define L1E_TX_RING_CNT_MIN             32
  77 #define L1E_TX_RING_CNT_MAX             1020
  78 #define L1E_TX_RING_ALIGN               8
  79 #define L1E_RX_PAGE_ALIGN               32
  80 #define L1E_CMB_ALIGN                   32
  81 #define L1E_MAX_FRAMELEN                ETHERMAX
  82
  83 #define L1E_RX_PAGE_SZ_MIN              (8 * 1024)
  84 #define L1E_RX_PAGE_SZ_MAX              (1024 * 1024)
  85 #define L1E_RX_FRAMES_PAGE              128
  86 #define L1E_RX_PAGE_SZ  \
  87         (ROUNDUP(L1E_MAX_FRAMELEN, L1E_RX_PAGE_ALIGN) * L1E_RX_FRAMES_PAGE)
  88 #define L1E_TX_CMB_SZ                   (sizeof (uint32_t))
  89 #define L1E_RX_CMB_SZ                   (sizeof (uint32_t))
  90
  91 #define L1E_PROC_MAX    \
  92         ((L1E_RX_PAGE_SZ * L1E_RX_PAGES) / ETHERMAX)
  93 #define L1E_PROC_DEFAULT                (L1E_PROC_MAX / 4)
  94
  95 #define L1E_INTRS                                               \
  96         (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST |              \
  97         INTR_RX_PKT | INTR_TX_PKT | INTR_RX_FIFO_OFLOW |        \
  98         INTR_TX_FIFO_UNDERRUN | INTR_SMB)
  99
 100 #define L1E_RSS_IDT_TABLE0              0x1560
 101 #define L1E_RSS_CPU                     0x157C
 102
 103 #define L1E_SRAM_RX_FIFO_LEN            0x1524
 104
 105 #define L1E_PHY_STATUS                  0x1418
 106 #define PHY_STATUS_100M                 0x00020000
 107
 108 #define L1E_SMB_STAT_TIMER              0x15C4
 109
 110 #define GPHY_CTRL_EXT_RESET             0x0001
 111 #define GPHY_CTRL_PIPE_MOD              0x0002
 112 #define GPHY_CTRL_BERT_START            0x0010
 113 #define GPHY_CTRL_GL1E_25M_ENB          0x0020
 114 #define GPHY_CTRL_LPW_EXIT              0x0040
 115 #define GPHY_CTRL_PHY_IDDQ              0x0080
 116 #define GPHY_CTRL_PHY_IDDQ_DIS          0x0100
 117 #define GPHY_CTRL_PCLK_SEL_DIS          0x0200
 118 #define GPHY_CTRL_HIB_EN                0x0400
 119 #define GPHY_CTRL_HIB_PULSE             0x0800
 120 #define GPHY_CTRL_SEL_ANA_RESET         0x1000
 121 #define GPHY_CTRL_PHY_PLL_ON            0x2000
 122 #define GPHY_CTRL_PWDOWN_HW             0x4000
 123
 124 #define RXF_VALID                       0x01
 125
 126 #define L1E_RXF0_PAGE0                  0x15F4
 127 #define L1E_RXF0_PAGE1                  0x15F5
 128
 129 #define L1E_RXF0_PAGE0_ADDR_LO          0x1544
 130 #define L1E_RXF0_PAGE1_ADDR_LO          0x1548
 131
 132 #define L1E_RXF_PAGE_SIZE               0x1558
 133
 134 #define L1E_INT_TRIG_THRESH             0x15C8
 135 #define INT_TRIG_TX_THRESH_MASK         0x0000FFFF
 136 #define INT_TRIG_RX_THRESH_MASK         0xFFFF0000
 137 #define INT_TRIG_TX_THRESH_SHIFT        0
 138 #define INT_TRIG_RX_THRESH_SHIFT        16
 139
 140 #define L1E_INT_TRIG_TIMER              0x15CC
 141 #define INT_TRIG_TX_TIMER_MASK          0x0000FFFF
 142 #define INT_TRIG_RX_TIMER_MASK          0x0000FFFF
 143 #define INT_TRIG_TX_TIMER_SHIFT         0
 144 #define INT_TRIG_RX_TIMER_SHIFT         16
 145
 146 #define TX_COALSC_PKT_1e                0x15C8  /* W: L1E */
 147 #define RX_COALSC_PKT_1e                0x15CA  /* W: L1E */
 148 #define TX_COALSC_TO_1e                 0x15CC  /* W: L1E */
 149 #define RX_COALSC_TO_1e                 0x15CE  /* W: L1E */
 150
 151 #define L1E_HOST_RXF0_PAGEOFF           0x1800
 152 #define L1E_TPD_CONS_IDX                0x1804
 153 #define L1E_HOST_RXF1_PAGEOFF           0x1808
 154 #define L1E_HOST_RXF2_PAGEOFF           0x180C
 155 #define L1E_HOST_RXF3_PAGEOFF           0x1810
 156 #define L1E_RXF0_CMB0_ADDR_LO           0x1820
 157 #define L1E_RXF0_CMB1_ADDR_LO           0x1824
 158 #define L1E_RXF1_CMB0_ADDR_LO           0x1828
 159 #define L1E_RXF1_CMB1_ADDR_LO           0x182C
 160 #define L1E_RXF2_CMB0_ADDR_LO           0x1830
 161 #define L1E_RXF2_CMB1_ADDR_LO           0x1834
 162 #define L1E_RXF3_CMB0_ADDR_LO           0x1838
 163 #define L1E_RXF3_CMB1_ADDR_LO           0x183C
 164 #define L1E_TX_CMB_ADDR_LO              0x1840
 165 #define L1E_SMB_ADDR_LO                 0x1844
 166
 167 #define L1E_RD_SEQNO_MASK               0x0000FFFF
 168 #define L1E_RD_HASH_MASK                0xFFFF0000
 169 #define L1E_RD_SEQNO_SHIFT              0
 170 #define L1E_RD_HASH_SHIFT               16
 171 #define L1E_RX_SEQNO(x)         \
 172         (((x) & L1E_RD_SEQNO_MASK) >> L1E_RD_SEQNO_SHIFT)
 173 #define L1E_RD_CSUM_MASK                0x0000FFFF
 174 #define L1E_RD_LEN_MASK                 0x3FFF0000
 175 #define L1E_RD_CPU_MASK                 0xC0000000
 176 #define L1E_RD_CSUM_SHIFT               0
 177 #define L1E_RD_LEN_SHIFT                16
 178 #define L1E_RD_CPU_SHIFT                30
 179 #define L1E_RX_CSUM(x)  \
 180         (((x) & L1E_RD_CSUM_MASK) >> L1E_RD_CSUM_SHIFT)
 181 #define L1E_RX_BYTES(x) \
 182         (((x) & L1E_RD_LEN_MASK) >> L1E_RD_LEN_SHIFT)
 183 #define L1E_RX_CPU(x)   \
 184         (((x) & L1E_RD_CPU_MASK) >> L1E_RD_CPU_SHIFT)
 185
 186 #define L1E_RD_RSS_IPV4                 0x00000001
 187 #define L1E_RD_RSS_IPV4_TCP             0x00000002
 188 #define L1E_RD_RSS_IPV6                 0x00000004
 189 #define L1E_RD_RSS_IPV6_TCP             0x00000008
 190 #define L1E_RD_IPV6                     0x00000010
 191 #define L1E_RD_IPV4_FRAG                0x00000020
 192 #define L1E_RD_IPV4_DF                  0x00000040
 193 #define L1E_RD_802_3                    0x00000080
 194 #define L1E_RD_VLAN                     0x00000100
 195 #define L1E_RD_ERROR                    0x00000200
 196 #define L1E_RD_IPV4                     0x00000400
 197 #define L1E_RD_UDP                      0x00000800
 198 #define L1E_RD_TCP                      0x00001000
 199 #define L1E_RD_BCAST                    0x00002000
 200 #define L1E_RD_MCAST                    0x00004000
 201 #define L1E_RD_PAUSE                    0x00008000
 202 #define L1E_RD_CRC                      0x00010000
 203 #define L1E_RD_CODE                     0x00020000
 204 #define L1E_RD_DRIBBLE                  0x00040000
 205 #define L1E_RD_RUNT                     0x00080000
 206 #define L1E_RD_OFLOW                    0x00100000
 207 #define L1E_RD_TRUNC                    0x00200000
 208 #define L1E_RD_IPCSUM_NOK               0x00400000
 209 #define L1E_RD_TCP_UDPCSUM_NOK          0x00800000
 210 #define L1E_RD_LENGTH_NOK               0x01000000
 211 #define L1E_RD_DES_ADDR_FILTERED        0x02000000
 212
 213 /* TX descriptor fields */
 214 #define L1E_TD_VLAN_MASK                0xFFFF0000
 215 #define L1E_TD_PKT_INT                  0x00008000
 216 #define L1E_TD_DMA_INT                  0x00004000
 217 #define L1E_TD_VLAN_SHIFT               16
 218 #define L1E_TX_VLAN_TAG(x)      \
 219         (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8))
 220 #define L1E_TD_BUFLEN_SHIFT             0
 221 #define L1E_TD_MSS                      0xFFF80000
 222 #define L1E_TD_TSO_HDR                  0x00040000
 223 #define L1E_TD_TCPHDR_LEN               0x0003C000
 224 #define L1E_TD_IPHDR_LEN                0x00003C00
 225 #define L1E_TD_IPV6HDR_LEN2             0x00003C00
 226 #define L1E_TD_LLC_SNAP                 0x00000200
 227 #define L1E_TD_VLAN_TAGGED              0x00000100
 228 #define L1E_TD_UDPCSUM                  0x00000080
 229 #define L1E_TD_TCPCSUM                  0x00000040
 230 #define L1E_TD_IPCSUM                   0x00000020
 231 #define L1E_TD_IPV6HDR_LEN1             0x000000E0
 232 #define L1E_TD_TSO                      0x00000010
 233 #define L1E_TD_CXSUM                    0x00000008
 234 #define L1E_TD_INSERT_VLAN_TAG          0x00000004
 235 #define L1E_TD_IPV6                     0x00000002
 236
 237 #define L1E_TD_CSUM_PLOADOFFSET         0x00FF0000
 238 #define L1E_TD_CSUM_XSUMOFFSET          0xFF000000
 239 #define L1E_TD_CSUM_XSUMOFFSET_SHIFT    24
 240 #define L1E_TD_CSUM_PLOADOFFSET_SHIFT   16
 241 #define L1E_TD_MSS_SHIFT                19
 242 #define L1E_TD_TCPHDR_LEN_SHIFT         14
 243 #define L1E_TD_IPHDR_LEN_SHIFT          10
 244
 245 #define L1E_JUMBO_FRAMELEN              8132
 246
 247 #define L1E_TX_JUMBO_THRESH             0x1584
 248 #define TX_JUMBO_THRESH_MASK            0x000007FF
 249 #define TX_JUMBO_THRESH_SHIFT           0
 250 #define TX_JUMBO_THRESH_UNIT            8
 251 #define TX_JUMBO_THRESH_UNIT_SHIFT      3
 252
 253 /*
 254  * Statistics counters collected by the MAC.
 255  * AR81xx requires register access to get MAC statistics
 256  * and the format of statistics seems to be the same of L1
 257  * except for tx_abort field in TX stats. So keep it separate for simplicity.
 258  */
 259 #define L1E_RX_MIB_BASE                 0x1700
 260 #define L1E_TX_MIB_BASE                 0x1760
 261
 262 #pragma pack(1)
 263 typedef struct smb {
 264         /* Rx stats. */
 265         uint32_t rx_frames;
 266         uint32_t rx_bcast_frames;
 267         uint32_t rx_mcast_frames;
 268         uint32_t rx_pause_frames;
 269         uint32_t rx_control_frames;
 270         uint32_t rx_crcerrs;
 271         uint32_t rx_lenerrs;
 272         uint32_t rx_bytes;
 273         uint32_t rx_runts;
 274         uint32_t rx_fragments;
 275         uint32_t rx_pkts_64;
 276         uint32_t rx_pkts_65_127;
 277         uint32_t rx_pkts_128_255;
 278         uint32_t rx_pkts_256_511;
 279         uint32_t rx_pkts_512_1023;
 280         uint32_t rx_pkts_1024_1518;
 281         uint32_t rx_pkts_1519_max;
 282         uint32_t rx_pkts_truncated;
 283         uint32_t rx_fifo_oflows;
 284         uint32_t rx_rrs_errs;
 285         uint32_t rx_alignerrs;
 286         uint32_t rx_bcast_bytes;
 287         uint32_t rx_mcast_bytes;
 288         uint32_t rx_pkts_filtered;
 289         /* Tx stats. */
 290         uint32_t tx_frames;
 291         uint32_t tx_bcast_frames;
 292         uint32_t tx_mcast_frames;
 293         uint32_t tx_pause_frames;
 294         uint32_t tx_excess_defer;
 295         uint32_t tx_control_frames;
 296         uint32_t tx_deferred;
 297         uint32_t tx_bytes;
 298         uint32_t tx_pkts_64;
 299         uint32_t tx_pkts_65_127;
 300         uint32_t tx_pkts_128_255;
 301         uint32_t tx_pkts_256_511;
 302         uint32_t tx_pkts_512_1023;
 303         uint32_t tx_pkts_1024_1518;
 304         uint32_t tx_pkts_1519_max;
 305         uint32_t tx_single_colls;
 306         uint32_t tx_multi_colls;
 307         uint32_t tx_late_colls;
 308         uint32_t tx_excess_colls;
 309         uint32_t tx_abort;
 310         uint32_t tx_underrun;
 311         uint32_t tx_desc_underrun;
 312         uint32_t tx_lenerrs;
 313         uint32_t tx_pkts_truncated;
 314         uint32_t tx_bcast_bytes;
 315         uint32_t tx_mcast_bytes;
 316 } atge_l1e_smb_t;
 317 #pragma pack()
 318
 319 #ifdef __cplusplus
 320 }
 321 #endif
 322
 323 #endif  /* _ATGE_L1E_REG_H */