?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge remote-tracking branch 'origin/master'
[unleashed/lotheac.git] / usr / src / uts / common / io / cxgbe / firmware / t4fw_interface.h
blob01d9db43feac4963744a5f88864878d6f70e7f73
1 /*
2 * Chelsio Terminator 4 (T4) Firmware interface header file.
3 *
4 * Copyright (C) 2009-2014 Chelsio Communications. All rights reserved.
5 *
6 * Written by felix marti (felix@chelsio.com)
7 *
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
11 * release for licensing terms and conditions.
12 */
13
14 #ifndef _T4FW_INTERFACE_H_
15 #define _T4FW_INTERFACE_H_
16
17 /******************************************************************************
18 * R E T U R N V A L U E S
19 ********************************/
20
21 enum fw_retval {
22 FW_SUCCESS = 0, /* completed sucessfully */
23 FW_EPERM = 1, /* operation not permitted */
24 FW_ENOENT = 2, /* no such file or directory */
25 FW_EIO = 5, /* input/output error; hw bad */
26 FW_ENOEXEC = 8, /* exec format error; inv microcode */
27 FW_EAGAIN = 11, /* try again */
28 FW_ENOMEM = 12, /* out of memory */
29 FW_EFAULT = 14, /* bad address; fw bad */
30 FW_EBUSY = 16, /* resource busy */
31 FW_EEXIST = 17, /* file exists */
32 FW_ENODEV = 19, /* no such device */
33 FW_EINVAL = 22, /* invalid argument */
34 FW_ENOSPC = 28, /* no space left on device */
35 FW_ENOSYS = 38, /* functionality not implemented */
36 FW_ENODATA = 61, /* no data available */
37 FW_EPROTO = 71, /* protocol error */
38 FW_EADDRINUSE = 98, /* address already in use */
39 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
40 FW_ENETDOWN = 100, /* network is down */
41 FW_ENETUNREACH = 101, /* network is unreachable */
42 FW_ENOBUFS = 105, /* no buffer space available */
43 FW_ETIMEDOUT = 110, /* timeout */
44 FW_EINPROGRESS = 115, /* fw internal */
45 FW_SCSI_ABORT_REQUESTED = 128, /* */
46 FW_SCSI_ABORT_TIMEDOUT = 129, /* */
47 FW_SCSI_ABORTED = 130, /* */
48 FW_SCSI_CLOSE_REQUESTED = 131, /* */
49 FW_ERR_LINK_DOWN = 132, /* */
50 FW_RDEV_NOT_READY = 133, /* */
51 FW_ERR_RDEV_LOST = 134, /* */
52 FW_ERR_RDEV_LOGO = 135, /* */
53 FW_FCOE_NO_XCHG = 136, /* */
54 FW_SCSI_RSP_ERR = 137, /* */
55 FW_ERR_RDEV_IMPL_LOGO = 138, /* */
56 FW_SCSI_UNDER_FLOW_ERR = 139, /* */
57 FW_SCSI_OVER_FLOW_ERR = 140, /* */
58 FW_SCSI_DDP_ERR = 141, /* DDP error*/
59 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
60 };
61
62 /******************************************************************************
63 * M E M O R Y T Y P E s
64 ******************************/
65
66 enum fw_memtype {
67 FW_MEMTYPE_EDC0 = 0x0,
68 FW_MEMTYPE_EDC1 = 0x1,
69 FW_MEMTYPE_EXTMEM = 0x2,
70 FW_MEMTYPE_FLASH = 0x4,
71 FW_MEMTYPE_INTERNAL = 0x5,
72 FW_MEMTYPE_EXTMEM1 = 0x6,
73 };
74
75 /******************************************************************************
76 * W O R K R E Q U E S T s
77 ********************************/
78
79 enum fw_wr_opcodes {
80 FW_FRAG_WR = 0x1d,
81 FW_FILTER_WR = 0x02,
82 FW_ULPTX_WR = 0x04,
83 FW_TP_WR = 0x05,
84 FW_ETH_TX_PKT_WR = 0x08,
85 FW_ETH_TX_PKT2_WR = 0x44,
86 FW_ETH_TX_PKTS_WR = 0x09,
87 FW_ETH_TX_PKTS2_WR = 0x78,
88 FW_ETH_TX_EO_WR = 0x1c,
89 FW_EQ_FLUSH_WR = 0x1b,
90 FW_OFLD_CONNECTION_WR = 0x2f,
91 FW_FLOWC_WR = 0x0a,
92 FW_OFLD_TX_DATA_WR = 0x0b,
93 FW_CMD_WR = 0x10,
94 FW_ETH_TX_PKT_VM_WR = 0x11,
95 FW_RI_RES_WR = 0x0c,
96 FW_RI_RDMA_WRITE_WR = 0x14,
97 FW_RI_SEND_WR = 0x15,
98 FW_RI_RDMA_READ_WR = 0x16,
99 FW_RI_RECV_WR = 0x17,
100 FW_RI_BIND_MW_WR = 0x18,
101 FW_RI_FR_NSMR_WR = 0x19,
102 FW_RI_FR_NSMR_TPTE_WR = 0x20,
103 FW_RI_INV_LSTAG_WR = 0x1a,
104 FW_RI_SEND_IMMEDIATE_WR = 0x15,
105 FW_RI_ATOMIC_WR = 0x16,
106 FW_RI_WR = 0x0d,
107 FW_CHNET_IFCONF_WR = 0x6b,
108 FW_RDEV_WR = 0x38,
109 FW_FOISCSI_NODE_WR = 0x60,
110 FW_FOISCSI_CTRL_WR = 0x6a,
111 FW_FOISCSI_CHAP_WR = 0x6c,
112 FW_FCOE_ELS_CT_WR = 0x30,
113 FW_SCSI_WRITE_WR = 0x31,
114 FW_SCSI_READ_WR = 0x32,
115 FW_SCSI_CMD_WR = 0x33,
116 FW_SCSI_ABRT_CLS_WR = 0x34,
117 FW_SCSI_TGT_ACC_WR = 0x35,
118 FW_SCSI_TGT_XMIT_WR = 0x36,
119 FW_SCSI_TGT_RSP_WR = 0x37,
120 FW_POFCOE_TCB_WR = 0x42,
121 FW_POFCOE_ULPTX_WR = 0x43,
122 FW_ISCSI_TX_DATA_WR = 0x45,
123 FW_PTP_TX_PKT_WR = 0x46,
124 FW_TLSTX_DATA_WR = 0x68,
125 FW_TLS_KEYCTX_TX_WR = 0x69,
126 FW_CRYPTO_LOOKASIDE_WR = 0x6d,
127 FW_COiSCSI_TGT_WR = 0x70,
128 FW_COiSCSI_TGT_CONN_WR = 0x71,
129 FW_COiSCSI_TGT_XMIT_WR = 0x72,
130 FW_ISNS_WR = 0x75,
131 FW_ISNS_XMIT_WR = 0x76,
132 FW_FILTER2_WR = 0x77,
133 FW_LASTC2E_WR = 0x80
134 };
135
136 /*
137 * Generic work request header flit0
138 */
139 struct fw_wr_hdr {
140 __be32 hi;
141 __be32 lo;
142 };
143
144 /* work request opcode (hi)
145 */
146 #define S_FW_WR_OP 24
147 #define M_FW_WR_OP 0xff
148 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP)
149 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP)
150
151 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
152 */
153 #define S_FW_WR_ATOMIC 23
154 #define M_FW_WR_ATOMIC 0x1
155 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC)
156 #define G_FW_WR_ATOMIC(x) \
157 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
158 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U)
159
160 /* flush flag (hi) - firmware flushes flushable work request buffered
161 * in the flow context.
162 */
163 #define S_FW_WR_FLUSH 22
164 #define M_FW_WR_FLUSH 0x1
165 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH)
166 #define G_FW_WR_FLUSH(x) \
167 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
168 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U)
169
170 /* completion flag (hi) - firmware generates a cpl_fw6_ack
171 */
172 #define S_FW_WR_COMPL 21
173 #define M_FW_WR_COMPL 0x1
174 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL)
175 #define G_FW_WR_COMPL(x) \
176 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
177 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U)
178
179
180 /* work request immediate data lengh (hi)
181 */
182 #define S_FW_WR_IMMDLEN 0
183 #define M_FW_WR_IMMDLEN 0xff
184 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN)
185 #define G_FW_WR_IMMDLEN(x) \
186 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
187
188 /* egress queue status update to associated ingress queue entry (lo)
189 */
190 #define S_FW_WR_EQUIQ 31
191 #define M_FW_WR_EQUIQ 0x1
192 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ)
193 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
194 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U)
195
196 /* egress queue status update to egress queue status entry (lo)
197 */
198 #define S_FW_WR_EQUEQ 30
199 #define M_FW_WR_EQUEQ 0x1
200 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ)
201 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
202 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U)
203
204 /* flow context identifier (lo)
205 */
206 #define S_FW_WR_FLOWID 8
207 #define M_FW_WR_FLOWID 0xfffff
208 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID)
209 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
210
211 /* length in units of 16-bytes (lo)
212 */
213 #define S_FW_WR_LEN16 0
214 #define M_FW_WR_LEN16 0xff
215 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16)
216 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
217
218 struct fw_frag_wr {
219 __be32 op_to_fragoff16;
220 __be32 flowid_len16;
221 __be64 r4;
222 };
223
224 #define S_FW_FRAG_WR_EOF 15
225 #define M_FW_FRAG_WR_EOF 0x1
226 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF)
227 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
228 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U)
229
230 #define S_FW_FRAG_WR_FRAGOFF16 8
231 #define M_FW_FRAG_WR_FRAGOFF16 0x7f
232 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16)
233 #define G_FW_FRAG_WR_FRAGOFF16(x) \
234 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
235
236 /* valid filter configurations for compressed tuple
237 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
238 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
239 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
240 * OV - Outer VLAN/VNIC_ID,
241 */
242 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3
243 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3
244 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B
245 #define HW_TPL_FR_MT_M_OV_P_FC 0x387
246 #define HW_TPL_FR_MT_E_PR_T 0x370
247 #define HW_TPL_FR_MT_E_PR_P_FC 0X363
248 #define HW_TPL_FR_MT_E_T_P_FC 0X353
249 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
250 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
251 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B
252 #define HW_TPL_FR_MT_T_OV_P_FC 0X317
253 #define HW_TPL_FR_M_E_PR_FC 0X2E1
254 #define HW_TPL_FR_M_E_T_FC 0X2D1
255 #define HW_TPL_FR_M_PR_IV_FC 0X2A9
256 #define HW_TPL_FR_M_PR_OV_FC 0X2A5
257 #define HW_TPL_FR_M_T_IV_FC 0X299
258 #define HW_TPL_FR_M_T_OV_FC 0X295
259 #define HW_TPL_FR_E_PR_T_P 0X272
260 #define HW_TPL_FR_E_PR_T_FC 0X271
261 #define HW_TPL_FR_E_IV_FC 0X249
262 #define HW_TPL_FR_E_OV_FC 0X245
263 #define HW_TPL_FR_PR_T_IV_FC 0X239
264 #define HW_TPL_FR_PR_T_OV_FC 0X235
265 #define HW_TPL_FR_IV_OV_FC 0X20D
266 #define HW_TPL_MT_M_E_PR 0X1E0
267 #define HW_TPL_MT_M_E_T 0X1D0
268 #define HW_TPL_MT_E_PR_T_FC 0X171
269 #define HW_TPL_MT_E_IV 0X148
270 #define HW_TPL_MT_E_OV 0X144
271 #define HW_TPL_MT_PR_T_IV 0X138
272 #define HW_TPL_MT_PR_T_OV 0X134
273 #define HW_TPL_M_E_PR_P 0X0E2
274 #define HW_TPL_M_E_T_P 0X0D2
275 #define HW_TPL_E_PR_T_P_FC 0X073
276 #define HW_TPL_E_IV_P 0X04A
277 #define HW_TPL_E_OV_P 0X046
278 #define HW_TPL_PR_T_IV_P 0X03A
279 #define HW_TPL_PR_T_OV_P 0X036
280
281 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
282 enum fw_filter_wr_cookie {
283 FW_FILTER_WR_SUCCESS,
284 FW_FILTER_WR_FLT_ADDED,
285 FW_FILTER_WR_FLT_DELETED,
286 FW_FILTER_WR_SMT_TBL_FULL,
287 FW_FILTER_WR_EINVAL,
288 };
289
290 enum fw_filter_wr_nat_mode {
291 FW_FILTER_WR_NATMODE_NONE = 0,
292 FW_FILTER_WR_NATMODE_DIP ,
293 FW_FILTER_WR_NATMODE_DIPDP,
294 FW_FILTER_WR_NATMODE_DIPDPSIP,
295 FW_FILTER_WR_NATMODE_DIPDPSP,
296 FW_FILTER_WR_NATMODE_SIPSP,
297 FW_FILTER_WR_NATMODE_DIPSIPSP,
298 FW_FILTER_WR_NATMODE_FOURTUPLE,
299 };
300
301 struct fw_filter_wr {
302 __be32 op_pkd;
303 __be32 len16_pkd;
304 __be64 r3;
305 __be32 tid_to_iq;
306 __be32 del_filter_to_l2tix;
307 __be16 ethtype;
308 __be16 ethtypem;
309 __u8 frag_to_ovlan_vldm;
310 __u8 smac_sel;
311 __be16 rx_chan_rx_rpl_iq;
312 __be32 maci_to_matchtypem;
313 __u8 ptcl;
314 __u8 ptclm;
315 __u8 ttyp;
316 __u8 ttypm;
317 __be16 ivlan;
318 __be16 ivlanm;
319 __be16 ovlan;
320 __be16 ovlanm;
321 __u8 lip[16];
322 __u8 lipm[16];
323 __u8 fip[16];
324 __u8 fipm[16];
325 __be16 lp;
326 __be16 lpm;
327 __be16 fp;
328 __be16 fpm;
329 __be16 r7;
330 __u8 sma[6];
331 };
332
333 struct fw_filter2_wr {
334 __be32 op_pkd;
335 __be32 len16_pkd;
336 __be64 r3;
337 __be32 tid_to_iq;
338 __be32 del_filter_to_l2tix;
339 __be16 ethtype;
340 __be16 ethtypem;
341 __u8 frag_to_ovlan_vldm;
342 __u8 smac_sel;
343 __be16 rx_chan_rx_rpl_iq;
344 __be32 maci_to_matchtypem;
345 __u8 ptcl;
346 __u8 ptclm;
347 __u8 ttyp;
348 __u8 ttypm;
349 __be16 ivlan;
350 __be16 ivlanm;
351 __be16 ovlan;
352 __be16 ovlanm;
353 __u8 lip[16];
354 __u8 lipm[16];
355 __u8 fip[16];
356 __u8 fipm[16];
357 __be16 lp;
358 __be16 lpm;
359 __be16 fp;
360 __be16 fpm;
361 __be16 r7;
362 __u8 sma[6];
363 __u8 r8_hi[2];
364 __u8 filter_type_swapmac;
365 __u8 natmode_to_ulp_type;
366 __be16 newlport;
367 __be16 newfport;
368 __u8 newlip[16];
369 __u8 newfip[16];
370 __be32 natseqcheck;
371 __be32 dip_hit_vni;
372 __be64 r10;
373 __be64 r11;
374 __be64 r12;
375 __be64 r13;
376 };
377
378 #define S_FW_FILTER_WR_TID 12
379 #define M_FW_FILTER_WR_TID 0xfffff
380 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID)
381 #define G_FW_FILTER_WR_TID(x) \
382 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
383
384 #define S_FW_FILTER_WR_RQTYPE 11
385 #define M_FW_FILTER_WR_RQTYPE 0x1
386 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE)
387 #define G_FW_FILTER_WR_RQTYPE(x) \
388 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
389 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U)
390
391 #define S_FW_FILTER_WR_NOREPLY 10
392 #define M_FW_FILTER_WR_NOREPLY 0x1
393 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY)
394 #define G_FW_FILTER_WR_NOREPLY(x) \
395 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
396 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U)
397
398 #define S_FW_FILTER_WR_IQ 0
399 #define M_FW_FILTER_WR_IQ 0x3ff
400 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ)
401 #define G_FW_FILTER_WR_IQ(x) \
402 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
403
404 #define S_FW_FILTER_WR_DEL_FILTER 31
405 #define M_FW_FILTER_WR_DEL_FILTER 0x1
406 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER)
407 #define G_FW_FILTER_WR_DEL_FILTER(x) \
408 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
409 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U)
410
411 #define S_FW_FILTER_WR_RPTTID 25
412 #define M_FW_FILTER_WR_RPTTID 0x1
413 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID)
414 #define G_FW_FILTER_WR_RPTTID(x) \
415 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
416 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U)
417
418 #define S_FW_FILTER_WR_DROP 24
419 #define M_FW_FILTER_WR_DROP 0x1
420 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP)
421 #define G_FW_FILTER_WR_DROP(x) \
422 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
423 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U)
424
425 #define S_FW_FILTER_WR_DIRSTEER 23
426 #define M_FW_FILTER_WR_DIRSTEER 0x1
427 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER)
428 #define G_FW_FILTER_WR_DIRSTEER(x) \
429 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
430 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U)
431
432 #define S_FW_FILTER_WR_MASKHASH 22
433 #define M_FW_FILTER_WR_MASKHASH 0x1
434 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH)
435 #define G_FW_FILTER_WR_MASKHASH(x) \
436 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
437 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U)
438
439 #define S_FW_FILTER_WR_DIRSTEERHASH 21
440 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1
441 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH)
442 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \
443 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
444 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U)
445
446 #define S_FW_FILTER_WR_LPBK 20
447 #define M_FW_FILTER_WR_LPBK 0x1
448 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK)
449 #define G_FW_FILTER_WR_LPBK(x) \
450 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
451 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U)
452
453 #define S_FW_FILTER_WR_DMAC 19
454 #define M_FW_FILTER_WR_DMAC 0x1
455 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC)
456 #define G_FW_FILTER_WR_DMAC(x) \
457 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
458 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U)
459
460 #define S_FW_FILTER_WR_SMAC 18
461 #define M_FW_FILTER_WR_SMAC 0x1
462 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC)
463 #define G_FW_FILTER_WR_SMAC(x) \
464 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
465 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U)
466
467 #define S_FW_FILTER_WR_INSVLAN 17
468 #define M_FW_FILTER_WR_INSVLAN 0x1
469 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN)
470 #define G_FW_FILTER_WR_INSVLAN(x) \
471 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
472 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U)
473
474 #define S_FW_FILTER_WR_RMVLAN 16
475 #define M_FW_FILTER_WR_RMVLAN 0x1
476 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN)
477 #define G_FW_FILTER_WR_RMVLAN(x) \
478 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
479 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U)
480
481 #define S_FW_FILTER_WR_HITCNTS 15
482 #define M_FW_FILTER_WR_HITCNTS 0x1
483 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS)
484 #define G_FW_FILTER_WR_HITCNTS(x) \
485 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
486 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U)
487
488 #define S_FW_FILTER_WR_TXCHAN 13
489 #define M_FW_FILTER_WR_TXCHAN 0x3
490 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN)
491 #define G_FW_FILTER_WR_TXCHAN(x) \
492 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
493
494 #define S_FW_FILTER_WR_PRIO 12
495 #define M_FW_FILTER_WR_PRIO 0x1
496 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO)
497 #define G_FW_FILTER_WR_PRIO(x) \
498 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
499 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U)
500
501 #define S_FW_FILTER_WR_L2TIX 0
502 #define M_FW_FILTER_WR_L2TIX 0xfff
503 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX)
504 #define G_FW_FILTER_WR_L2TIX(x) \
505 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
506
507 #define S_FW_FILTER_WR_FRAG 7
508 #define M_FW_FILTER_WR_FRAG 0x1
509 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG)
510 #define G_FW_FILTER_WR_FRAG(x) \
511 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
512 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U)
513
514 #define S_FW_FILTER_WR_FRAGM 6
515 #define M_FW_FILTER_WR_FRAGM 0x1
516 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM)
517 #define G_FW_FILTER_WR_FRAGM(x) \
518 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
519 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U)
520
521 #define S_FW_FILTER_WR_IVLAN_VLD 5
522 #define M_FW_FILTER_WR_IVLAN_VLD 0x1
523 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD)
524 #define G_FW_FILTER_WR_IVLAN_VLD(x) \
525 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
526 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U)
527
528 #define S_FW_FILTER_WR_OVLAN_VLD 4
529 #define M_FW_FILTER_WR_OVLAN_VLD 0x1
530 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD)
531 #define G_FW_FILTER_WR_OVLAN_VLD(x) \
532 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
533 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U)
534
535 #define S_FW_FILTER_WR_IVLAN_VLDM 3
536 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1
537 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM)
538 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \
539 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
540 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U)
541
542 #define S_FW_FILTER_WR_OVLAN_VLDM 2
543 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1
544 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM)
545 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \
546 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
547 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U)
548
549 #define S_FW_FILTER_WR_RX_CHAN 15
550 #define M_FW_FILTER_WR_RX_CHAN 0x1
551 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN)
552 #define G_FW_FILTER_WR_RX_CHAN(x) \
553 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
554 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U)
555
556 #define S_FW_FILTER_WR_RX_RPL_IQ 0
557 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff
558 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ)
559 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \
560 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
561
562 #define S_FW_FILTER2_WR_FILTER_TYPE 1
563 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1
564 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE)
565 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \
566 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE)
567 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U)
568
569 #define S_FW_FILTER2_WR_SWAPMAC 0
570 #define M_FW_FILTER2_WR_SWAPMAC 0x1
571 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC)
572 #define G_FW_FILTER2_WR_SWAPMAC(x) \
573 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC)
574 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U)
575
576 #define S_FW_FILTER2_WR_NATMODE 5
577 #define M_FW_FILTER2_WR_NATMODE 0x7
578 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE)
579 #define G_FW_FILTER2_WR_NATMODE(x) \
580 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE)
581
582 #define S_FW_FILTER2_WR_NATFLAGCHECK 4
583 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1
584 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK)
585 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \
586 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK)
587 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U)
588
589 #define S_FW_FILTER2_WR_ULP_TYPE 0
590 #define M_FW_FILTER2_WR_ULP_TYPE 0xf
591 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE)
592 #define G_FW_FILTER2_WR_ULP_TYPE(x) \
593 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)
594
595 #define S_FW_FILTER2_WR_DIP_HIT 24
596 #define M_FW_FILTER2_WR_DIP_HIT 0x1
597 #define V_FW_FILTER2_WR_DIP_HIT(x) ((x) << S_FW_FILTER2_WR_DIP_HIT)
598 #define G_FW_FILTER2_WR_DIP_HIT(x) \
599 (((x) >> S_FW_FILTER2_WR_DIP_HIT) & M_FW_FILTER2_WR_DIP_HIT)
600 #define F_FW_FILTER2_WR_DIP_HIT V_FW_FILTER2_WR_DIP_HIT(1U)
601
602 #define S_FW_FILTER2_WR_VNI 0
603 #define M_FW_FILTER2_WR_VNI 0xffffff
604 #define V_FW_FILTER2_WR_VNI(x) ((x) << S_FW_FILTER2_WR_VNI)
605 #define G_FW_FILTER2_WR_VNI(x) \
606 (((x) >> S_FW_FILTER2_WR_VNI) & M_FW_FILTER2_WR_VNI)
607
608 #define S_FW_FILTER_WR_MACI 23
609 #define M_FW_FILTER_WR_MACI 0x1ff
610 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI)
611 #define G_FW_FILTER_WR_MACI(x) \
612 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
613
614 #define S_FW_FILTER_WR_MACIM 14
615 #define M_FW_FILTER_WR_MACIM 0x1ff
616 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM)
617 #define G_FW_FILTER_WR_MACIM(x) \
618 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
619
620 #define S_FW_FILTER_WR_FCOE 13
621 #define M_FW_FILTER_WR_FCOE 0x1
622 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE)
623 #define G_FW_FILTER_WR_FCOE(x) \
624 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
625 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U)
626
627 #define S_FW_FILTER_WR_FCOEM 12
628 #define M_FW_FILTER_WR_FCOEM 0x1
629 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM)
630 #define G_FW_FILTER_WR_FCOEM(x) \
631 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
632 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U)
633
634 #define S_FW_FILTER_WR_PORT 9
635 #define M_FW_FILTER_WR_PORT 0x7
636 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT)
637 #define G_FW_FILTER_WR_PORT(x) \
638 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
639
640 #define S_FW_FILTER_WR_PORTM 6
641 #define M_FW_FILTER_WR_PORTM 0x7
642 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM)
643 #define G_FW_FILTER_WR_PORTM(x) \
644 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
645
646 #define S_FW_FILTER_WR_MATCHTYPE 3
647 #define M_FW_FILTER_WR_MATCHTYPE 0x7
648 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE)
649 #define G_FW_FILTER_WR_MATCHTYPE(x) \
650 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
651
652 #define S_FW_FILTER_WR_MATCHTYPEM 0
653 #define M_FW_FILTER_WR_MATCHTYPEM 0x7
654 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM)
655 #define G_FW_FILTER_WR_MATCHTYPEM(x) \
656 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
657
658 struct fw_ulptx_wr {
659 __be32 op_to_compl;
660 __be32 flowid_len16;
661 __u64 cookie;
662 };
663
664 struct fw_tp_wr {
665 __be32 op_to_immdlen;
666 __be32 flowid_len16;
667 __u64 cookie;
668 };
669
670 struct fw_eth_tx_pkt_wr {
671 __be32 op_immdlen;
672 __be32 equiq_to_len16;
673 __be64 r3;
674 };
675
676 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0
677 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff
678 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
679 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \
680 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
681
682 struct fw_eth_tx_pkt2_wr {
683 __be32 op_immdlen;
684 __be32 equiq_to_len16;
685 __be32 r3;
686 __be32 L4ChkDisable_to_IpHdrLen;
687 };
688
689 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0
690 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff
691 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
692 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \
693 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
694
695 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31
696 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1
697 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
698 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
699 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \
700 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
701 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
702 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \
703 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
704
705 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30
706 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1
707 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
708 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
709 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \
710 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
711 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
712 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \
713 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
714
715 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28
716 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1
717 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
718 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \
719 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
720 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
721
722 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12
723 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff
724 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
725 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \
726 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
727
728 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8
729 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf
730 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
731 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \
732 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
733
734 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0
735 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff
736 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
737 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \
738 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
739
740 struct fw_eth_tx_pkts_wr {
741 __be32 op_pkd;
742 __be32 equiq_to_len16;
743 __be32 r3;
744 __be16 plen;
745 __u8 npkt;
746 __u8 type;
747 };
748
749 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0
750 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff
751 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN)
752 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \
753 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN)
754
755 struct fw_eth_tx_pkt_ptp_wr {
756 __be32 op_immdlen;
757 __be32 equiq_to_len16;
758 __be64 r3;
759 };
760
761 enum fw_eth_tx_eo_type {
762 FW_ETH_TX_EO_TYPE_UDPSEG,
763 FW_ETH_TX_EO_TYPE_TCPSEG,
764 FW_ETH_TX_EO_TYPE_NVGRESEG,
765 FW_ETH_TX_EO_TYPE_VXLANSEG,
766 FW_ETH_TX_EO_TYPE_GENEVESEG,
767 };
768
769 struct fw_eth_tx_eo_wr {
770 __be32 op_immdlen;
771 __be32 equiq_to_len16;
772 __be64 r3;
773 union fw_eth_tx_eo {
774 struct fw_eth_tx_eo_udpseg {
775 __u8 type;
776 __u8 ethlen;
777 __be16 iplen;
778 __u8 udplen;
779 __u8 rtplen;
780 __be16 r4;
781 __be16 mss;
782 __be16 schedpktsize;
783 __be32 plen;
784 } udpseg;
785 struct fw_eth_tx_eo_tcpseg {
786 __u8 type;
787 __u8 ethlen;
788 __be16 iplen;
789 __u8 tcplen;
790 __u8 tsclk_tsoff;
791 __be16 r4;
792 __be16 mss;
793 __be16 r5;
794 __be32 plen;
795 } tcpseg;
796 struct fw_eth_tx_eo_nvgreseg {
797 __u8 type;
798 __u8 iphdroffout;
799 __be16 grehdroff;
800 __be16 iphdroffin;
801 __be16 tcphdroffin;
802 __be16 mss;
803 __be16 r4;
804 __be32 plen;
805 } nvgreseg;
806 struct fw_eth_tx_eo_vxlanseg {
807 __u8 type;
808 __u8 iphdroffout;
809 __be16 vxlanhdroff;
810 __be16 iphdroffin;
811 __be16 tcphdroffin;
812 __be16 mss;
813 __be16 r4;
814 __be32 plen;
815
816 } vxlanseg;
817 struct fw_eth_tx_eo_geneveseg {
818 __u8 type;
819 __u8 iphdroffout;
820 __be16 genevehdroff;
821 __be16 iphdroffin;
822 __be16 tcphdroffin;
823 __be16 mss;
824 __be16 r4;
825 __be32 plen;
826 } geneveseg;
827 } u;
828 };
829
830 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0
831 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff
832 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)
833 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \
834 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)
835
836 #define S_FW_ETH_TX_EO_WR_TSCLK 6
837 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3
838 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK)
839 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \
840 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)
841
842 #define S_FW_ETH_TX_EO_WR_TSOFF 0
843 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f
844 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF)
845 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \
846 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)
847
848 struct fw_eq_flush_wr {
849 __u8 opcode;
850 __u8 r1[3];
851 __be32 equiq_to_len16;
852 __be64 r3;
853 };
854
855 struct fw_ofld_connection_wr {
856 __be32 op_compl;
857 __be32 len16_pkd;
858 __u64 cookie;
859 __be64 r2;
860 __be64 r3;
861 struct fw_ofld_connection_le {
862 __be32 version_cpl;
863 __be32 filter;
864 __be32 r1;
865 __be16 lport;
866 __be16 pport;
867 union fw_ofld_connection_leip {
868 struct fw_ofld_connection_le_ipv4 {
869 __be32 pip;
870 __be32 lip;
871 __be64 r0;
872 __be64 r1;
873 __be64 r2;
874 } ipv4;
875 struct fw_ofld_connection_le_ipv6 {
876 __be64 pip_hi;
877 __be64 pip_lo;
878 __be64 lip_hi;
879 __be64 lip_lo;
880 } ipv6;
881 } u;
882 } le;
883 struct fw_ofld_connection_tcb {
884 __be32 t_state_to_astid;
885 __be16 cplrxdataack_cplpassacceptrpl;
886 __be16 rcv_adv;
887 __be32 rcv_nxt;
888 __be32 tx_max;
889 __be64 opt0;
890 __be32 opt2;
891 __be32 r1;
892 __be64 r2;
893 __be64 r3;
894 } tcb;
895 };
896
897 #define S_FW_OFLD_CONNECTION_WR_VERSION 31
898 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1
899 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \
900 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
901 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \
902 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
903 M_FW_OFLD_CONNECTION_WR_VERSION)
904 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U)
905
906 #define S_FW_OFLD_CONNECTION_WR_CPL 30
907 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1
908 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL)
909 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \
910 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
911 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U)
912
913 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28
914 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf
915 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \
916 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
917 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \
918 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
919 M_FW_OFLD_CONNECTION_WR_T_STATE)
920
921 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24
922 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf
923 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
924 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
925 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \
926 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
927 M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
928
929 #define S_FW_OFLD_CONNECTION_WR_ASTID 0
930 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff
931 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \
932 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
933 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \
934 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
935
936 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15
937 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1
938 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
939 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
940 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \
941 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
942 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
943 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \
944 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
945
946 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14
947 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1
948 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
949 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
950 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \
951 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
952 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
953 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \
954 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
955
956 enum fw_flowc_mnem_tcpstate {
957 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */
958 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */
959 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */
960 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
961 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
962 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
963 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and
964 * will resend FIN - equiv ESTAB
965 */
966 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and
967 * will resend FIN but have
968 * received FIN
969 */
970 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and
971 * will resend FIN but have
972 * received FIN
973 */
974 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK,
975 * waiting for FIN
976 */
977 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
978 };
979
980 enum fw_flowc_mnem_eostate {
981 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */
982 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
983 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending
984 * outstanding payload
985 */
986 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after
987 * discarding outstanding payload
988 */
989 };
990
991 enum fw_flowc_mnem {
992 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */
993 FW_FLOWC_MNEM_CH = 1,
994 FW_FLOWC_MNEM_PORT = 2,
995 FW_FLOWC_MNEM_IQID = 3,
996 FW_FLOWC_MNEM_SNDNXT = 4,
997 FW_FLOWC_MNEM_RCVNXT = 5,
998 FW_FLOWC_MNEM_SNDBUF = 6,
999 FW_FLOWC_MNEM_MSS = 7,
1000 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8,
1001 FW_FLOWC_MNEM_TCPSTATE = 9,
1002 FW_FLOWC_MNEM_EOSTATE = 10,
1003 FW_FLOWC_MNEM_SCHEDCLASS = 11,
1004 FW_FLOWC_MNEM_DCBPRIO = 12,
1005 FW_FLOWC_MNEM_SND_SCALE = 13,
1006 FW_FLOWC_MNEM_RCV_SCALE = 14,
1007 FW_FLOWC_MNEM_ULP_MODE = 15,
1008 FW_FLOWC_MNEM_MAX = 16,
1009 };
1010
1011 struct fw_flowc_mnemval {
1012 __u8 mnemonic;
1013 __u8 r4[3];
1014 __be32 val;
1015 };
1016
1017 struct fw_flowc_wr {
1018 __be32 op_to_nparams;
1019 __be32 flowid_len16;
1020 #ifndef C99_NOT_SUPPORTED
1021 struct fw_flowc_mnemval mnemval[0];
1022 #endif
1023 };
1024
1025 #define S_FW_FLOWC_WR_NPARAMS 0
1026 #define M_FW_FLOWC_WR_NPARAMS 0xff
1027 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS)
1028 #define G_FW_FLOWC_WR_NPARAMS(x) \
1029 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
1030
1031 struct fw_ofld_tx_data_wr {
1032 __be32 op_to_immdlen;
1033 __be32 flowid_len16;
1034 __be32 plen;
1035 __be32 lsodisable_to_flags;
1036 };
1037
1038 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31
1039 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1
1040 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
1041 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
1042 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \
1043 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
1044 M_FW_OFLD_TX_DATA_WR_LSODISABLE)
1045 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
1046
1047 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30
1048 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1
1049 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
1050 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1051 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \
1052 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1053 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
1054
1055 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29
1056 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1
1057 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
1058 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1059 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \
1060 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
1061 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1062 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \
1063 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
1064
1065 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0
1066 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff
1067 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS)
1068 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \
1069 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS)
1070
1071
1072 /* Use fw_ofld_tx_data_wr structure */
1073 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10
1074 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff
1075 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \
1076 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1077 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \
1078 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1079
1080 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9
1081 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1
1082 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \
1083 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1084 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \
1085 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \
1086 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1087 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \
1088 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U)
1089
1090 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8
1091 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1
1092 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \
1093 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1094 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \
1095 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \
1096 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1097 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \
1098 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U)
1099
1100 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7
1101 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1
1102 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \
1103 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1104 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \
1105 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \
1106 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1107 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \
1108 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U)
1109
1110 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6
1111 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1
1112 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \
1113 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1114 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \
1115 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \
1116 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1117 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \
1118 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U)
1119
1120 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0
1121 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f
1122 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \
1123 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1124 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \
1125 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1126
1127 struct fw_cmd_wr {
1128 __be32 op_dma;
1129 __be32 len16_pkd;
1130 __be64 cookie_daddr;
1131 };
1132
1133 #define S_FW_CMD_WR_DMA 17
1134 #define M_FW_CMD_WR_DMA 0x1
1135 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA)
1136 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
1137 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U)
1138
1139 struct fw_eth_tx_pkt_vm_wr {
1140 __be32 op_immdlen;
1141 __be32 equiq_to_len16;
1142 __be32 r3[2];
1143 __u8 ethmacdst[6];
1144 __u8 ethmacsrc[6];
1145 __be16 ethtype;
1146 __be16 vlantci;
1147 };
1148
1149 /******************************************************************************
1150 * R I W O R K R E Q U E S T s
1151 **************************************/
1152
1153 enum fw_ri_wr_opcode {
1154 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */
1155 FW_RI_READ_REQ = 0x1,
1156 FW_RI_READ_RESP = 0x2,
1157 FW_RI_SEND = 0x3,
1158 FW_RI_SEND_WITH_INV = 0x4,
1159 FW_RI_SEND_WITH_SE = 0x5,
1160 FW_RI_SEND_WITH_SE_INV = 0x6,
1161 FW_RI_TERMINATE = 0x7,
1162 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */
1163 FW_RI_BIND_MW = 0x9,
1164 FW_RI_FAST_REGISTER = 0xa,
1165 FW_RI_LOCAL_INV = 0xb,
1166 FW_RI_QP_MODIFY = 0xc,
1167 FW_RI_BYPASS = 0xd,
1168 FW_RI_RECEIVE = 0xe,
1169 #if 0
1170 FW_RI_SEND_IMMEDIATE = 0x8,
1171 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9,
1172 FW_RI_ATOMIC_REQUEST = 0xa,
1173 FW_RI_ATOMIC_RESPONSE = 0xb,
1174
1175 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */
1176 FW_RI_FAST_REGISTER = 0xd,
1177 FW_RI_LOCAL_INV = 0xe,
1178 #endif
1179 FW_RI_SGE_EC_CR_RETURN = 0xf
1180 };
1181
1182 enum fw_ri_wr_flags {
1183 FW_RI_COMPLETION_FLAG = 0x01,
1184 FW_RI_NOTIFICATION_FLAG = 0x02,
1185 FW_RI_SOLICITED_EVENT_FLAG = 0x04,
1186 FW_RI_READ_FENCE_FLAG = 0x08,
1187 FW_RI_LOCAL_FENCE_FLAG = 0x10,
1188 FW_RI_RDMA_READ_INVALIDATE = 0x20
1189 };
1190
1191 enum fw_ri_mpa_attrs {
1192 FW_RI_MPA_RX_MARKER_ENABLE = 0x01,
1193 FW_RI_MPA_TX_MARKER_ENABLE = 0x02,
1194 FW_RI_MPA_CRC_ENABLE = 0x04,
1195 FW_RI_MPA_IETF_ENABLE = 0x08
1196 };
1197
1198 enum fw_ri_qp_caps {
1199 FW_RI_QP_RDMA_READ_ENABLE = 0x01,
1200 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02,
1201 FW_RI_QP_BIND_ENABLE = 0x04,
1202 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08,
1203 FW_RI_QP_STAG0_ENABLE = 0x10,
1204 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80,
1205 };
1206
1207 enum fw_ri_addr_type {
1208 FW_RI_ZERO_BASED_TO = 0x00,
1209 FW_RI_VA_BASED_TO = 0x01
1210 };
1211
1212 enum fw_ri_mem_perms {
1213 FW_RI_MEM_ACCESS_REM_WRITE = 0x01,
1214 FW_RI_MEM_ACCESS_REM_READ = 0x02,
1215 FW_RI_MEM_ACCESS_REM = 0x03,
1216 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04,
1217 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08,
1218 FW_RI_MEM_ACCESS_LOCAL = 0x0C
1219 };
1220
1221 enum fw_ri_stag_type {
1222 FW_RI_STAG_NSMR = 0x00,
1223 FW_RI_STAG_SMR = 0x01,
1224 FW_RI_STAG_MW = 0x02,
1225 FW_RI_STAG_MW_RELAXED = 0x03
1226 };
1227
1228 enum fw_ri_data_op {
1229 FW_RI_DATA_IMMD = 0x81,
1230 FW_RI_DATA_DSGL = 0x82,
1231 FW_RI_DATA_ISGL = 0x83
1232 };
1233
1234 enum fw_ri_sgl_depth {
1235 FW_RI_SGL_DEPTH_MAX_SQ = 16,
1236 FW_RI_SGL_DEPTH_MAX_RQ = 4
1237 };
1238
1239 enum fw_ri_cqe_err {
1240 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */
1241 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */
1242 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */
1243 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */
1244 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */
1245 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */
1246 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */
1247 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */
1248 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */
1249 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */
1250 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */
1251 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */
1252 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */
1253 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */
1254 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */
1255 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */
1256 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */
1257 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */
1258 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */
1259 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */
1260 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */
1261 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */
1262 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */
1263 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */
1264 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */
1265 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */
1266 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */
1267 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */
1268
1269 };
1270
1271 struct fw_ri_dsge_pair {
1272 __be32 len[2];
1273 __be64 addr[2];
1274 };
1275
1276 struct fw_ri_dsgl {
1277 __u8 op;
1278 __u8 r1;
1279 __be16 nsge;
1280 __be32 len0;
1281 __be64 addr0;
1282 #ifndef C99_NOT_SUPPORTED
1283 struct fw_ri_dsge_pair sge[0];
1284 #endif
1285 };
1286
1287 struct fw_ri_sge {
1288 __be32 stag;
1289 __be32 len;
1290 __be64 to;
1291 };
1292
1293 struct fw_ri_isgl {
1294 __u8 op;
1295 __u8 r1;
1296 __be16 nsge;
1297 __be32 r2;
1298 #ifndef C99_NOT_SUPPORTED
1299 struct fw_ri_sge sge[0];
1300 #endif
1301 };
1302
1303 struct fw_ri_immd {
1304 __u8 op;
1305 __u8 r1;
1306 __be16 r2;
1307 __be32 immdlen;
1308 #ifndef C99_NOT_SUPPORTED
1309 __u8 data[0];
1310 #endif
1311 };
1312
1313 struct fw_ri_tpte {
1314 __be32 valid_to_pdid;
1315 __be32 locread_to_qpid;
1316 __be32 nosnoop_pbladdr;
1317 __be32 len_lo;
1318 __be32 va_hi;
1319 __be32 va_lo_fbo;
1320 __be32 dca_mwbcnt_pstag;
1321 __be32 len_hi;
1322 };
1323
1324 #define S_FW_RI_TPTE_VALID 31
1325 #define M_FW_RI_TPTE_VALID 0x1
1326 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID)
1327 #define G_FW_RI_TPTE_VALID(x) \
1328 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1329 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U)
1330
1331 #define S_FW_RI_TPTE_STAGKEY 23
1332 #define M_FW_RI_TPTE_STAGKEY 0xff
1333 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY)
1334 #define G_FW_RI_TPTE_STAGKEY(x) \
1335 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1336
1337 #define S_FW_RI_TPTE_STAGSTATE 22
1338 #define M_FW_RI_TPTE_STAGSTATE 0x1
1339 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE)
1340 #define G_FW_RI_TPTE_STAGSTATE(x) \
1341 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1342 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U)
1343
1344 #define S_FW_RI_TPTE_STAGTYPE 20
1345 #define M_FW_RI_TPTE_STAGTYPE 0x3
1346 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE)
1347 #define G_FW_RI_TPTE_STAGTYPE(x) \
1348 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1349
1350 #define S_FW_RI_TPTE_PDID 0
1351 #define M_FW_RI_TPTE_PDID 0xfffff
1352 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID)
1353 #define G_FW_RI_TPTE_PDID(x) \
1354 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1355
1356 #define S_FW_RI_TPTE_PERM 28
1357 #define M_FW_RI_TPTE_PERM 0xf
1358 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM)
1359 #define G_FW_RI_TPTE_PERM(x) \
1360 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1361
1362 #define S_FW_RI_TPTE_REMINVDIS 27
1363 #define M_FW_RI_TPTE_REMINVDIS 0x1
1364 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS)
1365 #define G_FW_RI_TPTE_REMINVDIS(x) \
1366 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1367 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U)
1368
1369 #define S_FW_RI_TPTE_ADDRTYPE 26
1370 #define M_FW_RI_TPTE_ADDRTYPE 1
1371 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE)
1372 #define G_FW_RI_TPTE_ADDRTYPE(x) \
1373 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1374 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U)
1375
1376 #define S_FW_RI_TPTE_MWBINDEN 25
1377 #define M_FW_RI_TPTE_MWBINDEN 0x1
1378 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN)
1379 #define G_FW_RI_TPTE_MWBINDEN(x) \
1380 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1381 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U)
1382
1383 #define S_FW_RI_TPTE_PS 20
1384 #define M_FW_RI_TPTE_PS 0x1f
1385 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS)
1386 #define G_FW_RI_TPTE_PS(x) \
1387 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1388
1389 #define S_FW_RI_TPTE_QPID 0
1390 #define M_FW_RI_TPTE_QPID 0xfffff
1391 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID)
1392 #define G_FW_RI_TPTE_QPID(x) \
1393 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1394
1395 #define S_FW_RI_TPTE_NOSNOOP 31
1396 #define M_FW_RI_TPTE_NOSNOOP 0x1
1397 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP)
1398 #define G_FW_RI_TPTE_NOSNOOP(x) \
1399 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1400 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U)
1401
1402 #define S_FW_RI_TPTE_PBLADDR 0
1403 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff
1404 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR)
1405 #define G_FW_RI_TPTE_PBLADDR(x) \
1406 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1407
1408 #define S_FW_RI_TPTE_DCA 24
1409 #define M_FW_RI_TPTE_DCA 0x1f
1410 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA)
1411 #define G_FW_RI_TPTE_DCA(x) \
1412 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1413
1414 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0
1415 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff
1416 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \
1417 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1418 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \
1419 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1420
1421 enum fw_ri_cqe_rxtx {
1422 FW_RI_CQE_RXTX_RX = 0x0,
1423 FW_RI_CQE_RXTX_TX = 0x1,
1424 };
1425
1426 struct fw_ri_cqe {
1427 union fw_ri_rxtx {
1428 struct fw_ri_scqe {
1429 __be32 qpid_n_stat_rxtx_type;
1430 __be32 plen;
1431 __be32 stag;
1432 __be32 wrid;
1433 } scqe;
1434 struct fw_ri_rcqe {
1435 __be32 qpid_n_stat_rxtx_type;
1436 __be32 plen;
1437 __be32 stag;
1438 __be32 msn;
1439 } rcqe;
1440 } u;
1441 };
1442
1443 #define S_FW_RI_CQE_QPID 12
1444 #define M_FW_RI_CQE_QPID 0xfffff
1445 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID)
1446 #define G_FW_RI_CQE_QPID(x) \
1447 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID)
1448
1449 #define S_FW_RI_CQE_NOTIFY 10
1450 #define M_FW_RI_CQE_NOTIFY 0x1
1451 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1452 #define G_FW_RI_CQE_NOTIFY(x) \
1453 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY)
1454
1455 #define S_FW_RI_CQE_STATUS 5
1456 #define M_FW_RI_CQE_STATUS 0x1f
1457 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1458 #define G_FW_RI_CQE_STATUS(x) \
1459 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS)
1460
1461
1462 #define S_FW_RI_CQE_RXTX 4
1463 #define M_FW_RI_CQE_RXTX 0x1
1464 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX)
1465 #define G_FW_RI_CQE_RXTX(x) \
1466 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX)
1467
1468 #define S_FW_RI_CQE_TYPE 0
1469 #define M_FW_RI_CQE_TYPE 0xf
1470 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE)
1471 #define G_FW_RI_CQE_TYPE(x) \
1472 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE)
1473
1474 enum fw_ri_res_type {
1475 FW_RI_RES_TYPE_SQ,
1476 FW_RI_RES_TYPE_RQ,
1477 FW_RI_RES_TYPE_CQ,
1478 FW_RI_RES_TYPE_SRQ,
1479 };
1480
1481 enum fw_ri_res_op {
1482 FW_RI_RES_OP_WRITE,
1483 FW_RI_RES_OP_RESET,
1484 };
1485
1486 struct fw_ri_res {
1487 union fw_ri_restype {
1488 struct fw_ri_res_sqrq {
1489 __u8 restype;
1490 __u8 op;
1491 __be16 r3;
1492 __be32 eqid;
1493 __be32 r4[2];
1494 __be32 fetchszm_to_iqid;
1495 __be32 dcaen_to_eqsize;
1496 __be64 eqaddr;
1497 } sqrq;
1498 struct fw_ri_res_cq {
1499 __u8 restype;
1500 __u8 op;
1501 __be16 r3;
1502 __be32 iqid;
1503 __be32 r4[2];
1504 __be32 iqandst_to_iqandstindex;
1505 __be16 iqdroprss_to_iqesize;
1506 __be16 iqsize;
1507 __be64 iqaddr;
1508 __be32 iqns_iqro;
1509 __be32 r6_lo;
1510 __be64 r7;
1511 } cq;
1512 struct fw_ri_res_srq {
1513 __u8 restype;
1514 __u8 op;
1515 __be16 r3;
1516 __be32 eqid;
1517 __be32 r4[2];
1518 __be32 fetchszm_to_iqid;
1519 __be32 dcaen_to_eqsize;
1520 __be64 eqaddr;
1521 __be32 srqid;
1522 __be32 pdid;
1523 __be32 hwsrqsize;
1524 __be32 hwsrqaddr;
1525 } srq;
1526 } u;
1527 };
1528
1529 struct fw_ri_res_wr {
1530 __be32 op_nres;
1531 __be32 len16_pkd;
1532 __u64 cookie;
1533 #ifndef C99_NOT_SUPPORTED
1534 struct fw_ri_res res[0];
1535 #endif
1536 };
1537
1538 #define S_FW_RI_RES_WR_VFN 8
1539 #define M_FW_RI_RES_WR_VFN 0xff
1540 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN)
1541 #define G_FW_RI_RES_WR_VFN(x) \
1542 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN)
1543
1544 #define S_FW_RI_RES_WR_NRES 0
1545 #define M_FW_RI_RES_WR_NRES 0xff
1546 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES)
1547 #define G_FW_RI_RES_WR_NRES(x) \
1548 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1549
1550 #define S_FW_RI_RES_WR_FETCHSZM 26
1551 #define M_FW_RI_RES_WR_FETCHSZM 0x1
1552 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM)
1553 #define G_FW_RI_RES_WR_FETCHSZM(x) \
1554 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1555 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U)
1556
1557 #define S_FW_RI_RES_WR_STATUSPGNS 25
1558 #define M_FW_RI_RES_WR_STATUSPGNS 0x1
1559 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS)
1560 #define G_FW_RI_RES_WR_STATUSPGNS(x) \
1561 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1562 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U)
1563
1564 #define S_FW_RI_RES_WR_STATUSPGRO 24
1565 #define M_FW_RI_RES_WR_STATUSPGRO 0x1
1566 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO)
1567 #define G_FW_RI_RES_WR_STATUSPGRO(x) \
1568 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1569 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U)
1570
1571 #define S_FW_RI_RES_WR_FETCHNS 23
1572 #define M_FW_RI_RES_WR_FETCHNS 0x1
1573 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS)
1574 #define G_FW_RI_RES_WR_FETCHNS(x) \
1575 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
1576 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U)
1577
1578 #define S_FW_RI_RES_WR_FETCHRO 22
1579 #define M_FW_RI_RES_WR_FETCHRO 0x1
1580 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO)
1581 #define G_FW_RI_RES_WR_FETCHRO(x) \
1582 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
1583 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U)
1584
1585 #define S_FW_RI_RES_WR_HOSTFCMODE 20
1586 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3
1587 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE)
1588 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \
1589 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
1590
1591 #define S_FW_RI_RES_WR_CPRIO 19
1592 #define M_FW_RI_RES_WR_CPRIO 0x1
1593 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO)
1594 #define G_FW_RI_RES_WR_CPRIO(x) \
1595 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
1596 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U)
1597
1598 #define S_FW_RI_RES_WR_ONCHIP 18
1599 #define M_FW_RI_RES_WR_ONCHIP 0x1
1600 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP)
1601 #define G_FW_RI_RES_WR_ONCHIP(x) \
1602 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
1603 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U)
1604
1605 #define S_FW_RI_RES_WR_PCIECHN 16
1606 #define M_FW_RI_RES_WR_PCIECHN 0x3
1607 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN)
1608 #define G_FW_RI_RES_WR_PCIECHN(x) \
1609 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
1610
1611 #define S_FW_RI_RES_WR_IQID 0
1612 #define M_FW_RI_RES_WR_IQID 0xffff
1613 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID)
1614 #define G_FW_RI_RES_WR_IQID(x) \
1615 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
1616
1617 #define S_FW_RI_RES_WR_DCAEN 31
1618 #define M_FW_RI_RES_WR_DCAEN 0x1
1619 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN)
1620 #define G_FW_RI_RES_WR_DCAEN(x) \
1621 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
1622 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U)
1623
1624 #define S_FW_RI_RES_WR_DCACPU 26
1625 #define M_FW_RI_RES_WR_DCACPU 0x1f
1626 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU)
1627 #define G_FW_RI_RES_WR_DCACPU(x) \
1628 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
1629
1630 #define S_FW_RI_RES_WR_FBMIN 23
1631 #define M_FW_RI_RES_WR_FBMIN 0x7
1632 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN)
1633 #define G_FW_RI_RES_WR_FBMIN(x) \
1634 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
1635
1636 #define S_FW_RI_RES_WR_FBMAX 20
1637 #define M_FW_RI_RES_WR_FBMAX 0x7
1638 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX)
1639 #define G_FW_RI_RES_WR_FBMAX(x) \
1640 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
1641
1642 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19
1643 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1
1644 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
1645 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \
1646 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
1647 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
1648
1649 #define S_FW_RI_RES_WR_CIDXFTHRESH 16
1650 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7
1651 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
1652 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \
1653 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
1654
1655 #define S_FW_RI_RES_WR_EQSIZE 0
1656 #define M_FW_RI_RES_WR_EQSIZE 0xffff
1657 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE)
1658 #define G_FW_RI_RES_WR_EQSIZE(x) \
1659 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
1660
1661 #define S_FW_RI_RES_WR_IQANDST 15
1662 #define M_FW_RI_RES_WR_IQANDST 0x1
1663 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST)
1664 #define G_FW_RI_RES_WR_IQANDST(x) \
1665 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
1666 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U)
1667
1668 #define S_FW_RI_RES_WR_IQANUS 14
1669 #define M_FW_RI_RES_WR_IQANUS 0x1
1670 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS)
1671 #define G_FW_RI_RES_WR_IQANUS(x) \
1672 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
1673 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U)
1674
1675 #define S_FW_RI_RES_WR_IQANUD 12
1676 #define M_FW_RI_RES_WR_IQANUD 0x3
1677 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD)
1678 #define G_FW_RI_RES_WR_IQANUD(x) \
1679 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
1680
1681 #define S_FW_RI_RES_WR_IQANDSTINDEX 0
1682 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff
1683 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
1684 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \
1685 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
1686
1687 #define S_FW_RI_RES_WR_IQDROPRSS 15
1688 #define M_FW_RI_RES_WR_IQDROPRSS 0x1
1689 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS)
1690 #define G_FW_RI_RES_WR_IQDROPRSS(x) \
1691 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
1692 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U)
1693
1694 #define S_FW_RI_RES_WR_IQGTSMODE 14
1695 #define M_FW_RI_RES_WR_IQGTSMODE 0x1
1696 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE)
1697 #define G_FW_RI_RES_WR_IQGTSMODE(x) \
1698 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
1699 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U)
1700
1701 #define S_FW_RI_RES_WR_IQPCIECH 12
1702 #define M_FW_RI_RES_WR_IQPCIECH 0x3
1703 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH)
1704 #define G_FW_RI_RES_WR_IQPCIECH(x) \
1705 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
1706
1707 #define S_FW_RI_RES_WR_IQDCAEN 11
1708 #define M_FW_RI_RES_WR_IQDCAEN 0x1
1709 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN)
1710 #define G_FW_RI_RES_WR_IQDCAEN(x) \
1711 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
1712 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U)
1713
1714 #define S_FW_RI_RES_WR_IQDCACPU 6
1715 #define M_FW_RI_RES_WR_IQDCACPU 0x1f
1716 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU)
1717 #define G_FW_RI_RES_WR_IQDCACPU(x) \
1718 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
1719
1720 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4
1721 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3
1722 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
1723 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
1724 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \
1725 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
1726
1727 #define S_FW_RI_RES_WR_IQO 3
1728 #define M_FW_RI_RES_WR_IQO 0x1
1729 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO)
1730 #define G_FW_RI_RES_WR_IQO(x) \
1731 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
1732 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U)
1733
1734 #define S_FW_RI_RES_WR_IQCPRIO 2
1735 #define M_FW_RI_RES_WR_IQCPRIO 0x1
1736 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO)
1737 #define G_FW_RI_RES_WR_IQCPRIO(x) \
1738 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
1739 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U)
1740
1741 #define S_FW_RI_RES_WR_IQESIZE 0
1742 #define M_FW_RI_RES_WR_IQESIZE 0x3
1743 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE)
1744 #define G_FW_RI_RES_WR_IQESIZE(x) \
1745 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
1746
1747 #define S_FW_RI_RES_WR_IQNS 31
1748 #define M_FW_RI_RES_WR_IQNS 0x1
1749 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS)
1750 #define G_FW_RI_RES_WR_IQNS(x) \
1751 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
1752 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U)
1753
1754 #define S_FW_RI_RES_WR_IQRO 30
1755 #define M_FW_RI_RES_WR_IQRO 0x1
1756 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO)
1757 #define G_FW_RI_RES_WR_IQRO(x) \
1758 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
1759 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U)
1760
1761 struct fw_ri_rdma_write_wr {
1762 __u8 opcode;
1763 __u8 flags;
1764 __u16 wrid;
1765 __u8 r1[3];
1766 __u8 len16;
1767 __be64 r2;
1768 __be32 plen;
1769 __be32 stag_sink;
1770 __be64 to_sink;
1771 #ifndef C99_NOT_SUPPORTED
1772 union {
1773 struct fw_ri_immd immd_src[0];
1774 struct fw_ri_isgl isgl_src[0];
1775 } u;
1776 #endif
1777 };
1778
1779 struct fw_ri_send_wr {
1780 __u8 opcode;
1781 __u8 flags;
1782 __u16 wrid;
1783 __u8 r1[3];
1784 __u8 len16;
1785 __be32 sendop_pkd;
1786 __be32 stag_inv;
1787 __be32 plen;
1788 __be32 r3;
1789 __be64 r4;
1790 #ifndef C99_NOT_SUPPORTED
1791 union {
1792 struct fw_ri_immd immd_src[0];
1793 struct fw_ri_isgl isgl_src[0];
1794 } u;
1795 #endif
1796 };
1797
1798 #define S_FW_RI_SEND_WR_SENDOP 0
1799 #define M_FW_RI_SEND_WR_SENDOP 0xf
1800 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP)
1801 #define G_FW_RI_SEND_WR_SENDOP(x) \
1802 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
1803
1804 struct fw_ri_rdma_read_wr {
1805 __u8 opcode;
1806 __u8 flags;
1807 __u16 wrid;
1808 __u8 r1[3];
1809 __u8 len16;
1810 __be64 r2;
1811 __be32 stag_sink;
1812 __be32 to_sink_hi;
1813 __be32 to_sink_lo;
1814 __be32 plen;
1815 __be32 stag_src;
1816 __be32 to_src_hi;
1817 __be32 to_src_lo;
1818 __be32 r5;
1819 };
1820
1821 struct fw_ri_recv_wr {
1822 __u8 opcode;
1823 __u8 r1;
1824 __u16 wrid;
1825 __u8 r2[3];
1826 __u8 len16;
1827 struct fw_ri_isgl isgl;
1828 };
1829
1830 struct fw_ri_bind_mw_wr {
1831 __u8 opcode;
1832 __u8 flags;
1833 __u16 wrid;
1834 __u8 r1[3];
1835 __u8 len16;
1836 __u8 qpbinde_to_dcacpu;
1837 __u8 pgsz_shift;
1838 __u8 addr_type;
1839 __u8 mem_perms;
1840 __be32 stag_mr;
1841 __be32 stag_mw;
1842 __be32 r3;
1843 __be64 len_mw;
1844 __be64 va_fbo;
1845 __be64 r4;
1846 };
1847
1848 #define S_FW_RI_BIND_MW_WR_QPBINDE 6
1849 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1
1850 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
1851 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \
1852 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
1853 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U)
1854
1855 #define S_FW_RI_BIND_MW_WR_NS 5
1856 #define M_FW_RI_BIND_MW_WR_NS 0x1
1857 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS)
1858 #define G_FW_RI_BIND_MW_WR_NS(x) \
1859 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
1860 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U)
1861
1862 #define S_FW_RI_BIND_MW_WR_DCACPU 0
1863 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f
1864 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU)
1865 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \
1866 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
1867
1868 struct fw_ri_fr_nsmr_wr {
1869 __u8 opcode;
1870 __u8 flags;
1871 __u16 wrid;
1872 __u8 r1[3];
1873 __u8 len16;
1874 __u8 qpbinde_to_dcacpu;
1875 __u8 pgsz_shift;
1876 __u8 addr_type;
1877 __u8 mem_perms;
1878 __be32 stag;
1879 __be32 len_hi;
1880 __be32 len_lo;
1881 __be32 va_hi;
1882 __be32 va_lo_fbo;
1883 };
1884
1885 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6
1886 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1
1887 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
1888 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \
1889 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
1890 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
1891
1892 #define S_FW_RI_FR_NSMR_WR_NS 5
1893 #define M_FW_RI_FR_NSMR_WR_NS 0x1
1894 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS)
1895 #define G_FW_RI_FR_NSMR_WR_NS(x) \
1896 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
1897 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U)
1898
1899 #define S_FW_RI_FR_NSMR_WR_DCACPU 0
1900 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f
1901 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
1902 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \
1903 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
1904
1905 struct fw_ri_fr_nsmr_tpte_wr {
1906 __u8 opcode;
1907 __u8 flags;
1908 __u16 wrid;
1909 __u8 r1[3];
1910 __u8 len16;
1911 __be32 r2;
1912 __be32 stag;
1913 struct fw_ri_tpte tpte;
1914 __be64 pbl[2];
1915 };
1916
1917 struct fw_ri_inv_lstag_wr {
1918 __u8 opcode;
1919 __u8 flags;
1920 __u16 wrid;
1921 __u8 r1[3];
1922 __u8 len16;
1923 __be32 r2;
1924 __be32 stag_inv;
1925 };
1926
1927 struct fw_ri_send_immediate_wr {
1928 __u8 opcode;
1929 __u8 flags;
1930 __u16 wrid;
1931 __u8 r1[3];
1932 __u8 len16;
1933 __be32 sendimmop_pkd;
1934 __be32 r3;
1935 __be32 plen;
1936 __be32 r4;
1937 __be64 r5;
1938 #ifndef C99_NOT_SUPPORTED
1939 struct fw_ri_immd immd_src[0];
1940 #endif
1941 };
1942
1943 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0
1944 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf
1945 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
1946 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1947 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \
1948 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
1949 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
1950
1951 enum fw_ri_atomic_op {
1952 FW_RI_ATOMIC_OP_FETCHADD,
1953 FW_RI_ATOMIC_OP_SWAP,
1954 FW_RI_ATOMIC_OP_CMDSWAP,
1955 };
1956
1957 struct fw_ri_atomic_wr {
1958 __u8 opcode;
1959 __u8 flags;
1960 __u16 wrid;
1961 __u8 r1[3];
1962 __u8 len16;
1963 __be32 atomicop_pkd;
1964 __be64 r3;
1965 __be32 aopcode_pkd;
1966 __be32 reqid;
1967 __be32 stag;
1968 __be32 to_hi;
1969 __be32 to_lo;
1970 __be32 addswap_data_hi;
1971 __be32 addswap_data_lo;
1972 __be32 addswap_mask_hi;
1973 __be32 addswap_mask_lo;
1974 __be32 compare_data_hi;
1975 __be32 compare_data_lo;
1976 __be32 compare_mask_hi;
1977 __be32 compare_mask_lo;
1978 __be32 r5;
1979 };
1980
1981 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0
1982 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf
1983 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
1984 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \
1985 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
1986
1987 #define S_FW_RI_ATOMIC_WR_AOPCODE 0
1988 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf
1989 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
1990 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \
1991 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
1992
1993 enum fw_ri_type {
1994 FW_RI_TYPE_INIT,
1995 FW_RI_TYPE_FINI,
1996 FW_RI_TYPE_TERMINATE
1997 };
1998
1999 enum fw_ri_init_p2ptype {
2000 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE,
2001 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ,
2002 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND,
2003 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV,
2004 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE,
2005 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV,
2006 FW_RI_INIT_P2PTYPE_DISABLED = 0xf,
2007 };
2008
2009 enum fw_ri_init_rqeqid_srq {
2010 FW_RI_INIT_RQEQID_SRQ = 1U << 31,
2011 };
2012
2013 struct fw_ri_wr {
2014 __be32 op_compl;
2015 __be32 flowid_len16;
2016 __u64 cookie;
2017 union fw_ri {
2018 struct fw_ri_init {
2019 __u8 type;
2020 __u8 mpareqbit_p2ptype;
2021 __u8 r4[2];
2022 __u8 mpa_attrs;
2023 __u8 qp_caps;
2024 __be16 nrqe;
2025 __be32 pdid;
2026 __be32 qpid;
2027 __be32 sq_eqid;
2028 __be32 rq_eqid;
2029 __be32 scqid;
2030 __be32 rcqid;
2031 __be32 ord_max;
2032 __be32 ird_max;
2033 __be32 iss;
2034 __be32 irs;
2035 __be32 hwrqsize;
2036 __be32 hwrqaddr;
2037 __be64 r5;
2038 union fw_ri_init_p2p {
2039 struct fw_ri_rdma_write_wr write;
2040 struct fw_ri_rdma_read_wr read;
2041 struct fw_ri_send_wr send;
2042 } u;
2043 } init;
2044 struct fw_ri_fini {
2045 __u8 type;
2046 __u8 r3[7];
2047 __be64 r4;
2048 } fini;
2049 struct fw_ri_terminate {
2050 __u8 type;
2051 __u8 r3[3];
2052 __be32 immdlen;
2053 __u8 termmsg[40];
2054 } terminate;
2055 } u;
2056 };
2057
2058 #define S_FW_RI_WR_MPAREQBIT 7
2059 #define M_FW_RI_WR_MPAREQBIT 0x1
2060 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT)
2061 #define G_FW_RI_WR_MPAREQBIT(x) \
2062 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
2063 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U)
2064
2065 #define S_FW_RI_WR_0BRRBIT 6
2066 #define M_FW_RI_WR_0BRRBIT 0x1
2067 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT)
2068 #define G_FW_RI_WR_0BRRBIT(x) \
2069 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
2070 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U)
2071
2072 #define S_FW_RI_WR_P2PTYPE 0
2073 #define M_FW_RI_WR_P2PTYPE 0xf
2074 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE)
2075 #define G_FW_RI_WR_P2PTYPE(x) \
2076 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
2077
2078 /******************************************************************************
2079 * F O i S C S I W O R K R E Q U E S T s
2080 *********************************************/
2081
2082 #define FW_FOISCSI_NAME_MAX_LEN 224
2083 #define FW_FOISCSI_ALIAS_MAX_LEN 224
2084 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128
2085 #define FW_FOISCSI_INIT_NODE_MAX 8
2086
2087 enum fw_chnet_ifconf_wr_subop {
2088 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
2089
2090 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
2091 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
2092
2093 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
2094 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
2095
2096 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
2097 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
2098
2099 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
2100 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
2101
2102 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
2103 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
2104
2105 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
2106 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
2107
2108 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET,
2109 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET,
2110
2111 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET,
2112 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET,
2113 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED,
2114
2115 FW_CHNET_IFCONF_WR_SUBOP_MAX,
2116 };
2117
2118 struct fw_chnet_ifconf_wr {
2119 __be32 op_compl;
2120 __be32 flowid_len16;
2121 __be64 cookie;
2122 __be32 if_flowid;
2123 __u8 idx;
2124 __u8 subop;
2125 __u8 retval;
2126 __u8 r2;
2127 __be64 r3;
2128 struct fw_chnet_ifconf_params {
2129 __be32 r0;
2130 __be16 vlanid;
2131 __be16 mtu;
2132 union fw_chnet_ifconf_addr_type {
2133 struct fw_chnet_ifconf_ipv4 {
2134 __be32 addr;
2135 __be32 mask;
2136 __be32 router;
2137 __be32 r0;
2138 __be64 r1;
2139 } ipv4;
2140 struct fw_chnet_ifconf_ipv6 {
2141 __u8 prefix_len;
2142 __u8 r0;
2143 __be16 r1;
2144 __be32 r2;
2145 __be64 addr_hi;
2146 __be64 addr_lo;
2147 __be64 router_hi;
2148 __be64 router_lo;
2149 } ipv6;
2150 } in_attr;
2151 } param;
2152 };
2153
2154 enum fw_foiscsi_node_type {
2155 FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
2156 FW_FOISCSI_NODE_TYPE_TARGET,
2157 };
2158
2159 enum fw_foiscsi_session_type {
2160 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
2161 FW_FOISCSI_SESSION_TYPE_NORMAL,
2162 };
2163
2164 enum fw_foiscsi_auth_policy {
2165 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
2166 FW_FOISCSI_AUTH_POLICY_MUTUAL,
2167 };
2168
2169 enum fw_foiscsi_auth_method {
2170 FW_FOISCSI_AUTH_METHOD_NONE = 0,
2171 FW_FOISCSI_AUTH_METHOD_CHAP,
2172 FW_FOISCSI_AUTH_METHOD_CHAP_FST,
2173 FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
2174 };
2175
2176 enum fw_foiscsi_digest_type {
2177 FW_FOISCSI_DIGEST_TYPE_NONE = 0,
2178 FW_FOISCSI_DIGEST_TYPE_CRC32,
2179 FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
2180 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
2181 };
2182
2183 enum fw_foiscsi_wr_subop {
2184 FW_FOISCSI_WR_SUBOP_ADD = 1,
2185 FW_FOISCSI_WR_SUBOP_DEL = 2,
2186 FW_FOISCSI_WR_SUBOP_MOD = 4,
2187 };
2188
2189 enum fw_foiscsi_ctrl_state {
2190 FW_FOISCSI_CTRL_STATE_FREE = 0,
2191 FW_FOISCSI_CTRL_STATE_ONLINE = 1,
2192 FW_FOISCSI_CTRL_STATE_FAILED,
2193 FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
2194 FW_FOISCSI_CTRL_STATE_REDIRECT,
2195 };
2196
2197 struct fw_rdev_wr {
2198 __be32 op_to_immdlen;
2199 __be32 alloc_to_len16;
2200 __be64 cookie;
2201 __u8 protocol;
2202 __u8 event_cause;
2203 __u8 cur_state;
2204 __u8 prev_state;
2205 __be32 flags_to_assoc_flowid;
2206 union rdev_entry {
2207 struct fcoe_rdev_entry {
2208 __be32 flowid;
2209 __u8 protocol;
2210 __u8 event_cause;
2211 __u8 flags;
2212 __u8 rjt_reason;
2213 __u8 cur_login_st;
2214 __u8 prev_login_st;
2215 __be16 rcv_fr_sz;
2216 __u8 rd_xfer_rdy_to_rport_type;
2217 __u8 vft_to_qos;
2218 __u8 org_proc_assoc_to_acc_rsp_code;
2219 __u8 enh_disc_to_tgt;
2220 __u8 wwnn[8];
2221 __u8 wwpn[8];
2222 __be16 iqid;
2223 __u8 fc_oui[3];
2224 __u8 r_id[3];
2225 } fcoe_rdev;
2226 struct iscsi_rdev_entry {
2227 __be32 flowid;
2228 __u8 protocol;
2229 __u8 event_cause;
2230 __u8 flags;
2231 __u8 r3;
2232 __be16 iscsi_opts;
2233 __be16 tcp_opts;
2234 __be16 ip_opts;
2235 __be16 max_rcv_len;
2236 __be16 max_snd_len;
2237 __be16 first_brst_len;
2238 __be16 max_brst_len;
2239 __be16 r4;
2240 __be16 def_time2wait;
2241 __be16 def_time2ret;
2242 __be16 nop_out_intrvl;
2243 __be16 non_scsi_to;
2244 __be16 isid;
2245 __be16 tsid;
2246 __be16 port;
2247 __be16 tpgt;
2248 __u8 r5[6];
2249 __be16 iqid;
2250 } iscsi_rdev;
2251 } u;
2252 };
2253
2254 #define S_FW_RDEV_WR_IMMDLEN 0
2255 #define M_FW_RDEV_WR_IMMDLEN 0xff
2256 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN)
2257 #define G_FW_RDEV_WR_IMMDLEN(x) \
2258 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
2259
2260 #define S_FW_RDEV_WR_ALLOC 31
2261 #define M_FW_RDEV_WR_ALLOC 0x1
2262 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC)
2263 #define G_FW_RDEV_WR_ALLOC(x) \
2264 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
2265 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U)
2266
2267 #define S_FW_RDEV_WR_FREE 30
2268 #define M_FW_RDEV_WR_FREE 0x1
2269 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE)
2270 #define G_FW_RDEV_WR_FREE(x) \
2271 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
2272 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U)
2273
2274 #define S_FW_RDEV_WR_MODIFY 29
2275 #define M_FW_RDEV_WR_MODIFY 0x1
2276 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY)
2277 #define G_FW_RDEV_WR_MODIFY(x) \
2278 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
2279 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U)
2280
2281 #define S_FW_RDEV_WR_FLOWID 8
2282 #define M_FW_RDEV_WR_FLOWID 0xfffff
2283 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID)
2284 #define G_FW_RDEV_WR_FLOWID(x) \
2285 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
2286
2287 #define S_FW_RDEV_WR_LEN16 0
2288 #define M_FW_RDEV_WR_LEN16 0xff
2289 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16)
2290 #define G_FW_RDEV_WR_LEN16(x) \
2291 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
2292
2293 #define S_FW_RDEV_WR_FLAGS 24
2294 #define M_FW_RDEV_WR_FLAGS 0xff
2295 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS)
2296 #define G_FW_RDEV_WR_FLAGS(x) \
2297 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
2298
2299 #define S_FW_RDEV_WR_GET_NEXT 20
2300 #define M_FW_RDEV_WR_GET_NEXT 0xf
2301 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT)
2302 #define G_FW_RDEV_WR_GET_NEXT(x) \
2303 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
2304
2305 #define S_FW_RDEV_WR_ASSOC_FLOWID 0
2306 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff
2307 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
2308 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \
2309 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
2310
2311 #define S_FW_RDEV_WR_RJT 7
2312 #define M_FW_RDEV_WR_RJT 0x1
2313 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT)
2314 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
2315 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U)
2316
2317 #define S_FW_RDEV_WR_REASON 0
2318 #define M_FW_RDEV_WR_REASON 0x7f
2319 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON)
2320 #define G_FW_RDEV_WR_REASON(x) \
2321 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
2322
2323 #define S_FW_RDEV_WR_RD_XFER_RDY 7
2324 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1
2325 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY)
2326 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \
2327 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
2328 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U)
2329
2330 #define S_FW_RDEV_WR_WR_XFER_RDY 6
2331 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1
2332 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY)
2333 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \
2334 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
2335 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U)
2336
2337 #define S_FW_RDEV_WR_FC_SP 5
2338 #define M_FW_RDEV_WR_FC_SP 0x1
2339 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP)
2340 #define G_FW_RDEV_WR_FC_SP(x) \
2341 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
2342 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U)
2343
2344 #define S_FW_RDEV_WR_RPORT_TYPE 0
2345 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f
2346 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE)
2347 #define G_FW_RDEV_WR_RPORT_TYPE(x) \
2348 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
2349
2350 #define S_FW_RDEV_WR_VFT 7
2351 #define M_FW_RDEV_WR_VFT 0x1
2352 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT)
2353 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
2354 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U)
2355
2356 #define S_FW_RDEV_WR_NPIV 6
2357 #define M_FW_RDEV_WR_NPIV 0x1
2358 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV)
2359 #define G_FW_RDEV_WR_NPIV(x) \
2360 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
2361 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U)
2362
2363 #define S_FW_RDEV_WR_CLASS 4
2364 #define M_FW_RDEV_WR_CLASS 0x3
2365 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS)
2366 #define G_FW_RDEV_WR_CLASS(x) \
2367 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
2368
2369 #define S_FW_RDEV_WR_SEQ_DEL 3
2370 #define M_FW_RDEV_WR_SEQ_DEL 0x1
2371 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL)
2372 #define G_FW_RDEV_WR_SEQ_DEL(x) \
2373 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
2374 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U)
2375
2376 #define S_FW_RDEV_WR_PRIO_PREEMP 2
2377 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1
2378 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP)
2379 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \
2380 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
2381 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U)
2382
2383 #define S_FW_RDEV_WR_PREF 1
2384 #define M_FW_RDEV_WR_PREF 0x1
2385 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF)
2386 #define G_FW_RDEV_WR_PREF(x) \
2387 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
2388 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U)
2389
2390 #define S_FW_RDEV_WR_QOS 0
2391 #define M_FW_RDEV_WR_QOS 0x1
2392 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS)
2393 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
2394 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U)
2395
2396 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7
2397 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1
2398 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
2399 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \
2400 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
2401 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
2402
2403 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6
2404 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1
2405 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
2406 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \
2407 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
2408 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
2409
2410 #define S_FW_RDEV_WR_IMAGE_PAIR 5
2411 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1
2412 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR)
2413 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \
2414 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
2415 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U)
2416
2417 #define S_FW_RDEV_WR_ACC_RSP_CODE 0
2418 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f
2419 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
2420 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \
2421 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
2422
2423 #define S_FW_RDEV_WR_ENH_DISC 7
2424 #define M_FW_RDEV_WR_ENH_DISC 0x1
2425 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC)
2426 #define G_FW_RDEV_WR_ENH_DISC(x) \
2427 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
2428 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U)
2429
2430 #define S_FW_RDEV_WR_REC 6
2431 #define M_FW_RDEV_WR_REC 0x1
2432 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC)
2433 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
2434 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U)
2435
2436 #define S_FW_RDEV_WR_TASK_RETRY_ID 5
2437 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1
2438 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
2439 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \
2440 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
2441 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U)
2442
2443 #define S_FW_RDEV_WR_RETRY 4
2444 #define M_FW_RDEV_WR_RETRY 0x1
2445 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY)
2446 #define G_FW_RDEV_WR_RETRY(x) \
2447 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
2448 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U)
2449
2450 #define S_FW_RDEV_WR_CONF_CMPL 3
2451 #define M_FW_RDEV_WR_CONF_CMPL 0x1
2452 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL)
2453 #define G_FW_RDEV_WR_CONF_CMPL(x) \
2454 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
2455 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U)
2456
2457 #define S_FW_RDEV_WR_DATA_OVLY 2
2458 #define M_FW_RDEV_WR_DATA_OVLY 0x1
2459 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY)
2460 #define G_FW_RDEV_WR_DATA_OVLY(x) \
2461 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
2462 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U)
2463
2464 #define S_FW_RDEV_WR_INI 1
2465 #define M_FW_RDEV_WR_INI 0x1
2466 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI)
2467 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
2468 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U)
2469
2470 #define S_FW_RDEV_WR_TGT 0
2471 #define M_FW_RDEV_WR_TGT 0x1
2472 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT)
2473 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
2474 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U)
2475
2476 struct fw_foiscsi_node_wr {
2477 __be32 op_to_immdlen;
2478 __be32 flowid_len16;
2479 __u64 cookie;
2480 __u8 subop;
2481 __u8 status;
2482 __u8 alias_len;
2483 __u8 iqn_len;
2484 __be32 node_flowid;
2485 __be16 nodeid;
2486 __be16 login_retry;
2487 __be16 retry_timeout;
2488 __be16 r3;
2489 __u8 iqn[224];
2490 __u8 alias[224];
2491 };
2492
2493 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0
2494 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff
2495 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
2496 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \
2497 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
2498
2499 struct fw_foiscsi_ctrl_wr {
2500 __be32 op_compl;
2501 __be32 flowid_len16;
2502 __u64 cookie;
2503 __u8 subop;
2504 __u8 status;
2505 __u8 ctrl_state;
2506 __u8 io_state;
2507 __be32 node_id;
2508 __be32 ctrl_id;
2509 __be32 io_id;
2510 struct fw_foiscsi_sess_attr {
2511 __be32 sess_type_to_erl;
2512 __be16 max_conn;
2513 __be16 max_r2t;
2514 __be16 time2wait;
2515 __be16 time2retain;
2516 __be32 max_burst;
2517 __be32 first_burst;
2518 __be32 r1;
2519 } sess_attr;
2520 struct fw_foiscsi_conn_attr {
2521 __be32 hdigest_to_ddp_pgsz;
2522 __be32 max_rcv_dsl;
2523 __be32 ping_tmo;
2524 __be16 dst_port;
2525 __be16 src_port;
2526 union fw_foiscsi_conn_attr_addr {
2527 struct fw_foiscsi_conn_attr_ipv6 {
2528 __be64 dst_addr[2];
2529 __be64 src_addr[2];
2530 } ipv6_addr;
2531 struct fw_foiscsi_conn_attr_ipv4 {
2532 __be32 dst_addr;
2533 __be32 src_addr;
2534 } ipv4_addr;
2535 } u;
2536 } conn_attr;
2537 __u8 tgt_name_len;
2538 __u8 r3[7];
2539 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN];
2540 };
2541
2542 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30
2543 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3
2544 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
2545 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2546 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \
2547 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
2548
2549 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29
2550 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1
2551 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
2552 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2553 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \
2554 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
2555 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
2556 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \
2557 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
2558
2559 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28
2560 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1
2561 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
2562 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2563 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \
2564 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
2565 M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
2566 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \
2567 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
2568
2569 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27
2570 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1
2571 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
2572 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2573 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \
2574 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
2575 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
2576 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \
2577 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
2578
2579 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26
2580 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1
2581 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
2582 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2583 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \
2584 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
2585 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
2586 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \
2587 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
2588
2589 #define S_FW_FOISCSI_CTRL_WR_ERL 24
2590 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3
2591 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL)
2592 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \
2593 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
2594
2595 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30
2596 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3
2597 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
2598 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \
2599 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
2600
2601 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28
2602 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3
2603 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
2604 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \
2605 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
2606
2607 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25
2608 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7
2609 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
2610 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2611 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \
2612 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
2613 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
2614
2615 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23
2616 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3
2617 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
2618 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2619 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \
2620 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
2621 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
2622
2623 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21
2624 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3
2625 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \
2626 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2627 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \
2628 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
2629
2630 #define S_FW_FOISCSI_CTRL_WR_IPV6 20
2631 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1
2632 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6)
2633 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \
2634 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6)
2635 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U)
2636
2637 struct fw_foiscsi_chap_wr {
2638 __be32 op_compl;
2639 __be32 flowid_len16;
2640 __u64 cookie;
2641 __u8 status;
2642 __u8 id_len;
2643 __u8 sec_len;
2644 __u8 node_type;
2645 __be16 node_id;
2646 __u8 r3[2];
2647 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN];
2648 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN];
2649 };
2650
2651 /******************************************************************************
2652 * C O i S C S I W O R K R E Q U E S T S
2653 ********************************************/
2654
2655 enum fw_chnet_addr_type {
2656 FW_CHNET_ADDD_TYPE_NONE = 0,
2657 FW_CHNET_ADDR_TYPE_IPV4,
2658 FW_CHNET_ADDR_TYPE_IPV6,
2659 };
2660
2661 enum fw_msg_wr_type {
2662 FW_MSG_WR_TYPE_RPL = 0,
2663 FW_MSG_WR_TYPE_ERR,
2664 FW_MSG_WR_TYPE_PLD,
2665 };
2666
2667 struct fw_coiscsi_tgt_wr {
2668 __be32 op_compl;
2669 __be32 flowid_len16;
2670 __u64 cookie;
2671 __u8 subop;
2672 __u8 status;
2673 __be16 r4;
2674 __be32 flags;
2675 struct fw_coiscsi_tgt_conn_attr {
2676 __be32 in_tid;
2677 __be16 in_port;
2678 __u8 in_type;
2679 __u8 r6;
2680 union fw_coiscsi_tgt_conn_attr_addr {
2681 struct fw_coiscsi_tgt_conn_attr_in_addr {
2682 __be32 addr;
2683 __be32 r7;
2684 __be32 r8[2];
2685 } in_addr;
2686 struct fw_coiscsi_tgt_conn_attr_in_addr6 {
2687 __be64 addr[2];
2688 } in_addr6;
2689 } u;
2690 } conn_attr;
2691 };
2692
2693 struct fw_coiscsi_tgt_xmit_wr {
2694 __be32 op_to_immdlen;
2695 __be32 flowid_len16;
2696 __be64 cookie;
2697 __be16 iq_id;
2698 __be16 r4;
2699 __be32 datasn;
2700 __be32 t_xfer_len;
2701 __be32 flags;
2702 __be32 tag;
2703 __be32 tidx;
2704 __be32 r5[2];
2705 };
2706
2707 #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23
2708 #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1
2709 #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \
2710 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST)
2711 #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \
2712 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST)
2713 #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U)
2714
2715 #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22
2716 #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1
2717 #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \
2718 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST)
2719 #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \
2720 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST)
2721 #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U)
2722
2723 #define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20
2724 #define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1
2725 #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP)
2726 #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \
2727 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP)
2728 #define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U)
2729
2730 #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT 19
2731 #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT 0x1
2732 #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \
2733 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT)
2734 #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \
2735 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT)
2736 #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U)
2737
2738 #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL 18
2739 #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL 0x1
2740 #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \
2741 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL)
2742 #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \
2743 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL)
2744 #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U)
2745
2746 #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN 16
2747 #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN 0x3
2748 #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \
2749 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN)
2750 #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \
2751 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \
2752 M_FW_COiSCSI_TGT_XMIT_WR_PADLEN)
2753
2754 #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0
2755 #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff
2756 #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \
2757 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
2758 #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \
2759 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \
2760 M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN)
2761
2762 struct fw_isns_wr {
2763 __be32 op_compl;
2764 __be32 flowid_len16;
2765 __u64 cookie;
2766 __u8 subop;
2767 __u8 status;
2768 __be16 iq_id;
2769 __be32 r4;
2770 struct fw_tcp_conn_attr {
2771 __be32 in_tid;
2772 __be16 in_port;
2773 __u8 in_type;
2774 __u8 r6;
2775 union fw_tcp_conn_attr_addr {
2776 struct fw_tcp_conn_attr_in_addr {
2777 __be32 addr;
2778 __be32 r7;
2779 __be32 r8[2];
2780 } in_addr;
2781 struct fw_tcp_conn_attr_in_addr6 {
2782 __be64 addr[2];
2783 } in_addr6;
2784 } u;
2785 } conn_attr;
2786 };
2787
2788 struct fw_isns_xmit_wr {
2789 __be32 op_to_immdlen;
2790 __be32 flowid_len16;
2791 __be64 cookie;
2792 __be16 iq_id;
2793 __be16 r4;
2794 __be32 xfer_len;
2795 __be64 r5;
2796 };
2797
2798 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0
2799 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff
2800 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN)
2801 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \
2802 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN)
2803
2804 /******************************************************************************
2805 * F O F C O E W O R K R E Q U E S T s
2806 *******************************************/
2807
2808 struct fw_fcoe_els_ct_wr {
2809 __be32 op_immdlen;
2810 __be32 flowid_len16;
2811 __be64 cookie;
2812 __be16 iqid;
2813 __u8 tmo_val;
2814 __u8 els_ct_type;
2815 __u8 ctl_pri;
2816 __u8 cp_en_class;
2817 __be16 xfer_cnt;
2818 __u8 fl_to_sp;
2819 __u8 l_id[3];
2820 __u8 r5;
2821 __u8 r_id[3];
2822 __be64 rsp_dmaaddr;
2823 __be32 rsp_dmalen;
2824 __be32 r6;
2825 };
2826
2827 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24
2828 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff
2829 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
2830 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \
2831 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
2832
2833 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0
2834 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff
2835 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
2836 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \
2837 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
2838
2839 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8
2840 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff
2841 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
2842 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \
2843 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
2844
2845 #define S_FW_FCOE_ELS_CT_WR_LEN16 0
2846 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff
2847 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
2848 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \
2849 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
2850
2851 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6
2852 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3
2853 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
2854 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \
2855 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
2856
2857 #define S_FW_FCOE_ELS_CT_WR_CLASS 4
2858 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3
2859 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
2860 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \
2861 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
2862
2863 #define S_FW_FCOE_ELS_CT_WR_FL 2
2864 #define M_FW_FCOE_ELS_CT_WR_FL 0x1
2865 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL)
2866 #define G_FW_FCOE_ELS_CT_WR_FL(x) \
2867 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
2868 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U)
2869
2870 #define S_FW_FCOE_ELS_CT_WR_NPIV 1
2871 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1
2872 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
2873 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \
2874 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
2875 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U)
2876
2877 #define S_FW_FCOE_ELS_CT_WR_SP 0
2878 #define M_FW_FCOE_ELS_CT_WR_SP 0x1
2879 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP)
2880 #define G_FW_FCOE_ELS_CT_WR_SP(x) \
2881 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
2882 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U)
2883
2884 /******************************************************************************
2885 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path)
2886 *****************************************************************************/
2887
2888 struct fw_scsi_write_wr {
2889 __be32 op_immdlen;
2890 __be32 flowid_len16;
2891 __be64 cookie;
2892 __be16 iqid;
2893 __u8 tmo_val;
2894 __u8 use_xfer_cnt;
2895 union fw_scsi_write_priv {
2896 struct fcoe_write_priv {
2897 __u8 ctl_pri;
2898 __u8 cp_en_class;
2899 __u8 r3_lo[2];
2900 } fcoe;
2901 struct iscsi_write_priv {
2902 __u8 r3[4];
2903 } iscsi;
2904 } u;
2905 __be32 xfer_cnt;
2906 __be32 ini_xfer_cnt;
2907 __be64 rsp_dmaaddr;
2908 __be32 rsp_dmalen;
2909 __be32 r4;
2910 };
2911
2912 #define S_FW_SCSI_WRITE_WR_OPCODE 24
2913 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff
2914 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE)
2915 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \
2916 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
2917
2918 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0
2919 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff
2920 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
2921 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \
2922 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
2923
2924 #define S_FW_SCSI_WRITE_WR_FLOWID 8
2925 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff
2926 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID)
2927 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \
2928 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
2929
2930 #define S_FW_SCSI_WRITE_WR_LEN16 0
2931 #define M_FW_SCSI_WRITE_WR_LEN16 0xff
2932 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16)
2933 #define G_FW_SCSI_WRITE_WR_LEN16(x) \
2934 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
2935
2936 #define S_FW_SCSI_WRITE_WR_CP_EN 6
2937 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3
2938 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN)
2939 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \
2940 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
2941
2942 #define S_FW_SCSI_WRITE_WR_CLASS 4
2943 #define M_FW_SCSI_WRITE_WR_CLASS 0x3
2944 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS)
2945 #define G_FW_SCSI_WRITE_WR_CLASS(x) \
2946 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
2947
2948 struct fw_scsi_read_wr {
2949 __be32 op_immdlen;
2950 __be32 flowid_len16;
2951 __be64 cookie;
2952 __be16 iqid;
2953 __u8 tmo_val;
2954 __u8 use_xfer_cnt;
2955 union fw_scsi_read_priv {
2956 struct fcoe_read_priv {
2957 __u8 ctl_pri;
2958 __u8 cp_en_class;
2959 __u8 r3_lo[2];
2960 } fcoe;
2961 struct iscsi_read_priv {
2962 __u8 r3[4];
2963 } iscsi;
2964 } u;
2965 __be32 xfer_cnt;
2966 __be32 ini_xfer_cnt;
2967 __be64 rsp_dmaaddr;
2968 __be32 rsp_dmalen;
2969 __be32 r4;
2970 };
2971
2972 #define S_FW_SCSI_READ_WR_OPCODE 24
2973 #define M_FW_SCSI_READ_WR_OPCODE 0xff
2974 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE)
2975 #define G_FW_SCSI_READ_WR_OPCODE(x) \
2976 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
2977
2978 #define S_FW_SCSI_READ_WR_IMMDLEN 0
2979 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff
2980 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN)
2981 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \
2982 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
2983
2984 #define S_FW_SCSI_READ_WR_FLOWID 8
2985 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff
2986 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID)
2987 #define G_FW_SCSI_READ_WR_FLOWID(x) \
2988 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
2989
2990 #define S_FW_SCSI_READ_WR_LEN16 0
2991 #define M_FW_SCSI_READ_WR_LEN16 0xff
2992 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16)
2993 #define G_FW_SCSI_READ_WR_LEN16(x) \
2994 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
2995
2996 #define S_FW_SCSI_READ_WR_CP_EN 6
2997 #define M_FW_SCSI_READ_WR_CP_EN 0x3
2998 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN)
2999 #define G_FW_SCSI_READ_WR_CP_EN(x) \
3000 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
3001
3002 #define S_FW_SCSI_READ_WR_CLASS 4
3003 #define M_FW_SCSI_READ_WR_CLASS 0x3
3004 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS)
3005 #define G_FW_SCSI_READ_WR_CLASS(x) \
3006 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
3007
3008 struct fw_scsi_cmd_wr {
3009 __be32 op_immdlen;
3010 __be32 flowid_len16;
3011 __be64 cookie;
3012 __be16 iqid;
3013 __u8 tmo_val;
3014 __u8 r3;
3015 union fw_scsi_cmd_priv {
3016 struct fcoe_cmd_priv {
3017 __u8 ctl_pri;
3018 __u8 cp_en_class;
3019 __u8 r4_lo[2];
3020 } fcoe;
3021 struct iscsi_cmd_priv {
3022 __u8 r4[4];
3023 } iscsi;
3024 } u;
3025 __u8 r5[8];
3026 __be64 rsp_dmaaddr;
3027 __be32 rsp_dmalen;
3028 __be32 r6;
3029 };
3030
3031 #define S_FW_SCSI_CMD_WR_OPCODE 24
3032 #define M_FW_SCSI_CMD_WR_OPCODE 0xff
3033 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE)
3034 #define G_FW_SCSI_CMD_WR_OPCODE(x) \
3035 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
3036
3037 #define S_FW_SCSI_CMD_WR_IMMDLEN 0
3038 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff
3039 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
3040 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \
3041 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
3042
3043 #define S_FW_SCSI_CMD_WR_FLOWID 8
3044 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff
3045 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID)
3046 #define G_FW_SCSI_CMD_WR_FLOWID(x) \
3047 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
3048
3049 #define S_FW_SCSI_CMD_WR_LEN16 0
3050 #define M_FW_SCSI_CMD_WR_LEN16 0xff
3051 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16)
3052 #define G_FW_SCSI_CMD_WR_LEN16(x) \
3053 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
3054
3055 #define S_FW_SCSI_CMD_WR_CP_EN 6
3056 #define M_FW_SCSI_CMD_WR_CP_EN 0x3
3057 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN)
3058 #define G_FW_SCSI_CMD_WR_CP_EN(x) \
3059 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
3060
3061 #define S_FW_SCSI_CMD_WR_CLASS 4
3062 #define M_FW_SCSI_CMD_WR_CLASS 0x3
3063 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS)
3064 #define G_FW_SCSI_CMD_WR_CLASS(x) \
3065 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
3066
3067 struct fw_scsi_abrt_cls_wr {
3068 __be32 op_immdlen;
3069 __be32 flowid_len16;
3070 __be64 cookie;
3071 __be16 iqid;
3072 __u8 tmo_val;
3073 __u8 sub_opcode_to_chk_all_io;
3074 __u8 r3[4];
3075 __be64 t_cookie;
3076 };
3077
3078 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24
3079 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff
3080 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
3081 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \
3082 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
3083
3084 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0
3085 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff
3086 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
3087 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3088 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \
3089 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
3090
3091 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8
3092 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff
3093 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
3094 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \
3095 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
3096
3097 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0
3098 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff
3099 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
3100 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \
3101 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
3102
3103 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2
3104 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f
3105 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
3106 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3107 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \
3108 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
3109 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
3110
3111 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1
3112 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1
3113 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
3114 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \
3115 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
3116 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
3117
3118 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0
3119 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1
3120 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
3121 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3122 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \
3123 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
3124 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
3125 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \
3126 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
3127
3128 struct fw_scsi_tgt_acc_wr {
3129 __be32 op_immdlen;
3130 __be32 flowid_len16;
3131 __be64 cookie;
3132 __be16 iqid;
3133 __u8 r3;
3134 __u8 use_burst_len;
3135 union fw_scsi_tgt_acc_priv {
3136 struct fcoe_tgt_acc_priv {
3137 __u8 ctl_pri;
3138 __u8 cp_en_class;
3139 __u8 r4_lo[2];
3140 } fcoe;
3141 struct iscsi_tgt_acc_priv {
3142 __u8 r4[4];
3143 } iscsi;
3144 } u;
3145 __be32 burst_len;
3146 __be32 rel_off;
3147 __be64 r5;
3148 __be32 r6;
3149 __be32 tot_xfer_len;
3150 };
3151
3152 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24
3153 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff
3154 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
3155 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \
3156 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
3157
3158 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0
3159 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff
3160 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3161 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \
3162 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
3163
3164 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8
3165 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff
3166 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
3167 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \
3168 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
3169
3170 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0
3171 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff
3172 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
3173 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \
3174 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
3175
3176 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6
3177 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3
3178 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
3179 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \
3180 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
3181
3182 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4
3183 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3
3184 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
3185 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \
3186 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
3187
3188 struct fw_scsi_tgt_xmit_wr {
3189 __be32 op_immdlen;
3190 __be32 flowid_len16;
3191 __be64 cookie;
3192 __be16 iqid;
3193 __u8 auto_rsp;
3194 __u8 use_xfer_cnt;
3195 union fw_scsi_tgt_xmit_priv {
3196 struct fcoe_tgt_xmit_priv {
3197 __u8 ctl_pri;
3198 __u8 cp_en_class;
3199 __u8 r3_lo[2];
3200 } fcoe;
3201 struct iscsi_tgt_xmit_priv {
3202 __u8 r3[4];
3203 } iscsi;
3204 } u;
3205 __be32 xfer_cnt;
3206 __be32 r4;
3207 __be64 r5;
3208 __be32 r6;
3209 __be32 tot_xfer_len;
3210 };
3211
3212 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24
3213 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff
3214 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
3215 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \
3216 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
3217
3218 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0
3219 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff
3220 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
3221 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3222 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \
3223 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
3224
3225 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8
3226 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff
3227 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
3228 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \
3229 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
3230
3231 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0
3232 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff
3233 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
3234 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \
3235 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
3236
3237 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6
3238 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3
3239 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
3240 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \
3241 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
3242
3243 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4
3244 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3
3245 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
3246 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \
3247 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
3248
3249 struct fw_scsi_tgt_rsp_wr {
3250 __be32 op_immdlen;
3251 __be32 flowid_len16;
3252 __be64 cookie;
3253 __be16 iqid;
3254 __u8 r3[2];
3255 union fw_scsi_tgt_rsp_priv {
3256 struct fcoe_tgt_rsp_priv {
3257 __u8 ctl_pri;
3258 __u8 cp_en_class;
3259 __u8 r4_lo[2];
3260 } fcoe;
3261 struct iscsi_tgt_rsp_priv {
3262 __u8 r4[4];
3263 } iscsi;
3264 } u;
3265 __u8 r5[8];
3266 };
3267
3268 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24
3269 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff
3270 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
3271 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \
3272 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
3273
3274 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0
3275 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff
3276 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3277 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \
3278 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
3279
3280 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8
3281 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff
3282 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
3283 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \
3284 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
3285
3286 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0
3287 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff
3288 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
3289 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \
3290 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
3291
3292 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6
3293 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3
3294 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
3295 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \
3296 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
3297
3298 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4
3299 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3
3300 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
3301 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \
3302 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
3303
3304 struct fw_pofcoe_tcb_wr {
3305 __be32 op_compl;
3306 __be32 equiq_to_len16;
3307 __be32 r4;
3308 __be32 xfer_len;
3309 __be32 tid_to_port;
3310 __be16 x_id;
3311 __be16 vlan_id;
3312 __be64 cookie;
3313 __be32 s_id;
3314 __be32 d_id;
3315 __be32 tag;
3316 __be16 r6;
3317 __be16 iqid;
3318 };
3319
3320 #define S_FW_POFCOE_TCB_WR_TID 12
3321 #define M_FW_POFCOE_TCB_WR_TID 0xfffff
3322 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID)
3323 #define G_FW_POFCOE_TCB_WR_TID(x) \
3324 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
3325
3326 #define S_FW_POFCOE_TCB_WR_ALLOC 4
3327 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1
3328 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC)
3329 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \
3330 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
3331 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U)
3332
3333 #define S_FW_POFCOE_TCB_WR_FREE 3
3334 #define M_FW_POFCOE_TCB_WR_FREE 0x1
3335 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE)
3336 #define G_FW_POFCOE_TCB_WR_FREE(x) \
3337 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
3338 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U)
3339
3340 #define S_FW_POFCOE_TCB_WR_PORT 0
3341 #define M_FW_POFCOE_TCB_WR_PORT 0x7
3342 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT)
3343 #define G_FW_POFCOE_TCB_WR_PORT(x) \
3344 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
3345
3346 struct fw_pofcoe_ulptx_wr {
3347 __be32 op_pkd;
3348 __be32 equiq_to_len16;
3349 __u64 cookie;
3350 };
3351
3352 /*******************************************************************
3353 * T10 DIF related definition
3354 *******************************************************************/
3355 struct fw_tx_pi_header {
3356 __be16 op_to_inline;
3357 __u8 pi_interval_tag_type;
3358 __u8 num_pi;
3359 __be32 pi_start4_pi_end4;
3360 __u8 tag_gen_enabled_pkd;
3361 __u8 num_pi_dsg;
3362 __be16 app_tag;
3363 __be32 ref_tag;
3364 };
3365
3366 #define S_FW_TX_PI_HEADER_OP 8
3367 #define M_FW_TX_PI_HEADER_OP 0xff
3368 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP)
3369 #define G_FW_TX_PI_HEADER_OP(x) \
3370 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP)
3371
3372 #define S_FW_TX_PI_HEADER_ULPTXMORE 7
3373 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1
3374 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE)
3375 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \
3376 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE)
3377 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U)
3378
3379 #define S_FW_TX_PI_HEADER_PI_CONTROL 4
3380 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7
3381 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL)
3382 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \
3383 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL)
3384
3385 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2
3386 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1
3387 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE)
3388 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \
3389 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE)
3390 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U)
3391
3392 #define S_FW_TX_PI_HEADER_VALIDATE 1
3393 #define M_FW_TX_PI_HEADER_VALIDATE 0x1
3394 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE)
3395 #define G_FW_TX_PI_HEADER_VALIDATE(x) \
3396 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE)
3397 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U)
3398
3399 #define S_FW_TX_PI_HEADER_INLINE 0
3400 #define M_FW_TX_PI_HEADER_INLINE 0x1
3401 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE)
3402 #define G_FW_TX_PI_HEADER_INLINE(x) \
3403 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE)
3404 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U)
3405
3406 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7
3407 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1
3408 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \
3409 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL)
3410 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \
3411 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL)
3412 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U)
3413
3414 #define S_FW_TX_PI_HEADER_TAG_TYPE 5
3415 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3
3416 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE)
3417 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \
3418 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE)
3419
3420 #define S_FW_TX_PI_HEADER_PI_START4 22
3421 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff
3422 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4)
3423 #define G_FW_TX_PI_HEADER_PI_START4(x) \
3424 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4)
3425
3426 #define S_FW_TX_PI_HEADER_PI_END4 0
3427 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff
3428 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4)
3429 #define G_FW_TX_PI_HEADER_PI_END4(x) \
3430 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4)
3431
3432 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6
3433 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3
3434 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \
3435 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3436 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \
3437 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \
3438 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
3439
3440 enum fw_pi_error_type {
3441 FW_PI_ERROR_GUARD_CHECK_FAILED = 0,
3442 };
3443
3444 struct fw_pi_error {
3445 __be32 err_type_pkd;
3446 __be32 flowid_len16;
3447 __be16 r2;
3448 __be16 app_tag;
3449 __be32 ref_tag;
3450 __be32 pisc[4];
3451 };
3452
3453 #define S_FW_PI_ERROR_ERR_TYPE 24
3454 #define M_FW_PI_ERROR_ERR_TYPE 0xff
3455 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE)
3456 #define G_FW_PI_ERROR_ERR_TYPE(x) \
3457 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
3458
3459 struct fw_tlstx_data_wr {
3460 __be32 op_to_immdlen;
3461 __be32 flowid_len16;
3462 __be32 plen;
3463 __be32 lsodisable_to_flags;
3464 __be32 r5;
3465 __be32 ctxloc_to_exp;
3466 __be16 mfs;
3467 __be16 adjustedplen_pkd;
3468 __be16 expinplenmax_pkd;
3469 __u8 pdusinplenmax_pkd;
3470 __u8 r10;
3471 };
3472
3473 #define S_FW_TLSTX_DATA_WR_OPCODE 24
3474 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff
3475 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE)
3476 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \
3477 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE)
3478
3479 #define S_FW_TLSTX_DATA_WR_COMPL 21
3480 #define M_FW_TLSTX_DATA_WR_COMPL 0x1
3481 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL)
3482 #define G_FW_TLSTX_DATA_WR_COMPL(x) \
3483 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL)
3484 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U)
3485
3486 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0
3487 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff
3488 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN)
3489 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \
3490 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN)
3491
3492 #define S_FW_TLSTX_DATA_WR_FLOWID 8
3493 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff
3494 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID)
3495 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \
3496 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID)
3497
3498 #define S_FW_TLSTX_DATA_WR_LEN16 0
3499 #define M_FW_TLSTX_DATA_WR_LEN16 0xff
3500 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16)
3501 #define G_FW_TLSTX_DATA_WR_LEN16(x) \
3502 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16)
3503
3504 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31
3505 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1
3506 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3507 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE)
3508 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \
3509 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE)
3510 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U)
3511
3512 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30
3513 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1
3514 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD)
3515 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \
3516 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD)
3517 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U)
3518
3519 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29
3520 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1
3521 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3522 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3523 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
3524 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \
3525 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
3526 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U)
3527
3528 #define S_FW_TLSTX_DATA_WR_FLAGS 0
3529 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff
3530 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS)
3531 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \
3532 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS)
3533
3534 #define S_FW_TLSTX_DATA_WR_CTXLOC 30
3535 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3
3536 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC)
3537 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \
3538 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC)
3539
3540 #define S_FW_TLSTX_DATA_WR_IVDSGL 29
3541 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1
3542 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL)
3543 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \
3544 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL)
3545 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U)
3546
3547 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24
3548 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f
3549 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE)
3550 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \
3551 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE)
3552
3553 #define S_FW_TLSTX_DATA_WR_NUMIVS 14
3554 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff
3555 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS)
3556 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \
3557 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS)
3558
3559 #define S_FW_TLSTX_DATA_WR_EXP 0
3560 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff
3561 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP)
3562 #define G_FW_TLSTX_DATA_WR_EXP(x) \
3563 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)
3564
3565 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1
3566 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff
3567 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3568 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3569 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
3570 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \
3571 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
3572
3573 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4
3574 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff
3575 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3576 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3577 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
3578 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \
3579 M_FW_TLSTX_DATA_WR_EXPINPLENMAX)
3580
3581 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2
3582 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f
3583 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3584 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3585 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
3586 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \
3587 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
3588
3589 struct fw_tls_keyctx_tx_wr {
3590 __be32 op_to_compl;
3591 __be32 flowid_len16;
3592 union fw_key_ctx {
3593 struct fw_tx_keyctx_hdr {
3594 __u8 ctxlen;
3595 __u8 r2;
3596 __be16 dualck_to_txvalid;
3597 __u8 txsalt[4];
3598 __be64 r5;
3599 } txhdr;
3600 struct fw_rx_keyctx_hdr {
3601 __u8 flitcnt_hmacctrl;
3602 __u8 protover_ciphmode;
3603 __u8 authmode_to_rxvalid;
3604 __u8 ivpresent_to_rxmk_size;
3605 __u8 rxsalt[4];
3606 __be64 ivinsert_to_authinsrt;
3607 } rxhdr;
3608 struct fw_keyctx_clear {
3609 __be32 tx_key;
3610 __be32 rx_key;
3611 } kctx_clr;
3612 } u;
3613 struct keys {
3614 __u8 edkey[32];
3615 __u8 ipad[64];
3616 __u8 opad[64];
3617 } keys;
3618 __u8 reneg_to_write_rx;
3619 __u8 protocol;
3620 __be16 mfs;
3621 __be32 ftid;
3622 };
3623
3624 #define S_FW_TLS_KEYCTX_TX_WR_OPCODE 24
3625 #define M_FW_TLS_KEYCTX_TX_WR_OPCODE 0xff
3626 #define V_FW_TLS_KEYCTX_TX_WR_OPCODE(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_OPCODE)
3627 #define G_FW_TLS_KEYCTX_TX_WR_OPCODE(x) \
3628 (((x) >> S_FW_TLS_KEYCTX_TX_WR_OPCODE) & M_FW_TLS_KEYCTX_TX_WR_OPCODE)
3629
3630 #define S_FW_TLS_KEYCTX_TX_WR_ATOMIC 23
3631 #define M_FW_TLS_KEYCTX_TX_WR_ATOMIC 0x1
3632 #define V_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_ATOMIC)
3633 #define G_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) \
3634 (((x) >> S_FW_TLS_KEYCTX_TX_WR_ATOMIC) & M_FW_TLS_KEYCTX_TX_WR_ATOMIC)
3635 #define F_FW_TLS_KEYCTX_TX_WR_ATOMIC V_FW_TLS_KEYCTX_TX_WR_ATOMIC(1U)
3636
3637 #define S_FW_TLS_KEYCTX_TX_WR_FLUSH 22
3638 #define M_FW_TLS_KEYCTX_TX_WR_FLUSH 0x1
3639 #define V_FW_TLS_KEYCTX_TX_WR_FLUSH(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLUSH)
3640 #define G_FW_TLS_KEYCTX_TX_WR_FLUSH(x) \
3641 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLUSH) & M_FW_TLS_KEYCTX_TX_WR_FLUSH)
3642 #define F_FW_TLS_KEYCTX_TX_WR_FLUSH V_FW_TLS_KEYCTX_TX_WR_FLUSH(1U)
3643
3644 #define S_FW_TLS_KEYCTX_TX_WR_COMPL 21
3645 #define M_FW_TLS_KEYCTX_TX_WR_COMPL 0x1
3646 #define V_FW_TLS_KEYCTX_TX_WR_COMPL(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_COMPL)
3647 #define G_FW_TLS_KEYCTX_TX_WR_COMPL(x) \
3648 (((x) >> S_FW_TLS_KEYCTX_TX_WR_COMPL) & M_FW_TLS_KEYCTX_TX_WR_COMPL)
3649 #define F_FW_TLS_KEYCTX_TX_WR_COMPL V_FW_TLS_KEYCTX_TX_WR_COMPL(1U)
3650
3651 #define S_FW_TLS_KEYCTX_TX_WR_FLOWID 8
3652 #define M_FW_TLS_KEYCTX_TX_WR_FLOWID 0xfffff
3653 #define V_FW_TLS_KEYCTX_TX_WR_FLOWID(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLOWID)
3654 #define G_FW_TLS_KEYCTX_TX_WR_FLOWID(x) \
3655 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLOWID) & M_FW_TLS_KEYCTX_TX_WR_FLOWID)
3656
3657 #define S_FW_TLS_KEYCTX_TX_WR_LEN16 0
3658 #define M_FW_TLS_KEYCTX_TX_WR_LEN16 0xff
3659 #define V_FW_TLS_KEYCTX_TX_WR_LEN16(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_LEN16)
3660 #define G_FW_TLS_KEYCTX_TX_WR_LEN16(x) \
3661 (((x) >> S_FW_TLS_KEYCTX_TX_WR_LEN16) & M_FW_TLS_KEYCTX_TX_WR_LEN16)
3662
3663 #define S_FW_TLS_KEYCTX_TX_WR_DUALCK 12
3664 #define M_FW_TLS_KEYCTX_TX_WR_DUALCK 0x1
3665 #define V_FW_TLS_KEYCTX_TX_WR_DUALCK(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_DUALCK)
3666 #define G_FW_TLS_KEYCTX_TX_WR_DUALCK(x) \
3667 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DUALCK) & M_FW_TLS_KEYCTX_TX_WR_DUALCK)
3668 #define F_FW_TLS_KEYCTX_TX_WR_DUALCK V_FW_TLS_KEYCTX_TX_WR_DUALCK(1U)
3669
3670 #define S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 11
3671 #define M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 0x1
3672 #define V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \
3673 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT)
3674 #define G_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \
3675 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) & \
3676 M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT)
3677 #define F_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT \
3678 V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(1U)
3679
3680 #define S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 10
3681 #define M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 0x1
3682 #define V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \
3683 ((x) << S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT)
3684 #define G_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \
3685 (((x) >> S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) & \
3686 M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT)
3687 #define F_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT \
3688 V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(1U)
3689
3690 #define S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 6
3691 #define M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 0xf
3692 #define V_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \
3693 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE)
3694 #define G_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \
3695 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) & \
3696 M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE)
3697
3698 #define S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 2
3699 #define M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 0xf
3700 #define V_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \
3701 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE)
3702 #define G_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \
3703 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) & \
3704 M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE)
3705
3706 #define S_FW_TLS_KEYCTX_TX_WR_TXVALID 0
3707 #define M_FW_TLS_KEYCTX_TX_WR_TXVALID 0x1
3708 #define V_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \
3709 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXVALID)
3710 #define G_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \
3711 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXVALID) & M_FW_TLS_KEYCTX_TX_WR_TXVALID)
3712 #define F_FW_TLS_KEYCTX_TX_WR_TXVALID V_FW_TLS_KEYCTX_TX_WR_TXVALID(1U)
3713
3714 #define S_FW_TLS_KEYCTX_TX_WR_FLITCNT 3
3715 #define M_FW_TLS_KEYCTX_TX_WR_FLITCNT 0x1f
3716 #define V_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \
3717 ((x) << S_FW_TLS_KEYCTX_TX_WR_FLITCNT)
3718 #define G_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \
3719 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLITCNT) & M_FW_TLS_KEYCTX_TX_WR_FLITCNT)
3720
3721 #define S_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0
3722 #define M_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0x7
3723 #define V_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \
3724 ((x) << S_FW_TLS_KEYCTX_TX_WR_HMACCTRL)
3725 #define G_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \
3726 (((x) >> S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) & M_FW_TLS_KEYCTX_TX_WR_HMACCTRL)
3727
3728 #define S_FW_TLS_KEYCTX_TX_WR_PROTOVER 4
3729 #define M_FW_TLS_KEYCTX_TX_WR_PROTOVER 0xf
3730 #define V_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \
3731 ((x) << S_FW_TLS_KEYCTX_TX_WR_PROTOVER)
3732 #define G_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \
3733 (((x) >> S_FW_TLS_KEYCTX_TX_WR_PROTOVER) & M_FW_TLS_KEYCTX_TX_WR_PROTOVER)
3734
3735 #define S_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0
3736 #define M_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0xf
3737 #define V_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \
3738 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHMODE)
3739 #define G_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \
3740 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) & M_FW_TLS_KEYCTX_TX_WR_CIPHMODE)
3741
3742 #define S_FW_TLS_KEYCTX_TX_WR_AUTHMODE 4
3743 #define M_FW_TLS_KEYCTX_TX_WR_AUTHMODE 0xf
3744 #define V_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \
3745 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHMODE)
3746 #define G_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \
3747 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) & M_FW_TLS_KEYCTX_TX_WR_AUTHMODE)
3748
3749 #define S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 3
3750 #define M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 0x1
3751 #define V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \
3752 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL)
3753 #define G_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \
3754 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) & \
3755 M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL)
3756 #define F_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL \
3757 V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(1U)
3758
3759 #define S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 1
3760 #define M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 0x3
3761 #define V_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \
3762 ((x) << S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL)
3763 #define G_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \
3764 (((x) >> S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) & \
3765 M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL)
3766
3767 #define S_FW_TLS_KEYCTX_TX_WR_RXVALID 0
3768 #define M_FW_TLS_KEYCTX_TX_WR_RXVALID 0x1
3769 #define V_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \
3770 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXVALID)
3771 #define G_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \
3772 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXVALID) & M_FW_TLS_KEYCTX_TX_WR_RXVALID)
3773 #define F_FW_TLS_KEYCTX_TX_WR_RXVALID V_FW_TLS_KEYCTX_TX_WR_RXVALID(1U)
3774
3775 #define S_FW_TLS_KEYCTX_TX_WR_IVPRESENT 7
3776 #define M_FW_TLS_KEYCTX_TX_WR_IVPRESENT 0x1
3777 #define V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \
3778 ((x) << S_FW_TLS_KEYCTX_TX_WR_IVPRESENT)
3779 #define G_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \
3780 (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) & \
3781 M_FW_TLS_KEYCTX_TX_WR_IVPRESENT)
3782 #define F_FW_TLS_KEYCTX_TX_WR_IVPRESENT V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(1U)
3783
3784 #define S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 6
3785 #define M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 0x1
3786 #define V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \
3787 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT)
3788 #define G_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \
3789 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) & \
3790 M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT)
3791 #define F_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT \
3792 V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(1U)
3793
3794 #define S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 3
3795 #define M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7
3796 #define V_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \
3797 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE)
3798 #define G_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \
3799 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) & \
3800 M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE)
3801
3802 #define S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0
3803 #define M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7
3804 #define V_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \
3805 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE)
3806 #define G_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \
3807 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) & \
3808 M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE)
3809
3810 #define S_FW_TLS_KEYCTX_TX_WR_IVINSERT 55
3811 #define M_FW_TLS_KEYCTX_TX_WR_IVINSERT 0x1ffULL
3812 #define V_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \
3813 ((x) << S_FW_TLS_KEYCTX_TX_WR_IVINSERT)
3814 #define G_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \
3815 (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVINSERT) & M_FW_TLS_KEYCTX_TX_WR_IVINSERT)
3816
3817 #define S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 47
3818 #define M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 0xffULL
3819 #define V_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \
3820 ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST)
3821 #define G_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \
3822 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) & \
3823 M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST)
3824
3825 #define S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 39
3826 #define M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 0xffULL
3827 #define V_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \
3828 ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST)
3829 #define G_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \
3830 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) & \
3831 M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST)
3832
3833 #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 30
3834 #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 0x1ffULL
3835 #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \
3836 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST)
3837 #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \
3838 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) & \
3839 M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST)
3840
3841 #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 23
3842 #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 0x7f
3843 #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \
3844 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST)
3845 #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \
3846 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) & \
3847 M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST)
3848
3849 #define S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 14
3850 #define M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 0x1ff
3851 #define V_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \
3852 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST)
3853 #define G_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \
3854 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) & \
3855 M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST)
3856
3857 #define S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 7
3858 #define M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 0x7f
3859 #define V_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \
3860 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST)
3861 #define G_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \
3862 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) & \
3863 M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST)
3864
3865 #define S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0
3866 #define M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0x7f
3867 #define V_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \
3868 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT)
3869 #define G_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \
3870 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) & \
3871 M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT)
3872
3873 #define S_FW_TLS_KEYCTX_TX_WR_RENEG 4
3874 #define M_FW_TLS_KEYCTX_TX_WR_RENEG 0x1
3875 #define V_FW_TLS_KEYCTX_TX_WR_RENEG(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_RENEG)
3876 #define G_FW_TLS_KEYCTX_TX_WR_RENEG(x) \
3877 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RENEG) & M_FW_TLS_KEYCTX_TX_WR_RENEG)
3878 #define F_FW_TLS_KEYCTX_TX_WR_RENEG V_FW_TLS_KEYCTX_TX_WR_RENEG(1U)
3879
3880 #define S_FW_TLS_KEYCTX_TX_WR_DELETE_TX 3
3881 #define M_FW_TLS_KEYCTX_TX_WR_DELETE_TX 0x1
3882 #define V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \
3883 ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_TX)
3884 #define G_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \
3885 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) & \
3886 M_FW_TLS_KEYCTX_TX_WR_DELETE_TX)
3887 #define F_FW_TLS_KEYCTX_TX_WR_DELETE_TX V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(1U)
3888
3889 #define S_FW_TLS_KEYCTX_TX_WR_DELETE_RX 2
3890 #define M_FW_TLS_KEYCTX_TX_WR_DELETE_RX 0x1
3891 #define V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \
3892 ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_RX)
3893 #define G_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \
3894 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) & \
3895 M_FW_TLS_KEYCTX_TX_WR_DELETE_RX)
3896 #define F_FW_TLS_KEYCTX_TX_WR_DELETE_RX V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(1U)
3897
3898 #define S_FW_TLS_KEYCTX_TX_WR_WRITE_TX 1
3899 #define M_FW_TLS_KEYCTX_TX_WR_WRITE_TX 0x1
3900 #define V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \
3901 ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_TX)
3902 #define G_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \
3903 (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_TX)
3904 #define F_FW_TLS_KEYCTX_TX_WR_WRITE_TX V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(1U)
3905
3906 #define S_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0
3907 #define M_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0x1
3908 #define V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \
3909 ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_RX)
3910 #define G_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \
3911 (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_RX)
3912 #define F_FW_TLS_KEYCTX_TX_WR_WRITE_RX V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(1U)
3913
3914 struct fw_crypto_lookaside_wr {
3915 __be32 op_to_cctx_size;
3916 __be32 len16_pkd;
3917 __be32 session_id;
3918 __be32 rx_chid_to_rx_q_id;
3919 __be32 key_addr;
3920 __be32 pld_size_hash_size;
3921 __be64 cookie;
3922 };
3923
3924 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24
3925 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff
3926 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3927 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3928 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
3929 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \
3930 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
3931
3932 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23
3933 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1
3934 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
3935 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL)
3936 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
3937 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \
3938 M_FW_CRYPTO_LOOKASIDE_WR_COMPL)
3939 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U)
3940
3941 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15
3942 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff
3943 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
3944 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
3945 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
3946 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \
3947 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
3948
3949 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5
3950 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3
3951 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
3952 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
3953 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
3954 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \
3955 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
3956
3957 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0
3958 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f
3959 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
3960 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
3961 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
3962 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \
3963 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
3964
3965 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0
3966 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff
3967 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
3968 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16)
3969 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
3970 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \
3971 M_FW_CRYPTO_LOOKASIDE_WR_LEN16)
3972
3973 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29
3974 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3
3975 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
3976 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
3977 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
3978 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \
3979 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
3980
3981 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27
3982 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3
3983 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
3984 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB)
3985 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
3986 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB)
3987
3988 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25
3989 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3
3990 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
3991 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH)
3992 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
3993 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \
3994 M_FW_CRYPTO_LOOKASIDE_WR_PHASH)
3995
3996 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23
3997 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3
3998 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
3999 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV)
4000 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
4001 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)
4002
4003 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15
4004 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff
4005 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
4006 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
4007 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
4008 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\
4009 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
4010
4011 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10
4012 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3
4013 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
4014 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
4015 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
4016 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \
4017 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
4018
4019 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0
4020 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff
4021 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
4022 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
4023 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
4024 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \
4025 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
4026
4027 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24
4028 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff
4029 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
4030 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
4031 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
4032 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \
4033 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
4034
4035 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17
4036 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f
4037 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
4038 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
4039 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
4040 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \
4041 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
4042
4043 /******************************************************************************
4044 * C O M M A N D s
4045 *********************/
4046
4047 /*
4048 * The maximum length of time, in miliseconds, that we expect any firmware
4049 * command to take to execute and return a reply to the host. The RESET
4050 * and INITIALIZE commands can take a fair amount of time to execute but
4051 * most execute in far less time than this maximum. This constant is used
4052 * by host software to determine how long to wait for a firmware command
4053 * reply before declaring the firmware as dead/unreachable ...
4054 */
4055 #define FW_CMD_MAX_TIMEOUT 10000
4056
4057 /*
4058 * If a host driver does a HELLO and discovers that there's already a MASTER
4059 * selected, we may have to wait for that MASTER to finish issuing RESET,
4060 * configuration and INITIALIZE commands. Also, there's a possibility that
4061 * our own HELLO may get lost if it happens right as the MASTER is issuign a
4062 * RESET command, so we need to be willing to make a few retries of our HELLO.
4063 */
4064 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
4065 #define FW_CMD_HELLO_RETRIES 3
4066
4067 enum fw_cmd_opcodes {
4068 FW_LDST_CMD = 0x01,
4069 FW_RESET_CMD = 0x03,
4070 FW_HELLO_CMD = 0x04,
4071 FW_BYE_CMD = 0x05,
4072 FW_INITIALIZE_CMD = 0x06,
4073 FW_CAPS_CONFIG_CMD = 0x07,
4074 FW_PARAMS_CMD = 0x08,
4075 FW_PFVF_CMD = 0x09,
4076 FW_IQ_CMD = 0x10,
4077 FW_EQ_MNGT_CMD = 0x11,
4078 FW_EQ_ETH_CMD = 0x12,
4079 FW_EQ_CTRL_CMD = 0x13,
4080 FW_EQ_OFLD_CMD = 0x21,
4081 FW_VI_CMD = 0x14,
4082 FW_VI_MAC_CMD = 0x15,
4083 FW_VI_RXMODE_CMD = 0x16,
4084 FW_VI_ENABLE_CMD = 0x17,
4085 FW_VI_STATS_CMD = 0x1a,
4086 FW_ACL_MAC_CMD = 0x18,
4087 FW_ACL_VLAN_CMD = 0x19,
4088 FW_PORT_CMD = 0x1b,
4089 FW_PORT_STATS_CMD = 0x1c,
4090 FW_PORT_LB_STATS_CMD = 0x1d,
4091 FW_PORT_TRACE_CMD = 0x1e,
4092 FW_PORT_TRACE_MMAP_CMD = 0x1f,
4093 FW_RSS_IND_TBL_CMD = 0x20,
4094 FW_RSS_GLB_CONFIG_CMD = 0x22,
4095 FW_RSS_VI_CONFIG_CMD = 0x23,
4096 FW_SCHED_CMD = 0x24,
4097 FW_DEVLOG_CMD = 0x25,
4098 FW_WATCHDOG_CMD = 0x27,
4099 FW_CLIP_CMD = 0x28,
4100 FW_CHNET_IFACE_CMD = 0x26,
4101 FW_FCOE_RES_INFO_CMD = 0x31,
4102 FW_FCOE_LINK_CMD = 0x32,
4103 FW_FCOE_VNP_CMD = 0x33,
4104 FW_FCOE_SPARAMS_CMD = 0x35,
4105 FW_FCOE_STATS_CMD = 0x37,
4106 FW_FCOE_FCF_CMD = 0x38,
4107 FW_DCB_IEEE_CMD = 0x3a,
4108 FW_DIAG_CMD = 0x3d,
4109 FW_PTP_CMD = 0x3e,
4110 FW_LASTC2E_CMD = 0x40,
4111 FW_ERROR_CMD = 0x80,
4112 FW_DEBUG_CMD = 0x81,
4113 };
4114
4115 enum fw_cmd_cap {
4116 FW_CMD_CAP_PF = 0x01,
4117 FW_CMD_CAP_DMAQ = 0x02,
4118 FW_CMD_CAP_PORT = 0x04,
4119 FW_CMD_CAP_PORTPROMISC = 0x08,
4120 FW_CMD_CAP_PORTSTATS = 0x10,
4121 FW_CMD_CAP_VF = 0x80,
4122 };
4123
4124 /*
4125 * Generic command header flit0
4126 */
4127 struct fw_cmd_hdr {
4128 __be32 hi;
4129 __be32 lo;
4130 };
4131
4132 #define S_FW_CMD_OP 24
4133 #define M_FW_CMD_OP 0xff
4134 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP)
4135 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
4136
4137 #define S_FW_CMD_REQUEST 23
4138 #define M_FW_CMD_REQUEST 0x1
4139 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST)
4140 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
4141 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U)
4142
4143 #define S_FW_CMD_READ 22
4144 #define M_FW_CMD_READ 0x1
4145 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ)
4146 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
4147 #define F_FW_CMD_READ V_FW_CMD_READ(1U)
4148
4149 #define S_FW_CMD_WRITE 21
4150 #define M_FW_CMD_WRITE 0x1
4151 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE)
4152 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
4153 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U)
4154
4155 #define S_FW_CMD_EXEC 20
4156 #define M_FW_CMD_EXEC 0x1
4157 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC)
4158 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
4159 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U)
4160
4161 #define S_FW_CMD_RAMASK 20
4162 #define M_FW_CMD_RAMASK 0xf
4163 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK)
4164 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
4165
4166 #define S_FW_CMD_RETVAL 8
4167 #define M_FW_CMD_RETVAL 0xff
4168 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL)
4169 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
4170
4171 #define S_FW_CMD_LEN16 0
4172 #define M_FW_CMD_LEN16 0xff
4173 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16)
4174 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
4175
4176 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
4177
4178 /*
4179 * address spaces
4180 */
4181 enum fw_ldst_addrspc {
4182 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
4183 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
4184 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
4185 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
4186 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
4187 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
4188 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
4189 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
4190 FW_LDST_ADDRSPC_MDIO = 0x0018,
4191 FW_LDST_ADDRSPC_MPS = 0x0020,
4192 FW_LDST_ADDRSPC_FUNC = 0x0028,
4193 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
4194 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */
4195 FW_LDST_ADDRSPC_LE = 0x0030,
4196 FW_LDST_ADDRSPC_I2C = 0x0038,
4197 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
4198 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041,
4199 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042,
4200 FW_LDST_ADDRSPC_CIM_Q = 0x0048,
4201 };
4202
4203 /*
4204 * MDIO VSC8634 register access control field
4205 */
4206 enum fw_ldst_mdio_vsc8634_aid {
4207 FW_LDST_MDIO_VS_STANDARD,
4208 FW_LDST_MDIO_VS_EXTENDED,
4209 FW_LDST_MDIO_VS_GPIO
4210 };
4211
4212 enum fw_ldst_mps_fid {
4213 FW_LDST_MPS_ATRB,
4214 FW_LDST_MPS_RPLC
4215 };
4216
4217 enum fw_ldst_func_access_ctl {
4218 FW_LDST_FUNC_ACC_CTL_VIID,
4219 FW_LDST_FUNC_ACC_CTL_FID
4220 };
4221
4222 enum fw_ldst_func_mod_index {
4223 FW_LDST_FUNC_MPS
4224 };
4225
4226 struct fw_ldst_cmd {
4227 __be32 op_to_addrspace;
4228 __be32 cycles_to_len16;
4229 union fw_ldst {
4230 struct fw_ldst_addrval {
4231 __be32 addr;
4232 __be32 val;
4233 } addrval;
4234 struct fw_ldst_idctxt {
4235 __be32 physid;
4236 __be32 msg_ctxtflush;
4237 __be32 ctxt_data7;
4238 __be32 ctxt_data6;
4239 __be32 ctxt_data5;
4240 __be32 ctxt_data4;
4241 __be32 ctxt_data3;
4242 __be32 ctxt_data2;
4243 __be32 ctxt_data1;
4244 __be32 ctxt_data0;
4245 } idctxt;
4246 struct fw_ldst_mdio {
4247 __be16 paddr_mmd;
4248 __be16 raddr;
4249 __be16 vctl;
4250 __be16 rval;
4251 } mdio;
4252 struct fw_ldst_cim_rq {
4253 __u8 req_first64[8];
4254 __u8 req_second64[8];
4255 __u8 resp_first64[8];
4256 __u8 resp_second64[8];
4257 __be32 r3[2];
4258 } cim_rq;
4259 union fw_ldst_mps {
4260 struct fw_ldst_mps_rplc {
4261 __be16 fid_idx;
4262 __be16 rplcpf_pkd;
4263 __be32 rplc255_224;
4264 __be32 rplc223_192;
4265 __be32 rplc191_160;
4266 __be32 rplc159_128;
4267 __be32 rplc127_96;
4268 __be32 rplc95_64;
4269 __be32 rplc63_32;
4270 __be32 rplc31_0;
4271 } rplc;
4272 struct fw_ldst_mps_atrb {
4273 __be16 fid_mpsid;
4274 __be16 r2[3];
4275 __be32 r3[2];
4276 __be32 r4;
4277 __be32 atrb;
4278 __be16 vlan[16];
4279 } atrb;
4280 } mps;
4281 struct fw_ldst_func {
4282 __u8 access_ctl;
4283 __u8 mod_index;
4284 __be16 ctl_id;
4285 __be32 offset;
4286 __be64 data0;
4287 __be64 data1;
4288 } func;
4289 struct fw_ldst_pcie {
4290 __u8 ctrl_to_fn;
4291 __u8 bnum;
4292 __u8 r;
4293 __u8 ext_r;
4294 __u8 select_naccess;
4295 __u8 pcie_fn;
4296 __be16 nset_pkd;
4297 __be32 data[12];
4298 } pcie;
4299 struct fw_ldst_i2c_deprecated {
4300 __u8 pid_pkd;
4301 __u8 base;
4302 __u8 boffset;
4303 __u8 data;
4304 __be32 r9;
4305 } i2c_deprecated;
4306 struct fw_ldst_i2c {
4307 __u8 pid;
4308 __u8 did;
4309 __u8 boffset;
4310 __u8 blen;
4311 __be32 r9;
4312 __u8 data[48];
4313 } i2c;
4314 struct fw_ldst_le {
4315 __be32 index;
4316 __be32 r9;
4317 __u8 val[33];
4318 __u8 r11[7];
4319 } le;
4320 } u;
4321 };
4322
4323 #define S_FW_LDST_CMD_ADDRSPACE 0
4324 #define M_FW_LDST_CMD_ADDRSPACE 0xff
4325 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE)
4326 #define G_FW_LDST_CMD_ADDRSPACE(x) \
4327 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
4328
4329 #define S_FW_LDST_CMD_CYCLES 16
4330 #define M_FW_LDST_CMD_CYCLES 0xffff
4331 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES)
4332 #define G_FW_LDST_CMD_CYCLES(x) \
4333 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
4334
4335 #define S_FW_LDST_CMD_MSG 31
4336 #define M_FW_LDST_CMD_MSG 0x1
4337 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG)
4338 #define G_FW_LDST_CMD_MSG(x) \
4339 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
4340 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U)
4341
4342 #define S_FW_LDST_CMD_CTXTFLUSH 30
4343 #define M_FW_LDST_CMD_CTXTFLUSH 0x1
4344 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH)
4345 #define G_FW_LDST_CMD_CTXTFLUSH(x) \
4346 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
4347 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U)
4348
4349 #define S_FW_LDST_CMD_PADDR 8
4350 #define M_FW_LDST_CMD_PADDR 0x1f
4351 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR)
4352 #define G_FW_LDST_CMD_PADDR(x) \
4353 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
4354
4355 #define S_FW_LDST_CMD_MMD 0
4356 #define M_FW_LDST_CMD_MMD 0x1f
4357 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD)
4358 #define G_FW_LDST_CMD_MMD(x) \
4359 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
4360
4361 #define S_FW_LDST_CMD_FID 15
4362 #define M_FW_LDST_CMD_FID 0x1
4363 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID)
4364 #define G_FW_LDST_CMD_FID(x) \
4365 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
4366 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U)
4367
4368 #define S_FW_LDST_CMD_IDX 0
4369 #define M_FW_LDST_CMD_IDX 0x7fff
4370 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX)
4371 #define G_FW_LDST_CMD_IDX(x) \
4372 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX)
4373
4374 #define S_FW_LDST_CMD_RPLCPF 0
4375 #define M_FW_LDST_CMD_RPLCPF 0xff
4376 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF)
4377 #define G_FW_LDST_CMD_RPLCPF(x) \
4378 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
4379
4380 #define S_FW_LDST_CMD_MPSID 0
4381 #define M_FW_LDST_CMD_MPSID 0x7fff
4382 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID)
4383 #define G_FW_LDST_CMD_MPSID(x) \
4384 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID)
4385
4386 #define S_FW_LDST_CMD_CTRL 7
4387 #define M_FW_LDST_CMD_CTRL 0x1
4388 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL)
4389 #define G_FW_LDST_CMD_CTRL(x) \
4390 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
4391 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U)
4392
4393 #define S_FW_LDST_CMD_LC 4
4394 #define M_FW_LDST_CMD_LC 0x1
4395 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC)
4396 #define G_FW_LDST_CMD_LC(x) \
4397 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)
4398 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U)
4399
4400 #define S_FW_LDST_CMD_AI 3
4401 #define M_FW_LDST_CMD_AI 0x1
4402 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI)
4403 #define G_FW_LDST_CMD_AI(x) \
4404 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)
4405 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U)
4406
4407 #define S_FW_LDST_CMD_FN 0
4408 #define M_FW_LDST_CMD_FN 0x7
4409 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN)
4410 #define G_FW_LDST_CMD_FN(x) \
4411 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)
4412
4413 #define S_FW_LDST_CMD_SELECT 4
4414 #define M_FW_LDST_CMD_SELECT 0xf
4415 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT)
4416 #define G_FW_LDST_CMD_SELECT(x) \
4417 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
4418
4419 #define S_FW_LDST_CMD_NACCESS 0
4420 #define M_FW_LDST_CMD_NACCESS 0xf
4421 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS)
4422 #define G_FW_LDST_CMD_NACCESS(x) \
4423 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
4424
4425 #define S_FW_LDST_CMD_NSET 14
4426 #define M_FW_LDST_CMD_NSET 0x3
4427 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET)
4428 #define G_FW_LDST_CMD_NSET(x) \
4429 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
4430
4431 #define S_FW_LDST_CMD_PID 6
4432 #define M_FW_LDST_CMD_PID 0x3
4433 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID)
4434 #define G_FW_LDST_CMD_PID(x) \
4435 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
4436
4437 struct fw_reset_cmd {
4438 __be32 op_to_write;
4439 __be32 retval_len16;
4440 __be32 val;
4441 __be32 halt_pkd;
4442 };
4443
4444 #define S_FW_RESET_CMD_HALT 31
4445 #define M_FW_RESET_CMD_HALT 0x1
4446 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT)
4447 #define G_FW_RESET_CMD_HALT(x) \
4448 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
4449 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U)
4450
4451 enum {
4452 FW_HELLO_CMD_STAGE_OS = 0,
4453 FW_HELLO_CMD_STAGE_PREOS0 = 1,
4454 FW_HELLO_CMD_STAGE_PREOS1 = 2,
4455 FW_HELLO_CMD_STAGE_POSTOS = 3,
4456 };
4457
4458 struct fw_hello_cmd {
4459 __be32 op_to_write;
4460 __be32 retval_len16;
4461 __be32 err_to_clearinit;
4462 __be32 fwrev;
4463 };
4464
4465 #define S_FW_HELLO_CMD_ERR 31
4466 #define M_FW_HELLO_CMD_ERR 0x1
4467 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR)
4468 #define G_FW_HELLO_CMD_ERR(x) \
4469 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
4470 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U)
4471
4472 #define S_FW_HELLO_CMD_INIT 30
4473 #define M_FW_HELLO_CMD_INIT 0x1
4474 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT)
4475 #define G_FW_HELLO_CMD_INIT(x) \
4476 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
4477 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U)
4478
4479 #define S_FW_HELLO_CMD_MASTERDIS 29
4480 #define M_FW_HELLO_CMD_MASTERDIS 0x1
4481 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS)
4482 #define G_FW_HELLO_CMD_MASTERDIS(x) \
4483 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
4484 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U)
4485
4486 #define S_FW_HELLO_CMD_MASTERFORCE 28
4487 #define M_FW_HELLO_CMD_MASTERFORCE 0x1
4488 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE)
4489 #define G_FW_HELLO_CMD_MASTERFORCE(x) \
4490 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
4491 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U)
4492
4493 #define S_FW_HELLO_CMD_MBMASTER 24
4494 #define M_FW_HELLO_CMD_MBMASTER 0xf
4495 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER)
4496 #define G_FW_HELLO_CMD_MBMASTER(x) \
4497 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
4498
4499 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23
4500 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1
4501 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)
4502 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \
4503 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
4504 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U)
4505
4506 #define S_FW_HELLO_CMD_MBASYNCNOT 20
4507 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7
4508 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT)
4509 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \
4510 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
4511
4512 #define S_FW_HELLO_CMD_STAGE 17
4513 #define M_FW_HELLO_CMD_STAGE 0x7
4514 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE)
4515 #define G_FW_HELLO_CMD_STAGE(x) \
4516 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
4517
4518 #define S_FW_HELLO_CMD_CLEARINIT 16
4519 #define M_FW_HELLO_CMD_CLEARINIT 0x1
4520 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT)
4521 #define G_FW_HELLO_CMD_CLEARINIT(x) \
4522 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
4523 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U)
4524
4525 struct fw_bye_cmd {
4526 __be32 op_to_write;
4527 __be32 retval_len16;
4528 __be64 r3;
4529 };
4530
4531 struct fw_initialize_cmd {
4532 __be32 op_to_write;
4533 __be32 retval_len16;
4534 __be64 r3;
4535 };
4536
4537 enum fw_caps_config_hm {
4538 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
4539 FW_CAPS_CONFIG_HM_PL = 0x00000002,
4540 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
4541 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
4542 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
4543 FW_CAPS_CONFIG_HM_TP = 0x00000020,
4544 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
4545 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
4546 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
4547 FW_CAPS_CONFIG_HM_MC = 0x00000200,
4548 FW_CAPS_CONFIG_HM_LE = 0x00000400,
4549 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
4550 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
4551 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
4552 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
4553 FW_CAPS_CONFIG_HM_MI = 0x00008000,
4554 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
4555 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
4556 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
4557 FW_CAPS_CONFIG_HM_MA = 0x00080000,
4558 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
4559 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
4560 FW_CAPS_CONFIG_HM_UART = 0x00400000,
4561 FW_CAPS_CONFIG_HM_SF = 0x00800000,
4562 };
4563
4564 /*
4565 * The VF Register Map.
4566 *
4567 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
4568 * bus module (PL) and CPU Interface Module (CIM) components are mapped via
4569 * the Slice to Module Map Table (see below) in the Physical Function Register
4570 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
4571 * and Offset registers in the PF Register Map. The MBDATA base address is
4572 * quite constrained as it determines the Mailbox Data addresses for both PFs
4573 * and VFs, and therefore must fit in both the VF and PF Register Maps without
4574 * overlapping other registers.
4575 */
4576 #define FW_T4VF_SGE_BASE_ADDR 0x0000
4577 #define FW_T4VF_MPS_BASE_ADDR 0x0100
4578 #define FW_T4VF_PL_BASE_ADDR 0x0200
4579 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
4580 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */
4581 #define FW_T4VF_CIM_BASE_ADDR 0x0300
4582
4583 #define FW_T4VF_REGMAP_START 0x0000
4584 #define FW_T4VF_REGMAP_SIZE 0x0400
4585
4586 enum fw_caps_config_nbm {
4587 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
4588 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
4589 };
4590
4591 enum fw_caps_config_link {
4592 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
4593 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
4594 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
4595 };
4596
4597 enum fw_caps_config_switch {
4598 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
4599 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
4600 };
4601
4602 enum fw_caps_config_nic {
4603 FW_CAPS_CONFIG_NIC = 0x00000001,
4604 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
4605 FW_CAPS_CONFIG_NIC_IDS = 0x00000004,
4606 FW_CAPS_CONFIG_NIC_UM = 0x00000008,
4607 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010,
4608 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020,
4609 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040,
4610 };
4611
4612 enum fw_caps_config_toe {
4613 FW_CAPS_CONFIG_TOE = 0x00000001,
4614 };
4615
4616 enum fw_caps_config_rdma {
4617 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
4618 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
4619 };
4620
4621 enum fw_caps_config_iscsi {
4622 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
4623 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
4624 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
4625 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
4626 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,
4627 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,
4628 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040,
4629 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080,
4630 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100,
4631 };
4632
4633 enum fw_caps_config_crypto {
4634 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001,
4635 FW_CAPS_CONFIG_TLSKEYS = 0x00000002,
4636 };
4637
4638 enum fw_caps_config_fcoe {
4639 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
4640 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
4641 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
4642 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
4643 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010,
4644 };
4645
4646 enum fw_memtype_cf {
4647 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0,
4648 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1,
4649 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM,
4650 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
4651 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL,
4652 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1,
4653 };
4654
4655 struct fw_caps_config_cmd {
4656 __be32 op_to_write;
4657 __be32 cfvalid_to_len16;
4658 __be32 r2;
4659 __be32 hwmbitmap;
4660 __be16 nbmcaps;
4661 __be16 linkcaps;
4662 __be16 switchcaps;
4663 __be16 r3;
4664 __be16 niccaps;
4665 __be16 toecaps;
4666 __be16 rdmacaps;
4667 __be16 cryptocaps;
4668 __be16 iscsicaps;
4669 __be16 fcoecaps;
4670 __be32 cfcsum;
4671 __be32 finiver;
4672 __be32 finicsum;
4673 };
4674
4675 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27
4676 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1
4677 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
4678 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \
4679 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
4680 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
4681
4682 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24
4683 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7
4684 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4685 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4686 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
4687 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
4688 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
4689
4690 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16
4691 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff
4692 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4693 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4694 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
4695 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
4696 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
4697
4698 /*
4699 * params command mnemonics
4700 */
4701 enum fw_params_mnem {
4702 FW_PARAMS_MNEM_DEV = 1, /* device params */
4703 FW_PARAMS_MNEM_PFVF = 2, /* function params */
4704 FW_PARAMS_MNEM_REG = 3, /* limited register access */
4705 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
4706 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */
4707 FW_PARAMS_MNEM_LAST
4708 };
4709
4710 /*
4711 * device parameters
4712 */
4713 enum fw_params_param_dev {
4714 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
4715 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
4716 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
4717 * allocated by the device's
4718 * Lookup Engine
4719 */
4720 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
4721 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04,
4722 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,
4723 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,
4724 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07,
4725 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,
4726 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,
4727 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,
4728 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
4729 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
4730 FW_PARAMS_PARAM_DEV_CF = 0x0D,
4731 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E,
4732 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F,
4733 FW_PARAMS_PARAM_DEV_LOAD = 0x10,
4734 FW_PARAMS_PARAM_DEV_DIAG = 0x11,
4735 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */
4736 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD
4737 */
4738 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD
4739 */
4740 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
4741 FW_PARAMS_PARAM_DEV_MCINIT = 0x16,
4742 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
4743 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
4744 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19,
4745 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A,
4746 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B,
4747 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C,
4748 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D,
4749
4750 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E,
4751 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F,
4752 };
4753
4754 /*
4755 * dev bypass parameters; actions and modes
4756 */
4757 enum fw_params_param_dev_bypass {
4758
4759 /* actions
4760 */
4761 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,
4762 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,
4763
4764 /* modes
4765 */
4766 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
4767 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1,
4768 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
4769 };
4770
4771 enum fw_params_param_dev_phyfw {
4772 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
4773 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
4774 };
4775
4776 enum fw_params_param_dev_diag {
4777 FW_PARAM_DEV_DIAG_TMP = 0x00,
4778 FW_PARAM_DEV_DIAG_VDD = 0x01,
4779 };
4780
4781 enum fw_params_param_dev_fwcache {
4782 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00,
4783 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01,
4784 };
4785
4786 /*
4787 * physical and virtual function parameters
4788 */
4789 enum fw_params_param_pfvf {
4790 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
4791 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
4792 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
4793 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
4794 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
4795 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
4796 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
4797 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
4798 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
4799 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
4800 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
4801 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
4802 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
4803 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
4804 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
4805 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
4806 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
4807 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
4808 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
4809 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
4810 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
4811 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
4812 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
4813 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
4814 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
4815 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19,
4816 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A,
4817 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
4818 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
4819 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
4820 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
4821 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
4822 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
4823 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
4824 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
4825 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
4826 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
4827 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
4828 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
4829 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
4830 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
4831 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31,
4832 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32,
4833 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33,
4834 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34,
4835 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35,
4836 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36,
4837 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37,
4838 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38,
4839 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39,
4840 };
4841
4842 /*
4843 * dma queue parameters
4844 */
4845 enum fw_params_param_dmaq {
4846 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
4847 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
4848 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02,
4849 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03,
4850 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
4851 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
4852 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
4853 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
4854 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14,
4855 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
4856 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30
4857 };
4858
4859 /*
4860 * chnet parameters
4861 */
4862 enum fw_params_param_chnet {
4863 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00,
4864 };
4865
4866 enum fw_params_param_chnet_flags {
4867 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1,
4868 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2,
4869 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4,
4870 };
4871
4872 #define S_FW_PARAMS_MNEM 24
4873 #define M_FW_PARAMS_MNEM 0xff
4874 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM)
4875 #define G_FW_PARAMS_MNEM(x) \
4876 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
4877
4878 #define S_FW_PARAMS_PARAM_X 16
4879 #define M_FW_PARAMS_PARAM_X 0xff
4880 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
4881 #define G_FW_PARAMS_PARAM_X(x) \
4882 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
4883
4884 #define S_FW_PARAMS_PARAM_Y 8
4885 #define M_FW_PARAMS_PARAM_Y 0xff
4886 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
4887 #define G_FW_PARAMS_PARAM_Y(x) \
4888 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
4889
4890 #define S_FW_PARAMS_PARAM_Z 0
4891 #define M_FW_PARAMS_PARAM_Z 0xff
4892 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
4893 #define G_FW_PARAMS_PARAM_Z(x) \
4894 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
4895
4896 #define S_FW_PARAMS_PARAM_XYZ 0
4897 #define M_FW_PARAMS_PARAM_XYZ 0xffffff
4898 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
4899 #define G_FW_PARAMS_PARAM_XYZ(x) \
4900 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
4901
4902 #define S_FW_PARAMS_PARAM_YZ 0
4903 #define M_FW_PARAMS_PARAM_YZ 0xffff
4904 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
4905 #define G_FW_PARAMS_PARAM_YZ(x) \
4906 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
4907
4908 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31
4909 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1
4910 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
4911 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
4912 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
4913 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \
4914 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
4915
4916 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24
4917 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3
4918 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
4919 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
4920 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
4921 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \
4922 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
4923
4924 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0
4925 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff
4926 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
4927 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST)
4928 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
4929 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST)
4930
4931 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29
4932 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7
4933 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \
4934 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
4935 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \
4936 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \
4937 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
4938
4939 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0
4940 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff
4941 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \
4942 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
4943 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \
4944 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \
4945 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
4946
4947 struct fw_params_cmd {
4948 __be32 op_to_vfn;
4949 __be32 retval_len16;
4950 struct fw_params_param {
4951 __be32 mnem;
4952 __be32 val;
4953 } param[7];
4954 };
4955
4956 #define S_FW_PARAMS_CMD_PFN 8
4957 #define M_FW_PARAMS_CMD_PFN 0x7
4958 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN)
4959 #define G_FW_PARAMS_CMD_PFN(x) \
4960 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
4961
4962 #define S_FW_PARAMS_CMD_VFN 0
4963 #define M_FW_PARAMS_CMD_VFN 0xff
4964 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN)
4965 #define G_FW_PARAMS_CMD_VFN(x) \
4966 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
4967
4968 struct fw_pfvf_cmd {
4969 __be32 op_to_vfn;
4970 __be32 retval_len16;
4971 __be32 niqflint_niq;
4972 __be32 type_to_neq;
4973 __be32 tc_to_nexactf;
4974 __be32 r_caps_to_nethctrl;
4975 __be16 nricq;
4976 __be16 nriqp;
4977 __be32 r4;
4978 };
4979
4980 #define S_FW_PFVF_CMD_PFN 8
4981 #define M_FW_PFVF_CMD_PFN 0x7
4982 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN)
4983 #define G_FW_PFVF_CMD_PFN(x) \
4984 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
4985
4986 #define S_FW_PFVF_CMD_VFN 0
4987 #define M_FW_PFVF_CMD_VFN 0xff
4988 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN)
4989 #define G_FW_PFVF_CMD_VFN(x) \
4990 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
4991
4992 #define S_FW_PFVF_CMD_NIQFLINT 20
4993 #define M_FW_PFVF_CMD_NIQFLINT 0xfff
4994 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT)
4995 #define G_FW_PFVF_CMD_NIQFLINT(x) \
4996 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
4997
4998 #define S_FW_PFVF_CMD_NIQ 0
4999 #define M_FW_PFVF_CMD_NIQ 0xfffff
5000 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ)
5001 #define G_FW_PFVF_CMD_NIQ(x) \
5002 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
5003
5004 #define S_FW_PFVF_CMD_TYPE 31
5005 #define M_FW_PFVF_CMD_TYPE 0x1
5006 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE)
5007 #define G_FW_PFVF_CMD_TYPE(x) \
5008 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
5009 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U)
5010
5011 #define S_FW_PFVF_CMD_CMASK 24
5012 #define M_FW_PFVF_CMD_CMASK 0xf
5013 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK)
5014 #define G_FW_PFVF_CMD_CMASK(x) \
5015 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
5016
5017 #define S_FW_PFVF_CMD_PMASK 20
5018 #define M_FW_PFVF_CMD_PMASK 0xf
5019 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK)
5020 #define G_FW_PFVF_CMD_PMASK(x) \
5021 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
5022
5023 #define S_FW_PFVF_CMD_NEQ 0
5024 #define M_FW_PFVF_CMD_NEQ 0xfffff
5025 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ)
5026 #define G_FW_PFVF_CMD_NEQ(x) \
5027 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
5028
5029 #define S_FW_PFVF_CMD_TC 24
5030 #define M_FW_PFVF_CMD_TC 0xff
5031 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC)
5032 #define G_FW_PFVF_CMD_TC(x) \
5033 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
5034
5035 #define S_FW_PFVF_CMD_NVI 16
5036 #define M_FW_PFVF_CMD_NVI 0xff
5037 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI)
5038 #define G_FW_PFVF_CMD_NVI(x) \
5039 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
5040
5041 #define S_FW_PFVF_CMD_NEXACTF 0
5042 #define M_FW_PFVF_CMD_NEXACTF 0xffff
5043 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF)
5044 #define G_FW_PFVF_CMD_NEXACTF(x) \
5045 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
5046
5047 #define S_FW_PFVF_CMD_R_CAPS 24
5048 #define M_FW_PFVF_CMD_R_CAPS 0xff
5049 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS)
5050 #define G_FW_PFVF_CMD_R_CAPS(x) \
5051 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
5052
5053 #define S_FW_PFVF_CMD_WX_CAPS 16
5054 #define M_FW_PFVF_CMD_WX_CAPS 0xff
5055 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS)
5056 #define G_FW_PFVF_CMD_WX_CAPS(x) \
5057 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
5058
5059 #define S_FW_PFVF_CMD_NETHCTRL 0
5060 #define M_FW_PFVF_CMD_NETHCTRL 0xffff
5061 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL)
5062 #define G_FW_PFVF_CMD_NETHCTRL(x) \
5063 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
5064
5065 /*
5066 * ingress queue type; the first 1K ingress queues can have associated 0,
5067 * 1 or 2 free lists and an interrupt, all other ingress queues lack these
5068 * capabilities
5069 */
5070 enum fw_iq_type {
5071 FW_IQ_TYPE_FL_INT_CAP,
5072 FW_IQ_TYPE_NO_FL_INT_CAP,
5073 FW_IQ_TYPE_VF_CQ
5074 };
5075
5076 struct fw_iq_cmd {
5077 __be32 op_to_vfn;
5078 __be32 alloc_to_len16;
5079 __be16 physiqid;
5080 __be16 iqid;
5081 __be16 fl0id;
5082 __be16 fl1id;
5083 __be32 type_to_iqandstindex;
5084 __be16 iqdroprss_to_iqesize;
5085 __be16 iqsize;
5086 __be64 iqaddr;
5087 __be32 iqns_to_fl0congen;
5088 __be16 fl0dcaen_to_fl0cidxfthresh;
5089 __be16 fl0size;
5090 __be64 fl0addr;
5091 __be32 fl1cngchmap_to_fl1congen;
5092 __be16 fl1dcaen_to_fl1cidxfthresh;
5093 __be16 fl1size;
5094 __be64 fl1addr;
5095 };
5096
5097 #define S_FW_IQ_CMD_PFN 8
5098 #define M_FW_IQ_CMD_PFN 0x7
5099 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN)
5100 #define G_FW_IQ_CMD_PFN(x) \
5101 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
5102
5103 #define S_FW_IQ_CMD_VFN 0
5104 #define M_FW_IQ_CMD_VFN 0xff
5105 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN)
5106 #define G_FW_IQ_CMD_VFN(x) \
5107 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
5108
5109 #define S_FW_IQ_CMD_ALLOC 31
5110 #define M_FW_IQ_CMD_ALLOC 0x1
5111 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC)
5112 #define G_FW_IQ_CMD_ALLOC(x) \
5113 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
5114 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U)
5115
5116 #define S_FW_IQ_CMD_FREE 30
5117 #define M_FW_IQ_CMD_FREE 0x1
5118 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE)
5119 #define G_FW_IQ_CMD_FREE(x) \
5120 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
5121 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U)
5122
5123 #define S_FW_IQ_CMD_MODIFY 29
5124 #define M_FW_IQ_CMD_MODIFY 0x1
5125 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY)
5126 #define G_FW_IQ_CMD_MODIFY(x) \
5127 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
5128 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U)
5129
5130 #define S_FW_IQ_CMD_IQSTART 28
5131 #define M_FW_IQ_CMD_IQSTART 0x1
5132 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART)
5133 #define G_FW_IQ_CMD_IQSTART(x) \
5134 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
5135 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U)
5136
5137 #define S_FW_IQ_CMD_IQSTOP 27
5138 #define M_FW_IQ_CMD_IQSTOP 0x1
5139 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP)
5140 #define G_FW_IQ_CMD_IQSTOP(x) \
5141 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
5142 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U)
5143
5144 #define S_FW_IQ_CMD_TYPE 29
5145 #define M_FW_IQ_CMD_TYPE 0x7
5146 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE)
5147 #define G_FW_IQ_CMD_TYPE(x) \
5148 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
5149
5150 #define S_FW_IQ_CMD_IQASYNCH 28
5151 #define M_FW_IQ_CMD_IQASYNCH 0x1
5152 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH)
5153 #define G_FW_IQ_CMD_IQASYNCH(x) \
5154 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
5155 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U)
5156
5157 #define S_FW_IQ_CMD_VIID 16
5158 #define M_FW_IQ_CMD_VIID 0xfff
5159 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID)
5160 #define G_FW_IQ_CMD_VIID(x) \
5161 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
5162
5163 #define S_FW_IQ_CMD_IQANDST 15
5164 #define M_FW_IQ_CMD_IQANDST 0x1
5165 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST)
5166 #define G_FW_IQ_CMD_IQANDST(x) \
5167 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
5168 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U)
5169
5170 #define S_FW_IQ_CMD_IQANUS 14
5171 #define M_FW_IQ_CMD_IQANUS 0x1
5172 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS)
5173 #define G_FW_IQ_CMD_IQANUS(x) \
5174 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
5175 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U)
5176
5177 #define S_FW_IQ_CMD_IQANUD 12
5178 #define M_FW_IQ_CMD_IQANUD 0x3
5179 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD)
5180 #define G_FW_IQ_CMD_IQANUD(x) \
5181 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
5182
5183 #define S_FW_IQ_CMD_IQANDSTINDEX 0
5184 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff
5185 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX)
5186 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \
5187 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
5188
5189 #define S_FW_IQ_CMD_IQDROPRSS 15
5190 #define M_FW_IQ_CMD_IQDROPRSS 0x1
5191 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS)
5192 #define G_FW_IQ_CMD_IQDROPRSS(x) \
5193 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
5194 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U)
5195
5196 #define S_FW_IQ_CMD_IQGTSMODE 14
5197 #define M_FW_IQ_CMD_IQGTSMODE 0x1
5198 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE)
5199 #define G_FW_IQ_CMD_IQGTSMODE(x) \
5200 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
5201 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U)
5202
5203 #define S_FW_IQ_CMD_IQPCIECH 12
5204 #define M_FW_IQ_CMD_IQPCIECH 0x3
5205 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH)
5206 #define G_FW_IQ_CMD_IQPCIECH(x) \
5207 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
5208
5209 #define S_FW_IQ_CMD_IQDCAEN 11
5210 #define M_FW_IQ_CMD_IQDCAEN 0x1
5211 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN)
5212 #define G_FW_IQ_CMD_IQDCAEN(x) \
5213 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
5214 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U)
5215
5216 #define S_FW_IQ_CMD_IQDCACPU 6
5217 #define M_FW_IQ_CMD_IQDCACPU 0x1f
5218 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU)
5219 #define G_FW_IQ_CMD_IQDCACPU(x) \
5220 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
5221
5222 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4
5223 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3
5224 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
5225 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \
5226 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
5227
5228 #define S_FW_IQ_CMD_IQO 3
5229 #define M_FW_IQ_CMD_IQO 0x1
5230 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO)
5231 #define G_FW_IQ_CMD_IQO(x) \
5232 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)
5233 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U)
5234
5235 #define S_FW_IQ_CMD_IQCPRIO 2
5236 #define M_FW_IQ_CMD_IQCPRIO 0x1
5237 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO)
5238 #define G_FW_IQ_CMD_IQCPRIO(x) \
5239 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
5240 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U)
5241
5242 #define S_FW_IQ_CMD_IQESIZE 0
5243 #define M_FW_IQ_CMD_IQESIZE 0x3
5244 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE)
5245 #define G_FW_IQ_CMD_IQESIZE(x) \
5246 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
5247
5248 #define S_FW_IQ_CMD_IQNS 31
5249 #define M_FW_IQ_CMD_IQNS 0x1
5250 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS)
5251 #define G_FW_IQ_CMD_IQNS(x) \
5252 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)
5253 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U)
5254
5255 #define S_FW_IQ_CMD_IQRO 30
5256 #define M_FW_IQ_CMD_IQRO 0x1
5257 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO)
5258 #define G_FW_IQ_CMD_IQRO(x) \
5259 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
5260 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U)
5261
5262 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28
5263 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3
5264 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)
5265 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \
5266 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
5267
5268 #define S_FW_IQ_CMD_IQFLINTCONGEN 27
5269 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1
5270 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
5271 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \
5272 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
5273 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U)
5274
5275 #define S_FW_IQ_CMD_IQFLINTISCSIC 26
5276 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1
5277 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC)
5278 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \
5279 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
5280 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U)
5281
5282 #define S_FW_IQ_CMD_FL0CNGCHMAP 20
5283 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf
5284 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
5285 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \
5286 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
5287
5288 #define S_FW_IQ_CMD_FL0CONGDROP 16
5289 #define M_FW_IQ_CMD_FL0CONGDROP 0x1
5290 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP)
5291 #define G_FW_IQ_CMD_FL0CONGDROP(x) \
5292 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP)
5293 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U)
5294
5295 #define S_FW_IQ_CMD_FL0CACHELOCK 15
5296 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1
5297 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK)
5298 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \
5299 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
5300 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U)
5301
5302 #define S_FW_IQ_CMD_FL0DBP 14
5303 #define M_FW_IQ_CMD_FL0DBP 0x1
5304 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP)
5305 #define G_FW_IQ_CMD_FL0DBP(x) \
5306 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
5307 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U)
5308
5309 #define S_FW_IQ_CMD_FL0DATANS 13
5310 #define M_FW_IQ_CMD_FL0DATANS 0x1
5311 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS)
5312 #define G_FW_IQ_CMD_FL0DATANS(x) \
5313 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
5314 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U)
5315
5316 #define S_FW_IQ_CMD_FL0DATARO 12
5317 #define M_FW_IQ_CMD_FL0DATARO 0x1
5318 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO)
5319 #define G_FW_IQ_CMD_FL0DATARO(x) \
5320 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
5321 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U)
5322
5323 #define S_FW_IQ_CMD_FL0CONGCIF 11
5324 #define M_FW_IQ_CMD_FL0CONGCIF 0x1
5325 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF)
5326 #define G_FW_IQ_CMD_FL0CONGCIF(x) \
5327 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
5328 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U)
5329
5330 #define S_FW_IQ_CMD_FL0ONCHIP 10
5331 #define M_FW_IQ_CMD_FL0ONCHIP 0x1
5332 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP)
5333 #define G_FW_IQ_CMD_FL0ONCHIP(x) \
5334 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
5335 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U)
5336
5337 #define S_FW_IQ_CMD_FL0STATUSPGNS 9
5338 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1
5339 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS)
5340 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \
5341 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
5342 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U)
5343
5344 #define S_FW_IQ_CMD_FL0STATUSPGRO 8
5345 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1
5346 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO)
5347 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \
5348 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
5349 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U)
5350
5351 #define S_FW_IQ_CMD_FL0FETCHNS 7
5352 #define M_FW_IQ_CMD_FL0FETCHNS 0x1
5353 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS)
5354 #define G_FW_IQ_CMD_FL0FETCHNS(x) \
5355 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
5356 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U)
5357
5358 #define S_FW_IQ_CMD_FL0FETCHRO 6
5359 #define M_FW_IQ_CMD_FL0FETCHRO 0x1
5360 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO)
5361 #define G_FW_IQ_CMD_FL0FETCHRO(x) \
5362 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
5363 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U)
5364
5365 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4
5366 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3
5367 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
5368 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \
5369 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
5370
5371 #define S_FW_IQ_CMD_FL0CPRIO 3
5372 #define M_FW_IQ_CMD_FL0CPRIO 0x1
5373 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO)
5374 #define G_FW_IQ_CMD_FL0CPRIO(x) \
5375 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
5376 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U)
5377
5378 #define S_FW_IQ_CMD_FL0PADEN 2
5379 #define M_FW_IQ_CMD_FL0PADEN 0x1
5380 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN)
5381 #define G_FW_IQ_CMD_FL0PADEN(x) \
5382 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
5383 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U)
5384
5385 #define S_FW_IQ_CMD_FL0PACKEN 1
5386 #define M_FW_IQ_CMD_FL0PACKEN 0x1
5387 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN)
5388 #define G_FW_IQ_CMD_FL0PACKEN(x) \
5389 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
5390 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U)
5391
5392 #define S_FW_IQ_CMD_FL0CONGEN 0
5393 #define M_FW_IQ_CMD_FL0CONGEN 0x1
5394 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN)
5395 #define G_FW_IQ_CMD_FL0CONGEN(x) \
5396 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
5397 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U)
5398
5399 #define S_FW_IQ_CMD_FL0DCAEN 15
5400 #define M_FW_IQ_CMD_FL0DCAEN 0x1
5401 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN)
5402 #define G_FW_IQ_CMD_FL0DCAEN(x) \
5403 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
5404 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U)
5405
5406 #define S_FW_IQ_CMD_FL0DCACPU 10
5407 #define M_FW_IQ_CMD_FL0DCACPU 0x1f
5408 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU)
5409 #define G_FW_IQ_CMD_FL0DCACPU(x) \
5410 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
5411
5412 #define S_FW_IQ_CMD_FL0FBMIN 7
5413 #define M_FW_IQ_CMD_FL0FBMIN 0x7
5414 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN)
5415 #define G_FW_IQ_CMD_FL0FBMIN(x) \
5416 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
5417
5418 #define S_FW_IQ_CMD_FL0FBMAX 4
5419 #define M_FW_IQ_CMD_FL0FBMAX 0x7
5420 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX)
5421 #define G_FW_IQ_CMD_FL0FBMAX(x) \
5422 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
5423
5424 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3
5425 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1
5426 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)
5427 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \
5428 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
5429 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)
5430
5431 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0
5432 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7
5433 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)
5434 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \
5435 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
5436
5437 #define S_FW_IQ_CMD_FL1CNGCHMAP 20
5438 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf
5439 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP)
5440 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \
5441 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
5442
5443 #define S_FW_IQ_CMD_FL1CONGDROP 16
5444 #define M_FW_IQ_CMD_FL1CONGDROP 0x1
5445 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP)
5446 #define G_FW_IQ_CMD_FL1CONGDROP(x) \
5447 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP)
5448 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U)
5449
5450 #define S_FW_IQ_CMD_FL1CACHELOCK 15
5451 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1
5452 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK)
5453 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \
5454 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
5455 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U)
5456
5457 #define S_FW_IQ_CMD_FL1DBP 14
5458 #define M_FW_IQ_CMD_FL1DBP 0x1
5459 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP)
5460 #define G_FW_IQ_CMD_FL1DBP(x) \
5461 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
5462 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U)
5463
5464 #define S_FW_IQ_CMD_FL1DATANS 13
5465 #define M_FW_IQ_CMD_FL1DATANS 0x1
5466 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS)
5467 #define G_FW_IQ_CMD_FL1DATANS(x) \
5468 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
5469 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U)
5470
5471 #define S_FW_IQ_CMD_FL1DATARO 12
5472 #define M_FW_IQ_CMD_FL1DATARO 0x1
5473 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO)
5474 #define G_FW_IQ_CMD_FL1DATARO(x) \
5475 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
5476 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U)
5477
5478 #define S_FW_IQ_CMD_FL1CONGCIF 11
5479 #define M_FW_IQ_CMD_FL1CONGCIF 0x1
5480 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF)
5481 #define G_FW_IQ_CMD_FL1CONGCIF(x) \
5482 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
5483 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U)
5484
5485 #define S_FW_IQ_CMD_FL1ONCHIP 10
5486 #define M_FW_IQ_CMD_FL1ONCHIP 0x1
5487 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP)
5488 #define G_FW_IQ_CMD_FL1ONCHIP(x) \
5489 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
5490 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U)
5491
5492 #define S_FW_IQ_CMD_FL1STATUSPGNS 9
5493 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1
5494 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS)
5495 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \
5496 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
5497 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U)
5498
5499 #define S_FW_IQ_CMD_FL1STATUSPGRO 8
5500 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1
5501 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO)
5502 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \
5503 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
5504 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U)
5505
5506 #define S_FW_IQ_CMD_FL1FETCHNS 7
5507 #define M_FW_IQ_CMD_FL1FETCHNS 0x1
5508 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS)
5509 #define G_FW_IQ_CMD_FL1FETCHNS(x) \
5510 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
5511 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U)
5512
5513 #define S_FW_IQ_CMD_FL1FETCHRO 6
5514 #define M_FW_IQ_CMD_FL1FETCHRO 0x1
5515 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO)
5516 #define G_FW_IQ_CMD_FL1FETCHRO(x) \
5517 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
5518 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U)
5519
5520 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4
5521 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3
5522 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)
5523 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \
5524 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
5525
5526 #define S_FW_IQ_CMD_FL1CPRIO 3
5527 #define M_FW_IQ_CMD_FL1CPRIO 0x1
5528 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO)
5529 #define G_FW_IQ_CMD_FL1CPRIO(x) \
5530 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
5531 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U)
5532
5533 #define S_FW_IQ_CMD_FL1PADEN 2
5534 #define M_FW_IQ_CMD_FL1PADEN 0x1
5535 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN)
5536 #define G_FW_IQ_CMD_FL1PADEN(x) \
5537 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
5538 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U)
5539
5540 #define S_FW_IQ_CMD_FL1PACKEN 1
5541 #define M_FW_IQ_CMD_FL1PACKEN 0x1
5542 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN)
5543 #define G_FW_IQ_CMD_FL1PACKEN(x) \
5544 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
5545 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U)
5546
5547 #define S_FW_IQ_CMD_FL1CONGEN 0
5548 #define M_FW_IQ_CMD_FL1CONGEN 0x1
5549 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN)
5550 #define G_FW_IQ_CMD_FL1CONGEN(x) \
5551 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
5552 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U)
5553
5554 #define S_FW_IQ_CMD_FL1DCAEN 15
5555 #define M_FW_IQ_CMD_FL1DCAEN 0x1
5556 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN)
5557 #define G_FW_IQ_CMD_FL1DCAEN(x) \
5558 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
5559 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U)
5560
5561 #define S_FW_IQ_CMD_FL1DCACPU 10
5562 #define M_FW_IQ_CMD_FL1DCACPU 0x1f
5563 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU)
5564 #define G_FW_IQ_CMD_FL1DCACPU(x) \
5565 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
5566
5567 #define S_FW_IQ_CMD_FL1FBMIN 7
5568 #define M_FW_IQ_CMD_FL1FBMIN 0x7
5569 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN)
5570 #define G_FW_IQ_CMD_FL1FBMIN(x) \
5571 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
5572
5573 #define S_FW_IQ_CMD_FL1FBMAX 4
5574 #define M_FW_IQ_CMD_FL1FBMAX 0x7
5575 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX)
5576 #define G_FW_IQ_CMD_FL1FBMAX(x) \
5577 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
5578
5579 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3
5580 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1
5581 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)
5582 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \
5583 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
5584 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)
5585
5586 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0
5587 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7
5588 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)
5589 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \
5590 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
5591
5592 struct fw_eq_mngt_cmd {
5593 __be32 op_to_vfn;
5594 __be32 alloc_to_len16;
5595 __be32 cmpliqid_eqid;
5596 __be32 physeqid_pkd;
5597 __be32 fetchszm_to_iqid;
5598 __be32 dcaen_to_eqsize;
5599 __be64 eqaddr;
5600 };
5601
5602 #define S_FW_EQ_MNGT_CMD_PFN 8
5603 #define M_FW_EQ_MNGT_CMD_PFN 0x7
5604 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN)
5605 #define G_FW_EQ_MNGT_CMD_PFN(x) \
5606 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
5607
5608 #define S_FW_EQ_MNGT_CMD_VFN 0
5609 #define M_FW_EQ_MNGT_CMD_VFN 0xff
5610 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN)
5611 #define G_FW_EQ_MNGT_CMD_VFN(x) \
5612 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
5613
5614 #define S_FW_EQ_MNGT_CMD_ALLOC 31
5615 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1
5616 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC)
5617 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \
5618 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
5619 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U)
5620
5621 #define S_FW_EQ_MNGT_CMD_FREE 30
5622 #define M_FW_EQ_MNGT_CMD_FREE 0x1
5623 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE)
5624 #define G_FW_EQ_MNGT_CMD_FREE(x) \
5625 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
5626 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U)
5627
5628 #define S_FW_EQ_MNGT_CMD_MODIFY 29
5629 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1
5630 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY)
5631 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \
5632 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
5633 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U)
5634
5635 #define S_FW_EQ_MNGT_CMD_EQSTART 28
5636 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1
5637 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART)
5638 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \
5639 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
5640 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U)
5641
5642 #define S_FW_EQ_MNGT_CMD_EQSTOP 27
5643 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1
5644 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP)
5645 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \
5646 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
5647 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U)
5648
5649 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20
5650 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff
5651 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
5652 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \
5653 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
5654
5655 #define S_FW_EQ_MNGT_CMD_EQID 0
5656 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff
5657 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID)
5658 #define G_FW_EQ_MNGT_CMD_EQID(x) \
5659 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
5660
5661 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0
5662 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff
5663 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)
5664 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \
5665 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
5666
5667 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26
5668 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1
5669 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)
5670 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \
5671 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
5672 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U)
5673
5674 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25
5675 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1
5676 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)
5677 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \
5678 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
5679 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)
5680
5681 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24
5682 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1
5683 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)
5684 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \
5685 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
5686 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)
5687
5688 #define S_FW_EQ_MNGT_CMD_FETCHNS 23
5689 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1
5690 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS)
5691 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \
5692 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
5693 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U)
5694
5695 #define S_FW_EQ_MNGT_CMD_FETCHRO 22
5696 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1
5697 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO)
5698 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \
5699 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
5700 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U)
5701
5702 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20
5703 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3
5704 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)
5705 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \
5706 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
5707
5708 #define S_FW_EQ_MNGT_CMD_CPRIO 19
5709 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1
5710 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO)
5711 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \
5712 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
5713 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U)
5714
5715 #define S_FW_EQ_MNGT_CMD_ONCHIP 18
5716 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1
5717 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP)
5718 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \
5719 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
5720 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U)
5721
5722 #define S_FW_EQ_MNGT_CMD_PCIECHN 16
5723 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3
5724 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN)
5725 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \
5726 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
5727
5728 #define S_FW_EQ_MNGT_CMD_IQID 0
5729 #define M_FW_EQ_MNGT_CMD_IQID 0xffff
5730 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID)
5731 #define G_FW_EQ_MNGT_CMD_IQID(x) \
5732 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
5733
5734 #define S_FW_EQ_MNGT_CMD_DCAEN 31
5735 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1
5736 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN)
5737 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \
5738 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
5739 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U)
5740
5741 #define S_FW_EQ_MNGT_CMD_DCACPU 26
5742 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f
5743 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU)
5744 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \
5745 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
5746
5747 #define S_FW_EQ_MNGT_CMD_FBMIN 23
5748 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7
5749 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN)
5750 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \
5751 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
5752
5753 #define S_FW_EQ_MNGT_CMD_FBMAX 20
5754 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7
5755 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX)
5756 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \
5757 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
5758
5759 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19
5760 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1
5761 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5762 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5763 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
5764 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
5765 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)
5766
5767 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16
5768 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7
5769 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5770 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \
5771 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
5772
5773 #define S_FW_EQ_MNGT_CMD_EQSIZE 0
5774 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff
5775 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE)
5776 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \
5777 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
5778
5779 struct fw_eq_eth_cmd {
5780 __be32 op_to_vfn;
5781 __be32 alloc_to_len16;
5782 __be32 eqid_pkd;
5783 __be32 physeqid_pkd;
5784 __be32 fetchszm_to_iqid;
5785 __be32 dcaen_to_eqsize;
5786 __be64 eqaddr;
5787 __be32 autoequiqe_to_viid;
5788 __be32 r8_lo;
5789 __be64 r9;
5790 };
5791
5792 #define S_FW_EQ_ETH_CMD_PFN 8
5793 #define M_FW_EQ_ETH_CMD_PFN 0x7
5794 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN)
5795 #define G_FW_EQ_ETH_CMD_PFN(x) \
5796 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
5797
5798 #define S_FW_EQ_ETH_CMD_VFN 0
5799 #define M_FW_EQ_ETH_CMD_VFN 0xff
5800 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN)
5801 #define G_FW_EQ_ETH_CMD_VFN(x) \
5802 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
5803
5804 #define S_FW_EQ_ETH_CMD_ALLOC 31
5805 #define M_FW_EQ_ETH_CMD_ALLOC 0x1
5806 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC)
5807 #define G_FW_EQ_ETH_CMD_ALLOC(x) \
5808 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
5809 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U)
5810
5811 #define S_FW_EQ_ETH_CMD_FREE 30
5812 #define M_FW_EQ_ETH_CMD_FREE 0x1
5813 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE)
5814 #define G_FW_EQ_ETH_CMD_FREE(x) \
5815 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
5816 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U)
5817
5818 #define S_FW_EQ_ETH_CMD_MODIFY 29
5819 #define M_FW_EQ_ETH_CMD_MODIFY 0x1
5820 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY)
5821 #define G_FW_EQ_ETH_CMD_MODIFY(x) \
5822 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
5823 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U)
5824
5825 #define S_FW_EQ_ETH_CMD_EQSTART 28
5826 #define M_FW_EQ_ETH_CMD_EQSTART 0x1
5827 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART)
5828 #define G_FW_EQ_ETH_CMD_EQSTART(x) \
5829 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
5830 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U)
5831
5832 #define S_FW_EQ_ETH_CMD_EQSTOP 27
5833 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1
5834 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP)
5835 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \
5836 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
5837 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U)
5838
5839 #define S_FW_EQ_ETH_CMD_EQID 0
5840 #define M_FW_EQ_ETH_CMD_EQID 0xfffff
5841 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID)
5842 #define G_FW_EQ_ETH_CMD_EQID(x) \
5843 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
5844
5845 #define S_FW_EQ_ETH_CMD_PHYSEQID 0
5846 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff
5847 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID)
5848 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \
5849 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
5850
5851 #define S_FW_EQ_ETH_CMD_FETCHSZM 26
5852 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1
5853 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM)
5854 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \
5855 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
5856 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U)
5857
5858 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25
5859 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1
5860 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)
5861 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \
5862 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
5863 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U)
5864
5865 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24
5866 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1
5867 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)
5868 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \
5869 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
5870 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U)
5871
5872 #define S_FW_EQ_ETH_CMD_FETCHNS 23
5873 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1
5874 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS)
5875 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \
5876 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
5877 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U)
5878
5879 #define S_FW_EQ_ETH_CMD_FETCHRO 22
5880 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1
5881 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO)
5882 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \
5883 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
5884 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U)
5885
5886 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20
5887 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3
5888 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
5889 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \
5890 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
5891
5892 #define S_FW_EQ_ETH_CMD_CPRIO 19
5893 #define M_FW_EQ_ETH_CMD_CPRIO 0x1
5894 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO)
5895 #define G_FW_EQ_ETH_CMD_CPRIO(x) \
5896 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
5897 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U)
5898
5899 #define S_FW_EQ_ETH_CMD_ONCHIP 18
5900 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1
5901 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP)
5902 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \
5903 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
5904 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U)
5905
5906 #define S_FW_EQ_ETH_CMD_PCIECHN 16
5907 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3
5908 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN)
5909 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \
5910 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
5911
5912 #define S_FW_EQ_ETH_CMD_IQID 0
5913 #define M_FW_EQ_ETH_CMD_IQID 0xffff
5914 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID)
5915 #define G_FW_EQ_ETH_CMD_IQID(x) \
5916 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
5917
5918 #define S_FW_EQ_ETH_CMD_DCAEN 31
5919 #define M_FW_EQ_ETH_CMD_DCAEN 0x1
5920 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN)
5921 #define G_FW_EQ_ETH_CMD_DCAEN(x) \
5922 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
5923 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U)
5924
5925 #define S_FW_EQ_ETH_CMD_DCACPU 26
5926 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f
5927 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU)
5928 #define G_FW_EQ_ETH_CMD_DCACPU(x) \
5929 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
5930
5931 #define S_FW_EQ_ETH_CMD_FBMIN 23
5932 #define M_FW_EQ_ETH_CMD_FBMIN 0x7
5933 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN)
5934 #define G_FW_EQ_ETH_CMD_FBMIN(x) \
5935 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
5936
5937 #define S_FW_EQ_ETH_CMD_FBMAX 20
5938 #define M_FW_EQ_ETH_CMD_FBMAX 0x7
5939 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX)
5940 #define G_FW_EQ_ETH_CMD_FBMAX(x) \
5941 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
5942
5943 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19
5944 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1
5945 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)
5946 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \
5947 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
5948 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)
5949
5950 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16
5951 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7
5952 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
5953 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \
5954 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
5955
5956 #define S_FW_EQ_ETH_CMD_EQSIZE 0
5957 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff
5958 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE)
5959 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \
5960 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
5961
5962 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31
5963 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1
5964 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE)
5965 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \
5966 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE)
5967 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U)
5968
5969 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
5970 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
5971 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
5972 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
5973 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
5974 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
5975
5976 #define S_FW_EQ_ETH_CMD_VIID 16
5977 #define M_FW_EQ_ETH_CMD_VIID 0xfff
5978 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
5979 #define G_FW_EQ_ETH_CMD_VIID(x) \
5980 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
5981
5982 struct fw_eq_ctrl_cmd {
5983 __be32 op_to_vfn;
5984 __be32 alloc_to_len16;
5985 __be32 cmpliqid_eqid;
5986 __be32 physeqid_pkd;
5987 __be32 fetchszm_to_iqid;
5988 __be32 dcaen_to_eqsize;
5989 __be64 eqaddr;
5990 };
5991
5992 #define S_FW_EQ_CTRL_CMD_PFN 8
5993 #define M_FW_EQ_CTRL_CMD_PFN 0x7
5994 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN)
5995 #define G_FW_EQ_CTRL_CMD_PFN(x) \
5996 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
5997
5998 #define S_FW_EQ_CTRL_CMD_VFN 0
5999 #define M_FW_EQ_CTRL_CMD_VFN 0xff
6000 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN)
6001 #define G_FW_EQ_CTRL_CMD_VFN(x) \
6002 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
6003
6004 #define S_FW_EQ_CTRL_CMD_ALLOC 31
6005 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1
6006 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC)
6007 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \
6008 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
6009 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U)
6010
6011 #define S_FW_EQ_CTRL_CMD_FREE 30
6012 #define M_FW_EQ_CTRL_CMD_FREE 0x1
6013 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE)
6014 #define G_FW_EQ_CTRL_CMD_FREE(x) \
6015 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
6016 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U)
6017
6018 #define S_FW_EQ_CTRL_CMD_MODIFY 29
6019 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1
6020 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY)
6021 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \
6022 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
6023 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U)
6024
6025 #define S_FW_EQ_CTRL_CMD_EQSTART 28
6026 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1
6027 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART)
6028 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \
6029 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
6030 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U)
6031
6032 #define S_FW_EQ_CTRL_CMD_EQSTOP 27
6033 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1
6034 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP)
6035 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \
6036 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
6037 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U)
6038
6039 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20
6040 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff
6041 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
6042 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \
6043 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
6044
6045 #define S_FW_EQ_CTRL_CMD_EQID 0
6046 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff
6047 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID)
6048 #define G_FW_EQ_CTRL_CMD_EQID(x) \
6049 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
6050
6051 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0
6052 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff
6053 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
6054 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \
6055 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
6056
6057 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26
6058 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1
6059 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)
6060 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \
6061 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
6062 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U)
6063
6064 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25
6065 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1
6066 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)
6067 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \
6068 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
6069 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)
6070
6071 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24
6072 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1
6073 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)
6074 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \
6075 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
6076 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)
6077
6078 #define S_FW_EQ_CTRL_CMD_FETCHNS 23
6079 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1
6080 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS)
6081 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \
6082 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
6083 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U)
6084
6085 #define S_FW_EQ_CTRL_CMD_FETCHRO 22
6086 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1
6087 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
6088 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \
6089 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
6090 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U)
6091
6092 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20
6093 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3
6094 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
6095 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \
6096 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
6097
6098 #define S_FW_EQ_CTRL_CMD_CPRIO 19
6099 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1
6100 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO)
6101 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \
6102 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
6103 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U)
6104
6105 #define S_FW_EQ_CTRL_CMD_ONCHIP 18
6106 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1
6107 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP)
6108 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \
6109 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
6110 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U)
6111
6112 #define S_FW_EQ_CTRL_CMD_PCIECHN 16
6113 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3
6114 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
6115 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \
6116 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
6117
6118 #define S_FW_EQ_CTRL_CMD_IQID 0
6119 #define M_FW_EQ_CTRL_CMD_IQID 0xffff
6120 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID)
6121 #define G_FW_EQ_CTRL_CMD_IQID(x) \
6122 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
6123
6124 #define S_FW_EQ_CTRL_CMD_DCAEN 31
6125 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1
6126 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN)
6127 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \
6128 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
6129 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U)
6130
6131 #define S_FW_EQ_CTRL_CMD_DCACPU 26
6132 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f
6133 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU)
6134 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \
6135 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
6136
6137 #define S_FW_EQ_CTRL_CMD_FBMIN 23
6138 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7
6139 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN)
6140 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \
6141 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
6142
6143 #define S_FW_EQ_CTRL_CMD_FBMAX 20
6144 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7
6145 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX)
6146 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \
6147 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
6148
6149 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19
6150 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1
6151 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
6152 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
6153 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
6154 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
6155 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)
6156
6157 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16
6158 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7
6159 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
6160 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \
6161 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
6162
6163 #define S_FW_EQ_CTRL_CMD_EQSIZE 0
6164 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff
6165 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
6166 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \
6167 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
6168
6169 struct fw_eq_ofld_cmd {
6170 __be32 op_to_vfn;
6171 __be32 alloc_to_len16;
6172 __be32 eqid_pkd;
6173 __be32 physeqid_pkd;
6174 __be32 fetchszm_to_iqid;
6175 __be32 dcaen_to_eqsize;
6176 __be64 eqaddr;
6177 };
6178
6179 #define S_FW_EQ_OFLD_CMD_PFN 8
6180 #define M_FW_EQ_OFLD_CMD_PFN 0x7
6181 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN)
6182 #define G_FW_EQ_OFLD_CMD_PFN(x) \
6183 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
6184
6185 #define S_FW_EQ_OFLD_CMD_VFN 0
6186 #define M_FW_EQ_OFLD_CMD_VFN 0xff
6187 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN)
6188 #define G_FW_EQ_OFLD_CMD_VFN(x) \
6189 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
6190
6191 #define S_FW_EQ_OFLD_CMD_ALLOC 31
6192 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1
6193 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC)
6194 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \
6195 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
6196 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U)
6197
6198 #define S_FW_EQ_OFLD_CMD_FREE 30
6199 #define M_FW_EQ_OFLD_CMD_FREE 0x1
6200 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE)
6201 #define G_FW_EQ_OFLD_CMD_FREE(x) \
6202 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
6203 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U)
6204
6205 #define S_FW_EQ_OFLD_CMD_MODIFY 29
6206 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1
6207 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY)
6208 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \
6209 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
6210 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U)
6211
6212 #define S_FW_EQ_OFLD_CMD_EQSTART 28
6213 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1
6214 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART)
6215 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \
6216 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
6217 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U)
6218
6219 #define S_FW_EQ_OFLD_CMD_EQSTOP 27
6220 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1
6221 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP)
6222 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \
6223 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
6224 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U)
6225
6226 #define S_FW_EQ_OFLD_CMD_EQID 0
6227 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff
6228 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID)
6229 #define G_FW_EQ_OFLD_CMD_EQID(x) \
6230 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
6231
6232 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0
6233 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff
6234 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)
6235 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \
6236 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
6237
6238 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26
6239 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1
6240 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)
6241 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \
6242 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
6243 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U)
6244
6245 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25
6246 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1
6247 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)
6248 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \
6249 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
6250 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)
6251
6252 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24
6253 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1
6254 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)
6255 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \
6256 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
6257 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)
6258
6259 #define S_FW_EQ_OFLD_CMD_FETCHNS 23
6260 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1
6261 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS)
6262 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \
6263 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
6264 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U)
6265
6266 #define S_FW_EQ_OFLD_CMD_FETCHRO 22
6267 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1
6268 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO)
6269 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \
6270 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
6271 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U)
6272
6273 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20
6274 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3
6275 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)
6276 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \
6277 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
6278
6279 #define S_FW_EQ_OFLD_CMD_CPRIO 19
6280 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1
6281 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO)
6282 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \
6283 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
6284 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U)
6285
6286 #define S_FW_EQ_OFLD_CMD_ONCHIP 18
6287 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1
6288 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP)
6289 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \
6290 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
6291 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U)
6292
6293 #define S_FW_EQ_OFLD_CMD_PCIECHN 16
6294 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3
6295 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN)
6296 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \
6297 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
6298
6299 #define S_FW_EQ_OFLD_CMD_IQID 0
6300 #define M_FW_EQ_OFLD_CMD_IQID 0xffff
6301 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID)
6302 #define G_FW_EQ_OFLD_CMD_IQID(x) \
6303 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
6304
6305 #define S_FW_EQ_OFLD_CMD_DCAEN 31
6306 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1
6307 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN)
6308 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \
6309 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
6310 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U)
6311
6312 #define S_FW_EQ_OFLD_CMD_DCACPU 26
6313 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f
6314 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU)
6315 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \
6316 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
6317
6318 #define S_FW_EQ_OFLD_CMD_FBMIN 23
6319 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7
6320 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN)
6321 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \
6322 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
6323
6324 #define S_FW_EQ_OFLD_CMD_FBMAX 20
6325 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7
6326 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX)
6327 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \
6328 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
6329
6330 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19
6331 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1
6332 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6333 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6334 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
6335 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
6336 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)
6337
6338 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16
6339 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7
6340 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6341 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \
6342 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
6343
6344 #define S_FW_EQ_OFLD_CMD_EQSIZE 0
6345 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff
6346 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
6347 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \
6348 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
6349
6350 /* Macros for VIID parsing:
6351 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */
6352 #define S_FW_VIID_PFN 8
6353 #define M_FW_VIID_PFN 0x7
6354 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN)
6355 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)
6356
6357 #define S_FW_VIID_VIVLD 7
6358 #define M_FW_VIID_VIVLD 0x1
6359 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD)
6360 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
6361
6362 #define S_FW_VIID_VIN 0
6363 #define M_FW_VIID_VIN 0x7F
6364 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN)
6365 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
6366
6367 enum fw_vi_func {
6368 FW_VI_FUNC_ETH,
6369 FW_VI_FUNC_OFLD,
6370 FW_VI_FUNC_IWARP,
6371 FW_VI_FUNC_OPENISCSI,
6372 FW_VI_FUNC_OPENFCOE,
6373 FW_VI_FUNC_FOISCSI,
6374 FW_VI_FUNC_FOFCOE,
6375 FW_VI_FUNC_FW,
6376 };
6377
6378 struct fw_vi_cmd {
6379 __be32 op_to_vfn;
6380 __be32 alloc_to_len16;
6381 __be16 type_to_viid;
6382 __u8 mac[6];
6383 __u8 portid_pkd;
6384 __u8 nmac;
6385 __u8 nmac0[6];
6386 __be16 norss_rsssize;
6387 __u8 nmac1[6];
6388 __be16 idsiiq_pkd;
6389 __u8 nmac2[6];
6390 __be16 idseiq_pkd;
6391 __u8 nmac3[6];
6392 __be64 r9;
6393 __be64 r10;
6394 };
6395
6396 #define S_FW_VI_CMD_PFN 8
6397 #define M_FW_VI_CMD_PFN 0x7
6398 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN)
6399 #define G_FW_VI_CMD_PFN(x) \
6400 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
6401
6402 #define S_FW_VI_CMD_VFN 0
6403 #define M_FW_VI_CMD_VFN 0xff
6404 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN)
6405 #define G_FW_VI_CMD_VFN(x) \
6406 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
6407
6408 #define S_FW_VI_CMD_ALLOC 31
6409 #define M_FW_VI_CMD_ALLOC 0x1
6410 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC)
6411 #define G_FW_VI_CMD_ALLOC(x) \
6412 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
6413 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U)
6414
6415 #define S_FW_VI_CMD_FREE 30
6416 #define M_FW_VI_CMD_FREE 0x1
6417 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE)
6418 #define G_FW_VI_CMD_FREE(x) \
6419 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
6420 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U)
6421
6422 #define S_FW_VI_CMD_TYPE 15
6423 #define M_FW_VI_CMD_TYPE 0x1
6424 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE)
6425 #define G_FW_VI_CMD_TYPE(x) \
6426 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
6427 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U)
6428
6429 #define S_FW_VI_CMD_FUNC 12
6430 #define M_FW_VI_CMD_FUNC 0x7
6431 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC)
6432 #define G_FW_VI_CMD_FUNC(x) \
6433 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
6434
6435 #define S_FW_VI_CMD_VIID 0
6436 #define M_FW_VI_CMD_VIID 0xfff
6437 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID)
6438 #define G_FW_VI_CMD_VIID(x) \
6439 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
6440
6441 #define S_FW_VI_CMD_PORTID 4
6442 #define M_FW_VI_CMD_PORTID 0xf
6443 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID)
6444 #define G_FW_VI_CMD_PORTID(x) \
6445 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
6446
6447 #define S_FW_VI_CMD_NORSS 11
6448 #define M_FW_VI_CMD_NORSS 0x1
6449 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS)
6450 #define G_FW_VI_CMD_NORSS(x) \
6451 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)
6452 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U)
6453
6454 #define S_FW_VI_CMD_RSSSIZE 0
6455 #define M_FW_VI_CMD_RSSSIZE 0x7ff
6456 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE)
6457 #define G_FW_VI_CMD_RSSSIZE(x) \
6458 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
6459
6460 #define S_FW_VI_CMD_IDSIIQ 0
6461 #define M_FW_VI_CMD_IDSIIQ 0x3ff
6462 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ)
6463 #define G_FW_VI_CMD_IDSIIQ(x) \
6464 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
6465
6466 #define S_FW_VI_CMD_IDSEIQ 0
6467 #define M_FW_VI_CMD_IDSEIQ 0x3ff
6468 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ)
6469 #define G_FW_VI_CMD_IDSEIQ(x) \
6470 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
6471
6472 /* Special VI_MAC command index ids */
6473 #define FW_VI_MAC_ADD_MAC 0x3FF
6474 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
6475 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
6476
6477 enum fw_vi_mac_smac {
6478 FW_VI_MAC_MPS_TCAM_ENTRY,
6479 FW_VI_MAC_MPS_TCAM_ONLY,
6480 FW_VI_MAC_SMT_ONLY,
6481 FW_VI_MAC_SMT_AND_MPSTCAM
6482 };
6483
6484 enum fw_vi_mac_result {
6485 FW_VI_MAC_R_SUCCESS,
6486 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
6487 FW_VI_MAC_R_SMAC_FAIL,
6488 FW_VI_MAC_R_F_ACL_CHECK
6489 };
6490
6491 enum fw_vi_mac_entry_types {
6492 FW_VI_MAC_TYPE_EXACTMAC,
6493 FW_VI_MAC_TYPE_HASHVEC,
6494 FW_VI_MAC_TYPE_RAW,
6495 };
6496
6497 struct fw_vi_mac_cmd {
6498 __be32 op_to_viid;
6499 __be32 freemacs_to_len16;
6500 union fw_vi_mac {
6501 struct fw_vi_mac_exact {
6502 __be16 valid_to_idx;
6503 __u8 macaddr[6];
6504 } exact[7];
6505 struct fw_vi_mac_hash {
6506 __be64 hashvec;
6507 } hash;
6508 struct fw_vi_mac_raw {
6509 __be32 raw_idx_pkd;
6510 __be32 data0_pkd;
6511 __be32 data1[2];
6512 __be64 data0m_pkd;
6513 __be32 data1m[2];
6514 } raw;
6515 } u;
6516 };
6517
6518 #define S_FW_VI_MAC_CMD_VIID 0
6519 #define M_FW_VI_MAC_CMD_VIID 0xfff
6520 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID)
6521 #define G_FW_VI_MAC_CMD_VIID(x) \
6522 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
6523
6524 #define S_FW_VI_MAC_CMD_FREEMACS 31
6525 #define M_FW_VI_MAC_CMD_FREEMACS 0x1
6526 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS)
6527 #define G_FW_VI_MAC_CMD_FREEMACS(x) \
6528 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
6529 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U)
6530
6531 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23
6532 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7
6533 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
6534 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \
6535 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE)
6536
6537 #define S_FW_VI_MAC_CMD_HASHUNIEN 22
6538 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1
6539 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN)
6540 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \
6541 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
6542 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U)
6543
6544 #define S_FW_VI_MAC_CMD_VALID 15
6545 #define M_FW_VI_MAC_CMD_VALID 0x1
6546 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID)
6547 #define G_FW_VI_MAC_CMD_VALID(x) \
6548 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
6549 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U)
6550
6551 #define S_FW_VI_MAC_CMD_PRIO 12
6552 #define M_FW_VI_MAC_CMD_PRIO 0x7
6553 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO)
6554 #define G_FW_VI_MAC_CMD_PRIO(x) \
6555 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
6556
6557 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10
6558 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3
6559 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
6560 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \
6561 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
6562
6563 #define S_FW_VI_MAC_CMD_IDX 0
6564 #define M_FW_VI_MAC_CMD_IDX 0x3ff
6565 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX)
6566 #define G_FW_VI_MAC_CMD_IDX(x) \
6567 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
6568
6569 #define S_FW_VI_MAC_CMD_RAW_IDX 16
6570 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff
6571 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX)
6572 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \
6573 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
6574
6575 #define S_FW_VI_MAC_CMD_DATA0 0
6576 #define M_FW_VI_MAC_CMD_DATA0 0xffff
6577 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0)
6578 #define G_FW_VI_MAC_CMD_DATA0(x) \
6579 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0)
6580
6581 /* T4 max MTU supported */
6582 #define T4_MAX_MTU_SUPPORTED 9600
6583 #define FW_RXMODE_MTU_NO_CHG 65535
6584
6585 struct fw_vi_rxmode_cmd {
6586 __be32 op_to_viid;
6587 __be32 retval_len16;
6588 __be32 mtu_to_vlanexen;
6589 __be32 r4_lo;
6590 };
6591
6592 #define S_FW_VI_RXMODE_CMD_VIID 0
6593 #define M_FW_VI_RXMODE_CMD_VIID 0xfff
6594 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID)
6595 #define G_FW_VI_RXMODE_CMD_VIID(x) \
6596 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
6597
6598 #define S_FW_VI_RXMODE_CMD_MTU 16
6599 #define M_FW_VI_RXMODE_CMD_MTU 0xffff
6600 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU)
6601 #define G_FW_VI_RXMODE_CMD_MTU(x) \
6602 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
6603
6604 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14
6605 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3
6606 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
6607 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \
6608 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
6609
6610 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12
6611 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3
6612 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6613 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
6614 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
6615 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
6616
6617 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10
6618 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3
6619 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6620 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
6621 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
6622 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN)
6623
6624 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8
6625 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3
6626 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
6627 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \
6628 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
6629
6630 struct fw_vi_enable_cmd {
6631 __be32 op_to_viid;
6632 __be32 ien_to_len16;
6633 __be16 blinkdur;
6634 __be16 r3;
6635 __be32 r4;
6636 };
6637
6638 #define S_FW_VI_ENABLE_CMD_VIID 0
6639 #define M_FW_VI_ENABLE_CMD_VIID 0xfff
6640 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID)
6641 #define G_FW_VI_ENABLE_CMD_VIID(x) \
6642 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
6643
6644 #define S_FW_VI_ENABLE_CMD_IEN 31
6645 #define M_FW_VI_ENABLE_CMD_IEN 0x1
6646 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN)
6647 #define G_FW_VI_ENABLE_CMD_IEN(x) \
6648 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
6649 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U)
6650
6651 #define S_FW_VI_ENABLE_CMD_EEN 30
6652 #define M_FW_VI_ENABLE_CMD_EEN 0x1
6653 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN)
6654 #define G_FW_VI_ENABLE_CMD_EEN(x) \
6655 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
6656 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U)
6657
6658 #define S_FW_VI_ENABLE_CMD_LED 29
6659 #define M_FW_VI_ENABLE_CMD_LED 0x1
6660 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED)
6661 #define G_FW_VI_ENABLE_CMD_LED(x) \
6662 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
6663 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U)
6664
6665 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28
6666 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1
6667 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
6668 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \
6669 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
6670 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
6671
6672 /* VI VF stats offset definitions */
6673 #define VI_VF_NUM_STATS 16
6674 enum fw_vi_stats_vf_index {
6675 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
6676 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
6677 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
6678 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
6679 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
6680 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
6681 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
6682 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
6683 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
6684 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
6685 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
6686 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
6687 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
6688 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
6689 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
6690 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
6691 };
6692
6693 /* VI PF stats offset definitions */
6694 #define VI_PF_NUM_STATS 17
6695 enum fw_vi_stats_pf_index {
6696 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
6697 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
6698 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
6699 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
6700 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
6701 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
6702 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
6703 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
6704 FW_VI_PF_STAT_RX_BYTES_IX,
6705 FW_VI_PF_STAT_RX_FRAMES_IX,
6706 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
6707 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
6708 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
6709 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
6710 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
6711 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
6712 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
6713 };
6714
6715 struct fw_vi_stats_cmd {
6716 __be32 op_to_viid;
6717 __be32 retval_len16;
6718 union fw_vi_stats {
6719 struct fw_vi_stats_ctl {
6720 __be16 nstats_ix;
6721 __be16 r6;
6722 __be32 r7;
6723 __be64 stat0;
6724 __be64 stat1;
6725 __be64 stat2;
6726 __be64 stat3;
6727 __be64 stat4;
6728 __be64 stat5;
6729 } ctl;
6730 struct fw_vi_stats_pf {
6731 __be64 tx_bcast_bytes;
6732 __be64 tx_bcast_frames;
6733 __be64 tx_mcast_bytes;
6734 __be64 tx_mcast_frames;
6735 __be64 tx_ucast_bytes;
6736 __be64 tx_ucast_frames;
6737 __be64 tx_offload_bytes;
6738 __be64 tx_offload_frames;
6739 __be64 rx_pf_bytes;
6740 __be64 rx_pf_frames;
6741 __be64 rx_bcast_bytes;
6742 __be64 rx_bcast_frames;
6743 __be64 rx_mcast_bytes;
6744 __be64 rx_mcast_frames;
6745 __be64 rx_ucast_bytes;
6746 __be64 rx_ucast_frames;
6747 __be64 rx_err_frames;
6748 } pf;
6749 struct fw_vi_stats_vf {
6750 __be64 tx_bcast_bytes;
6751 __be64 tx_bcast_frames;
6752 __be64 tx_mcast_bytes;
6753 __be64 tx_mcast_frames;
6754 __be64 tx_ucast_bytes;
6755 __be64 tx_ucast_frames;
6756 __be64 tx_drop_frames;
6757 __be64 tx_offload_bytes;
6758 __be64 tx_offload_frames;
6759 __be64 rx_bcast_bytes;
6760 __be64 rx_bcast_frames;
6761 __be64 rx_mcast_bytes;
6762 __be64 rx_mcast_frames;
6763 __be64 rx_ucast_bytes;
6764 __be64 rx_ucast_frames;
6765 __be64 rx_err_frames;
6766 } vf;
6767 } u;
6768 };
6769
6770 #define S_FW_VI_STATS_CMD_VIID 0
6771 #define M_FW_VI_STATS_CMD_VIID 0xfff
6772 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID)
6773 #define G_FW_VI_STATS_CMD_VIID(x) \
6774 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
6775
6776 #define S_FW_VI_STATS_CMD_NSTATS 12
6777 #define M_FW_VI_STATS_CMD_NSTATS 0x7
6778 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS)
6779 #define G_FW_VI_STATS_CMD_NSTATS(x) \
6780 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
6781
6782 #define S_FW_VI_STATS_CMD_IX 0
6783 #define M_FW_VI_STATS_CMD_IX 0x1f
6784 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX)
6785 #define G_FW_VI_STATS_CMD_IX(x) \
6786 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
6787
6788 struct fw_acl_mac_cmd {
6789 __be32 op_to_vfn;
6790 __be32 en_to_len16;
6791 __u8 nmac;
6792 __u8 r3[7];
6793 __be16 r4;
6794 __u8 macaddr0[6];
6795 __be16 r5;
6796 __u8 macaddr1[6];
6797 __be16 r6;
6798 __u8 macaddr2[6];
6799 __be16 r7;
6800 __u8 macaddr3[6];
6801 };
6802
6803 #define S_FW_ACL_MAC_CMD_PFN 8
6804 #define M_FW_ACL_MAC_CMD_PFN 0x7
6805 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN)
6806 #define G_FW_ACL_MAC_CMD_PFN(x) \
6807 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
6808
6809 #define S_FW_ACL_MAC_CMD_VFN 0
6810 #define M_FW_ACL_MAC_CMD_VFN 0xff
6811 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN)
6812 #define G_FW_ACL_MAC_CMD_VFN(x) \
6813 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
6814
6815 #define S_FW_ACL_MAC_CMD_EN 31
6816 #define M_FW_ACL_MAC_CMD_EN 0x1
6817 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN)
6818 #define G_FW_ACL_MAC_CMD_EN(x) \
6819 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
6820 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U)
6821
6822 struct fw_acl_vlan_cmd {
6823 __be32 op_to_vfn;
6824 __be32 en_to_len16;
6825 __u8 nvlan;
6826 __u8 dropnovlan_fm;
6827 __u8 r3_lo[6];
6828 __be16 vlanid[16];
6829 };
6830
6831 #define S_FW_ACL_VLAN_CMD_PFN 8
6832 #define M_FW_ACL_VLAN_CMD_PFN 0x7
6833 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN)
6834 #define G_FW_ACL_VLAN_CMD_PFN(x) \
6835 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
6836
6837 #define S_FW_ACL_VLAN_CMD_VFN 0
6838 #define M_FW_ACL_VLAN_CMD_VFN 0xff
6839 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN)
6840 #define G_FW_ACL_VLAN_CMD_VFN(x) \
6841 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
6842
6843 #define S_FW_ACL_VLAN_CMD_EN 31
6844 #define M_FW_ACL_VLAN_CMD_EN 0x1
6845 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN)
6846 #define G_FW_ACL_VLAN_CMD_EN(x) \
6847 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
6848 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U)
6849
6850 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7
6851 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1
6852 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
6853 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \
6854 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
6855 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)
6856
6857 #define S_FW_ACL_VLAN_CMD_FM 6
6858 #define M_FW_ACL_VLAN_CMD_FM 0x1
6859 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM)
6860 #define G_FW_ACL_VLAN_CMD_FM(x) \
6861 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
6862 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U)
6863
6864 /* port capabilities bitmap */
6865 enum fw_port_cap {
6866 FW_PORT_CAP_SPEED_100M = 0x0001,
6867 FW_PORT_CAP_SPEED_1G = 0x0002,
6868 FW_PORT_CAP_SPEED_25G = 0x0004,
6869 FW_PORT_CAP_SPEED_10G = 0x0008,
6870 FW_PORT_CAP_SPEED_40G = 0x0010,
6871 FW_PORT_CAP_SPEED_100G = 0x0020,
6872 FW_PORT_CAP_FC_RX = 0x0040,
6873 FW_PORT_CAP_FC_TX = 0x0080,
6874 FW_PORT_CAP_ANEG = 0x0100,
6875 FW_PORT_CAP_MDIX = 0x0200,
6876 FW_PORT_CAP_MDIAUTO = 0x0400,
6877 FW_PORT_CAP_FEC_RS = 0x0800,
6878 FW_PORT_CAP_FEC_BASER_RS = 0x1000,
6879 FW_PORT_CAP_FEC_RESERVED = 0x2000,
6880 FW_PORT_CAP_802_3_PAUSE = 0x4000,
6881 FW_PORT_CAP_802_3_ASM_DIR = 0x8000,
6882 };
6883
6884 #define S_FW_PORT_CAP_SPEED 0
6885 #define M_FW_PORT_CAP_SPEED 0x3f
6886 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED)
6887 #define G_FW_PORT_CAP_SPEED(x) \
6888 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
6889
6890 #define S_FW_PORT_CAP_FC 6
6891 #define M_FW_PORT_CAP_FC 0x3
6892 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC)
6893 #define G_FW_PORT_CAP_FC(x) \
6894 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
6895
6896 #define S_FW_PORT_CAP_ANEG 8
6897 #define M_FW_PORT_CAP_ANEG 0x1
6898 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG)
6899 #define G_FW_PORT_CAP_ANEG(x) \
6900 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
6901
6902 #define S_FW_PORT_CAP_FEC 11
6903 #define M_FW_PORT_CAP_FEC 0x7
6904 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC)
6905 #define G_FW_PORT_CAP_FEC(x) \
6906 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC)
6907
6908 #define S_FW_PORT_CAP_802_3 14
6909 #define M_FW_PORT_CAP_802_3 0x3
6910 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3)
6911 #define G_FW_PORT_CAP_802_3(x) \
6912 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3)
6913
6914 enum fw_port_mdi {
6915 FW_PORT_CAP_MDI_UNCHANGED,
6916 FW_PORT_CAP_MDI_AUTO,
6917 FW_PORT_CAP_MDI_F_STRAIGHT,
6918 FW_PORT_CAP_MDI_F_CROSSOVER
6919 };
6920
6921 #define S_FW_PORT_CAP_MDI 9
6922 #define M_FW_PORT_CAP_MDI 3
6923 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
6924 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
6925
6926 #define S_FW_PORT_AUXLINFO_KX4 2
6927 #define M_FW_PORT_AUXLINFO_KX4 0x1
6928 #define V_FW_PORT_AUXLINFO_KX4(x) \
6929 ((x) << S_FW_PORT_AUXLINFO_KX4)
6930 #define G_FW_PORT_AUXLINFO_KX4(x) \
6931 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
6932 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U)
6933
6934 #define S_FW_PORT_AUXLINFO_KR 1
6935 #define M_FW_PORT_AUXLINFO_KR 0x1
6936 #define V_FW_PORT_AUXLINFO_KR(x) \
6937 ((x) << S_FW_PORT_AUXLINFO_KR)
6938 #define G_FW_PORT_AUXLINFO_KR(x) \
6939 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
6940 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U)
6941
6942 enum fw_port_action {
6943 FW_PORT_ACTION_L1_CFG = 0x0001,
6944 FW_PORT_ACTION_L2_CFG = 0x0002,
6945 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
6946 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
6947 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
6948 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
6949 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
6950 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
6951 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
6952 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
6953 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
6954 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
6955 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022,
6956 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023,
6957 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025,
6958 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026,
6959 FW_PORT_ACTION_DIAGNOSTICS = 0x0027,
6960 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028,
6961 FW_PORT_ACTION_PHY_RESET = 0x0040,
6962 FW_PORT_ACTION_PMA_RESET = 0x0041,
6963 FW_PORT_ACTION_PCS_RESET = 0x0042,
6964 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
6965 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
6966 FW_PORT_ACTION_AN_RESET = 0x0045,
6967
6968 };
6969
6970 enum fw_port_l2cfg_ctlbf {
6971 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
6972 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
6973 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
6974 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
6975 FW_PORT_L2_CTLBF_IVLAN = 0x10,
6976 FW_PORT_L2_CTLBF_TXIPG = 0x20,
6977 FW_PORT_L2_CTLBF_MTU = 0x40
6978 };
6979
6980 enum fw_dcb_app_tlv_sf {
6981 FW_DCB_APP_SF_ETHERTYPE,
6982 FW_DCB_APP_SF_SOCKET_TCP,
6983 FW_DCB_APP_SF_SOCKET_UDP,
6984 FW_DCB_APP_SF_SOCKET_ALL,
6985 };
6986
6987 enum fw_port_dcb_versions {
6988 FW_PORT_DCB_VER_UNKNOWN,
6989 FW_PORT_DCB_VER_CEE1D0,
6990 FW_PORT_DCB_VER_CEE1D01,
6991 FW_PORT_DCB_VER_IEEE,
6992 FW_PORT_DCB_VER_AUTO=7
6993 };
6994
6995 enum fw_port_dcb_cfg {
6996 FW_PORT_DCB_CFG_PG = 0x01,
6997 FW_PORT_DCB_CFG_PFC = 0x02,
6998 FW_PORT_DCB_CFG_APPL = 0x04
6999 };
7000
7001 enum fw_port_dcb_cfg_rc {
7002 FW_PORT_DCB_CFG_SUCCESS = 0x0,
7003 FW_PORT_DCB_CFG_ERROR = 0x1
7004 };
7005
7006 enum fw_port_dcb_type {
7007 FW_PORT_DCB_TYPE_PGID = 0x00,
7008 FW_PORT_DCB_TYPE_PGRATE = 0x01,
7009 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
7010 FW_PORT_DCB_TYPE_PFC = 0x03,
7011 FW_PORT_DCB_TYPE_APP_ID = 0x04,
7012 FW_PORT_DCB_TYPE_CONTROL = 0x05,
7013 };
7014
7015 enum fw_port_dcb_feature_state {
7016 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
7017 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
7018 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
7019 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
7020 };
7021
7022 enum fw_port_diag_ops {
7023 FW_PORT_DIAGS_TEMP = 0x00,
7024 FW_PORT_DIAGS_TX_POWER = 0x01,
7025 FW_PORT_DIAGS_RX_POWER = 0x02,
7026 FW_PORT_DIAGS_TX_DIS = 0x03,
7027 };
7028
7029 struct fw_port_cmd {
7030 __be32 op_to_portid;
7031 __be32 action_to_len16;
7032 union fw_port {
7033 struct fw_port_l1cfg {
7034 __be32 rcap;
7035 __be32 r;
7036 } l1cfg;
7037 struct fw_port_l2cfg {
7038 __u8 ctlbf;
7039 __u8 ovlan3_to_ivlan0;
7040 __be16 ivlantype;
7041 __be16 txipg_force_pinfo;
7042 __be16 mtu;
7043 __be16 ovlan0mask;
7044 __be16 ovlan0type;
7045 __be16 ovlan1mask;
7046 __be16 ovlan1type;
7047 __be16 ovlan2mask;
7048 __be16 ovlan2type;
7049 __be16 ovlan3mask;
7050 __be16 ovlan3type;
7051 } l2cfg;
7052 struct fw_port_info {
7053 __be32 lstatus_to_modtype;
7054 __be16 pcap;
7055 __be16 acap;
7056 __be16 mtu;
7057 __u8 cbllen;
7058 __u8 auxlinfo;
7059 __u8 dcbxdis_pkd;
7060 __u8 r8_lo;
7061 __be16 lpacap;
7062 __be64 r9;
7063 } info;
7064 struct fw_port_diags {
7065 __u8 diagop;
7066 __u8 r[3];
7067 __be32 diagval;
7068 } diags;
7069 union fw_port_dcb {
7070 struct fw_port_dcb_pgid {
7071 __u8 type;
7072 __u8 apply_pkd;
7073 __u8 r10_lo[2];
7074 __be32 pgid;
7075 __be64 r11;
7076 } pgid;
7077 struct fw_port_dcb_pgrate {
7078 __u8 type;
7079 __u8 apply_pkd;
7080 __u8 r10_lo[5];
7081 __u8 num_tcs_supported;
7082 __u8 pgrate[8];
7083 __u8 tsa[8];
7084 } pgrate;
7085 struct fw_port_dcb_priorate {
7086 __u8 type;
7087 __u8 apply_pkd;
7088 __u8 r10_lo[6];
7089 __u8 strict_priorate[8];
7090 } priorate;
7091 struct fw_port_dcb_pfc {
7092 __u8 type;
7093 __u8 pfcen;
7094 __u8 r10[5];
7095 __u8 max_pfc_tcs;
7096 __be64 r11;
7097 } pfc;
7098 struct fw_port_app_priority {
7099 __u8 type;
7100 __u8 r10[2];
7101 __u8 idx;
7102 __u8 user_prio_map;
7103 __u8 sel_field;
7104 __be16 protocolid;
7105 __be64 r12;
7106 } app_priority;
7107 struct fw_port_dcb_control {
7108 __u8 type;
7109 __u8 all_syncd_pkd;
7110 __be16 dcb_version_to_app_state;
7111 __be32 r11;
7112 __be64 r12;
7113 } control;
7114 } dcb;
7115 } u;
7116 };
7117
7118 #define S_FW_PORT_CMD_READ 22
7119 #define M_FW_PORT_CMD_READ 0x1
7120 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ)
7121 #define G_FW_PORT_CMD_READ(x) \
7122 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
7123 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U)
7124
7125 #define S_FW_PORT_CMD_PORTID 0
7126 #define M_FW_PORT_CMD_PORTID 0xf
7127 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID)
7128 #define G_FW_PORT_CMD_PORTID(x) \
7129 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
7130
7131 #define S_FW_PORT_CMD_ACTION 16
7132 #define M_FW_PORT_CMD_ACTION 0xffff
7133 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION)
7134 #define G_FW_PORT_CMD_ACTION(x) \
7135 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
7136
7137 #define S_FW_PORT_CMD_OVLAN3 7
7138 #define M_FW_PORT_CMD_OVLAN3 0x1
7139 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3)
7140 #define G_FW_PORT_CMD_OVLAN3(x) \
7141 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
7142 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U)
7143
7144 #define S_FW_PORT_CMD_OVLAN2 6
7145 #define M_FW_PORT_CMD_OVLAN2 0x1
7146 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2)
7147 #define G_FW_PORT_CMD_OVLAN2(x) \
7148 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
7149 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U)
7150
7151 #define S_FW_PORT_CMD_OVLAN1 5
7152 #define M_FW_PORT_CMD_OVLAN1 0x1
7153 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1)
7154 #define G_FW_PORT_CMD_OVLAN1(x) \
7155 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
7156 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U)
7157
7158 #define S_FW_PORT_CMD_OVLAN0 4
7159 #define M_FW_PORT_CMD_OVLAN0 0x1
7160 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0)
7161 #define G_FW_PORT_CMD_OVLAN0(x) \
7162 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
7163 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U)
7164
7165 #define S_FW_PORT_CMD_IVLAN0 3
7166 #define M_FW_PORT_CMD_IVLAN0 0x1
7167 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0)
7168 #define G_FW_PORT_CMD_IVLAN0(x) \
7169 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
7170 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U)
7171
7172 #define S_FW_PORT_CMD_TXIPG 3
7173 #define M_FW_PORT_CMD_TXIPG 0x1fff
7174 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG)
7175 #define G_FW_PORT_CMD_TXIPG(x) \
7176 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
7177
7178 #define S_FW_PORT_CMD_FORCE_PINFO 0
7179 #define M_FW_PORT_CMD_FORCE_PINFO 0x1
7180 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO)
7181 #define G_FW_PORT_CMD_FORCE_PINFO(x) \
7182 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
7183 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U)
7184
7185 #define S_FW_PORT_CMD_LSTATUS 31
7186 #define M_FW_PORT_CMD_LSTATUS 0x1
7187 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS)
7188 #define G_FW_PORT_CMD_LSTATUS(x) \
7189 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
7190 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U)
7191
7192 #define S_FW_PORT_CMD_LSPEED 24
7193 #define M_FW_PORT_CMD_LSPEED 0x3f
7194 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED)
7195 #define G_FW_PORT_CMD_LSPEED(x) \
7196 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
7197
7198 #define S_FW_PORT_CMD_TXPAUSE 23
7199 #define M_FW_PORT_CMD_TXPAUSE 0x1
7200 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE)
7201 #define G_FW_PORT_CMD_TXPAUSE(x) \
7202 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
7203 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U)
7204
7205 #define S_FW_PORT_CMD_RXPAUSE 22
7206 #define M_FW_PORT_CMD_RXPAUSE 0x1
7207 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE)
7208 #define G_FW_PORT_CMD_RXPAUSE(x) \
7209 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
7210 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U)
7211
7212 #define S_FW_PORT_CMD_MDIOCAP 21
7213 #define M_FW_PORT_CMD_MDIOCAP 0x1
7214 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP)
7215 #define G_FW_PORT_CMD_MDIOCAP(x) \
7216 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
7217 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U)
7218
7219 #define S_FW_PORT_CMD_MDIOADDR 16
7220 #define M_FW_PORT_CMD_MDIOADDR 0x1f
7221 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR)
7222 #define G_FW_PORT_CMD_MDIOADDR(x) \
7223 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
7224
7225 #define S_FW_PORT_CMD_LPTXPAUSE 15
7226 #define M_FW_PORT_CMD_LPTXPAUSE 0x1
7227 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE)
7228 #define G_FW_PORT_CMD_LPTXPAUSE(x) \
7229 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
7230 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U)
7231
7232 #define S_FW_PORT_CMD_LPRXPAUSE 14
7233 #define M_FW_PORT_CMD_LPRXPAUSE 0x1
7234 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE)
7235 #define G_FW_PORT_CMD_LPRXPAUSE(x) \
7236 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
7237 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U)
7238
7239 #define S_FW_PORT_CMD_PTYPE 8
7240 #define M_FW_PORT_CMD_PTYPE 0x1f
7241 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE)
7242 #define G_FW_PORT_CMD_PTYPE(x) \
7243 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
7244
7245 #define S_FW_PORT_CMD_LINKDNRC 5
7246 #define M_FW_PORT_CMD_LINKDNRC 0x7
7247 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC)
7248 #define G_FW_PORT_CMD_LINKDNRC(x) \
7249 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
7250
7251 #define S_FW_PORT_CMD_MODTYPE 0
7252 #define M_FW_PORT_CMD_MODTYPE 0x1f
7253 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE)
7254 #define G_FW_PORT_CMD_MODTYPE(x) \
7255 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
7256
7257 #define S_FW_PORT_CMD_DCBXDIS 7
7258 #define M_FW_PORT_CMD_DCBXDIS 0x1
7259 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS)
7260 #define G_FW_PORT_CMD_DCBXDIS(x) \
7261 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)
7262 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U)
7263
7264 #define S_FW_PORT_CMD_APPLY 7
7265 #define M_FW_PORT_CMD_APPLY 0x1
7266 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY)
7267 #define G_FW_PORT_CMD_APPLY(x) \
7268 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
7269 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U)
7270
7271 #define S_FW_PORT_CMD_ALL_SYNCD 7
7272 #define M_FW_PORT_CMD_ALL_SYNCD 0x1
7273 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD)
7274 #define G_FW_PORT_CMD_ALL_SYNCD(x) \
7275 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
7276 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U)
7277
7278 #define S_FW_PORT_CMD_DCB_VERSION 12
7279 #define M_FW_PORT_CMD_DCB_VERSION 0x7
7280 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION)
7281 #define G_FW_PORT_CMD_DCB_VERSION(x) \
7282 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION)
7283
7284 #define S_FW_PORT_CMD_PFC_STATE 8
7285 #define M_FW_PORT_CMD_PFC_STATE 0xf
7286 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE)
7287 #define G_FW_PORT_CMD_PFC_STATE(x) \
7288 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)
7289
7290 #define S_FW_PORT_CMD_ETS_STATE 4
7291 #define M_FW_PORT_CMD_ETS_STATE 0xf
7292 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE)
7293 #define G_FW_PORT_CMD_ETS_STATE(x) \
7294 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)
7295
7296 #define S_FW_PORT_CMD_APP_STATE 0
7297 #define M_FW_PORT_CMD_APP_STATE 0xf
7298 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE)
7299 #define G_FW_PORT_CMD_APP_STATE(x) \
7300 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
7301
7302 /*
7303 * These are configured into the VPD and hence tools that generate
7304 * VPD may use this enumeration.
7305 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
7306 *
7307 * REMEMBER:
7308 * Update the Common Code t4_hw.c:t4_get_port_type_description()
7309 * with any new Firmware Port Technology Types!
7310 */
7311 enum fw_port_type {
7312 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
7313 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */
7314 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */
7315 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */
7316 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */
7317 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */
7318 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */
7319 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */
7320 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */
7321 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */
7322 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
7323 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
7324 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */
7325 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */
7326 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */
7327 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
7328 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */
7329 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */
7330 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */
7331 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */
7332 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */
7333 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */
7334 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
7335 };
7336
7337 /* These are read from module's EEPROM and determined once the
7338 module is inserted. */
7339 enum fw_port_module_type {
7340 FW_PORT_MOD_TYPE_NA = 0x0,
7341 FW_PORT_MOD_TYPE_LR = 0x1,
7342 FW_PORT_MOD_TYPE_SR = 0x2,
7343 FW_PORT_MOD_TYPE_ER = 0x3,
7344 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4,
7345 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5,
7346 FW_PORT_MOD_TYPE_LRM = 0x6,
7347 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3,
7348 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2,
7349 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1,
7350 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE
7351 };
7352
7353 /* used by FW and tools may use this to generate VPD */
7354 enum fw_port_mod_sub_type {
7355 FW_PORT_MOD_SUB_TYPE_NA,
7356 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1,
7357 FW_PORT_MOD_SUB_TYPE_TN8022=0x2,
7358 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,
7359 FW_PORT_MOD_SUB_TYPE_88x3120=0x4,
7360 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,
7361 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6,
7362 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7,
7363 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,
7364
7365 /*
7366 * The following will never been in the VPD. They are TWINAX cable
7367 * lengths decoded from SFP+ module i2c PROMs. These should almost
7368 * certainly go somewhere else ...
7369 */
7370 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9,
7371 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA,
7372 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB,
7373 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC,
7374 };
7375
7376 /* link down reason codes (3b) */
7377 enum fw_port_link_dn_rc {
7378 FW_PORT_LINK_DN_RC_NONE,
7379 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */
7380 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */
7381 FW_PORT_LINK_DN_RESERVED3,
7382 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */
7383 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */
7384 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */
7385 FW_PORT_LINK_DN_RESERVED7
7386 };
7387 enum fw_port_stats_tx_index {
7388 FW_STAT_TX_PORT_BYTES_IX = 0,
7389 FW_STAT_TX_PORT_FRAMES_IX,
7390 FW_STAT_TX_PORT_BCAST_IX,
7391 FW_STAT_TX_PORT_MCAST_IX,
7392 FW_STAT_TX_PORT_UCAST_IX,
7393 FW_STAT_TX_PORT_ERROR_IX,
7394 FW_STAT_TX_PORT_64B_IX,
7395 FW_STAT_TX_PORT_65B_127B_IX,
7396 FW_STAT_TX_PORT_128B_255B_IX,
7397 FW_STAT_TX_PORT_256B_511B_IX,
7398 FW_STAT_TX_PORT_512B_1023B_IX,
7399 FW_STAT_TX_PORT_1024B_1518B_IX,
7400 FW_STAT_TX_PORT_1519B_MAX_IX,
7401 FW_STAT_TX_PORT_DROP_IX,
7402 FW_STAT_TX_PORT_PAUSE_IX,
7403 FW_STAT_TX_PORT_PPP0_IX,
7404 FW_STAT_TX_PORT_PPP1_IX,
7405 FW_STAT_TX_PORT_PPP2_IX,
7406 FW_STAT_TX_PORT_PPP3_IX,
7407 FW_STAT_TX_PORT_PPP4_IX,
7408 FW_STAT_TX_PORT_PPP5_IX,
7409 FW_STAT_TX_PORT_PPP6_IX,
7410 FW_STAT_TX_PORT_PPP7_IX,
7411 FW_NUM_PORT_TX_STATS
7412 };
7413
7414 enum fw_port_stat_rx_index {
7415 FW_STAT_RX_PORT_BYTES_IX = 0,
7416 FW_STAT_RX_PORT_FRAMES_IX,
7417 FW_STAT_RX_PORT_BCAST_IX,
7418 FW_STAT_RX_PORT_MCAST_IX,
7419 FW_STAT_RX_PORT_UCAST_IX,
7420 FW_STAT_RX_PORT_MTU_ERROR_IX,
7421 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
7422 FW_STAT_RX_PORT_CRC_ERROR_IX,
7423 FW_STAT_RX_PORT_LEN_ERROR_IX,
7424 FW_STAT_RX_PORT_SYM_ERROR_IX,
7425 FW_STAT_RX_PORT_64B_IX,
7426 FW_STAT_RX_PORT_65B_127B_IX,
7427 FW_STAT_RX_PORT_128B_255B_IX,
7428 FW_STAT_RX_PORT_256B_511B_IX,
7429 FW_STAT_RX_PORT_512B_1023B_IX,
7430 FW_STAT_RX_PORT_1024B_1518B_IX,
7431 FW_STAT_RX_PORT_1519B_MAX_IX,
7432 FW_STAT_RX_PORT_PAUSE_IX,
7433 FW_STAT_RX_PORT_PPP0_IX,
7434 FW_STAT_RX_PORT_PPP1_IX,
7435 FW_STAT_RX_PORT_PPP2_IX,
7436 FW_STAT_RX_PORT_PPP3_IX,
7437 FW_STAT_RX_PORT_PPP4_IX,
7438 FW_STAT_RX_PORT_PPP5_IX,
7439 FW_STAT_RX_PORT_PPP6_IX,
7440 FW_STAT_RX_PORT_PPP7_IX,
7441 FW_STAT_RX_PORT_LESS_64B_IX,
7442 FW_STAT_RX_PORT_MAC_ERROR_IX,
7443 FW_NUM_PORT_RX_STATS
7444 };
7445 /* port stats */
7446 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \
7447 FW_NUM_PORT_RX_STATS)
7448
7449
7450 struct fw_port_stats_cmd {
7451 __be32 op_to_portid;
7452 __be32 retval_len16;
7453 union fw_port_stats {
7454 struct fw_port_stats_ctl {
7455 __u8 nstats_bg_bm;
7456 __u8 tx_ix;
7457 __be16 r6;
7458 __be32 r7;
7459 __be64 stat0;
7460 __be64 stat1;
7461 __be64 stat2;
7462 __be64 stat3;
7463 __be64 stat4;
7464 __be64 stat5;
7465 } ctl;
7466 struct fw_port_stats_all {
7467 __be64 tx_bytes;
7468 __be64 tx_frames;
7469 __be64 tx_bcast;
7470 __be64 tx_mcast;
7471 __be64 tx_ucast;
7472 __be64 tx_error;
7473 __be64 tx_64b;
7474 __be64 tx_65b_127b;
7475 __be64 tx_128b_255b;
7476 __be64 tx_256b_511b;
7477 __be64 tx_512b_1023b;
7478 __be64 tx_1024b_1518b;
7479 __be64 tx_1519b_max;
7480 __be64 tx_drop;
7481 __be64 tx_pause;
7482 __be64 tx_ppp0;
7483 __be64 tx_ppp1;
7484 __be64 tx_ppp2;
7485 __be64 tx_ppp3;
7486 __be64 tx_ppp4;
7487 __be64 tx_ppp5;
7488 __be64 tx_ppp6;
7489 __be64 tx_ppp7;
7490 __be64 rx_bytes;
7491 __be64 rx_frames;
7492 __be64 rx_bcast;
7493 __be64 rx_mcast;
7494 __be64 rx_ucast;
7495 __be64 rx_mtu_error;
7496 __be64 rx_mtu_crc_error;
7497 __be64 rx_crc_error;
7498 __be64 rx_len_error;
7499 __be64 rx_sym_error;
7500 __be64 rx_64b;
7501 __be64 rx_65b_127b;
7502 __be64 rx_128b_255b;
7503 __be64 rx_256b_511b;
7504 __be64 rx_512b_1023b;
7505 __be64 rx_1024b_1518b;
7506 __be64 rx_1519b_max;
7507 __be64 rx_pause;
7508 __be64 rx_ppp0;
7509 __be64 rx_ppp1;
7510 __be64 rx_ppp2;
7511 __be64 rx_ppp3;
7512 __be64 rx_ppp4;
7513 __be64 rx_ppp5;
7514 __be64 rx_ppp6;
7515 __be64 rx_ppp7;
7516 __be64 rx_less_64b;
7517 __be64 rx_bg_drop;
7518 __be64 rx_bg_trunc;
7519 } all;
7520 } u;
7521 };
7522
7523 #define S_FW_PORT_STATS_CMD_NSTATS 4
7524 #define M_FW_PORT_STATS_CMD_NSTATS 0x7
7525 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS)
7526 #define G_FW_PORT_STATS_CMD_NSTATS(x) \
7527 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
7528
7529 #define S_FW_PORT_STATS_CMD_BG_BM 0
7530 #define M_FW_PORT_STATS_CMD_BG_BM 0x3
7531 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM)
7532 #define G_FW_PORT_STATS_CMD_BG_BM(x) \
7533 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
7534
7535 #define S_FW_PORT_STATS_CMD_TX 7
7536 #define M_FW_PORT_STATS_CMD_TX 0x1
7537 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX)
7538 #define G_FW_PORT_STATS_CMD_TX(x) \
7539 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
7540 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U)
7541
7542 #define S_FW_PORT_STATS_CMD_IX 0
7543 #define M_FW_PORT_STATS_CMD_IX 0x3f
7544 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX)
7545 #define G_FW_PORT_STATS_CMD_IX(x) \
7546 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
7547
7548 /* port loopback stats */
7549 #define FW_NUM_LB_STATS 14
7550 enum fw_port_lb_stats_index {
7551 FW_STAT_LB_PORT_BYTES_IX,
7552 FW_STAT_LB_PORT_FRAMES_IX,
7553 FW_STAT_LB_PORT_BCAST_IX,
7554 FW_STAT_LB_PORT_MCAST_IX,
7555 FW_STAT_LB_PORT_UCAST_IX,
7556 FW_STAT_LB_PORT_ERROR_IX,
7557 FW_STAT_LB_PORT_64B_IX,
7558 FW_STAT_LB_PORT_65B_127B_IX,
7559 FW_STAT_LB_PORT_128B_255B_IX,
7560 FW_STAT_LB_PORT_256B_511B_IX,
7561 FW_STAT_LB_PORT_512B_1023B_IX,
7562 FW_STAT_LB_PORT_1024B_1518B_IX,
7563 FW_STAT_LB_PORT_1519B_MAX_IX,
7564 FW_STAT_LB_PORT_DROP_FRAMES_IX
7565 };
7566
7567 struct fw_port_lb_stats_cmd {
7568 __be32 op_to_lbport;
7569 __be32 retval_len16;
7570 union fw_port_lb_stats {
7571 struct fw_port_lb_stats_ctl {
7572 __u8 nstats_bg_bm;
7573 __u8 ix_pkd;
7574 __be16 r6;
7575 __be32 r7;
7576 __be64 stat0;
7577 __be64 stat1;
7578 __be64 stat2;
7579 __be64 stat3;
7580 __be64 stat4;
7581 __be64 stat5;
7582 } ctl;
7583 struct fw_port_lb_stats_all {
7584 __be64 tx_bytes;
7585 __be64 tx_frames;
7586 __be64 tx_bcast;
7587 __be64 tx_mcast;
7588 __be64 tx_ucast;
7589 __be64 tx_error;
7590 __be64 tx_64b;
7591 __be64 tx_65b_127b;
7592 __be64 tx_128b_255b;
7593 __be64 tx_256b_511b;
7594 __be64 tx_512b_1023b;
7595 __be64 tx_1024b_1518b;
7596 __be64 tx_1519b_max;
7597 __be64 rx_lb_drop;
7598 __be64 rx_lb_trunc;
7599 } all;
7600 } u;
7601 };
7602
7603 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0
7604 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf
7605 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \
7606 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
7607 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \
7608 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)
7609
7610 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4
7611 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7
7612 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \
7613 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
7614 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \
7615 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)
7616
7617 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0
7618 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3
7619 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)
7620 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \
7621 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
7622
7623 #define S_FW_PORT_LB_STATS_CMD_IX 0
7624 #define M_FW_PORT_LB_STATS_CMD_IX 0xf
7625 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX)
7626 #define G_FW_PORT_LB_STATS_CMD_IX(x) \
7627 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
7628
7629 /* Trace related defines */
7630 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240
7631 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560
7632
7633 struct fw_port_trace_cmd {
7634 __be32 op_to_portid;
7635 __be32 retval_len16;
7636 __be16 traceen_to_pciech;
7637 __be16 qnum;
7638 __be32 r5;
7639 };
7640
7641 #define S_FW_PORT_TRACE_CMD_PORTID 0
7642 #define M_FW_PORT_TRACE_CMD_PORTID 0xf
7643 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID)
7644 #define G_FW_PORT_TRACE_CMD_PORTID(x) \
7645 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
7646
7647 #define S_FW_PORT_TRACE_CMD_TRACEEN 15
7648 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1
7649 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN)
7650 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \
7651 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
7652 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U)
7653
7654 #define S_FW_PORT_TRACE_CMD_FLTMODE 14
7655 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1
7656 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE)
7657 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \
7658 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
7659 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U)
7660
7661 #define S_FW_PORT_TRACE_CMD_DUPLEN 13
7662 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1
7663 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN)
7664 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \
7665 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
7666 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U)
7667
7668 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8
7669 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f
7670 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
7671 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
7672 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
7673 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
7674 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
7675
7676 #define S_FW_PORT_TRACE_CMD_PCIECH 6
7677 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3
7678 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH)
7679 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \
7680 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
7681
7682 struct fw_port_trace_mmap_cmd {
7683 __be32 op_to_portid;
7684 __be32 retval_len16;
7685 __be32 fid_to_skipoffset;
7686 __be32 minpktsize_capturemax;
7687 __u8 map[224];
7688 };
7689
7690 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0
7691 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf
7692 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
7693 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
7694 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
7695 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
7696 M_FW_PORT_TRACE_MMAP_CMD_PORTID)
7697
7698 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30
7699 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3
7700 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)
7701 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \
7702 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
7703
7704 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29
7705 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1
7706 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
7707 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
7708 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
7709 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
7710 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
7711 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)
7712
7713 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28
7714 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1
7715 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
7716 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
7717 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
7718 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
7719 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
7720 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)
7721
7722 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8
7723 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f
7724 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
7725 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
7726 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
7727 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
7728 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
7729
7730 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0
7731 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f
7732 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
7733 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
7734 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
7735 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
7736 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
7737
7738 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18
7739 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff
7740 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
7741 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
7742 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
7743 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
7744 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
7745
7746 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0
7747 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff
7748 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
7749 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
7750 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
7751 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
7752 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
7753
7754 enum fw_ptp_subop {
7755
7756 /* none */
7757 FW_PTP_SC_INIT_TIMER = 0x00,
7758 FW_PTP_SC_TX_TYPE = 0x01,
7759
7760 /* init */
7761 FW_PTP_SC_RXTIME_STAMP = 0x08,
7762 FW_PTP_SC_RDRX_TYPE = 0x09,
7763
7764 /* ts */
7765 FW_PTP_SC_ADJ_FREQ = 0x10,
7766 FW_PTP_SC_ADJ_TIME = 0x11,
7767 FW_PTP_SC_ADJ_FTIME = 0x12,
7768 FW_PTP_SC_WALL_CLOCK = 0x13,
7769 FW_PTP_SC_GET_TIME = 0x14,
7770 FW_PTP_SC_SET_TIME = 0x15,
7771 };
7772
7773 struct fw_ptp_cmd {
7774 __be32 op_to_portid;
7775 __be32 retval_len16;
7776 union fw_ptp {
7777 struct fw_ptp_sc {
7778 __u8 sc;
7779 __u8 r3[7];
7780 } scmd;
7781 struct fw_ptp_init {
7782 __u8 sc;
7783 __u8 txchan;
7784 __be16 absid;
7785 __be16 mode;
7786 __be16 r3;
7787 } init;
7788 struct fw_ptp_ts {
7789 __u8 sc;
7790 __u8 sign;
7791 __be16 r3;
7792 __be32 ppb;
7793 __be64 tm;
7794 } ts;
7795 } u;
7796 __be64 r3;
7797 };
7798
7799 #define S_FW_PTP_CMD_PORTID 0
7800 #define M_FW_PTP_CMD_PORTID 0xf
7801 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID)
7802 #define G_FW_PTP_CMD_PORTID(x) \
7803 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID)
7804
7805 struct fw_rss_ind_tbl_cmd {
7806 __be32 op_to_viid;
7807 __be32 retval_len16;
7808 __be16 niqid;
7809 __be16 startidx;
7810 __be32 r3;
7811 __be32 iq0_to_iq2;
7812 __be32 iq3_to_iq5;
7813 __be32 iq6_to_iq8;
7814 __be32 iq9_to_iq11;
7815 __be32 iq12_to_iq14;
7816 __be32 iq15_to_iq17;
7817 __be32 iq18_to_iq20;
7818 __be32 iq21_to_iq23;
7819 __be32 iq24_to_iq26;
7820 __be32 iq27_to_iq29;
7821 __be32 iq30_iq31;
7822 __be32 r15_lo;
7823 };
7824
7825 #define S_FW_RSS_IND_TBL_CMD_VIID 0
7826 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff
7827 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID)
7828 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \
7829 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
7830
7831 #define S_FW_RSS_IND_TBL_CMD_IQ0 20
7832 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff
7833 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
7834 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \
7835 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
7836
7837 #define S_FW_RSS_IND_TBL_CMD_IQ1 10
7838 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff
7839 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
7840 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \
7841 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
7842
7843 #define S_FW_RSS_IND_TBL_CMD_IQ2 0
7844 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff
7845 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
7846 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \
7847 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
7848
7849 #define S_FW_RSS_IND_TBL_CMD_IQ3 20
7850 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff
7851 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3)
7852 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \
7853 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
7854
7855 #define S_FW_RSS_IND_TBL_CMD_IQ4 10
7856 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff
7857 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4)
7858 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \
7859 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
7860
7861 #define S_FW_RSS_IND_TBL_CMD_IQ5 0
7862 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff
7863 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5)
7864 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \
7865 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
7866
7867 #define S_FW_RSS_IND_TBL_CMD_IQ6 20
7868 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff
7869 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6)
7870 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \
7871 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
7872
7873 #define S_FW_RSS_IND_TBL_CMD_IQ7 10
7874 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff
7875 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7)
7876 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \
7877 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
7878
7879 #define S_FW_RSS_IND_TBL_CMD_IQ8 0
7880 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff
7881 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8)
7882 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \
7883 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
7884
7885 #define S_FW_RSS_IND_TBL_CMD_IQ9 20
7886 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff
7887 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9)
7888 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \
7889 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
7890
7891 #define S_FW_RSS_IND_TBL_CMD_IQ10 10
7892 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff
7893 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10)
7894 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \
7895 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
7896
7897 #define S_FW_RSS_IND_TBL_CMD_IQ11 0
7898 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff
7899 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11)
7900 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \
7901 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
7902
7903 #define S_FW_RSS_IND_TBL_CMD_IQ12 20
7904 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff
7905 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12)
7906 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \
7907 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
7908
7909 #define S_FW_RSS_IND_TBL_CMD_IQ13 10
7910 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff
7911 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13)
7912 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \
7913 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
7914
7915 #define S_FW_RSS_IND_TBL_CMD_IQ14 0
7916 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff
7917 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14)
7918 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \
7919 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
7920
7921 #define S_FW_RSS_IND_TBL_CMD_IQ15 20
7922 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff
7923 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15)
7924 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \
7925 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
7926
7927 #define S_FW_RSS_IND_TBL_CMD_IQ16 10
7928 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff
7929 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16)
7930 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \
7931 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
7932
7933 #define S_FW_RSS_IND_TBL_CMD_IQ17 0
7934 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff
7935 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17)
7936 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \
7937 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
7938
7939 #define S_FW_RSS_IND_TBL_CMD_IQ18 20
7940 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff
7941 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18)
7942 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \
7943 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
7944
7945 #define S_FW_RSS_IND_TBL_CMD_IQ19 10
7946 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff
7947 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19)
7948 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \
7949 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
7950
7951 #define S_FW_RSS_IND_TBL_CMD_IQ20 0
7952 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff
7953 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20)
7954 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \
7955 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
7956
7957 #define S_FW_RSS_IND_TBL_CMD_IQ21 20
7958 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff
7959 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21)
7960 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \
7961 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
7962
7963 #define S_FW_RSS_IND_TBL_CMD_IQ22 10
7964 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff
7965 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22)
7966 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \
7967 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
7968
7969 #define S_FW_RSS_IND_TBL_CMD_IQ23 0
7970 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff
7971 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23)
7972 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \
7973 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
7974
7975 #define S_FW_RSS_IND_TBL_CMD_IQ24 20
7976 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff
7977 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24)
7978 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \
7979 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
7980
7981 #define S_FW_RSS_IND_TBL_CMD_IQ25 10
7982 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff
7983 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25)
7984 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \
7985 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
7986
7987 #define S_FW_RSS_IND_TBL_CMD_IQ26 0
7988 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff
7989 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26)
7990 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \
7991 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
7992
7993 #define S_FW_RSS_IND_TBL_CMD_IQ27 20
7994 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff
7995 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27)
7996 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \
7997 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
7998
7999 #define S_FW_RSS_IND_TBL_CMD_IQ28 10
8000 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff
8001 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28)
8002 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \
8003 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
8004
8005 #define S_FW_RSS_IND_TBL_CMD_IQ29 0
8006 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff
8007 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29)
8008 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \
8009 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
8010
8011 #define S_FW_RSS_IND_TBL_CMD_IQ30 20
8012 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff
8013 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30)
8014 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \
8015 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
8016
8017 #define S_FW_RSS_IND_TBL_CMD_IQ31 10
8018 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff
8019 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31)
8020 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \
8021 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
8022
8023 struct fw_rss_glb_config_cmd {
8024 __be32 op_to_write;
8025 __be32 retval_len16;
8026 union fw_rss_glb_config {
8027 struct fw_rss_glb_config_manual {
8028 __be32 mode_pkd;
8029 __be32 r3;
8030 __be64 r4;
8031 __be64 r5;
8032 } manual;
8033 struct fw_rss_glb_config_basicvirtual {
8034 __be32 mode_keymode;
8035 __be32 synmapen_to_hashtoeplitz;
8036 __be64 r8;
8037 __be64 r9;
8038 } basicvirtual;
8039 } u;
8040 };
8041
8042 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28
8043 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf
8044 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)
8045 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \
8046 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
8047
8048 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
8049 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
8050 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1
8051
8052 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26
8053 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3
8054 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
8055 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
8056 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
8057 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \
8058 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
8059
8060 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0
8061 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1
8062 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2
8063 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3
8064
8065 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8
8066 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1
8067 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
8068 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
8069 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
8070 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
8071 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
8072 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
8073
8074 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7
8075 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1
8076 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8077 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8078 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
8079 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
8080 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
8081 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \
8082 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
8083
8084 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6
8085 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1
8086 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8087 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8088 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
8089 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
8090 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
8091 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \
8092 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
8093
8094 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5
8095 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1
8096 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8097 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8098 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
8099 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
8100 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
8101 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \
8102 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
8103
8104 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4
8105 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1
8106 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8107 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8108 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
8109 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
8110 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
8111 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \
8112 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
8113
8114 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3
8115 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1
8116 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8117 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8118 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
8119 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
8120 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
8121 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
8122
8123 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2
8124 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1
8125 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8126 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8127 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
8128 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
8129 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
8130 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
8131
8132 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
8133 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1
8134 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8135 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8136 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
8137 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
8138 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
8139 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \
8140 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
8141
8142 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0
8143 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1
8144 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8145 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8146 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
8147 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
8148 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
8149 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \
8150 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
8151
8152 struct fw_rss_vi_config_cmd {
8153 __be32 op_to_viid;
8154 __be32 retval_len16;
8155 union fw_rss_vi_config {
8156 struct fw_rss_vi_config_manual {
8157 __be64 r3;
8158 __be64 r4;
8159 __be64 r5;
8160 } manual;
8161 struct fw_rss_vi_config_basicvirtual {
8162 __be32 r6;
8163 __be32 defaultq_to_udpen;
8164 __be32 secretkeyidx_pkd;
8165 __be32 secretkeyxor;
8166 __be64 r10;
8167 } basicvirtual;
8168 } u;
8169 };
8170
8171 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0
8172 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff
8173 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
8174 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \
8175 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
8176
8177 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16
8178 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff
8179 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8180 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8181 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
8182 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
8183 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
8184
8185 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4
8186 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1
8187 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8188 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8189 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
8190 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
8191 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
8192 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \
8193 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
8194
8195 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3
8196 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1
8197 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8198 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8199 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
8200 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
8201 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
8202 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \
8203 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
8204
8205 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2
8206 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1
8207 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8208 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8209 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
8210 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
8211 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
8212 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \
8213 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
8214
8215 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
8216 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1
8217 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8218 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8219 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
8220 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
8221 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
8222 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \
8223 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
8224
8225 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0
8226 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1
8227 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
8228 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \
8229 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
8230 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
8231
8232 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0
8233 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf
8234 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8235 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8236 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
8237 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \
8238 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
8239
8240 enum fw_sched_sc {
8241 FW_SCHED_SC_CONFIG = 0,
8242 FW_SCHED_SC_PARAMS = 1,
8243 };
8244
8245 enum fw_sched_type {
8246 FW_SCHED_TYPE_PKTSCHED = 0,
8247 FW_SCHED_TYPE_STREAMSCHED = 1,
8248 };
8249
8250 enum fw_sched_params_level {
8251 FW_SCHED_PARAMS_LEVEL_CL_RL = 0,
8252 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1,
8253 FW_SCHED_PARAMS_LEVEL_CH_RL = 2,
8254 };
8255
8256 enum fw_sched_params_mode {
8257 FW_SCHED_PARAMS_MODE_CLASS = 0,
8258 FW_SCHED_PARAMS_MODE_FLOW = 1,
8259 };
8260
8261 enum fw_sched_params_unit {
8262 FW_SCHED_PARAMS_UNIT_BITRATE = 0,
8263 FW_SCHED_PARAMS_UNIT_PKTRATE = 1,
8264 };
8265
8266 enum fw_sched_params_rate {
8267 FW_SCHED_PARAMS_RATE_REL = 0,
8268 FW_SCHED_PARAMS_RATE_ABS = 1,
8269 };
8270
8271 struct fw_sched_cmd {
8272 __be32 op_to_write;
8273 __be32 retval_len16;
8274 union fw_sched {
8275 struct fw_sched_config {
8276 __u8 sc;
8277 __u8 type;
8278 __u8 minmaxen;
8279 __u8 r3[5];
8280 __u8 nclasses[4];
8281 __be32 r4;
8282 } config;
8283 struct fw_sched_params {
8284 __u8 sc;
8285 __u8 type;
8286 __u8 level;
8287 __u8 mode;
8288 __u8 unit;
8289 __u8 rate;
8290 __u8 ch;
8291 __u8 cl;
8292 __be32 min;
8293 __be32 max;
8294 __be16 weight;
8295 __be16 pktsize;
8296 __be16 burstsize;
8297 __be16 r4;
8298 } params;
8299 } u;
8300 };
8301
8302 /*
8303 * length of the formatting string
8304 */
8305 #define FW_DEVLOG_FMT_LEN 192
8306
8307 /*
8308 * maximum number of the formatting string parameters
8309 */
8310 #define FW_DEVLOG_FMT_PARAMS_NUM 8
8311
8312 /*
8313 * priority levels
8314 */
8315 enum fw_devlog_level {
8316 FW_DEVLOG_LEVEL_EMERG = 0x0,
8317 FW_DEVLOG_LEVEL_CRIT = 0x1,
8318 FW_DEVLOG_LEVEL_ERR = 0x2,
8319 FW_DEVLOG_LEVEL_NOTICE = 0x3,
8320 FW_DEVLOG_LEVEL_INFO = 0x4,
8321 FW_DEVLOG_LEVEL_DEBUG = 0x5,
8322 FW_DEVLOG_LEVEL_MAX = 0x5,
8323 };
8324
8325 /*
8326 * facilities that may send a log message
8327 */
8328 enum fw_devlog_facility {
8329 FW_DEVLOG_FACILITY_CORE = 0x00,
8330 FW_DEVLOG_FACILITY_CF = 0x01,
8331 FW_DEVLOG_FACILITY_SCHED = 0x02,
8332 FW_DEVLOG_FACILITY_TIMER = 0x04,
8333 FW_DEVLOG_FACILITY_RES = 0x06,
8334 FW_DEVLOG_FACILITY_HW = 0x08,
8335 FW_DEVLOG_FACILITY_FLR = 0x10,
8336 FW_DEVLOG_FACILITY_DMAQ = 0x12,
8337 FW_DEVLOG_FACILITY_PHY = 0x14,
8338 FW_DEVLOG_FACILITY_MAC = 0x16,
8339 FW_DEVLOG_FACILITY_PORT = 0x18,
8340 FW_DEVLOG_FACILITY_VI = 0x1A,
8341 FW_DEVLOG_FACILITY_FILTER = 0x1C,
8342 FW_DEVLOG_FACILITY_ACL = 0x1E,
8343 FW_DEVLOG_FACILITY_TM = 0x20,
8344 FW_DEVLOG_FACILITY_QFC = 0x22,
8345 FW_DEVLOG_FACILITY_DCB = 0x24,
8346 FW_DEVLOG_FACILITY_ETH = 0x26,
8347 FW_DEVLOG_FACILITY_OFLD = 0x28,
8348 FW_DEVLOG_FACILITY_RI = 0x2A,
8349 FW_DEVLOG_FACILITY_ISCSI = 0x2C,
8350 FW_DEVLOG_FACILITY_FCOE = 0x2E,
8351 FW_DEVLOG_FACILITY_FOISCSI = 0x30,
8352 FW_DEVLOG_FACILITY_FOFCOE = 0x32,
8353 FW_DEVLOG_FACILITY_CHNET = 0x34,
8354 FW_DEVLOG_FACILITY_COiSCSI = 0x36,
8355 FW_DEVLOG_FACILITY_MAX = 0x38,
8356 };
8357
8358 /*
8359 * log message format
8360 */
8361 struct fw_devlog_e {
8362 __be64 timestamp;
8363 __be32 seqno;
8364 __be16 reserved1;
8365 __u8 level;
8366 __u8 facility;
8367 __u8 fmt[FW_DEVLOG_FMT_LEN];
8368 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
8369 __be32 reserved3[4];
8370 };
8371
8372 struct fw_devlog_cmd {
8373 __be32 op_to_write;
8374 __be32 retval_len16;
8375 __u8 level;
8376 __u8 r2[7];
8377 __be32 memtype_devlog_memaddr16_devlog;
8378 __be32 memsize_devlog;
8379 __be32 r3[2];
8380 };
8381
8382 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28
8383 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf
8384 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8385 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8386 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
8387 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
8388
8389 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0
8390 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff
8391 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8392 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8393 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
8394 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
8395 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
8396
8397 enum fw_watchdog_actions {
8398 FW_WATCHDOG_ACTION_SHUTDOWN = 0,
8399 FW_WATCHDOG_ACTION_FLR = 1,
8400 FW_WATCHDOG_ACTION_BYPASS = 2,
8401 FW_WATCHDOG_ACTION_TMPCHK = 3,
8402 FW_WATCHDOG_ACTION_PAUSEOFF = 4,
8403
8404 FW_WATCHDOG_ACTION_MAX = 5,
8405 };
8406
8407 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60
8408
8409 struct fw_watchdog_cmd {
8410 __be32 op_to_vfn;
8411 __be32 retval_len16;
8412 __be32 timeout;
8413 __be32 action;
8414 };
8415
8416 #define S_FW_WATCHDOG_CMD_PFN 8
8417 #define M_FW_WATCHDOG_CMD_PFN 0x7
8418 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN)
8419 #define G_FW_WATCHDOG_CMD_PFN(x) \
8420 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN)
8421
8422 #define S_FW_WATCHDOG_CMD_VFN 0
8423 #define M_FW_WATCHDOG_CMD_VFN 0xff
8424 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN)
8425 #define G_FW_WATCHDOG_CMD_VFN(x) \
8426 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN)
8427
8428 struct fw_clip_cmd {
8429 __be32 op_to_write;
8430 __be32 alloc_to_len16;
8431 __be64 ip_hi;
8432 __be64 ip_lo;
8433 __be32 r4[2];
8434 };
8435
8436 #define S_FW_CLIP_CMD_ALLOC 31
8437 #define M_FW_CLIP_CMD_ALLOC 0x1
8438 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC)
8439 #define G_FW_CLIP_CMD_ALLOC(x) \
8440 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
8441 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U)
8442
8443 #define S_FW_CLIP_CMD_FREE 30
8444 #define M_FW_CLIP_CMD_FREE 0x1
8445 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE)
8446 #define G_FW_CLIP_CMD_FREE(x) \
8447 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
8448 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U)
8449
8450 /******************************************************************************
8451 * F O i S C S I C O M M A N D s
8452 **************************************/
8453
8454 #define FW_CHNET_IFACE_ADDR_MAX 3
8455
8456 enum fw_chnet_iface_cmd_subop {
8457 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0,
8458
8459 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP,
8460 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN,
8461
8462 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET,
8463 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET,
8464
8465 FW_CHNET_IFACE_CMD_SUBOP_MAX,
8466 };
8467
8468 struct fw_chnet_iface_cmd {
8469 __be32 op_to_portid;
8470 __be32 retval_len16;
8471 __u8 subop;
8472 __u8 r2[3];
8473 __be32 ifid_ifstate;
8474 __be16 mtu;
8475 __be16 vlanid;
8476 __be32 r3;
8477 __be16 r4;
8478 __u8 mac[6];
8479 };
8480
8481 #define S_FW_CHNET_IFACE_CMD_PORTID 0
8482 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf
8483 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID)
8484 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \
8485 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
8486
8487 #define S_FW_CHNET_IFACE_CMD_IFID 8
8488 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff
8489 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID)
8490 #define G_FW_CHNET_IFACE_CMD_IFID(x) \
8491 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
8492
8493 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0
8494 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff
8495 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)
8496 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \
8497 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
8498
8499 struct fw_fcoe_res_info_cmd {
8500 __be32 op_to_read;
8501 __be32 retval_len16;
8502 __be16 e_d_tov;
8503 __be16 r_a_tov_seq;
8504 __be16 r_a_tov_els;
8505 __be16 r_r_tov;
8506 __be32 max_xchgs;
8507 __be32 max_ssns;
8508 __be32 used_xchgs;
8509 __be32 used_ssns;
8510 __be32 max_fcfs;
8511 __be32 max_vnps;
8512 __be32 used_fcfs;
8513 __be32 used_vnps;
8514 };
8515
8516 struct fw_fcoe_link_cmd {
8517 __be32 op_to_portid;
8518 __be32 retval_len16;
8519 __be32 sub_opcode_fcfi;
8520 __u8 r3;
8521 __u8 lstatus;
8522 __be16 flags;
8523 __u8 r4;
8524 __u8 set_vlan;
8525 __be16 vlan_id;
8526 __be32 vnpi_pkd;
8527 __be16 r6;
8528 __u8 phy_mac[6];
8529 __u8 vnport_wwnn[8];
8530 __u8 vnport_wwpn[8];
8531 };
8532
8533 #define S_FW_FCOE_LINK_CMD_PORTID 0
8534 #define M_FW_FCOE_LINK_CMD_PORTID 0xf
8535 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID)
8536 #define G_FW_FCOE_LINK_CMD_PORTID(x) \
8537 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
8538
8539 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24
8540 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff
8541 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
8542 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
8543 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
8544 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)
8545
8546 #define S_FW_FCOE_LINK_CMD_FCFI 0
8547 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff
8548 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI)
8549 #define G_FW_FCOE_LINK_CMD_FCFI(x) \
8550 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
8551
8552 #define S_FW_FCOE_LINK_CMD_VNPI 0
8553 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff
8554 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI)
8555 #define G_FW_FCOE_LINK_CMD_VNPI(x) \
8556 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
8557
8558 struct fw_fcoe_vnp_cmd {
8559 __be32 op_to_fcfi;
8560 __be32 alloc_to_len16;
8561 __be32 gen_wwn_to_vnpi;
8562 __be32 vf_id;
8563 __be16 iqid;
8564 __u8 vnport_mac[6];
8565 __u8 vnport_wwnn[8];
8566 __u8 vnport_wwpn[8];
8567 __u8 cmn_srv_parms[16];
8568 __u8 clsp_word_0_1[8];
8569 };
8570
8571 #define S_FW_FCOE_VNP_CMD_FCFI 0
8572 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff
8573 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI)
8574 #define G_FW_FCOE_VNP_CMD_FCFI(x) \
8575 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
8576
8577 #define S_FW_FCOE_VNP_CMD_ALLOC 31
8578 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1
8579 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC)
8580 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \
8581 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
8582 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U)
8583
8584 #define S_FW_FCOE_VNP_CMD_FREE 30
8585 #define M_FW_FCOE_VNP_CMD_FREE 0x1
8586 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE)
8587 #define G_FW_FCOE_VNP_CMD_FREE(x) \
8588 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
8589 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U)
8590
8591 #define S_FW_FCOE_VNP_CMD_MODIFY 29
8592 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1
8593 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY)
8594 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \
8595 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
8596 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U)
8597
8598 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22
8599 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1
8600 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)
8601 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \
8602 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
8603 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U)
8604
8605 #define S_FW_FCOE_VNP_CMD_PERSIST 21
8606 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1
8607 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST)
8608 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \
8609 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
8610 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U)
8611
8612 #define S_FW_FCOE_VNP_CMD_VFID_EN 20
8613 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1
8614 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN)
8615 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \
8616 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
8617 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U)
8618
8619 #define S_FW_FCOE_VNP_CMD_VNPI 0
8620 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff
8621 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI)
8622 #define G_FW_FCOE_VNP_CMD_VNPI(x) \
8623 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
8624
8625 struct fw_fcoe_sparams_cmd {
8626 __be32 op_to_portid;
8627 __be32 retval_len16;
8628 __u8 r3[7];
8629 __u8 cos;
8630 __u8 lport_wwnn[8];
8631 __u8 lport_wwpn[8];
8632 __u8 cmn_srv_parms[16];
8633 __u8 cls_srv_parms[16];
8634 };
8635
8636 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0
8637 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf
8638 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)
8639 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \
8640 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
8641
8642 struct fw_fcoe_stats_cmd {
8643 __be32 op_to_flowid;
8644 __be32 free_to_len16;
8645 union fw_fcoe_stats {
8646 struct fw_fcoe_stats_ctl {
8647 __u8 nstats_port;
8648 __u8 port_valid_ix;
8649 __be16 r6;
8650 __be32 r7;
8651 __be64 stat0;
8652 __be64 stat1;
8653 __be64 stat2;
8654 __be64 stat3;
8655 __be64 stat4;
8656 __be64 stat5;
8657 } ctl;
8658 struct fw_fcoe_port_stats {
8659 __be64 tx_bcast_bytes;
8660 __be64 tx_bcast_frames;
8661 __be64 tx_mcast_bytes;
8662 __be64 tx_mcast_frames;
8663 __be64 tx_ucast_bytes;
8664 __be64 tx_ucast_frames;
8665 __be64 tx_drop_frames;
8666 __be64 tx_offload_bytes;
8667 __be64 tx_offload_frames;
8668 __be64 rx_bcast_bytes;
8669 __be64 rx_bcast_frames;
8670 __be64 rx_mcast_bytes;
8671 __be64 rx_mcast_frames;
8672 __be64 rx_ucast_bytes;
8673 __be64 rx_ucast_frames;
8674 __be64 rx_err_frames;
8675 } port_stats;
8676 struct fw_fcoe_fcf_stats {
8677 __be32 fip_tx_bytes;
8678 __be32 fip_tx_fr;
8679 __be64 fcf_ka;
8680 __be64 mcast_adv_rcvd;
8681 __be16 ucast_adv_rcvd;
8682 __be16 sol_sent;
8683 __be16 vlan_req;
8684 __be16 vlan_rpl;
8685 __be16 clr_vlink;
8686 __be16 link_down;
8687 __be16 link_up;
8688 __be16 logo;
8689 __be16 flogi_req;
8690 __be16 flogi_rpl;
8691 __be16 fdisc_req;
8692 __be16 fdisc_rpl;
8693 __be16 fka_prd_chg;
8694 __be16 fc_map_chg;
8695 __be16 vfid_chg;
8696 __u8 no_fka_req;
8697 __u8 no_vnp;
8698 } fcf_stats;
8699 struct fw_fcoe_pcb_stats {
8700 __be64 tx_bytes;
8701 __be64 tx_frames;
8702 __be64 rx_bytes;
8703 __be64 rx_frames;
8704 __be32 vnp_ka;
8705 __be32 unsol_els_rcvd;
8706 __be64 unsol_cmd_rcvd;
8707 __be16 implicit_logo;
8708 __be16 flogi_inv_sparm;
8709 __be16 fdisc_inv_sparm;
8710 __be16 flogi_rjt;
8711 __be16 fdisc_rjt;
8712 __be16 no_ssn;
8713 __be16 mac_flt_fail;
8714 __be16 inv_fr_rcvd;
8715 } pcb_stats;
8716 struct fw_fcoe_scb_stats {
8717 __be64 tx_bytes;
8718 __be64 tx_frames;
8719 __be64 rx_bytes;
8720 __be64 rx_frames;
8721 __be32 host_abrt_req;
8722 __be32 adap_auto_abrt;
8723 __be32 adap_abrt_rsp;
8724 __be32 host_ios_req;
8725 __be16 ssn_offl_ios;
8726 __be16 ssn_not_rdy_ios;
8727 __u8 rx_data_ddp_err;
8728 __u8 ddp_flt_set_err;
8729 __be16 rx_data_fr_err;
8730 __u8 bad_st_abrt_req;
8731 __u8 no_io_abrt_req;
8732 __u8 abort_tmo;
8733 __u8 abort_tmo_2;
8734 __be32 abort_req;
8735 __u8 no_ppod_res_tmo;
8736 __u8 bp_tmo;
8737 __u8 adap_auto_cls;
8738 __u8 no_io_cls_req;
8739 __be32 host_cls_req;
8740 __be64 unsol_cmd_rcvd;
8741 __be32 plogi_req_rcvd;
8742 __be32 prli_req_rcvd;
8743 __be16 logo_req_rcvd;
8744 __be16 prlo_req_rcvd;
8745 __be16 plogi_rjt_rcvd;
8746 __be16 prli_rjt_rcvd;
8747 __be32 adisc_req_rcvd;
8748 __be32 rscn_rcvd;
8749 __be32 rrq_req_rcvd;
8750 __be32 unsol_els_rcvd;
8751 __u8 adisc_rjt_rcvd;
8752 __u8 scr_rjt;
8753 __u8 ct_rjt;
8754 __u8 inval_bls_rcvd;
8755 __be32 ba_rjt_rcvd;
8756 } scb_stats;
8757 } u;
8758 };
8759
8760 #define S_FW_FCOE_STATS_CMD_FLOWID 0
8761 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff
8762 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID)
8763 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \
8764 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
8765
8766 #define S_FW_FCOE_STATS_CMD_FREE 30
8767 #define M_FW_FCOE_STATS_CMD_FREE 0x1
8768 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE)
8769 #define G_FW_FCOE_STATS_CMD_FREE(x) \
8770 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
8771 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U)
8772
8773 #define S_FW_FCOE_STATS_CMD_NSTATS 4
8774 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7
8775 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS)
8776 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \
8777 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
8778
8779 #define S_FW_FCOE_STATS_CMD_PORT 0
8780 #define M_FW_FCOE_STATS_CMD_PORT 0x3
8781 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT)
8782 #define G_FW_FCOE_STATS_CMD_PORT(x) \
8783 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
8784
8785 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7
8786 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1
8787 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \
8788 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
8789 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \
8790 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID)
8791 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U)
8792
8793 #define S_FW_FCOE_STATS_CMD_IX 0
8794 #define M_FW_FCOE_STATS_CMD_IX 0x3f
8795 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX)
8796 #define G_FW_FCOE_STATS_CMD_IX(x) \
8797 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
8798
8799 struct fw_fcoe_fcf_cmd {
8800 __be32 op_to_fcfi;
8801 __be32 retval_len16;
8802 __be16 priority_pkd;
8803 __u8 mac[6];
8804 __u8 name_id[8];
8805 __u8 fabric[8];
8806 __be16 vf_id;
8807 __be16 max_fcoe_size;
8808 __u8 vlan_id;
8809 __u8 fc_map[3];
8810 __be32 fka_adv;
8811 __be32 r6;
8812 __u8 r7_hi;
8813 __u8 fpma_to_portid;
8814 __u8 spma_mac[6];
8815 __be64 r8;
8816 };
8817
8818 #define S_FW_FCOE_FCF_CMD_FCFI 0
8819 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff
8820 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI)
8821 #define G_FW_FCOE_FCF_CMD_FCFI(x) \
8822 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
8823
8824 #define S_FW_FCOE_FCF_CMD_PRIORITY 0
8825 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff
8826 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY)
8827 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \
8828 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
8829
8830 #define S_FW_FCOE_FCF_CMD_FPMA 6
8831 #define M_FW_FCOE_FCF_CMD_FPMA 0x1
8832 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA)
8833 #define G_FW_FCOE_FCF_CMD_FPMA(x) \
8834 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
8835 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U)
8836
8837 #define S_FW_FCOE_FCF_CMD_SPMA 5
8838 #define M_FW_FCOE_FCF_CMD_SPMA 0x1
8839 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA)
8840 #define G_FW_FCOE_FCF_CMD_SPMA(x) \
8841 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
8842 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U)
8843
8844 #define S_FW_FCOE_FCF_CMD_LOGIN 4
8845 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1
8846 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN)
8847 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \
8848 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
8849 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U)
8850
8851 #define S_FW_FCOE_FCF_CMD_PORTID 0
8852 #define M_FW_FCOE_FCF_CMD_PORTID 0xf
8853 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID)
8854 #define G_FW_FCOE_FCF_CMD_PORTID(x) \
8855 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
8856
8857 /******************************************************************************
8858 * E R R O R a n d D E B U G C O M M A N D s
8859 ******************************************************/
8860
8861 enum fw_error_type {
8862 FW_ERROR_TYPE_EXCEPTION = 0x0,
8863 FW_ERROR_TYPE_HWMODULE = 0x1,
8864 FW_ERROR_TYPE_WR = 0x2,
8865 FW_ERROR_TYPE_ACL = 0x3,
8866 };
8867
8868 enum fw_dcb_ieee_locations {
8869 FW_IEEE_LOC_LOCAL,
8870 FW_IEEE_LOC_PEER,
8871 FW_IEEE_LOC_OPERATIONAL,
8872 };
8873
8874 struct fw_dcb_ieee_cmd {
8875 __be32 op_to_location;
8876 __be32 changed_to_len16;
8877 union fw_dcbx_stats {
8878 struct fw_dcbx_pfc_stats_ieee {
8879 __be32 pfc_mbc_pkd;
8880 __be32 pfc_willing_to_pfc_en;
8881 } dcbx_pfc_stats;
8882 struct fw_dcbx_ets_stats_ieee {
8883 __be32 cbs_to_ets_max_tc;
8884 __be32 pg_table;
8885 __u8 pg_percent[8];
8886 __u8 tsa[8];
8887 } dcbx_ets_stats;
8888 struct fw_dcbx_app_stats_ieee {
8889 __be32 num_apps_pkd;
8890 __be32 r6;
8891 __be32 app[4];
8892 } dcbx_app_stats;
8893 struct fw_dcbx_control {
8894 __be32 multi_peer_invalidated;
8895 __be32 r5_lo;
8896 } dcbx_control;
8897 } u;
8898 };
8899
8900 #define S_FW_DCB_IEEE_CMD_PORT 8
8901 #define M_FW_DCB_IEEE_CMD_PORT 0x7
8902 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT)
8903 #define G_FW_DCB_IEEE_CMD_PORT(x) \
8904 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT)
8905
8906 #define S_FW_DCB_IEEE_CMD_FEATURE 2
8907 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7
8908 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE)
8909 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \
8910 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE)
8911
8912 #define S_FW_DCB_IEEE_CMD_LOCATION 0
8913 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3
8914 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION)
8915 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \
8916 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION)
8917
8918 #define S_FW_DCB_IEEE_CMD_CHANGED 20
8919 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1
8920 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED)
8921 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \
8922 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED)
8923 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U)
8924
8925 #define S_FW_DCB_IEEE_CMD_RECEIVED 19
8926 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1
8927 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED)
8928 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \
8929 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED)
8930 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U)
8931
8932 #define S_FW_DCB_IEEE_CMD_APPLY 18
8933 #define M_FW_DCB_IEEE_CMD_APPLY 0x1
8934 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY)
8935 #define G_FW_DCB_IEEE_CMD_APPLY(x) \
8936 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY)
8937 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U)
8938
8939 #define S_FW_DCB_IEEE_CMD_DISABLED 17
8940 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1
8941 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED)
8942 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \
8943 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED)
8944 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U)
8945
8946 #define S_FW_DCB_IEEE_CMD_MORE 16
8947 #define M_FW_DCB_IEEE_CMD_MORE 0x1
8948 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE)
8949 #define G_FW_DCB_IEEE_CMD_MORE(x) \
8950 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE)
8951 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U)
8952
8953 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0
8954 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1
8955 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC)
8956 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \
8957 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC)
8958 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U)
8959
8960 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16
8961 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1
8962 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \
8963 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING)
8964 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \
8965 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING)
8966 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U)
8967
8968 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8
8969 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff
8970 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC)
8971 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \
8972 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC)
8973
8974 #define S_FW_DCB_IEEE_CMD_PFC_EN 0
8975 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff
8976 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN)
8977 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \
8978 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN)
8979
8980 #define S_FW_DCB_IEEE_CMD_CBS 16
8981 #define M_FW_DCB_IEEE_CMD_CBS 0x1
8982 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS)
8983 #define G_FW_DCB_IEEE_CMD_CBS(x) \
8984 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS)
8985 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U)
8986
8987 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8
8988 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1
8989 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \
8990 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING)
8991 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \
8992 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING)
8993 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U)
8994
8995 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0
8996 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff
8997 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC)
8998 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \
8999 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC)
9000
9001 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0
9002 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7
9003 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS)
9004 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \
9005 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS)
9006
9007 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31
9008 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1
9009 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER)
9010 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \
9011 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER)
9012 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U)
9013
9014 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30
9015 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1
9016 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \
9017 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED)
9018 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \
9019 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED)
9020 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U)
9021
9022 /* Hand-written */
9023 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16
9024 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff
9025 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL)
9026 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \
9027 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL)
9028
9029 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3
9030 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7
9031 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT)
9032 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \
9033 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT)
9034
9035 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0
9036 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7
9037 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY)
9038 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \
9039 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY)
9040
9041
9042 struct fw_error_cmd {
9043 __be32 op_to_type;
9044 __be32 len16_pkd;
9045 union fw_error {
9046 struct fw_error_exception {
9047 __be32 info[6];
9048 } exception;
9049 struct fw_error_hwmodule {
9050 __be32 regaddr;
9051 __be32 regval;
9052 } hwmodule;
9053 struct fw_error_wr {
9054 __be16 cidx;
9055 __be16 pfn_vfn;
9056 __be32 eqid;
9057 __u8 wrhdr[16];
9058 } wr;
9059 struct fw_error_acl {
9060 __be16 cidx;
9061 __be16 pfn_vfn;
9062 __be32 eqid;
9063 __be16 mv_pkd;
9064 __u8 val[6];
9065 __be64 r4;
9066 } acl;
9067 } u;
9068 };
9069
9070 #define S_FW_ERROR_CMD_FATAL 4
9071 #define M_FW_ERROR_CMD_FATAL 0x1
9072 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL)
9073 #define G_FW_ERROR_CMD_FATAL(x) \
9074 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
9075 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U)
9076
9077 #define S_FW_ERROR_CMD_TYPE 0
9078 #define M_FW_ERROR_CMD_TYPE 0xf
9079 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE)
9080 #define G_FW_ERROR_CMD_TYPE(x) \
9081 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
9082
9083 #define S_FW_ERROR_CMD_PFN 8
9084 #define M_FW_ERROR_CMD_PFN 0x7
9085 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN)
9086 #define G_FW_ERROR_CMD_PFN(x) \
9087 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9088
9089 #define S_FW_ERROR_CMD_VFN 0
9090 #define M_FW_ERROR_CMD_VFN 0xff
9091 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN)
9092 #define G_FW_ERROR_CMD_VFN(x) \
9093 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9094
9095 #define S_FW_ERROR_CMD_PFN 8
9096 #define M_FW_ERROR_CMD_PFN 0x7
9097 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN)
9098 #define G_FW_ERROR_CMD_PFN(x) \
9099 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
9100
9101 #define S_FW_ERROR_CMD_VFN 0
9102 #define M_FW_ERROR_CMD_VFN 0xff
9103 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN)
9104 #define G_FW_ERROR_CMD_VFN(x) \
9105 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
9106
9107 #define S_FW_ERROR_CMD_MV 15
9108 #define M_FW_ERROR_CMD_MV 0x1
9109 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV)
9110 #define G_FW_ERROR_CMD_MV(x) \
9111 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
9112 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U)
9113
9114 struct fw_debug_cmd {
9115 __be32 op_type;
9116 __be32 len16_pkd;
9117 union fw_debug {
9118 struct fw_debug_assert {
9119 __be32 fcid;
9120 __be32 line;
9121 __be32 x;
9122 __be32 y;
9123 __u8 filename_0_7[8];
9124 __u8 filename_8_15[8];
9125 __be64 r3;
9126 } assert;
9127 struct fw_debug_prt {
9128 __be16 dprtstridx;
9129 __be16 r3[3];
9130 __be32 dprtstrparam0;
9131 __be32 dprtstrparam1;
9132 __be32 dprtstrparam2;
9133 __be32 dprtstrparam3;
9134 } prt;
9135 } u;
9136 };
9137
9138 #define S_FW_DEBUG_CMD_TYPE 0
9139 #define M_FW_DEBUG_CMD_TYPE 0xff
9140 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE)
9141 #define G_FW_DEBUG_CMD_TYPE(x) \
9142 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
9143
9144 enum fw_diag_cmd_type {
9145 FW_DIAG_CMD_TYPE_OFLDIAG = 0,
9146 };
9147
9148 enum fw_diag_cmd_ofldiag_op {
9149 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0,
9150 FW_DIAG_CMD_OFLDIAG_TEST_START,
9151 FW_DIAG_CMD_OFLDIAG_TEST_STOP,
9152 FW_DIAG_CMD_OFLDIAG_TEST_STATUS,
9153 };
9154
9155 enum fw_diag_cmd_ofldiag_status {
9156 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0,
9157 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING,
9158 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED,
9159 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED,
9160 };
9161
9162 struct fw_diag_cmd {
9163 __be32 op_type;
9164 __be32 len16_pkd;
9165 union fw_diag_test {
9166 struct fw_diag_test_ofldiag {
9167 __u8 test_op;
9168 __u8 r3;
9169 __be16 test_status;
9170 __be32 duration;
9171 } ofldiag;
9172 } u;
9173 };
9174
9175 #define S_FW_DIAG_CMD_TYPE 0
9176 #define M_FW_DIAG_CMD_TYPE 0xff
9177 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE)
9178 #define G_FW_DIAG_CMD_TYPE(x) \
9179 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
9180
9181 /******************************************************************************
9182 * P C I E F W R E G I S T E R
9183 **************************************/
9184
9185 enum pcie_fw_eval {
9186 PCIE_FW_EVAL_CRASH = 0,
9187 PCIE_FW_EVAL_PREP = 1,
9188 PCIE_FW_EVAL_CONF = 2,
9189 PCIE_FW_EVAL_INIT = 3,
9190 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4,
9191 PCIE_FW_EVAL_OVERHEAT = 5,
9192 PCIE_FW_EVAL_DEVICESHUTDOWN = 6,
9193 };
9194
9195 /**
9196 * Register definitions for the PCIE_FW register which the firmware uses
9197 * to retain status across RESETs. This register should be considered
9198 * as a READ-ONLY register for Host Software and only to be used to
9199 * track firmware initialization/error state, etc.
9200 */
9201 #define S_PCIE_FW_ERR 31
9202 #define M_PCIE_FW_ERR 0x1
9203 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR)
9204 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
9205 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U)
9206
9207 #define S_PCIE_FW_INIT 30
9208 #define M_PCIE_FW_INIT 0x1
9209 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT)
9210 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
9211 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U)
9212
9213 #define S_PCIE_FW_HALT 29
9214 #define M_PCIE_FW_HALT 0x1
9215 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT)
9216 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
9217 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U)
9218
9219 #define S_PCIE_FW_EVAL 24
9220 #define M_PCIE_FW_EVAL 0x7
9221 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL)
9222 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
9223
9224 #define S_PCIE_FW_STAGE 21
9225 #define M_PCIE_FW_STAGE 0x7
9226 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE)
9227 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
9228
9229 #define S_PCIE_FW_ASYNCNOT_VLD 20
9230 #define M_PCIE_FW_ASYNCNOT_VLD 0x1
9231 #define V_PCIE_FW_ASYNCNOT_VLD(x) \
9232 ((x) << S_PCIE_FW_ASYNCNOT_VLD)
9233 #define G_PCIE_FW_ASYNCNOT_VLD(x) \
9234 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
9235 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U)
9236
9237 #define S_PCIE_FW_ASYNCNOTINT 19
9238 #define M_PCIE_FW_ASYNCNOTINT 0x1
9239 #define V_PCIE_FW_ASYNCNOTINT(x) \
9240 ((x) << S_PCIE_FW_ASYNCNOTINT)
9241 #define G_PCIE_FW_ASYNCNOTINT(x) \
9242 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
9243 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U)
9244
9245 #define S_PCIE_FW_ASYNCNOT 16
9246 #define M_PCIE_FW_ASYNCNOT 0x7
9247 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT)
9248 #define G_PCIE_FW_ASYNCNOT(x) \
9249 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
9250
9251 #define S_PCIE_FW_MASTER_VLD 15
9252 #define M_PCIE_FW_MASTER_VLD 0x1
9253 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD)
9254 #define G_PCIE_FW_MASTER_VLD(x) \
9255 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
9256 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U)
9257
9258 #define S_PCIE_FW_MASTER 12
9259 #define M_PCIE_FW_MASTER 0x7
9260 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER)
9261 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
9262
9263 #define S_PCIE_FW_RESET_VLD 11
9264 #define M_PCIE_FW_RESET_VLD 0x1
9265 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD)
9266 #define G_PCIE_FW_RESET_VLD(x) \
9267 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
9268 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U)
9269
9270 #define S_PCIE_FW_RESET 8
9271 #define M_PCIE_FW_RESET 0x7
9272 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET)
9273 #define G_PCIE_FW_RESET(x) \
9274 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
9275
9276 #define S_PCIE_FW_REGISTERED 0
9277 #define M_PCIE_FW_REGISTERED 0xff
9278 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED)
9279 #define G_PCIE_FW_REGISTERED(x) \
9280 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
9281
9282
9283 /******************************************************************************
9284 * P C I E F W P F 0 R E G I S T E R
9285 **********************************************/
9286
9287 /*
9288 * this register is available as 32-bit of persistent storage (accross
9289 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver
9290 * will not write it)
9291 */
9292
9293
9294 /******************************************************************************
9295 * P C I E F W P F 7 R E G I S T E R
9296 **********************************************/
9297
9298 /*
9299 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to
9300 * access the "devlog" which needing to contact firmware. The encoding is
9301 * mostly the same as that returned by the DEVLOG command except for the size
9302 * which is encoded as the number of entries in multiples-1 of 128 here rather
9303 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128
9304 * and 15 means 2048. This of course in turn constrains the allowed values
9305 * for the devlog size ...
9306 */
9307 #define PCIE_FW_PF_DEVLOG 7
9308
9309 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28
9310 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf
9311 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9312 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128)
9313 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
9314 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \
9315 M_PCIE_FW_PF_DEVLOG_NENTRIES128)
9316
9317 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4
9318 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff
9319 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16)
9320 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \
9321 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16)
9322
9323 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0
9324 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf
9325 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE)
9326 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \
9327 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE)
9328
9329
9330 /******************************************************************************
9331 * B I N A R Y H E A D E R F O R M A T
9332 **********************************************/
9333
9334 /*
9335 * firmware binary header format
9336 */
9337 struct fw_hdr {
9338 __u8 ver;
9339 __u8 chip; /* terminator chip family */
9340 __be16 len512; /* bin length in units of 512-bytes */
9341 __be32 fw_ver; /* firmware version */
9342 __be32 tp_microcode_ver; /* tcp processor microcode version */
9343 __u8 intfver_nic;
9344 __u8 intfver_vnic;
9345 __u8 intfver_ofld;
9346 __u8 intfver_ri;
9347 __u8 intfver_iscsipdu;
9348 __u8 intfver_iscsi;
9349 __u8 intfver_fcoepdu;
9350 __u8 intfver_fcoe;
9351 __u32 reserved2;
9352 __u32 reserved3;
9353 __be32 magic; /* runtime or bootstrap fw */
9354 __be32 flags;
9355 __be32 reserved6[23];
9356 };
9357
9358 enum fw_hdr_chip {
9359 FW_HDR_CHIP_T4,
9360 FW_HDR_CHIP_T5,
9361 FW_HDR_CHIP_T6
9362 };
9363
9364 #define S_FW_HDR_FW_VER_MAJOR 24
9365 #define M_FW_HDR_FW_VER_MAJOR 0xff
9366 #define V_FW_HDR_FW_VER_MAJOR(x) \
9367 ((x) << S_FW_HDR_FW_VER_MAJOR)
9368 #define G_FW_HDR_FW_VER_MAJOR(x) \
9369 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
9370
9371 #define S_FW_HDR_FW_VER_MINOR 16
9372 #define M_FW_HDR_FW_VER_MINOR 0xff
9373 #define V_FW_HDR_FW_VER_MINOR(x) \
9374 ((x) << S_FW_HDR_FW_VER_MINOR)
9375 #define G_FW_HDR_FW_VER_MINOR(x) \
9376 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
9377
9378 #define S_FW_HDR_FW_VER_MICRO 8
9379 #define M_FW_HDR_FW_VER_MICRO 0xff
9380 #define V_FW_HDR_FW_VER_MICRO(x) \
9381 ((x) << S_FW_HDR_FW_VER_MICRO)
9382 #define G_FW_HDR_FW_VER_MICRO(x) \
9383 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
9384
9385 #define S_FW_HDR_FW_VER_BUILD 0
9386 #define M_FW_HDR_FW_VER_BUILD 0xff
9387 #define V_FW_HDR_FW_VER_BUILD(x) \
9388 ((x) << S_FW_HDR_FW_VER_BUILD)
9389 #define G_FW_HDR_FW_VER_BUILD(x) \
9390 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
9391
9392 enum {
9393 /* T4
9394 */
9395 FW_HDR_INTFVER_NIC = 0x00,
9396 FW_HDR_INTFVER_VNIC = 0x00,
9397 FW_HDR_INTFVER_OFLD = 0x00,
9398 FW_HDR_INTFVER_RI = 0x00,
9399 FW_HDR_INTFVER_ISCSIPDU = 0x00,
9400 FW_HDR_INTFVER_ISCSI = 0x00,
9401 FW_HDR_INTFVER_FCOEPDU = 0x00,
9402 FW_HDR_INTFVER_FCOE = 0x00,
9403
9404 /* T5
9405 */
9406 T5FW_HDR_INTFVER_NIC = 0x00,
9407 T5FW_HDR_INTFVER_VNIC = 0x00,
9408 T5FW_HDR_INTFVER_OFLD = 0x00,
9409 T5FW_HDR_INTFVER_RI = 0x00,
9410 T5FW_HDR_INTFVER_ISCSIPDU= 0x00,
9411 T5FW_HDR_INTFVER_ISCSI = 0x00,
9412 T5FW_HDR_INTFVER_FCOEPDU= 0x00,
9413 T5FW_HDR_INTFVER_FCOE = 0x00,
9414
9415 /* T6
9416 */
9417 T6FW_HDR_INTFVER_NIC = 0x00,
9418 T6FW_HDR_INTFVER_VNIC = 0x00,
9419 T6FW_HDR_INTFVER_OFLD = 0x00,
9420 T6FW_HDR_INTFVER_RI = 0x00,
9421 T6FW_HDR_INTFVER_ISCSIPDU= 0x00,
9422 T6FW_HDR_INTFVER_ISCSI = 0x00,
9423 T6FW_HDR_INTFVER_FCOEPDU= 0x00,
9424 T6FW_HDR_INTFVER_FCOE = 0x00,
9425 };
9426
9427 enum {
9428 FW_HDR_MAGIC_RUNTIME = 0x00000000,
9429 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74,
9430 };
9431
9432 enum fw_hdr_flags {
9433 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
9434 };
9435
9436 /*
9437 * External PHY firmware binary header format
9438 */
9439 struct fw_ephy_hdr {
9440 __u8 ver;
9441 __u8 reserved;
9442 __be16 len512; /* bin length in units of 512-bytes */
9443 __be32 magic;
9444
9445 __be16 vendor_id;
9446 __be16 device_id;
9447 __be32 version;
9448
9449 __be32 reserved1[4];
9450 };
9451
9452 enum {
9453 FW_EPHY_HDR_MAGIC = 0x65706879,
9454 };
9455
9456 #endif /* _T4FW_INTERFACE_H_ */