2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
13 * This file is part of the Chelsio T4 support code.
15 * Copyright (C) 2011-2013 Chelsio Communications. All rights reserved.
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this
20 * release for licensing terms and conditions.
24 #include <sys/sunddi.h>
25 #include <sys/queue.h>
28 #include "common/common.h"
29 #include "common/t4_regs.h"
32 static int pci_rw(struct adapter
*sc
, void *data
, int flags
, int write
);
33 static int reg_rw(struct adapter
*sc
, void *data
, int flags
, int write
);
34 static void reg_block_dump(struct adapter
*sc
, uint8_t *buf
, unsigned int start
,
36 static int regdump(struct adapter
*sc
, void *data
, int flags
);
37 static int get_sge_context(struct adapter
*sc
, void *data
, int flags
);
38 static int get_devlog(struct adapter
*sc
, void *data
, int flags
);
39 static int validate_mem_range(struct adapter
*, uint32_t, int);
40 static int read_card_mem(struct adapter
*sc
, void *data
, int flags
);
41 static int read_tid_tab(struct adapter
*sc
, void *data
, int flags
);
42 static int read_mbox(struct adapter
*sc
, void *data
, int flags
);
43 static int read_cim_la(struct adapter
*sc
, void *data
, int flags
);
44 static int read_cim_qcfg(struct adapter
*sc
, void *data
, int flags
);
45 static int read_cim_ibq(struct adapter
*sc
, void *data
, int flags
);
46 static int read_edc(struct adapter
*sc
, void *data
, int flags
);
47 static int flash_fw(struct adapter
*, void *, int);
50 t4_ioctl(struct adapter
*sc
, int cmd
, void *data
, int mode
)
55 case T4_IOCTL_PCIGET32
:
56 case T4_IOCTL_PCIPUT32
:
57 rc
= pci_rw(sc
, data
, mode
, cmd
== T4_IOCTL_PCIPUT32
);
61 rc
= reg_rw(sc
, data
, mode
, cmd
== T4_IOCTL_PUT32
);
63 case T4_IOCTL_REGDUMP
:
64 rc
= regdump(sc
, data
, mode
);
66 case T4_IOCTL_SGE_CONTEXT
:
67 rc
= get_sge_context(sc
, data
, mode
);
70 rc
= get_devlog(sc
, data
, mode
);
72 case T4_IOCTL_GET_MEM
:
73 rc
= read_card_mem(sc
, data
, mode
);
75 case T4_IOCTL_GET_TID_TAB
:
76 rc
= read_tid_tab(sc
, data
, mode
);
78 case T4_IOCTL_GET_MBOX
:
79 rc
= read_mbox(sc
, data
, mode
);
81 case T4_IOCTL_GET_CIM_LA
:
82 rc
= read_cim_la(sc
, data
, mode
);
84 case T4_IOCTL_GET_CIM_QCFG
:
85 rc
= read_cim_qcfg(sc
, data
, mode
);
87 case T4_IOCTL_GET_CIM_IBQ
:
88 rc
= read_cim_ibq(sc
, data
, mode
);
90 case T4_IOCTL_GET_EDC
:
91 rc
= read_edc(sc
, data
, mode
);
93 case T4_IOCTL_LOAD_FW
:
94 rc
= flash_fw(sc
, data
, mode
);
104 pci_rw(struct adapter
*sc
, void *data
, int flags
, int write
)
106 struct t4_reg32_cmd r
;
108 if (ddi_copyin(data
, &r
, sizeof (r
), flags
) < 0)
111 /* address must be 32 bit aligned */
115 t4_os_pci_write_cfg4(sc
, r
.reg
, r
.value
);
117 t4_os_pci_read_cfg4(sc
, r
.reg
, &r
.value
);
118 if (ddi_copyout(&r
, data
, sizeof (r
), flags
) < 0)
126 reg_rw(struct adapter
*sc
, void *data
, int flags
, int write
)
128 struct t4_reg32_cmd r
;
130 if (ddi_copyin(data
, &r
, sizeof (r
), flags
) < 0)
133 /* Register address must be 32 bit aligned */
137 t4_write_reg(sc
, r
.reg
, r
.value
);
139 r
.value
= t4_read_reg(sc
, r
.reg
);
140 if (ddi_copyout(&r
, data
, sizeof (r
), flags
) < 0)
148 reg_block_dump(struct adapter
*sc
, uint8_t *buf
, unsigned int start
,
151 /* LINTED: E_BAD_PTR_CAST_ALIGN */
152 uint32_t *p
= (uint32_t *)(buf
+ start
);
154 for (/* */; start
<= end
; start
+= sizeof (uint32_t))
155 *p
++ = t4_read_reg(sc
, start
);
159 * Return a version number to identify the type of adapter. The scheme is:
160 * - bits 0..9: chip version
161 * - bits 10..15: chip revision
162 * - bits 16..23: register dump version
165 unsigned int mk_adap_vers(const struct adapter
*sc
)
167 return CHELSIO_CHIP_VERSION(sc
->params
.chip
) |
168 (CHELSIO_CHIP_RELEASE(sc
->params
.chip
) << 10) | (1 << 16);
172 regdump(struct adapter
*sc
, void *data
, int flags
)
176 static const unsigned int *reg_ranges
;
177 int rc
= 0, arr_size
= 0, buf_size
= 0, i
;
178 static const unsigned int t4_reg_ranges
[] = {
396 static const unsigned int t5_reg_ranges
[] = {
1171 if (ddi_copyin(data
, &r
, sizeof (r
), flags
) < 0)
1174 if (r
.len
> T4_REGDUMP_SIZE
)
1175 r
.len
= T4_REGDUMP_SIZE
;
1176 else if (r
.len
< T4_REGDUMP_SIZE
)
1179 r
.version
= mk_adap_vers(sc
);
1181 if (is_t4(sc
->params
.chip
)) {
1182 reg_ranges
= &t4_reg_ranges
[0];
1183 arr_size
= ARRAY_SIZE(t4_reg_ranges
);
1184 buf_size
= T4_REGDUMP_SIZE
;
1186 reg_ranges
= &t5_reg_ranges
[0];
1187 arr_size
= ARRAY_SIZE(t5_reg_ranges
);
1188 buf_size
= T5_REGDUMP_SIZE
;
1191 buf
= kmem_zalloc(buf_size
, KM_SLEEP
);
1195 for (i
= 0; i
< arr_size
; i
+= 2)
1196 reg_block_dump(sc
, buf
, reg_ranges
[i
], reg_ranges
[i
+ 1]);
1198 if (ddi_copyout(buf
, r
.data
, r
.len
, flags
) < 0)
1201 if (rc
== 0 && ddi_copyout(&r
, data
, sizeof (r
), flags
) < 0)
1204 kmem_free(buf
, buf_size
);
1209 get_sge_context(struct adapter
*sc
, void *data
, int flags
)
1211 struct t4_sge_context sgec
;
1212 uint32_t buff
[SGE_CTXT_SIZE
/ 4];
1215 if (ddi_copyin(data
, &sgec
, sizeof (sgec
), flags
) < 0) {
1220 if (sgec
.len
< SGE_CTXT_SIZE
|| sgec
.addr
> M_CTXTQID
) {
1225 if ((sgec
.mem_id
!= T4_CTXT_EGRESS
) && (sgec
.mem_id
!= T4_CTXT_FLM
) &&
1226 (sgec
.mem_id
!= T4_CTXT_INGRESS
)) {
1231 rc
= (sc
->flags
& FW_OK
) ?
1232 -t4_sge_ctxt_rd(sc
, sc
->mbox
, sgec
.addr
, sgec
.mem_id
, buff
) :
1233 -t4_sge_ctxt_rd_bd(sc
, sgec
.addr
, sgec
.mem_id
, buff
);
1237 sgec
.version
= 4 | (sc
->params
.chip
<< 10);
1239 /* copyout data and then t4_sge_context */
1240 rc
= ddi_copyout(buff
, sgec
.data
, sgec
.len
, flags
);
1242 rc
= ddi_copyout(&sgec
, data
, sizeof (sgec
), flags
);
1243 /* if ddi_copyout fails, return EFAULT - for either of the two */
1252 read_tid_tab(struct adapter
*sc
, void *data
, int flags
)
1254 struct t4_tid_info t4tid
;
1256 struct tid_info
*t
= &sc
->tids
;
1259 if (ddi_copyin(data
, &t4tid
, sizeof (t4tid
), flags
) < 0) {
1264 buf
= b
= kmem_zalloc(t4tid
.len
, KM_NOSLEEP
);
1270 *b
++ = t
->tids_in_use
;
1271 *b
++ = t
->atids_in_use
;
1272 *b
= t
->stids_in_use
;
1274 if (ddi_copyout(buf
, t4tid
.data
, t4tid
.len
, flags
) < 0)
1277 kmem_free(buf
, t4tid
.len
);
1284 * Verify that the memory range specified by the addr/len pair is valid and lies
1285 * entirely within a single region (EDCx or MCx).
1288 validate_mem_range(struct adapter
*sc
, uint32_t addr
, int len
)
1290 uint32_t em
, addr_len
, maddr
, mlen
;
1292 /* Memory can only be accessed in naturally aligned 4 byte units */
1293 if (addr
& 3 || len
& 3 || len
== 0)
1296 /* Enabled memories */
1297 em
= t4_read_reg(sc
, A_MA_TARGET_MEM_ENABLE
);
1298 if (em
& F_EDRAM0_ENABLE
) {
1299 addr_len
= t4_read_reg(sc
, A_MA_EDRAM0_BAR
);
1300 maddr
= G_EDRAM0_BASE(addr_len
) << 20;
1301 mlen
= G_EDRAM0_SIZE(addr_len
) << 20;
1302 if (mlen
> 0 && addr
>= maddr
&& addr
< maddr
+ mlen
&&
1303 addr
+ len
<= maddr
+ mlen
)
1306 if (em
& F_EDRAM1_ENABLE
) {
1307 addr_len
= t4_read_reg(sc
, A_MA_EDRAM1_BAR
);
1308 maddr
= G_EDRAM1_BASE(addr_len
) << 20;
1309 mlen
= G_EDRAM1_SIZE(addr_len
) << 20;
1310 if (mlen
> 0 && addr
>= maddr
&& addr
< maddr
+ mlen
&&
1311 addr
+ len
<= maddr
+ mlen
)
1314 if (em
& F_EXT_MEM_ENABLE
) {
1315 addr_len
= t4_read_reg(sc
, A_MA_EXT_MEMORY_BAR
);
1316 maddr
= G_EXT_MEM_BASE(addr_len
) << 20;
1317 mlen
= G_EXT_MEM_SIZE(addr_len
) << 20;
1318 if (mlen
> 0 && addr
>= maddr
&& addr
< maddr
+ mlen
&&
1319 addr
+ len
<= maddr
+ mlen
)
1322 if (!is_t4(sc
->params
.chip
) && em
& F_EXT_MEM1_ENABLE
) {
1323 addr_len
= t4_read_reg(sc
, A_MA_EXT_MEMORY1_BAR
);
1324 maddr
= G_EXT_MEM1_BASE(addr_len
) << 20;
1325 mlen
= G_EXT_MEM1_SIZE(addr_len
) << 20;
1326 if (mlen
> 0 && addr
>= maddr
&& addr
< maddr
+ mlen
&&
1327 addr
+ len
<= maddr
+ mlen
)
1335 read_card_mem(struct adapter
*sc
, void *data
, int flags
)
1337 struct t4_mem_range mr
;
1338 uint32_t addr
, off
, remaining
, i
, n
;
1341 uint32_t mw_base
, mw_aperture
;
1344 if (ddi_copyin(data
, &mr
, sizeof (mr
), flags
) < 0) {
1349 rc
= validate_mem_range(sc
, mr
.addr
, mr
.len
);
1353 memwin_info(sc
, 2, &mw_base
, &mw_aperture
);
1354 buf
= b
= kmem_zalloc(min(mr
.len
, mw_aperture
), KM_NOSLEEP
);
1362 dst
= (void *)mr
.data
;
1365 off
= position_memwin(sc
, 2, addr
);
1367 /* number of bytes that we'll copy in the inner loop */
1368 n
= min(remaining
, mw_aperture
- off
);
1370 for (i
= 0; i
< n
; i
+= 4)
1371 *b
++ = t4_read_reg(sc
, mw_base
+ off
+ i
);
1372 rc
= ddi_copyout(buf
, dst
, n
, flags
);
1384 kmem_free(buf
, min(mr
.len
, mw_aperture
));
1390 get_devlog(struct adapter
*sc
, void *data
, int flags
)
1392 struct devlog_params
*dparams
= &sc
->params
.devlog
;
1393 struct fw_devlog_e
*buf
;
1394 struct t4_devlog dl
;
1397 if (ddi_copyin(data
, &dl
, sizeof (dl
), flags
) < 0) {
1402 if (dparams
->start
== 0) {
1403 dparams
->memtype
= 0;
1404 dparams
->start
= 0x84000;
1405 dparams
->size
= 32768;
1408 if (dl
.len
< dparams
->size
) {
1409 dl
.len
= dparams
->size
;
1410 rc
= ddi_copyout(&dl
, data
, sizeof (dl
), flags
);
1412 * rc = 0 indicates copyout was successful, then return ENOBUFS
1413 * to indicate that the buffer size was not enough. Return of
1414 * EFAULT indicates that the copyout was not successful.
1416 rc
= (rc
== 0) ? ENOBUFS
: EFAULT
;
1420 buf
= kmem_zalloc(dparams
->size
, KM_NOSLEEP
);
1426 rc
= -t4_memory_rw(sc
, sc
->params
.drv_memwin
, dparams
->memtype
,
1427 dparams
->start
, dparams
->size
, (void *)buf
,
1432 /* Copyout device log buffer and then carrier buffer */
1433 if (ddi_copyout(buf
, (void *)((uintptr_t)data
+ sizeof(dl
)), dl
.len
,
1437 if (ddi_copyout(&dl
, data
, sizeof(dl
), flags
) < 0)
1441 kmem_free(buf
, dparams
->size
);
1448 read_cim_qcfg(struct adapter
*sc
, void *data
, int flags
)
1450 struct t4_cim_qcfg t4cimqcfg
;
1452 unsigned int ibq_rdaddr
, obq_rdaddr
, nq
;
1454 if (ddi_copyin(data
, &t4cimqcfg
, sizeof (t4cimqcfg
), flags
) < 0) {
1459 if (is_t4(sc
->params
.chip
)) {
1460 t4cimqcfg
.num_obq
= CIM_NUM_OBQ
;
1461 ibq_rdaddr
= A_UP_IBQ_0_RDADDR
;
1462 obq_rdaddr
= A_UP_OBQ_0_REALADDR
;
1464 t4cimqcfg
.num_obq
= CIM_NUM_OBQ_T5
;
1465 ibq_rdaddr
= A_UP_IBQ_0_SHADOW_RDADDR
;
1466 obq_rdaddr
= A_UP_OBQ_0_SHADOW_REALADDR
;
1468 nq
= CIM_NUM_IBQ
+ t4cimqcfg
.num_obq
;
1470 rc
= -t4_cim_read(sc
, ibq_rdaddr
, 4 * nq
, t4cimqcfg
.stat
);
1472 rc
= -t4_cim_read(sc
, obq_rdaddr
, 2 * t4cimqcfg
.num_obq
,
1477 t4_read_cimq_cfg(sc
, t4cimqcfg
.base
, t4cimqcfg
.size
, t4cimqcfg
.thres
);
1479 if (ddi_copyout(&t4cimqcfg
, data
, sizeof (t4cimqcfg
), flags
) < 0)
1487 read_edc(struct adapter
*sc
, void *data
, int flags
)
1489 struct t4_edc t4edc
;
1495 if (ddi_copyin(data
, &t4edc
, sizeof (t4edc
), flags
) < 0) {
1503 edc
= kmem_zalloc(t4edc
.len
, KM_NOSLEEP
);
1509 * Offset into the region of memory which is being accessed
1514 memoffset
= (t4edc
.mem
* (5 * 1024 * 1024));
1521 rc
= t4_memory_rw(sc
, sc
->params
.drv_memwin
, memoffset
, pos
,
1522 count
, edc
, T4_MEMORY_READ
);
1524 kmem_free(edc
, t4edc
.len
);
1528 len
= MEMWIN0_APERTURE
;
1533 if (ddi_copyout(edc
, t4edc
.data
, t4edc
.len
, flags
) < 0)
1536 kmem_free(edc
, t4edc
.len
);
1542 read_cim_ibq(struct adapter
*sc
, void *data
, int flags
)
1544 struct t4_ibq t4ibq
;
1548 if (ddi_copyin(data
, &t4ibq
, sizeof (t4ibq
), flags
) < 0) {
1553 buf
= kmem_zalloc(t4ibq
.len
, KM_NOSLEEP
);
1559 rc
= t4_read_cim_ibq(sc
, 3, (u32
*)buf
, CIM_IBQ_SIZE
* 4);
1561 kmem_free(buf
, t4ibq
.len
);
1566 if (ddi_copyout(buf
, t4ibq
.data
, t4ibq
.len
, flags
) < 0)
1569 kmem_free(buf
, t4ibq
.len
);
1576 read_cim_la(struct adapter
*sc
, void *data
, int flags
)
1578 struct t4_cim_la t4cimla
;
1583 rc
= t4_cim_read(sc
, A_UP_UP_DBG_LA_CFG
, 1, &cfg
);
1587 if (ddi_copyin(data
, &t4cimla
, sizeof (t4cimla
), flags
) < 0) {
1592 buf
= kmem_zalloc(t4cimla
.len
, KM_NOSLEEP
);
1598 rc
= t4_cim_read_la(sc
, (u32
*)buf
, NULL
);
1600 kmem_free(buf
, t4cimla
.len
);
1604 if (ddi_copyout(buf
, t4cimla
.data
, t4cimla
.len
, flags
) < 0)
1607 kmem_free(buf
, t4cimla
.len
);
1614 read_mbox(struct adapter
*sc
, void *data
, int flags
)
1616 struct t4_mbox t4mbox
;
1620 u32 data_reg
= PF_REG(4, A_CIM_PF_MAILBOX_DATA
);
1622 if (ddi_copyin(data
, &t4mbox
, sizeof (t4mbox
), flags
) < 0) {
1627 buf
= p
= kmem_zalloc(t4mbox
.len
, KM_NOSLEEP
);
1633 for (i
= 0; i
< t4mbox
.len
; i
+= 8, p
++)
1634 *p
= t4_read_reg64(sc
, data_reg
+ i
);
1636 if (ddi_copyout(buf
, t4mbox
.data
, t4mbox
.len
, flags
) < 0)
1639 kmem_free(buf
, t4mbox
.len
);
1646 flash_fw(struct adapter
*sc
, void *data
, int flags
)
1648 unsigned int mbox
= M_PCIE_FW_MASTER
+ 1;
1653 if (ddi_copyin(data
, &fw
, sizeof(struct t4_ldfw
), flags
) < 0)
1659 ptr
= (u8
*)kmem_zalloc(fw
.len
, KM_NOSLEEP
);
1663 if (ddi_copyin((void *)((uintptr_t)data
+ sizeof(fw
)), ptr
, fw
.len
,
1665 kmem_free(ptr
, fw
.len
);
1669 if (sc
->flags
& FULL_INIT_DONE
)
1672 rc
= -t4_fw_upgrade(sc
, mbox
, ptr
, fw
.len
, true);
1674 kmem_free(ptr
, fw
.len
);