usr/src/uts/common/io/ntxn/unm_brdcfg.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21
  22 /*
  23  * Copyright 2008 NetXen, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 #ifndef _UNM_BRDINFO_H_
  28 #define _UNM_BRDINFO_H_
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The version of the main data structure */
  35 #define UNM_BDINFO_VERSION 1
  36
  37 /* Magic number to let user know flash is programmed */
  38 #define UNM_BDINFO_MAGIC 0x12345678
  39
  40 #define P2_CHIP 2
  41 #define P3_CHIP 3
  42 #define NX_P2_C0                0x24
  43 #define NX_P2_C1                0x25
  44 #define NX_P3_A0                0x30
  45 #define NX_P3_A2                0x32
  46 #define NX_P3_B0                0x40
  47 #define NX_P3_B1                0x41
  48 #define NX_P3_B2                0x42
  49
  50 #define NX_IS_REVISION_P2(REVISION)     (REVISION <= NX_P2_C1)
  51 #define NX_IS_REVISION_P3(REVISION)     (REVISION >= NX_P3_A0)
  52
  53 typedef enum {
  54     UNM_BRDTYPE_P1_BD   = 0x0000,
  55     UNM_BRDTYPE_P1_SB   = 0x0001,
  56     UNM_BRDTYPE_P1_SMAX = 0x0002,
  57     UNM_BRDTYPE_P1_SOCK = 0x0003,
  58
  59     UNM_BRDTYPE_P2_SOCK_31  =  0x0008,
  60     UNM_BRDTYPE_P2_SOCK_35  =  0x0009,
  61     UNM_BRDTYPE_P2_SB35_4G  =  0x000a,
  62     UNM_BRDTYPE_P2_SB31_10G =  0x000b,
  63     UNM_BRDTYPE_P2_SB31_2G  =  0x000c,
  64
  65     UNM_BRDTYPE_P2_SB31_10G_IMEZ =  0x000d,
  66     UNM_BRDTYPE_P2_SB31_10G_HMEZ =  0x000e,
  67     UNM_BRDTYPE_P2_SB31_10G_CX4  =  0x000f,
  68
  69         /* Reference quad gig */
  70         UNM_BRDTYPE_P3_REF_QG           =       0x0021,
  71         UNM_BRDTYPE_P3_HMEZ                     =       0x0022,
  72         /* Dual CX4 - Low Profile - Red card */
  73         UNM_BRDTYPE_P3_10G_CX4_LP       =  0x0023,
  74         UNM_BRDTYPE_P3_4_GB                     =       0x0024,
  75         UNM_BRDTYPE_P3_IMEZ                     =       0x0025,
  76         UNM_BRDTYPE_P3_10G_SFP_PLUS     =       0x0026,
  77         UNM_BRDTYPE_P3_10000_BASE_T     =       0x0027,
  78         UNM_BRDTYPE_P3_XG_LOM           =       0x0028,
  79
  80         UNM_BRDTYPE_P3_4_GB_MM          =       0x0029,
  81         UNM_BRDTYPE_P3_10G_CX4          =       0x0031, /* Reference CX4 */
  82         UNM_BRDTYPE_P3_10G_XFP          =       0x0032, /* Reference XFP */
  83
  84     UNM_BRDTYPE_P3_10G_TRP       =  0x0080
  85
  86 } unm_brdtype_t;
  87
  88 typedef enum {
  89         NX_UNKNOWN_TYPE_ROMIMAGE = 0,
  90         NX_P2_MN_TYPE_ROMIMAGE = 1,
  91         NX_P3_CT_TYPE_ROMIMAGE,
  92         NX_P3_MN_TYPE_ROMIMAGE,
  93         NX_P3_MS_TYPE_ROMIMAGE,
  94         NX_UNKNOWN_TYPE_ROMIMAGE_LAST
  95 } nx_fw_type_t;
  96
  97 /* board type specific information */
  98 typedef struct {
  99         unm_brdtype_t   brdtype; /* type of board */
 100         long                    ports; /* max no of physical ports */
 101         nx_fw_type_t    fwtype; /* The FW Associated with board type */
 102         char                    *short_name;
 103 } unm_brdinfo_t;
 104
 105 #define NUM_SUPPORTED_BOARDS (sizeof (unm_boards)/sizeof (unm_brdinfo_t))
 106
 107 #define GET_BRD_NAME_BY_TYPE(type, name)            \
 108 {                                                   \
 109         int i, found = 0;                               \
 110         for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {    \
 111                 if (unm_boards[i].brdtype == type) {        \
 112                         name = unm_boards[i].short_name;        \
 113                         found = 1;                              \
 114                         break;                                  \
 115                 }                                           \
 116         }                                               \
 117         if (!found)                                   \
 118         name = "Unknown";                           \
 119 }
 120
 121 typedef struct {
 122     __uint32_t header_version;
 123
 124     __uint32_t board_mfg;
 125     __uint32_t board_type;
 126     __uint32_t board_num;
 127     __uint32_t chip_id;
 128     __uint32_t chip_minor;
 129     __uint32_t chip_major;
 130     __uint32_t chip_pkg;
 131     __uint32_t chip_lot;
 132
 133
 134         __uint32_t port_mask; /* available niu ports */
 135         __uint32_t peg_mask; /* available pegs */
 136         __uint32_t icache_ok; /* can we run with icache? */
 137         __uint32_t dcache_ok; /* can we run with dcache? */
 138         __uint32_t casper_ok;
 139
 140         /* unm_eth_addr_t  mac_address[MAX_PORTS]; */
 141     __uint32_t mac_addr_lo_0;
 142     __uint32_t mac_addr_lo_1;
 143     __uint32_t mac_addr_lo_2;
 144     __uint32_t mac_addr_lo_3;
 145
 146         /* MN-related config */
 147     __uint32_t mn_sync_mode;    /* enable/ sync shift cclk/ sync shift mclk */
 148     __uint32_t mn_sync_shift_cclk;
 149     __uint32_t mn_sync_shift_mclk;
 150     __uint32_t mn_wb_en;
 151     __uint32_t mn_crystal_freq; /* in MHz */
 152     __uint32_t mn_speed; /* in MHz */
 153     __uint32_t mn_org;
 154     __uint32_t mn_depth;
 155     __uint32_t mn_ranks_0; /* ranks per slot */
 156     __uint32_t mn_ranks_1; /* ranks per slot */
 157     __uint32_t mn_rd_latency_0;
 158     __uint32_t mn_rd_latency_1;
 159     __uint32_t mn_rd_latency_2;
 160     __uint32_t mn_rd_latency_3;
 161     __uint32_t mn_rd_latency_4;
 162     __uint32_t mn_rd_latency_5;
 163     __uint32_t mn_rd_latency_6;
 164     __uint32_t mn_rd_latency_7;
 165     __uint32_t mn_rd_latency_8;
 166     __uint32_t mn_dll_val[18];
 167     __uint32_t mn_mode_reg; /* See MIU DDR Mode Register */
 168     __uint32_t mn_ext_mode_reg; /* See MIU DDR Extended Mode Register */
 169     __uint32_t mn_timing_0; /* See MIU Memory Control Timing Rgister */
 170     __uint32_t mn_timing_1; /* See MIU Extended Memory Ctrl Timing Register */
 171     __uint32_t mn_timing_2; /* See MIU Extended Memory Ctrl Timing2 Register */
 172
 173         /* SN-related config */
 174     __uint32_t sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
 175     __uint32_t sn_pt_mode; /* pass through mode */
 176     __uint32_t sn_ecc_en;
 177     __uint32_t sn_wb_en;
 178     __uint32_t sn_crystal_freq;
 179     __uint32_t sn_speed;
 180     __uint32_t sn_org;
 181     __uint32_t sn_depth;
 182     __uint32_t sn_dll_tap;
 183     __uint32_t sn_rd_latency;
 184
 185     __uint32_t mac_addr_hi_0;
 186     __uint32_t mac_addr_hi_1;
 187     __uint32_t mac_addr_hi_2;
 188     __uint32_t mac_addr_hi_3;
 189
 190     __uint32_t magic; /* indicates flash has been initialized */
 191
 192     __uint32_t mn_rdimm;
 193     __uint32_t mn_dll_override;
 194     __uint32_t coreclock_speed;
 195 }  unm_board_info_t;
 196
 197 #define FLASH_NUM_PORTS         4
 198
 199 typedef struct {
 200     __uint32_t flash_addr[32];
 201 } unm_flash_mac_addr_t;
 202
 203 /* flash user area */
 204 typedef struct {
 205     __uint8_t  flash_md5[16];
 206     __uint8_t  crbinit_md5[16];
 207     __uint8_t  brdcfg_md5[16];
 208         /* bootloader */
 209     __uint32_t bootld_version;
 210     __uint32_t bootld_size;
 211     __uint8_t  bootld_md5[16];
 212         /* image */
 213     __uint32_t image_version;
 214     __uint32_t image_size;
 215     __uint8_t  image_md5[16];
 216         /* primary image status */
 217     __uint32_t primary_status;
 218     __uint32_t secondary_present;
 219
 220         /* MAC address , 4 ports */
 221     unm_flash_mac_addr_t mac_addr[FLASH_NUM_PORTS];
 222
 223         /* Any user defined data */
 224 } unm_old_user_info_t;
 225
 226 #define FLASH_NUM_MAC_PER_PORT          32
 227 typedef struct {
 228     __uint8_t  flash_md5[16 * 64];
 229         /* __uint8_t  crbinit_md5[16]; */
 230         /* __uint8_t  brdcfg_md5[16]; */
 231         /* bootloader */
 232     __uint32_t bootld_version;
 233     __uint32_t bootld_size;
 234         /* __uint8_t  bootld_md5[16]; */
 235         /* image */
 236     __uint32_t image_version;
 237     __uint32_t image_size;
 238         /* U8  image_md5[16]; */
 239         /* primary image status */
 240     __uint32_t primary_status;
 241     __uint32_t secondary_present;
 242
 243         /* MAC address , 4 ports, 32 address per port */
 244     __uint64_t mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 245     __uint32_t sub_sys_id;
 246     __uint8_t  serial_num[32];
 247         __uint32_t bios_version;
 248     __uint32_t pxe_enable;  /* bitmask, per port */
 249     __uint32_t vlan_tag[FLASH_NUM_PORTS];
 250
 251         /* Any user defined data */
 252 } unm_user_info_t;
 253
 254 /* Flash memory map */
 255 typedef enum {
 256     CRBINIT_START   = 0,                /* Crbinit section */
 257     BRDCFG_START    = 0x4000,   /* board config */
 258     INITCODE_START  = 0x6000,   /* pegtune code */
 259     BOOTLD_START    = 0x10000,  /* bootld */
 260     BOOTLD1_START   = 0x14000,  /* Start of booloader 1 */
 261         IMAGE_START             = 0x43000,      /* compressed image */
 262     SECONDARY_START = 0x200000, /* backup images */
 263     PXE_FIRST_STAGE_INTEL = 0x3C0000, /* Intel First Stage info */
 264     PXE_FIRST_STAGE_PPC = 0x3C4000, /* PPC First Stage info */
 265     PXE_SECOND_STAGE_INTEL = 0x3B0000, /* Intel Second Stage info */
 266     PXE_SECOND_STAGE_PPC = 0x3A0000, /* Intel Second Stage info */
 267 /*    LICENSE_TIME_START = 0x3C0000,  license expiry time info */
 268         PXE_START               = 0x3D0000,   /* PXE image area */
 269     DEFAULT_DATA_START = 0x3e0000, /* where we place default factory data */
 270         /* User defined region for new boards */
 271         USER_START              = 0x3E8000,
 272     VPD_START           = 0x3E8C00,   /* Vendor private data */
 273     LICENSE_START       = 0x3E9000,   /* Firmware License */
 274     FIXED_START         = 0x3F0000    /* backup of crbinit */
 275 } unm_flash_map_t;
 276
 277 #define USER_START_OLD          PXE_START /* for backward compatibility */
 278
 279 #ifdef __cplusplus
 280 }
 281 #endif
 282
 283 #endif  /* !_UNM_BRDINFO_H_ */