usr/src/uts/common/io/ntxn/unm_nic.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21
  22 /*
  23  * Copyright 2008 NetXen, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26 /*
  27  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  28  * Use is subject to license terms.
  29  */
  30
  31 #ifndef _UNM_NIC_
  32 #define _UNM_NIC_
  33
  34 #ifdef __cplusplus
  35 extern "C" {
  36 #endif
  37
  38 #include <sys/inttypes.h>
  39 #include <sys/rwlock.h>
  40 #include <sys/mutex.h>
  41 #include <sys/ddi.h>
  42
  43 #include <sys/sunddi.h>
  44 #include <sys/types.h>
  45 #include <sys/stream.h>
  46 #include <sys/strsun.h>
  47 #include <sys/strsubr.h>
  48 #include <sys/dlpi.h>
  49 #include <sys/devops.h>
  50 #include <sys/stat.h>
  51 #include <sys/pci.h>
  52 #include <sys/note.h>
  53 #include <sys/modctl.h>
  54 #include <sys/kstat.h>
  55 #include <sys/ethernet.h>
  56 #include <sys/errno.h>
  57 #include <netinet/ip6.h>
  58 #include <inet/common.h>
  59 #include <sys/pattr.h>
  60 #include <inet/mi.h>
  61 #include <inet/nd.h>
  62
  63 #ifdef SOLARIS11
  64 #include <sys/mac_provider.h>
  65 #include <sys/mac_ether.h>
  66 #else
  67 #include "mac.h"
  68 #include "mac_ether.h"
  69 #endif
  70 #include <sys/miiregs.h> /* by fjlite out of intel */
  71
  72 #include "unm_nic_hw.h"
  73 #include "nic_cmn.h"
  74 #include "unm_inc.h" /* For MAX_RCV_CTX */
  75 #include "unm_brdcfg.h"
  76 #include "unm_version.h"
  77 #include "nic_phan_reg.h"
  78 #include "unm_nic_ioctl.h"
  79
  80 #define MAX_ADDR_LEN     6
  81
  82 #define ADDR_IN_WINDOW1(off)    \
  83         ((off > UNM_CRB_PCIX_HOST2) && (off < UNM_CRB_MAX)) ? 1 : 0
  84
  85 typedef unsigned long uptr_t;
  86
  87 #define FIRST_PAGE_GROUP_START  0
  88 #define FIRST_PAGE_GROUP_END    0x100000
  89
  90 #define SECOND_PAGE_GROUP_START 0x6000000
  91 #define SECOND_PAGE_GROUP_END   0x68BC000
  92
  93 #define THIRD_PAGE_GROUP_START  0x70E4000
  94 #define THIRD_PAGE_GROUP_END    0x8000000
  95
  96 #define FIRST_PAGE_GROUP_SIZE   FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
  97 #define SECOND_PAGE_GROUP_SIZE  SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
  98 #define THIRD_PAGE_GROUP_SIZE   THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
  99
 100 /*
 101  * normalize a 64MB crb address to 32MB PCI window
 102  * To use CRB_NORMALIZE, window _must_ be set to 1
 103  */
 104 #define CRB_NORMAL(reg) \
 105         (reg) - UNM_CRB_PCIX_HOST2 + UNM_CRB_PCIX_HOST
 106 #define CRB_NORMALIZE(adapter, reg) \
 107         (void *)(unsigned long)(pci_base_offset(adapter, CRB_NORMAL(reg)))
 108
 109 #define DB_NORMALIZE(adapter, off) \
 110         (void *)((unsigned long)adapter->ahw.db_base + (off))
 111
 112 #define find_diff_among(a, b, range) \
 113         ((a) < (b)?((b)-(a)):((b)+(range)-(a)))
 114
 115 #define __FUNCTION__            __func__
 116 #define nx_msleep(_msecs_)      ddi_msleep(_msecs_)
 117
 118 #define HOST_TO_LE_64                   LE_64
 119 #define HOST_TO_LE_32                   LE_32
 120 #define LE_TO_HOST_32                   LE_32
 121 #define HOST_TO_LE_16                   LE_16
 122 #define LE_TO_HOST_16                   LE_16
 123
 124 #define dbwritel(DATA, ADDRESS) \
 125         ddi_put32(adapter->db_handle, (uint32_t *)(ADDRESS), (DATA))
 126
 127 /*
 128  * Following macros require the mapped addresses to access
 129  * the Phantom memory.
 130  */
 131 #define UNM_NIC_PCI_READ_8(ADDRESS) \
 132         ddi_get8(adapter->regs_handle, (uint8_t *)(ADDRESS))
 133 #define UNM_NIC_PCI_READ_16(ADDRESS) \
 134         ddi_get16(adapter->regs_handle, (uint16_t *)(ADDRESS))
 135 #define UNM_NIC_PCI_READ_32(ADDRESS) \
 136         ddi_get32(adapter->regs_handle, (uint32_t *)(ADDRESS))
 137 #define UNM_NIC_PCI_READ_64(ADDRESS) \
 138         ddi_get64(adapter->regs_handle, (uint64_t *)(ADDRESS))
 139
 140 #define UNM_NIC_PCI_WRITE_8(DATA, ADDRESS) \
 141         ddi_put8(adapter->regs_handle, (uint8_t *)(ADDRESS), (DATA))
 142 #define UNM_NIC_PCI_WRITE_16(DATA, ADDRESS) \
 143         ddi_put16(adapter->regs_handle, (uint16_t *)(ADDRESS), (DATA))
 144 #define UNM_NIC_PCI_WRITE_32(DATA, ADDRESS) \
 145         ddi_put32(adapter->regs_handle, (uint32_t *)(ADDRESS), (DATA))
 146 #define UNM_NIC_PCI_WRITE_64(DATA, ADDRESS) \
 147         ddi_put64(adapter->regs_handle, (uint64_t *)(ADDRESS), (DATA))
 148
 149 #ifdef DEBUG_LEVEL
 150 #define DPRINTF(n, args)        if (DEBUG_LEVEL > (n)) cmn_err args;
 151 #else
 152 #define DPRINTF(n, args)
 153 #endif
 154
 155 #define UNM_SPIN_LOCK(_lp_)                     mutex_enter((_lp_))
 156 #define UNM_SPIN_UNLOCK(_lp_)                   mutex_exit((_lp_))
 157 #define UNM_SPIN_LOCK_ISR(_lp_)                 mutex_enter((_lp_))
 158 #define UNM_SPIN_UNLOCK_ISR(_lp_)               mutex_exit((_lp_))
 159
 160 #define UNM_WRITE_LOCK(_lp_)                    rw_enter((_lp_), RW_WRITER)
 161 #define UNM_WRITE_UNLOCK(_lp_)                  rw_exit((_lp_))
 162 #define UNM_READ_LOCK(_lp_)                     rw_enter((_lp_), RW_READER)
 163 #define UNM_READ_UNLOCK(_lp_)                   rw_exit((_lp_))
 164 #define UNM_WRITE_LOCK_IRQS(_lp_, _fl_)         rw_enter((_lp_), RW_WRITER)
 165 #define UNM_WRITE_UNLOCK_IRQR(_lp_, _fl_)       rw_exit((_lp_))
 166
 167 extern char unm_nic_driver_name[];
 168 extern int verbmsg;
 169
 170 typedef struct unm_dmah_node {
 171         struct unm_dmah_node *next;
 172         ddi_dma_handle_t dmahdl;
 173 }unm_dmah_node_t;
 174
 175 typedef struct dma_area {
 176         ddi_acc_handle_t        acc_hdl;        /* handle for memory    */
 177         ddi_dma_handle_t        dma_hdl;        /* DMA handle           */
 178         uint32_t                ncookies;
 179         u64                     dma_addr;
 180         void                    *vaddr;
 181 } dma_area_t;
 182
 183 struct unm_cmd_buffer {
 184         dma_area_t      dma_area;
 185         mblk_t          *msg;
 186         unm_dmah_node_t *head, *tail;
 187 };
 188
 189 typedef struct pkt_info {
 190         uint32_t        total_len;
 191         uint16_t        mblk_no;
 192         uint16_t        etype;
 193         uint16_t        mac_hlen;
 194         uint16_t        ip_hlen;
 195         uint16_t        l4_proto;
 196 } pktinfo_t;
 197
 198 typedef struct unm_rcv_desc_context_s unm_rcv_desc_ctx_t;
 199 typedef struct unm_adapter_s unm_adapter;
 200
 201 typedef struct unm_rx_buffer {
 202         struct unm_rx_buffer    *next;
 203         dma_area_t              dma_info;
 204         frtn_t                  rx_recycle;     /* recycle function */
 205         mblk_t                  *mp;
 206         unm_rcv_desc_ctx_t      *rcv_desc;
 207         unm_adapter             *adapter;
 208 }unm_rx_buffer_t;
 209
 210 /* Board types */
 211 #define UNM_NIC_GBE             0x01
 212 #define UNM_NIC_XGBE    0x02
 213
 214 /*
 215  * One hardware_context{} per adapter
 216  * contains interrupt info as well shared hardware info.
 217  */
 218 typedef struct _hardware_context {
 219         unsigned long   pci_base0;
 220         unsigned long   pci_len0;
 221         unsigned long   pci_base1;
 222         unsigned long   pci_len1;
 223         unsigned long   pci_base2;
 224         unsigned long   pci_len2;
 225         unsigned long   first_page_group_end;
 226         unsigned long   first_page_group_start;
 227         uint8_t                 revision_id;
 228         uint8_t                 cut_through;
 229         uint16_t                board_type;
 230         int                             pci_func;
 231         uint16_t                max_ports;
 232         unm_board_info_t        boardcfg;
 233         uint32_t                linkup;
 234
 235         struct unm_adapter_s    *adapter;
 236         cmdDescType0_t                  *cmdDescHead;
 237
 238         uint32_t                cmdProducer;
 239         uint32_t                cmdConsumer;
 240         uint32_t                rcvFlag;
 241         uint32_t                crb_base;
 242         unsigned long   db_base;    /* base of mapped db memory */
 243         unsigned long   db_len;    /* length of mapped db memory */
 244
 245
 246         uint64_t                cmdDesc_physAddr;
 247         int                             qdr_sn_window, ddr_mn_window;
 248         unsigned long   mn_win_crb, ms_win_crb;
 249         ddi_dma_handle_t cmd_desc_dma_handle;
 250         ddi_acc_handle_t cmd_desc_acc_handle;
 251         ddi_dma_cookie_t cmd_desc_dma_cookie;
 252 } hardware_context, *phardware_context;
 253
 254 #define NX_CT_DEFAULT_RX_BUF_LEN        2048
 255 #define MTU_SIZE                        1500
 256 #define MAX_COOKIES_PER_CMD             15
 257 #define UNM_DB_MAPSIZE_BYTES            0x1000
 258 #define EXTRA_HANDLES                   512
 259 #define UNM_TX_BCOPY_THRESHOLD          128
 260 #define UNM_RX_BCOPY_THRESHOLD          128
 261 #define NX_MIN_DRIVER_RDS_SIZE          64
 262
 263 typedef struct unm_pauseparam {
 264         uint16_t rx_pause;
 265         uint16_t tx_pause;
 266 } unm_pauseparam_t;
 267
 268 /*
 269  * The driver supports the NDD ioctls ND_GET/ND_SET, and the loopback
 270  * ioctls LB_GET_INFO_SIZE/LB_GET_INFO/LB_GET_MODE/LB_SET_MODE
 271  *
 272  * These are the values to use with LD_SET_MODE.
 273  */
 274 #define UNM_LOOP_NONE      0
 275 #define UNM_LOOP_INTERNAL_PHY   1
 276 #define UNM_LOOP_INTERNAL_MAC   2
 277
 278 /*
 279  * Named Data (ND) Parameter Management Structure
 280  */
 281 typedef struct {
 282         int                     ndp_info;
 283         int                     ndp_min;
 284         int                     ndp_max;
 285         int                     ndp_val;
 286         char            *ndp_name;
 287 } nd_param_t; /* 0x18 (24) bytes  */
 288
 289 /*
 290  * NDD parameter indexes, divided into:
 291  *
 292  *      read-only parameters describing the hardware's capabilities
 293  *      read-write parameters controlling the advertised capabilities
 294  *      read-only parameters describing the partner's capabilities
 295  *      read-only parameters describing the link state
 296  */
 297 enum {
 298         PARAM_AUTONEG_CAP = 0,
 299         PARAM_PAUSE_CAP,
 300         PARAM_ASYM_PAUSE_CAP,
 301         PARAM_10000FDX_CAP,
 302         PARAM_1000FDX_CAP,
 303         PARAM_1000HDX_CAP,
 304         PARAM_100T4_CAP,
 305         PARAM_100FDX_CAP,
 306         PARAM_100HDX_CAP,
 307         PARAM_10FDX_CAP,
 308         PARAM_10HDX_CAP,
 309
 310         PARAM_ADV_AUTONEG_CAP,
 311         PARAM_ADV_PAUSE_CAP,
 312         PARAM_ADV_ASYM_PAUSE_CAP,
 313         PARAM_ADV_10000FDX_CAP,
 314         PARAM_ADV_1000FDX_CAP,
 315         PARAM_ADV_1000HDX_CAP,
 316         PARAM_ADV_100T4_CAP,
 317         PARAM_ADV_100FDX_CAP,
 318         PARAM_ADV_100HDX_CAP,
 319         PARAM_ADV_10FDX_CAP,
 320         PARAM_ADV_10HDX_CAP,
 321
 322         PARAM_LINK_STATUS,
 323         PARAM_LINK_SPEED,
 324         PARAM_LINK_DUPLEX,
 325
 326         PARAM_LOOP_MODE,
 327
 328         PARAM_COUNT
 329 };
 330
 331 struct unm_adapter_stats {
 332         uint64_t  rcvdbadmsg;
 333         uint64_t  xmitcalled;
 334         uint64_t  xmitedframes;
 335         uint64_t  xmitfinished;
 336         uint64_t  badmsglen;
 337         uint64_t  nocmddescriptor;
 338         uint64_t  polled;
 339         uint64_t  uphappy;
 340         uint64_t  updropped;
 341         uint64_t  uplcong;
 342         uint64_t  uphcong;
 343         uint64_t  upmcong;
 344         uint64_t  updunno;
 345         uint64_t  msgfreed;
 346         uint64_t  txdropped;
 347         uint64_t  txnullmsg;
 348         uint64_t  csummed;
 349         uint64_t  no_rcv;
 350         uint64_t  rxbytes;
 351         uint64_t  txbytes;
 352         uint64_t  ints;
 353         uint64_t  desballocfailed;
 354         uint64_t  txcopyed;
 355         uint64_t  txmapped;
 356         uint64_t  outoftxdmahdl;
 357         uint64_t  outofcmddesc;
 358         uint64_t  rxcopyed;
 359         uint64_t  rxmapped;
 360         uint64_t  outofrxbuf;
 361         uint64_t  promiscmode;
 362         uint64_t  rxbufshort;
 363         uint64_t  allocbfailed;
 364 };
 365
 366 /* descriptor types */
 367 #define RCV_RING_STD            RCV_DESC_NORMAL
 368 #define RCV_RING_JUMBO          RCV_DESC_JUMBO
 369 #define RCV_RING_LRO            RCV_DESC_LRO
 370
 371 /*
 372  * Rcv Descriptor Context. One such per Rcv Descriptor. There may
 373  * be one Rcv Descriptor for normal packets, one for jumbo,
 374  * one for LRO and may be expanded.
 375  */
 376 struct unm_rcv_desc_context_s {
 377         uint32_t        producer;
 378
 379         uint64_t        phys_addr;
 380         dev_info_t      *phys_pdev;
 381         /* address of rx ring in Phantom */
 382         rcvDesc_t       *desc_head;
 383
 384         uint32_t        MaxRxDescCount;
 385         uint32_t        rx_desc_handled;
 386         uint32_t        rx_buf_card;
 387         uint32_t        rx_buf_total;
 388         uint32_t        rx_buf_free;
 389         uint32_t        rx_buf_recycle;
 390         unm_rx_buffer_t *rx_buf_pool;
 391         unm_rx_buffer_t *pool_list;
 392         unm_rx_buffer_t *recycle_list;
 393         kmutex_t        pool_lock[1];   /* buffer pool lock */
 394         kmutex_t        recycle_lock[1]; /* buffer recycle lock */
 395         /* size of the receive buf */
 396         uint32_t        buf_size;
 397         /* rx buffers for receive   */
 398
 399         ddi_dma_handle_t        rx_desc_dma_handle;
 400         ddi_acc_handle_t        rx_desc_acc_handle;
 401         ddi_dma_cookie_t        rx_desc_dma_cookie;
 402         uint32_t                host_rx_producer;
 403         uint32_t                dma_size;
 404 };
 405
 406 /*
 407  * Receive context. There is one such structure per instance of the
 408  * receive processing. Any state information that is relevant to
 409  * the receive, and is must be in this structure. The global data may be
 410  * present elsewhere.
 411  */
 412 typedef struct unm_recv_context_s {
 413         unm_rcv_desc_ctx_t      rcv_desc[NUM_RCV_DESC_RINGS];
 414
 415         uint32_t                        statusRxConsumer;
 416
 417         uint64_t                        rcvStatusDesc_physAddr;
 418         statusDesc_t            *rcvStatusDescHead;
 419
 420         ddi_dma_handle_t        status_desc_dma_handle;
 421         ddi_acc_handle_t        status_desc_acc_handle;
 422         ddi_dma_cookie_t        status_desc_dma_cookie;
 423
 424         uint32_t                state, host_sds_consumer;
 425         uint16_t                context_id, virt_port;
 426 } unm_recv_context_t;
 427
 428 #define UNM_NIC_MSI_ENABLED     0x02
 429 #define UNM_NIC_MSIX_ENABLED    0x04
 430 #define UNM_IS_MSI_FAMILY(ADAPTER)      \
 431         ((ADAPTER)->flags & (UNM_NIC_MSI_ENABLED | UNM_NIC_MSIX_ENABLED))
 432
 433 #define NX_USE_MSIX
 434
 435 /* msix defines */
 436 #define MSIX_ENTRIES_PER_ADAPTER        8
 437 #define UNM_MSIX_TBL_SPACE              8192
 438 #define UNM_PCI_REG_MSIX_TBL            0x44
 439
 440 /*
 441  * Bug: word or char write on MSI-X capcabilities register (0x40) in PCI config
 442  * space has no effect on register values. Need to write dword.
 443  */
 444 #define UNM_HWBUG_8_WORKAROUND
 445
 446 /*
 447  * Bug: Can not reset bit 32 (msix enable bit) on MSI-X capcabilities
 448  * register (0x40) independently.
 449  * Need to write 0x0 (zero) to MSI-X capcabilities register in order to reset
 450  * msix enable bit. On writing zero rest of the bits are not touched.
 451  */
 452 #define UNM_HWBUG_9_WORKAROUND
 453
 454 #define UNM_MC_COUNT    38      /* == ((UNM_ADDR_L2LU_COUNT-1)/4) -2 */
 455
 456 /* Following structure is for specific port information */
 457 struct unm_adapter_s {
 458         hardware_context        ahw;
 459         uint8_t                 id[32];
 460         uint16_t                portnum;
 461         uint16_t                physical_port;
 462         uint16_t                link_speed;
 463         uint16_t                link_duplex;
 464
 465         struct unm_adapter_stats stats;
 466         int                     rx_csum;
 467         int                     status;
 468         kmutex_t                stats_lock;
 469         unsigned char           mac_addr[MAX_ADDR_LEN];
 470         int                     mtu;            /* active mtu */
 471         int                     maxmtu;         /* max possible mtu value */
 472         uint32_t                promisc;
 473
 474         mac_resource_handle_t   mac_rx_ring_ha;
 475         mac_handle_t    mach;
 476         int                             flags;
 477
 478         int               instance;
 479         dev_info_t        *dip;
 480         ddi_acc_handle_t  pci_cfg_handle;
 481         ddi_acc_handle_t  regs_handle;
 482         ddi_dma_attr_t    gc_dma_attr_desc;
 483
 484         struct ddi_device_acc_attr  gc_attr_desc;
 485         ddi_iblock_cookie_t iblock_cookie;
 486         const char *name;
 487         ddi_acc_handle_t  db_handle;
 488
 489         ddi_intr_handle_t       intr_handle;
 490         int                     intr_type;
 491         uint_t          intr_pri;
 492         unm_dmah_node_t         *dmahdl_pool;
 493         unm_dmah_node_t         tx_dma_hdls[MAX_CMD_DESCRIPTORS+EXTRA_HANDLES];
 494         uint64_t                freehdls;
 495         uint64_t                freecmds;
 496         int                     tx_bcopy_threshold;
 497         kmutex_t                tx_lock;
 498         krwlock_t               adapter_lock;
 499         kmutex_t                lock;
 500         struct nx_legacy_intr_set       legacy_intr;
 501         timeout_id_t            watchdog_timer;
 502         kstat_t                 *kstats[1];
 503
 504         uint32_t                curr_window;
 505         uint32_t                crb_win;
 506         uint32_t                cmdProducer;
 507         uint32_t                *cmdConsumer;
 508
 509         uint32_t                interrupt_crb;
 510         uint32_t                fw_major;
 511         uint32_t                crb_addr_cmd_producer;
 512         uint32_t                crb_addr_cmd_consumer;
 513         uint16_t                tx_context_id;
 514         short                   context_alloced;
 515         int                     max_rds_rings;
 516
 517         uint32_t                lastCmdConsumer;
 518         /* Num of bufs posted in phantom */
 519         uint32_t        pendingCmdCount;
 520         uint32_t        MaxTxDescCount;
 521         uint32_t        MaxRxDescCount;
 522         uint32_t        MaxJumboRxDescCount;
 523         uint32_t        MaxLroRxDescCount;
 524         /* Num of instances active on cmd buffer ring */
 525         int             resched_needed;
 526
 527         int                     driver_mismatch;
 528         uint32_t        temp;
 529
 530         struct unm_cmd_buffer *cmd_buf_arr;  /* Command buffers for xmit */
 531         int             rx_bcopy_threshold;
 532
 533         /*
 534          * Receive instances. These can be either one per port,
 535          * or one per peg, etc.
 536          */
 537         unm_recv_context_t      recv_ctx[MAX_RCV_CTX];
 538         int             is_up;
 539
 540         /* context interface shared between card and host */
 541         RingContext             *ctxDesc;
 542         uint64_t                ctxDesc_physAddr;
 543         ddi_dma_handle_t        ctxDesc_dma_handle;
 544         ddi_acc_handle_t        ctxDesc_acc_handle;
 545
 546         struct {
 547                 void                    *addr;
 548                 uint64_t                phys_addr;
 549                 ddi_dma_handle_t        dma_handle;
 550                 ddi_acc_handle_t        acc_handle;
 551         } dummy_dma;
 552
 553         void    (*unm_nic_pci_change_crbwindow)(struct unm_adapter_s *,
 554                     uint32_t);
 555         int     (*unm_crb_writelit_adapter)(struct unm_adapter_s *,
 556                     unsigned long, int);
 557         unsigned long long
 558                 (*unm_nic_pci_set_window)(struct unm_adapter_s *,
 559                     unsigned long long);
 560         int     (*unm_nic_fill_statistics)(struct unm_adapter_s *,
 561                     struct unm_statistics *);
 562         int     (*unm_nic_clear_statistics)(struct unm_adapter_s *);
 563         int     (*unm_nic_hw_write_wx)(struct unm_adapter_s *, u64,
 564             void *, int);
 565         int     (*unm_nic_hw_read_wx)(struct unm_adapter_s *, u64, void *, int);
 566         int     (*unm_nic_hw_write_ioctl)(struct unm_adapter_s *, u64, void *,
 567                     int);
 568         int     (*unm_nic_hw_read_ioctl)(struct unm_adapter_s *, u64, void *,
 569                     int);
 570         int     (*unm_nic_pci_mem_write)(struct unm_adapter_s *, u64, void *,
 571                     int);
 572         int     (*unm_nic_pci_mem_read)(struct unm_adapter_s *, u64, void *,
 573                     int);
 574         int     (*unm_nic_pci_write_immediate)(struct unm_adapter_s *, u64,
 575                     u32 *);
 576         int     (*unm_nic_pci_read_immediate)(struct unm_adapter_s *, u64,
 577                     u32 *);
 578         void    (*unm_nic_pci_write_normalize)(struct unm_adapter_s *, u64,
 579                     u32);
 580         u32     (*unm_nic_pci_read_normalize)(struct unm_adapter_s *, u64);
 581
 582         caddr_t                 nd_data_p;
 583         nd_param_t              nd_params[PARAM_COUNT];
 584 };  /* unm_adapter structure */
 585
 586 #define UNM_HOST_DUMMY_DMA_SIZE  1024
 587
 588 /* Following structure is for specific port information    */
 589
 590 #define PCI_OFFSET_FIRST_RANGE(adapter, off)    \
 591         ((adapter)->ahw.pci_base0 + off)
 592 #define PCI_OFFSET_SECOND_RANGE(adapter, off)   \
 593         ((adapter)->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START)
 594 #define PCI_OFFSET_THIRD_RANGE(adapter, off)    \
 595         ((adapter)->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START)
 596
 597 #define pci_base_offset(adapter, off)   \
 598         ((((off) < ((adapter)->ahw.first_page_group_end)) &&    \
 599             ((off) >= ((adapter)->ahw.first_page_group_start))) ?       \
 600             ((adapter)->ahw.pci_base0 + (off)) :        \
 601             ((((off) < SECOND_PAGE_GROUP_END) &&        \
 602             ((off) >= SECOND_PAGE_GROUP_START)) ?       \
 603             ((adapter)->ahw.pci_base1 +         \
 604             (off) - SECOND_PAGE_GROUP_START) :  \
 605                 ((((off) < THIRD_PAGE_GROUP_END) &&     \
 606             ((off) >= THIRD_PAGE_GROUP_START)) ?        \
 607             ((adapter)->ahw.pci_base2 + (off) - \
 608             THIRD_PAGE_GROUP_START) :           \
 609             0)))
 610 #define unm_nic_reg_write(_adp_, _off_, _val_)                  \
 611         {                                                       \
 612                 __uint32_t      _v1_ = (_val_);                 \
 613                 ((_adp_)->unm_nic_hw_write_wx((_adp_), (_off_), \
 614                     &_v1_, 4));                                 \
 615         }
 616
 617 #define unm_nic_reg_read(_adp_, _off_, _ptr_)                   \
 618         ((_adp_)->unm_nic_hw_read_wx((_adp_), (_off_), (_ptr_), 4))
 619
 620
 621 #define unm_nic_write_w0(_adp_, _idx_, _val_)                   \
 622         ((_adp_)->unm_nic_hw_write_wx((_adp_), (_idx_), &(_val_), 4))
 623
 624 #define unm_nic_read_w0(_adp_, _idx_, _val_)                    \
 625         ((_adp_)->unm_nic_hw_read_wx((_adp_), (_idx_), (_val_), 4))
 626
 627 /* Functions available from unm_nic_hw.c */
 628 int unm_nic_get_board_info(struct unm_adapter_s *adapter);
 629 void _unm_nic_write_crb(struct unm_adapter_s *adapter, uint32_t index,
 630                                 uint32_t value);
 631 void  unm_nic_write_crb(struct unm_adapter_s *adapter, uint32_t index,
 632                                 uint32_t value);
 633 void _unm_nic_read_crb(struct unm_adapter_s *adapter, uint32_t index,
 634                                 uint32_t *value);
 635 void  unm_nic_read_crb(struct unm_adapter_s *adapter, uint32_t index,
 636                                 uint32_t *value);
 637 // int   unm_nic_reg_read (unm_adapter *adapter, u64 off);
 638 int _unm_nic_hw_write(struct unm_adapter_s *adapter,
 639                                 u64 off, void *data, int len);
 640 int  unm_nic_hw_write(struct unm_adapter_s *adapter,
 641                                 u64 off, void *data, int len);
 642 int _unm_nic_hw_read(struct unm_adapter_s *adapter,
 643                                 u64 off, void *data, int len);
 644 int  unm_nic_hw_read(struct unm_adapter_s *adapter,
 645                                 u64 off, void *data, int len);
 646 void _unm_nic_hw_block_read(struct unm_adapter_s *adapter,
 647                                 u64 off, void *data, int num_words);
 648 void  unm_nic_hw_block_read(struct unm_adapter_s *adapter,
 649                                 u64 off, void *data, int num_words);
 650 void _unm_nic_hw_block_write(struct unm_adapter_s *adapter,
 651                                 u64 off, void *data, int num_words);
 652 void unm_nic_hw_block_write(struct unm_adapter_s *adapter,
 653                                 u64 off, void *data, int num_words);
 654 int  unm_nic_pci_mem_write(struct unm_adapter_s *adapter,
 655                                 u64 off, void *data, int size);
 656 void unm_nic_mem_block_read(struct unm_adapter_s *adapter, u64 off,
 657                                 void *data, int num_words);
 658 void unm_nic_mem_block_write(struct unm_adapter_s *adapter, u64 off,
 659                                 void *data, int num_words);
 660 int unm_nic_hw_read_ioctl(unm_adapter *adapter, u64 off, void *data, int len);
 661 int unm_nic_hw_write_ioctl(unm_adapter *adapter, u64 off, void *data, int len);
 662 int  unm_nic_macaddr_set(struct unm_adapter_s *, __uint8_t *addr);
 663 void unm_tcl_resetall(struct unm_adapter_s *adapter);
 664 void unm_tcl_phaninit(struct unm_adapter_s *adapter);
 665 void unm_tcl_postimage(struct unm_adapter_s *adapter);
 666 int unm_nic_set_mtu(struct unm_adapter_s *adapter, int new_mtu);
 667 long unm_nic_phy_read(unm_adapter *adapter, long reg, __uint32_t *);
 668 long unm_nic_init_port(struct unm_adapter_s *adapter);
 669 void unm_crb_write_adapter(unsigned long off, void *data,
 670                 struct unm_adapter_s *adapter);
 671 int unm_crb_read_adapter(unsigned long off, void *data,
 672                 struct unm_adapter_s *adapter);
 673 int unm_crb_read_val_adapter(unsigned long off,
 674                 struct unm_adapter_s *adapter);
 675 void unm_nic_stop_port(struct unm_adapter_s *adapter);
 676 int unm_nic_set_promisc_mode(struct unm_adapter_s *adapter);
 677 int unm_nic_unset_promisc_mode(struct unm_adapter_s *adapter);
 678
 679 /* unm_nic_hw.c */
 680 void unm_nic_pci_change_crbwindow_128M(unm_adapter *adapter, uint32_t wndw);
 681 int unm_crb_writelit_adapter_128M(struct unm_adapter_s *, unsigned long, int);
 682 int unm_nic_hw_write_wx_128M(unm_adapter *adapter, u64 off, void *data,
 683     int len);
 684 int unm_nic_hw_read_wx_128M(unm_adapter *adapter, u64 off, void *data, int len);
 685 int unm_nic_hw_write_ioctl_128M(unm_adapter *adapter, u64 off, void *data,
 686     int len);
 687 int unm_nic_hw_read_ioctl_128M(unm_adapter *adapter, u64 off, void *data,
 688     int len);
 689 int unm_nic_pci_mem_write_128M(struct unm_adapter_s *adapter, u64 off,
 690     void *data, int size);
 691 int unm_nic_pci_mem_read_128M(struct unm_adapter_s *adapter, u64 off,
 692     void *data, int size);
 693 void unm_nic_pci_write_normalize_128M(unm_adapter *adapter, u64 off, u32 data);
 694 u32 unm_nic_pci_read_normalize_128M(unm_adapter *adapter, u64 off);
 695 int unm_nic_pci_write_immediate_128M(unm_adapter *adapter, u64 off, u32 *data);
 696 int unm_nic_pci_read_immediate_128M(unm_adapter *adapter, u64 off, u32 *data);
 697 unsigned long long unm_nic_pci_set_window_128M(unm_adapter *adapter,
 698     unsigned long long addr);
 699 int unm_nic_clear_statistics_128M(struct unm_adapter_s *adapter);
 700 int unm_nic_fill_statistics_128M(struct unm_adapter_s *adapter,
 701     struct unm_statistics *unm_stats);
 702
 703 void unm_nic_pci_change_crbwindow_2M(unm_adapter *adapter, uint32_t wndw);
 704 int unm_crb_writelit_adapter_2M(struct unm_adapter_s *, unsigned long, int);
 705 int unm_nic_hw_write_wx_2M(unm_adapter *adapter, u64 off, void *data, int len);
 706 int unm_nic_pci_mem_write_2M(struct unm_adapter_s *adapter, u64 off,
 707     void *data, int size);
 708 int unm_nic_pci_mem_read_2M(struct unm_adapter_s *adapter, u64 off,
 709     void *data, int size);
 710 int unm_nic_hw_read_wx_2M(unm_adapter *adapter, u64 off, void *data, int len);
 711 void unm_nic_pci_write_normalize_2M(unm_adapter *adapter, u64 off, u32 data);
 712 u32 unm_nic_pci_read_normalize_2M(unm_adapter *adapter, u64 off);
 713 int unm_nic_pci_write_immediate_2M(unm_adapter *adapter, u64 off, u32 *data);
 714 int unm_nic_pci_read_immediate_2M(unm_adapter *adapter, u64 off, u32 *data);
 715 unsigned long long unm_nic_pci_set_window_2M(unm_adapter *adapter,
 716     unsigned long long addr);
 717 int unm_nic_clear_statistics_2M(struct unm_adapter_s *adapter);
 718 int unm_nic_fill_statistics_2M(struct unm_adapter_s *adapter,
 719     struct unm_statistics *unm_stats);
 720 void nx_p3_nic_set_multi(unm_adapter *adapter);
 721
 722 /* unm_nic_init.c */
 723 int phantom_init(struct unm_adapter_s *adapter, int first_time);
 724 int load_from_flash(struct unm_adapter_s *adapter);
 725 int  pinit_from_rom(unm_adapter *adapter, int verbose);
 726 int  rom_fast_read(struct unm_adapter_s *adapter, int addr, int *valp);
 727
 728 /* unm_nic_isr.c */
 729 void unm_nic_handle_phy_intr(unm_adapter *adapter);
 730
 731 /* niu.c */
 732 native_t unm_niu_set_promiscuous_mode(struct unm_adapter_s *adapter,
 733                 unm_niu_prom_mode_t mode);
 734 native_t unm_niu_xg_set_promiscuous_mode(struct unm_adapter_s *adapter,
 735                 unm_niu_prom_mode_t mode);
 736
 737 int unm_niu_xg_macaddr_set(struct unm_adapter_s *adapter,
 738                 unm_ethernet_macaddr_t addr);
 739 native_t unm_niu_disable_xg_port(struct unm_adapter_s *adapter);
 740
 741 long unm_niu_gbe_init_port(long port);
 742 native_t unm_niu_enable_gbe_port(struct unm_adapter_s *adapter);
 743 native_t unm_niu_disable_gbe_port(struct unm_adapter_s *adapter);
 744
 745 int unm_niu_macaddr_get(struct unm_adapter_s *adapter, unsigned char *addr);
 746 int unm_niu_macaddr_set(struct unm_adapter_s *adapter,
 747                 unm_ethernet_macaddr_t addr);
 748
 749 int unm_niu_xg_set_tx_flow_ctl(struct unm_adapter_s *adapter, int enable);
 750 int unm_niu_gbe_set_rx_flow_ctl(struct unm_adapter_s *adapter, int enable);
 751 int unm_niu_gbe_set_tx_flow_ctl(struct unm_adapter_s *adapter, int enable);
 752 long unm_niu_gbe_disable_phy_interrupts(struct unm_adapter_s *);
 753 long unm_niu_gbe_phy_read(struct unm_adapter_s *,
 754                 long reg, unm_crbword_t *readval);
 755
 756 /* unm_nic_ctx.c */
 757 int netxen_create_rxtx(struct unm_adapter_s *adapter);
 758 void netxen_destroy_rxtx(struct unm_adapter_s *adapter);
 759 int nx_fw_cmd_set_mtu(struct unm_adapter_s *adapter, int mtu);
 760
 761 /* unm_nic_main.c */
 762 int receive_peg_ready(struct unm_adapter_s *adapter);
 763 void unm_nic_update_cmd_producer(struct unm_adapter_s *adapter,
 764     uint32_t crb_producer);
 765 void unm_desc_dma_sync(ddi_dma_handle_t handle, uint_t start, uint_t count,
 766     uint_t range, uint_t unit_size, uint_t direction);
 767 int unm_pci_alloc_consistent(unm_adapter *, int, caddr_t *,
 768     ddi_dma_cookie_t *, ddi_dma_handle_t *, ddi_acc_handle_t *);
 769 void unm_pci_free_consistent(ddi_dma_handle_t *, ddi_acc_handle_t *);
 770
 771 /* unm_ndd.c */
 772 int unm_nd_init(unm_adapter *adapter);
 773 enum ioc_reply unm_nd_ioctl(unm_adapter *adapter, queue_t *wq,
 774                 mblk_t *mp, struct iocblk *iocp);
 775 void unm_nd_cleanup(unm_adapter *adapter);
 776
 777 /* unm_gem.c */
 778 void unm_destroy_intr(unm_adapter *adapter);
 779 void unm_free_dummy_dma(unm_adapter *adapter);
 780
 781 /*
 782  * (Internal) return values from ioctl subroutines
 783  */
 784 enum ioc_reply {
 785         IOC_INVAL = -1, /* bad, NAK with EINVAL */
 786         IOC_DONE, /* OK, reply sent  */
 787         IOC_ACK, /* OK, just send ACK  */
 788         IOC_REPLY, /* OK, just send reply */
 789         IOC_RESTART_ACK, /* OK, restart & ACK */
 790         IOC_RESTART_REPLY /* OK, restart & reply */
 791 };
 792
 793 /*
 794  * Shorthand for the NDD parameters
 795  */
 796 #define param_adv_autoneg       nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val
 797 #define param_adv_pause         nd_params[PARAM_ADV_PAUSE_CAP].ndp_val
 798 #define param_adv_asym_pause    nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val
 799 #define param_adv_10000fdx      nd_params[PARAM_ADV_10000FDX_CAP].ndp_val
 800 #define param_adv_1000fdx       nd_params[PARAM_ADV_1000FDX_CAP].ndp_val
 801 #define param_adv_1000hdx       nd_params[PARAM_ADV_1000HDX_CAP].ndp_val
 802 #define param_adv_100fdx        nd_params[PARAM_ADV_100FDX_CAP].ndp_val
 803 #define param_adv_100hdx        nd_params[PARAM_ADV_100HDX_CAP].ndp_val
 804 #define param_adv_10fdx         nd_params[PARAM_ADV_10FDX_CAP].ndp_val
 805 #define param_adv_10hdx         nd_params[PARAM_ADV_10HDX_CAP].ndp_val
 806 #define param_link_up           nd_params[PARAM_LINK_STATUS].ndp_val
 807 #define param_link_speed        nd_params[PARAM_LINK_SPEED].ndp_val
 808 #define param_link_duplex       nd_params[PARAM_LINK_DUPLEX].ndp_val
 809 #define param_loop_mode         nd_params[PARAM_LOOP_MODE].ndp_val
 810
 811 /*
 812  * Property lookups
 813  */
 814 #define UNM_PROP_EXISTS(d, n) \
 815         ddi_prop_exists(DDI_DEV_T_ANY, (d), DDI_PROP_DONTPASS, (n))
 816 #define UNM_PROP_GET_INT(d, n) \
 817         ddi_prop_get_int(DDI_DEV_T_ANY, (d), DDI_PROP_DONTPASS, (n), -1)
 818
 819 /*
 820  * Bit flags in the 'debug' word ...
 821  */
 822 #define UNM_DBG_TRACE   0x00000002 /* general flow tracing */
 823 #define UNM_DBG_NDD             0x20000000 /* NDD operations */
 824
 825 #define MBPS_10         10
 826 #define MBPS_100        100
 827 #define MBPS_1000       1000
 828
 829 #ifdef __cplusplus
 830 }
 831 #endif
 832
 833 #endif  /* !_UNM_NIC_ */