usr/src/uts/common/io/rtls/rtls.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21
  22 /*
  23  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 /*
  28  * Copyright 2012 Nexenta Systems, Inc.  All rights reserved.
  29  */
  30
  31 /*
  32  * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver.
  33  *
  34  * This product is covered by one or more of the following patents:
  35  * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and
  36  * US6,327,625.
  37  *
  38  * Currently supports:
  39  *      RTL8139
  40  */
  41
  42
  43 #ifndef _SYS_RTLS_H
  44 #define _SYS_RTLS_H
  45
  46 #ifdef __cplusplus
  47 extern "C" {
  48 #endif
  49
  50 /* Debug flags */
  51 #define RTLS_TRACE              0x01
  52 #define RTLS_ERRS               0x02
  53 #define RTLS_RECV               0x04
  54 #define RTLS_DDI                0x08
  55 #define RTLS_SEND               0x10
  56 #define RTLS_INT                0x20
  57 #define RTLS_SENSE              0x40
  58 #define RTLS_REGCFG             0x80
  59
  60 #ifdef DEBUG
  61 #define RTLS_DEBUG              1
  62 #endif
  63
  64 /*
  65  * Driver support device
  66  */
  67 #define RT_VENDOR_ID            0x10EC  /* RealTek */
  68 #define RT_DEVICE_8139          0x8139
  69 #define RTLS_SUPPORT_DEVICE_1   ((RT_VENDOR_ID << 16) | RT_DEVICE_8139)
  70         /* bind vendor and device id together */
  71
  72 #define RTLS_VENDOR_ID_2        0x1186  /* D-link */
  73 #define RTLS_DEVICE_ID_2        0x1301
  74 #define RTLS_SUPPORT_DEVICE_2   ((RTLS_VENDOR_ID_2 << 16) | RTLS_DEVICE_ID_2)
  75
  76 #define RTLS_VENDOR_ID_3        0x1113  /* Accton */
  77 #define RTLS_DEVICE_ID_3        0x1211
  78 #define RTLS_SUPPORT_DEVICE_3   ((RTLS_VENDOR_ID_3 << 16) | RTLS_DEVICE_ID_3)
  79
  80 #define RTLS_VENDOR_ID_4        0x1186  /* D-link */
  81 #define RTLS_DEVICE_ID_4        0x1300
  82 #define RTLS_SUPPORT_DEVICE_4   ((RTLS_VENDOR_ID_4 << 16) | RTLS_DEVICE_ID_4)
  83
  84 /*
  85  * Driver tx/rx parameters
  86  */
  87 #define RTLS_MAX_TX_DESC        4
  88 #define RTLS_TX_BUF_COUNT       8
  89 #define RTLS_TX_BUF_SIZE        2048
  90 #define RTLS_RX_BUF_RING        (32*1024)       /* 32K */
  91 #define RTLS_RX_BUF_SIZE        (RTLS_RX_BUF_RING + 2*1024)
  92 #define RTLS_MCAST_BUF_SIZE     64      /* multicast hash table size in bits */
  93
  94 /*
  95  * RTL8139 CRC poly
  96  */
  97 #define RTLS_HASH_POLY          0x04C11DB7      /* 0x04C11DB6 */
  98 #define RTLS_HASH_CRC           0xFFFFFFFFU
  99
 100 /*
 101  * STREAMS parameters
 102  */
 103 #define RTLS_HIWAT              (RTLS_MAX_TX_DESC * ETHERMAX)
 104                                         /* driver flow control high water */
 105 #define RTLS_LOWAT              1       /* driver flow control low water */
 106 #define RTLS_IDNUM              0       /* RTL Id; zero works */
 107
 108 /*
 109  * Helpful defines for register access
 110  */
 111 #define REG32(reg, off)         ((uint32_t *)((uintptr_t)(reg) + off))
 112 #define REG16(reg, off)         ((uint16_t *)((uintptr_t)(reg) + off))
 113 #define REG8(reg, off)          ((uint8_t *)((uintptr_t)(reg) + off))
 114
 115 typedef struct {
 116         ddi_acc_handle_t        acc_hdl;        /* handle for memory */
 117         void                    *mem_va;        /* CPU VA of memory */
 118         size_t                  alength;        /* allocated size */
 119         ddi_dma_handle_t        dma_hdl;        /* DMA handle */
 120         ddi_dma_cookie_t        cookie;         /* associated cookie */
 121         uint32_t                ncookies;       /* must be 1 */
 122 } dma_area_t;
 123
 124 typedef struct rtls_stats {
 125         uint64_t        ipackets;
 126         uint64_t        multi_rcv;      /* ifInMulticastPkts */
 127         uint64_t        brdcst_rcv;     /* ifInBroadcastPkts */
 128         uint64_t        rbytes;
 129         uint64_t        opackets;
 130         uint64_t        multi_xmt;
 131         uint64_t        brdcst_xmt;
 132         uint64_t        obytes;
 133         uint32_t        collisions;
 134         uint32_t        firstcol;
 135         uint32_t        multicol;
 136         uint32_t        rcv_err;        /* ifInErrors */
 137         uint32_t        xmt_err;        /* ifOutErrors */
 138         uint32_t        mac_rcv_err;
 139         uint32_t        mac_xmt_err;
 140         uint32_t        overflow;
 141         uint32_t        underflow;
 142         uint32_t        no_carrier;     /* dot3StatsCarrierSenseErrors */
 143         uint32_t        xmt_latecoll;   /* dot3StatsLateCollisions */
 144         uint32_t        defer;          /* dot3StatsDeferredTransmissions */
 145         uint32_t        frame_err;      /* dot3StatsAlignErrors */
 146         uint32_t        crc_err;        /* dot3StatsFCSErrors */
 147         uint32_t        in_short;
 148         uint32_t        too_long;
 149         uint32_t        no_rcvbuf;      /* ifInDiscards */
 150 } rtls_stats_t;
 151
 152 typedef struct rtls_instance {
 153         mac_handle_t    mh;
 154         mii_handle_t    mii;
 155         dev_info_t      *devinfo;       /* device instance */
 156         int32_t         instance;
 157
 158         caddr_t         io_reg;         /* mapped chip register address */
 159
 160
 161         /* io handle & iblock */
 162         ddi_acc_handle_t        io_handle;      /* ddi I/O handle */
 163         ddi_iblock_cookie_t     iblk;
 164
 165         /* dma buffer alloc used */
 166         dma_area_t              dma_area_rx;    /* receive dma area */
 167         dma_area_t              dma_area_tx[RTLS_MAX_TX_DESC];
 168                                                 /* transmit dma area */
 169
 170         uint8_t         netaddr[ETHERADDRL];    /* mac address */
 171         uint16_t        int_mask;               /* interrupt mask */
 172
 173         /* used for multicast set */
 174         char            multicast_cnt[RTLS_MCAST_BUF_SIZE];
 175         uint32_t        multi_hash[2];
 176
 177         boolean_t       promisc;                /* promisc state flag */
 178
 179         /* used for send */
 180         uint8_t         *tx_buf[RTLS_MAX_TX_DESC];
 181         uint16_t        tx_current_desc;        /* Current Tx page */
 182         uint16_t        tx_first_loop;
 183
 184         uint32_t        tx_retry;
 185
 186         /* used for recv */
 187         uint8_t         *rx_ring;
 188         uint32_t        cur_rx;
 189
 190         /* mutex */
 191         kmutex_t        rtls_io_lock;   /* i/o reg access */
 192         kmutex_t        rtls_tx_lock;   /* send access */
 193         kmutex_t        rtls_rx_lock;   /* receive access */
 194
 195         /* send reschedule used */
 196         boolean_t       need_sched;
 197
 198         boolean_t       chip_error;     /* chip error flag */
 199
 200         /* current MAC state */
 201         boolean_t       rtls_running;
 202         boolean_t       rtls_suspended;
 203
 204         /* rtls statistics */
 205         rtls_stats_t    stats;
 206 } rtls_t;
 207
 208 #define RTLS_TX_RETRY_NUM       16
 209 #define RTLS_TX_WAIT_TIMEOUT    (void) (drv_usectohz(100 * 1000)) /* 100ms */
 210 #define RTLS_RESET_WAIT_NUM     0x100
 211 #define RTLS_RESET_WAIT_INTERVAL        (void) (drv_usecwait(100))
 212 #define RTLS_RX_ADDR_ALIGNED(addr)      (((addr + 3) & ~3) % RTLS_RX_BUF_RING)
 213                 /* 4-bytes aligned, also with RTLS_RX_BUF_RING boundary */
 214
 215 /* parameter definition in rtls.conf file */
 216 #define FOECE_NONE              0       /* no force */
 217 #define FORCE_AUTO_NEGO         5       /* auto negotioation mode */
 218 #define FORCE_100_FDX           4       /* 100 full_duplex mode */
 219 #define FORCE_100_HDX           3       /* 100 half_duplex mode */
 220 #define FORCE_10_FDX            2       /* 10 full_duplex mode */
 221 #define FORCE_10_HDX            1       /* 10 half_duplex mode */
 222
 223 /*
 224  * RealTek 8129/8139 register offsets definition
 225  */
 226
 227 /*
 228  * MAC address register, initial value isautoloaded from the
 229  * EEPROM EthernetID field
 230  */
 231 #define ID_0_REG        0x0000
 232 #define ID_1_REG        0x0001
 233 #define ID_2_REG        0x0002
 234 #define ID_3_REG        0x0003
 235 #define ID_4_REG        0x0004
 236 #define ID_5_REG        0x0005
 237
 238 /*
 239  * Multicast register
 240  */
 241 #define MULTICAST_0_REG         0x0008
 242 #define MULTICAST_1_REG         0x0009
 243 #define MULTICAST_2_REG         0x000a
 244 #define MULTICAST_3_REG         0x000b
 245 #define MULTICAST_4_REG         0x000c
 246 #define MULTICAST_5_REG         0x000d
 247 #define MULTICAST_6_REG         0x000e
 248 #define MULTICAST_7_REG         0x000f
 249
 250 #define RCV_ALL_MULTI_PACKETS   0xffffffff
 251
 252 /*
 253  * Transmit status register
 254  */
 255 #define TX_STATUS_DESC0_REG     0x0010
 256 #define TX_STATUS_DESC1_REG     0x0014
 257 #define TX_STATUS_DESC2_REG     0x0018
 258 #define TX_STATUS_DESC3_REG     0x001c
 259 #define TX_STATUS_CS_LOST       0x80000000      /* Carrier Sense Lost */
 260 #define TX_STATUS_TX_ABORT      0x40000000      /* Transmit Abort */
 261 #define TX_STATUS_OWC           0x20000000      /* Out of Window Collision */
 262 #define TX_STATUS_CDH           0x10000000      /* CD Heart Beat */
 263 #define TX_STATUS_NCC           0x0f000000      /* Number of Collision Count */
 264 #define TX_STATUS_NCC_SHIFT     24
 265 #define TX_STATUS_TX_THRESHOLD  0x003f0000      /* Early Tx Threshold */
 266 #define TX_STATUS_TX_THRESHOLD_SHIFT    16
 267 #define TX_STATUS_TX_THRESHOLD_MAX      0x3f    /* 0x3f * 32 Bytes */
 268 #define TX_STATUS_TX_OK         0x00008000      /* Transmit OK */
 269 #define TX_STATUS_TX_UNDERRUN   0x00004000      /* Transmit FIFO Underrun */
 270 #define TX_STATUS_OWN           0x00002000      /* RTL8139 Own bit */
 271 #define TX_STATUS_PACKET_SIZE   0x00001fff
 272         /* The total size in bytes of the data in this descriptor */
 273
 274 /*
 275  * The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared
 276  * by the RTL8139 when the Transmit Byte Count (bit12-0) in the corresponding
 277  * Tx descriptor is written. If h/w transmit finish, at least some of these
 278  * bits are none zero.
 279  */
 280 #define TX_COMPLETE_FLAG        (TX_STATUS_TX_ABORT | TX_STATUS_TX_OK | \
 281                                     TX_STATUS_TX_UNDERRUN)
 282 #define TX_ERR_FLAG             (TX_STATUS_TX_ABORT | TX_STATUS_TX_UNDERRUN | \
 283                                     TX_STATUS_CS_LOST | TX_STATUS_OWC)
 284
 285 /*
 286  * Transmit start address of descriptors
 287  */
 288 #define TX_ADDR_DESC0_REG       0x0020
 289 #define TX_ADDR_DESC1_REG       0x0024
 290 #define TX_ADDR_DESC2_REG       0x0028
 291 #define TX_ADDR_DESC3_REG       0x002c
 292
 293 /*
 294  * Receive buffer start address
 295  */
 296 #define RX_BUFF_ADDR_REG        0x0030
 297
 298 /*
 299  * Early receive byte count register
 300  */
 301 #define RX_STATUS_REG           0x0036
 302 #define RX_STATUS_GOOD          0x08
 303 #define RX_STARUS_BAD           0x04
 304 #define RX_STATUS_COVERWRITE    0x02
 305 #define RX_STATUS_OK            0x01
 306
 307 /*
 308  * Commond register
 309  */
 310 #define RT_COMMAND_REG          0x0037
 311 #define RT_COMMAND_REG_RESERVE  0xe0
 312 #define RT_COMMAND_RESET        0x10
 313 #define RT_COMMAND_RX_ENABLE    0x08
 314 #define RT_COMMAND_TX_ENABLE    0x04
 315 #define RT_COMMAND_BUFF_EMPTY   0x01
 316
 317 /*
 318  * Rx current read address register
 319  */
 320 #define RX_CURRENT_READ_ADDR_REG        0x0038
 321 #define RX_READ_RESET_VAL               0xfff0
 322 /*
 323  * Value in RX_CURRENT_READ_ADDR_REG is 16 less than
 324  * the actual rx read address
 325  */
 326 #define READ_ADDR_GAP                   16
 327
 328 #define RX_CURRENT_BUFF_ADDR_REG        0x003a
 329
 330 /*
 331  * Interrupt register
 332  */
 333 #define RT_INT_MASK_REG         0x003c
 334 #define RT_INT_STATUS_REG       0x003e
 335 #define RT_INT_STATUS_INTS      0xe07f
 336 #define SYS_ERR_INT             0x8000
 337 #define TIME_OUT_INT            0x4000
 338 #define CABLE_LEN_CHANGE_INT    0x2000
 339 #define RX_FIFO_OVERFLOW_INT    0x0040
 340 #define LINK_CHANGE_INT         0x0020
 341 #define RX_BUF_OVERFLOW_INT     0x0010
 342 #define TX_ERR_INT              0x0008
 343 #define TX_OK_INT               0x0004
 344 #define RX_ERR_INT              0x0002
 345 #define RX_OK_INT               0x0001
 346
 347 #define RTLS_INT_MASK_ALL       0xe07f
 348 #define RTLS_INT_MASK_NONE      0x0000
 349 #define RTLS_RX_INT     (RX_OK_INT | RX_ERR_INT | \
 350                             RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT)
 351 #define RX_OVERFLOW_INT (RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT)
 352 #define RTLS_INT_MASK   (LINK_CHANGE_INT | TX_ERR_INT | TX_OK_INT | \
 353                             RX_BUF_OVERFLOW_INT | RX_FIFO_OVERFLOW_INT | \
 354                             RX_ERR_INT | RX_OK_INT)
 355
 356 /*
 357  * Transmit configuration register
 358  */
 359 #define TX_CONFIG_REG           0x0040
 360 #define TX_CONSIG_REG_RESERVE   0x8078f80e
 361 #define HW_VERSION_ID_5         0x7c000000
 362 #define TX_INTERFRAME_GAP_BITS  0x03000000
 363 #define TX_INTERFRAME_GAP_SHIFT 24
 364 #define TX_INTERFRAME_GAP_802_3 0x03000000
 365 #define HW_VERSION_ID_1         0x00800000
 366 #define LOOPBACK_MODE_ENABLE    0x00060000
 367 #define CRC_APPEND_ENABLE       0x00010000
 368 #define TX_DMA_BURST_BYTES      0x00000700
 369 #define TX_DMA_BURST_2048B      0x00000700
 370 #define TX_DMA_BURST_1024B      0x00000600
 371 #define TX_RETRY_COUNT_BITS     0x000000f0
 372 #define TX_RETRY_COUNT_DEFUALT  0x00000010
 373         /* re-transmit count (16 + 1 * 16) = 32 times before aborting */
 374 #define TX_CLEAR_ABORT          0x00000001
 375
 376 #define TX_CONFIG_DEFAULT       (TX_INTERFRAME_GAP_802_3 | \
 377                                     TX_DMA_BURST_1024B | \
 378                                     TX_RETRY_COUNT_DEFUALT)
 379 #define TX_FIFO_THRESHHOLD      1024
 380 /*
 381  * Receive configuration register
 382  */
 383 #define RX_CONFIG_REG           0x0044
 384 #define RX_CONSIG_REG_RESERVE   0xf0fc0000
 385
 386 #define RX_THRESHOLD_BITS       0x0f000000
 387 #define RX_EARLY_INT_SEL        0x00020000
 388 #define RX_RER8_ENABLE          0x00010000
 389
 390 #define RX_FIFO_THRESHOLD_BITS  0x0000e000
 391 #define RX_FIFO_THRESHOLD_16B   0x00000000
 392 #define RX_FIFO_THRESHOLD_32B   0x00002000
 393 #define RX_FIFO_THRESHOLD_64B   0x00004000
 394 #define RX_FIFO_THRESHOLD_128B  0x00006000
 395 #define RX_FIFO_THRESHOLD_256B  0x00008000
 396 #define RX_FIFO_THRESHOLD_512B  0x0000a000
 397 #define RX_FIFO_THRESHOLD_1024B 0x0000c000
 398 #define RX_FIFO_THRESHOLD_NONE  0x0000e000
 399
 400 #define RX_BUF_LEN_BITS         0x00001800
 401 #define RX_BUF_LEN_8K           0x00000000
 402 #define RX_BUF_LEN_16K          0x00000800
 403 #define RX_BUF_LEN_32K          0x00001000
 404 #define RX_BUF_LEN_64K          0x00001800
 405
 406 #define RX_DMA_BURST_BYTES      0x00000700
 407 #define RX_DMA_BURST_16B        0x00000000
 408 #define RX_DMA_BURST_32B        0x00000100
 409 #define RX_DMA_BURST_64B        0x00000200
 410 #define RX_DMA_BURST_128B       0x00000300
 411 #define RX_DMA_BURST_256B       0x00000400
 412 #define RX_DMA_BURST_512B       0x00000500
 413 #define RX_DMA_BURST_1024B      0x00000600
 414 #define RX_DMA_BURST_UNLIMITED  0x00000700
 415
 416 #define RX_NOWRAP_ENABLE        0x00000080
 417 #define RX_EEPROM_9356          0x00000040
 418 #define RX_ACCEPT_ERR_PACKET    0x00000020
 419 #define RX_ACCEPT_RUNT_PACKET   0x00000010
 420 #define RX_ACCEPT_BROADCAST_PACKET      0x000000008
 421 #define RX_ACCEPT_MULTICAST_PACKET      0x000000004
 422 #define RX_ACCEPT_MAC_MATCH_PACKET      0x000000002
 423 #define RX_ACCEPT_ALL_PACKET            0x000000001
 424
 425 #define RX_CONFIG_DEFAULT       (RX_FIFO_THRESHOLD_NONE | \
 426                                     RX_BUF_LEN_32K | \
 427                                     RX_DMA_BURST_1024B | \
 428                                     RX_ACCEPT_BROADCAST_PACKET | \
 429                                     RX_ACCEPT_MULTICAST_PACKET | \
 430                                     RX_ACCEPT_MAC_MATCH_PACKET)
 431 /*
 432  * Missed packet counter: indicates the number of packets
 433  * discarded due to rx FIFO overflow
 434  */
 435 #define RX_PACKET_MISS_COUNT_REG        0x004c
 436
 437 /*
 438  * 93c46(93c56) commond register:
 439  */
 440 #define RT_93c46_COMMAND_REG    0x0050
 441 #define RT_93c46_MODE_BITS      0xc0
 442 #define RT_93c46_MODE_NORMAL    0x00
 443 #define RT_93c46_MODE_AUTOLOAD  0x40
 444 #define RT_93c46_MODE_PROGRAM   0x80
 445 #define RT_93c46_MODE_CONFIG    0xc0
 446
 447 #define RT_93c46_EECS           0x08
 448 #define RT_93c46_EESK           0x04
 449 #define RT_93c46_EEDI           0x02
 450 #define RT_93c46_EEDO           0x01
 451
 452 /*
 453  * Configuration registers
 454  */
 455 #define RT_CONFIG_0_REG         0x0051
 456 #define RT_CONFIG_1_REG         0x0052
 457 #define RT_CONFIG_3_REG         0x0059
 458 #define RT_CONFIG_4_REG         0x005a
 459
 460 /*
 461  * Media status register
 462  */
 463 #define MEDIA_STATUS_REG        0x0058
 464 #define MEDIA_STATUS_LINK       0x04
 465 #define MEDIA_STATUS_SPEED      0x08
 466
 467 #define RTLS_SPEED_100M         100000000
 468 #define RTLS_SPEED_10M          10000000
 469 #define RTLS_SPEED_UNKNOWN      0
 470 /*
 471  * Multiple interrupt select register
 472  */
 473 #define RT_MUL_INTSEL_REG       0x005c
 474 #define RT_MUL_INTSEL_BITS      0x0fff
 475
 476 /*
 477  * Transmit status of all descriptor registers register
 478  */
 479 #define TX_DESC_STAUS_REG               0x0060
 480 #define TX_DESC_STAUS_OWN_0             0x0001
 481 #define TX_DESC_STAUS_ABORT_0           0x0010
 482 #define TX_DESC_STAUS_UNDERRUN_0        0x0100
 483 #define TX_DESC_STAUS_TXOK_0            0x1000
 484 #define TX_DESC_STAUS_OWN_1             0x0002
 485 #define TX_DESC_STAUS_ABORT_1           0x0020
 486 #define TX_DESC_STAUS_UNDERRUN_1        0x0200
 487 #define TX_DESC_STAUS_TXOK_1            0x2000
 488 #define TX_DESC_STAUS_OWN_2             0x0004
 489 #define TX_DESC_STAUS_ABORT_2           0x0040
 490 #define TX_DESC_STAUS_UNDERRUN_2        0x0400
 491 #define TX_DESC_STAUS_TXOK_2            0x4000
 492 #define TX_DESC_STAUS_OWN_3             0x0008
 493 #define TX_DESC_STAUS_ABORT_3           0x0080
 494 #define TX_DESC_STAUS_UNDERRUN_3        0x0800
 495 #define TX_DESC_STAUS_TXOK_3            0x8000
 496
 497 /*
 498  * Basic mode control register
 499  */
 500 #define BASIC_MODE_CONTROL_REG          0x0062
 501 #define BASIC_MODE_CONTROL_BITS         0x3300
 502
 503 #define BASIC_MODE_SPEED                0x2000
 504 #define BASIC_MODE_SPEED_100            0x2000
 505
 506 #define BASIC_MODE_AUTONEGO             0x1000
 507
 508 #define BASIC_MODE_RESTAR_AUTONEGO      0x0200
 509
 510 #define BASIC_MODE_DUPLEX               0x0100
 511 #define BASIC_MODE_DUPLEX_FULL          0x0100
 512
 513 /*
 514  * Basic mode status register
 515  */
 516 #define BASIC_MODE_STATUS_REG           0x0064
 517 #define BASIC_MODE_STATUS_AUTONEGO_DONE 0x0020
 518 #define BASIC_MODE_STATUS_REMOTE_FAULT  0x0010
 519
 520 /*
 521  * Auto-negotiation advertisement register
 522  */
 523 #define AUTO_NEGO_AD_REG                0x0066
 524 #define AUTO_NEGO_MODE_BITS             0x01e0
 525 #define AUTO_NEGO_100FULL               0x0100
 526 #define AUTO_NEGO_100HALF               0x0080
 527 #define AUTO_NEGO_10FULL                0x0040
 528 #define AUTO_NEGO_10HALF                0x0020
 529
 530 /*
 531  * Auto-negotiation link partner ability register
 532  */
 533 #define AUTO_NEGO_LP_REG                0x0068
 534
 535 /*
 536  * Auto-negotiation expansion register
 537  */
 538 #define AUTO_NEGO_EXP_REG               0x006a
 539 #define AUTO_NEGO_EXP_LPCANAN           0x0001
 540
 541 /*
 542  * Receive status in rx packet header
 543  */
 544 #define RX_HEADER_SIZE                  4
 545
 546 #define RX_HEADER_LEN_BITS              0xffff0000
 547 #define RX_HEADER_STATUS_BITS           0x0000ffff
 548 #define RX_STATUS_DMA_BUSY              0xfff0
 549 #define RX_HEADER_STATUS_MULTI          0x8000
 550 #define RX_HEADER_STATUS_PAM            0x4000
 551 #define RX_HEADER_STATUS_BCAST          0x2000
 552
 553 #define RX_HEADER_STATUS_ISE            0x0020
 554 #define RX_HEADER_STATUS_RUNT           0x0010
 555 #define RX_HEADER_STATUS_LONG           0x0008
 556 #define RX_HEADER_STATUS_CRC            0x0004
 557 #define RX_HEADER_STATUS_FAE            0x0002
 558 #define RX_HEADER_STATUS_ROK            0x0001
 559
 560 #define RX_ERR_FLAGS    (RX_HEADER_STATUS_ISE | RX_HEADER_STATUS_RUNT | \
 561                         RX_HEADER_STATUS_FAE | RX_HEADER_STATUS_CRC)
 562
 563 #ifdef __cplusplus
 564 }
 565 #endif
 566
 567 #endif  /* _SYS_RTLS_H */