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Merge remote-tracking branch 'origin/master'
[unleashed/lotheac.git] / usr / src / uts / common / io / skd / skd_s1120.h
blob9a020c382048550c6eb74368789fd4beb4ee3d62
1 /*
2 * This file and its contents are supplied under the terms of the
3 * Common Development and Distribution License ("CDDL"), version 1.0.
4 * You may only use this file in accordance with the terms of version
5 * 1.0 of the CDDL.
6 *
7 * A full copy of the text of the CDDL should have accompanied this
8 * source. A copy of the CDDL is also available via the Internet at
9 * http://www.illumos.org/license/CDDL.
10 */
11
12 /*
13 * Copyright 2013 STEC, Inc. All rights reserved.
14 */
15
16 #ifndef _SKD_S1120_H
17 #define _SKD_S1120_H
18
19 /*
20 * Q-channel, 64-bit r/w
21 */
22 #define FIT_Q_COMMAND 0x400u
23 #define FIT_QCMD_QID_MASK (0x3 << 1)
24 #define FIT_QCMD_QID0 (0x0 << 1)
25 #define FIT_QCMD_QID_NORMAL FIT_QCMD_QID0
26 #ifndef SKD_OMIT_FROM_SRC_DIST
27 #define FIT_QCMD_QID1 (0x1 << 1)
28 #define FIT_QCMD_QID2 (0x2 << 1)
29 #define FIT_QCMD_QID3 (0x3 << 1)
30 #endif /* SKD_OMIT_FROM_SRC_DIST */
31 #define FIT_QCMD_FLUSH_QUEUE (0ull) /* add QID */
32 #define FIT_QCMD_MSGSIZE_MASK (0x3 << 4)
33 #define FIT_QCMD_MSGSIZE_64 (0x0 << 4)
34 #define FIT_QCMD_MSGSIZE_128 (0x1 << 4)
35 #define FIT_QCMD_MSGSIZE_256 (0x2 << 4)
36 #define FIT_QCMD_MSGSIZE_512 (0x3 << 4)
37 #define FIT_QCMD_BASE_ADDRESS_MASK (0xFFFFFFFFFFFFFFC0ull)
38
39
40 /*
41 * Control, 32-bit r/w
42 */
43 #define FIT_CONTROL 0x500u
44 #ifndef SKD_OMIT_FROM_SRC_DIST
45 #define FIT_CR_HARD_RESET (1u << 0u)
46 #endif /* SKD_OMIT_FROM_SRC_DIST */
47 #define FIT_CR_SOFT_RESET (1u << 1u)
48 #ifndef SKD_OMIT_FROM_SRC_DIST
49 #define FIT_CR_DIS_TIMESTAMPS (1u << 6u)
50 #endif /* SKD_OMIT_FROM_SRC_DIST */
51 #define FIT_CR_ENABLE_INTERRUPTS (1u << 7u)
52
53 /*
54 * Status, 32-bit, r/o
55 */
56 #define FIT_STATUS 0x510u
57 #define FIT_SR_DRIVE_STATE_MASK 0x000000FFu
58 #ifndef SKD_OMIT_FROM_SRC_DIST
59 #define FIT_SR_SIGNATURE (0xFF << 8)
60 #define FIT_SR_PIO_DMA (1 << 16)
61 #endif /* SKD_OMIT_FROM_SRC_DIST */
62 #define FIT_SR_DRIVE_OFFLINE 0x00
63 #define FIT_SR_DRIVE_INIT 0x01
64 /* #define FIT_SR_DRIVE_READY 0x02 */
65 #define FIT_SR_DRIVE_ONLINE 0x03
66 #define FIT_SR_DRIVE_BUSY 0x04
67 #define FIT_SR_DRIVE_FAULT 0x05
68 #define FIT_SR_DRIVE_DEGRADED 0x06
69 #define FIT_SR_PCIE_LINK_DOWN 0x07
70 #define FIT_SR_DRIVE_SOFT_RESET 0x08
71 #define FIT_SR_DRIVE_INIT_FAULT 0x09
72 #define FIT_SR_DRIVE_BUSY_SANITIZE 0x0A
73 #define FIT_SR_DRIVE_BUSY_ERASE 0x0B
74 #define FIT_SR_DRIVE_FW_BOOTING 0x0C
75 #define FIT_SR_DRIVE_NEED_FW_DOWNLOAD 0xFE
76 #define FIT_SR_DEVICE_MISSING 0xFF
77 #define FIT_SR__RESERVED 0xFFFFFF00u
78
79 #ifndef SKD_OMIT_FROM_SRC_DIST
80 /*
81 * FIT_STATUS - Status register data definition
82 */
83 #define FIT_SR_STATE_MASK (0xFF << 0)
84 #define FIT_SR_SIGNATURE (0xFF << 8)
85 #define FIT_SR_PIO_DMA (1 << 16)
86 #endif /* SKD_OMIT_FROM_SRC_DIST */
87
88
89 /*
90 * Interrupt status, 32-bit r/w1c (w1c ==> write 1 to clear)
91 */
92 #define FIT_INT_STATUS_HOST 0x520u
93 #define FIT_ISH_FW_STATE_CHANGE (1u << 0u)
94 #define FIT_ISH_COMPLETION_POSTED (1u << 1u)
95 #define FIT_ISH_MSG_FROM_DEV (1u << 2u)
96 #define FIT_ISH_UNDEFINED_3 (1u << 3u)
97 #define FIT_ISH_UNDEFINED_4 (1u << 4u)
98 #define FIT_ISH_Q0_FULL (1u << 5u)
99 #define FIT_ISH_Q1_FULL (1u << 6u)
100 #define FIT_ISH_Q2_FULL (1u << 7u)
101 #define FIT_ISH_Q3_FULL (1u << 8u)
102 #define FIT_ISH_QCMD_FIFO_OVERRUN (1u << 9u)
103 #define FIT_ISH_BAD_EXP_ROM_READ (1u << 10u)
104
105
106 #define FIT_INT_DEF_MASK \
107 (FIT_ISH_FW_STATE_CHANGE | \
108 FIT_ISH_COMPLETION_POSTED | \
109 FIT_ISH_MSG_FROM_DEV | \
110 FIT_ISH_Q0_FULL | \
111 FIT_ISH_Q1_FULL | \
112 FIT_ISH_Q2_FULL | \
113 FIT_ISH_Q3_FULL | \
114 FIT_ISH_QCMD_FIFO_OVERRUN | \
115 FIT_ISH_BAD_EXP_ROM_READ)
116
117 #define FIT_INT_QUEUE_FULL \
118 (FIT_ISH_Q0_FULL | \
119 FIT_ISH_Q1_FULL | \
120 FIT_ISH_Q2_FULL | \
121 FIT_ISH_Q3_FULL)
122
123
124 #define MSI_MSG_NWL_ERROR_0 0x00000000
125 #define MSI_MSG_NWL_ERROR_1 0x00000001
126 #define MSI_MSG_NWL_ERROR_2 0x00000002
127 #define MSI_MSG_NWL_ERROR_3 0x00000003
128 #define MSI_MSG_STATE_CHANGE 0x00000004
129 #define MSI_MSG_COMPLETION_POSTED 0x00000005
130 #define MSI_MSG_MSG_FROM_DEV 0x00000006
131 #define MSI_MSG_RESERVED_0 0x00000007
132 #define MSI_MSG_RESERVED_1 0x00000008
133 #define MSI_MSG_QUEUE_0_FULL 0x00000009
134 #define MSI_MSG_QUEUE_1_FULL 0x0000000A
135 #define MSI_MSG_QUEUE_2_FULL 0x0000000B
136 #define MSI_MSG_QUEUE_3_FULL 0x0000000C
137
138
139
140 #define FIT_INT_RESERVED_MASK \
141 (FIT_ISH_UNDEFINED_3 | \
142 FIT_ISH_UNDEFINED_4)
143 /*
144 * Interrupt mask, 32-bit r/w
145 * Bit definitions are the same as FIT_INT_STATUS_HOST
146 */
147 #define FIT_INT_MASK_HOST 0x528u
148
149
150 /*
151 * Message to device, 32-bit r/w
152 */
153 #define FIT_MSG_TO_DEVICE 0x540u
154
155 /*
156 * Message from device, 32-bit, r/o
157 */
158 #define FIT_MSG_FROM_DEVICE 0x548u
159
160
161 /*
162 * 32-bit messages to/from device, composition/extraction macros
163 */
164 #define FIT_MXD_CONS(TYPE, PARAM, DATA) \
165 ((((TYPE) & 0xFFu) << 24u) | \
166 (((PARAM) & 0xFFu) << 16u) | \
167 (((DATA) & 0xFFFFu) << 0u))
168 #define FIT_MXD_TYPE(MXD) (((MXD) >> 24u) & 0xFFu)
169 #define FIT_MXD_PARAM(MXD) (((MXD) >> 16u) & 0xFFu)
170 #define FIT_MXD_DATA(MXD) (((MXD) >> 0u) & 0xFFFFu)
171
172
173 /*
174 * Types of messages to/from device
175 */
176 #define FIT_MTD_FITFW_INIT 0x01u
177 #define FIT_MTD_GET_CMDQ_DEPTH 0x02u
178 #define FIT_MTD_SET_COMPQ_DEPTH 0x03u
179 #define FIT_MTD_SET_COMPQ_ADDR 0x04u
180 #define FIT_MTD_ARM_QUEUE 0x05u
181 #define FIT_MTD_CMD_LOG_HOST_ID 0x07u
182 #define FIT_MTD_CMD_LOG_TIME_STAMP_LO 0x08u
183 #define FIT_MTD_CMD_LOG_TIME_STAMP_HI 0x09u
184 #define FIT_MFD_SMART_EXCEEDED 0x10u
185 #define FIT_MFD_POWER_DOWN 0x11u
186 #define FIT_MFD_OFFLINE 0x12u
187 #define FIT_MFD_ONLINE 0x13u
188 #define FIT_MFD_FW_RESTARTING 0x14u
189 #define FIT_MFD_PM_ACTIVE 0x15u
190 #define FIT_MFD_PM_STANDBY 0x16u
191 #define FIT_MFD_PM_SLEEP 0x17u
192 #define FIT_MFD_CMD_PROGRESS 0x18u
193
194 #ifndef SKD_OMIT_FROM_SRC_DIST
195 #define FIT_MTD_DEBUG 0xFEu
196 #define FIT_MFD_DEBUG 0xFFu
197 #endif /* SKD_OMIT_FROM_SRC_DIST */
198
199 #define FIT_MFD_MASK (0xFFu)
200 #define FIT_MFD_DATA_MASK (0xFFu)
201 #define FIT_MFD_MSG(x) (((x) >> 24) & FIT_MFD_MASK)
202 #define FIT_MFD_DATA(x) ((x) & FIT_MFD_MASK)
203
204
205 /*
206 * Extra arg to FIT_MSG_TO_DEVICE, 64-bit r/w
207 * Used to set completion queue address (FIT_MTD_SET_COMPQ_ADDR)
208 * (was Response buffer in docs)
209 */
210 #define FIT_MSG_TO_DEVICE_ARG 0x580u
211
212 /*
213 * Hardware (ASIC) version, 32-bit r/o
214 */
215 #define FIT_HW_VERSION 0x588u
216
217 /*
218 * Scatter/gather list descriptor.
219 * 32-bytes and must be aligned on a 32-byte boundary.
220 * All fields are in little endian order.
221 */
222 struct fit_sg_descriptor {
223 uint32_t control;
224 uint32_t byte_count;
225 uint64_t host_side_addr;
226 uint64_t dev_side_addr;
227 uint64_t next_desc_ptr;
228 };
229
230 #define FIT_SGD_CONTROL_NOT_LAST 0x000u
231 #define FIT_SGD_CONTROL_LAST 0x40Eu
232
233 /*
234 * Header at the beginning of a FIT message. The header
235 * is followed by SSDI requests each 64 bytes.
236 * A FIT message can be up to 512 bytes long and must start
237 * on a 64-byte boundary.
238 */
239 struct fit_msg_hdr {
240 uint8_t protocol_id;
241 uint8_t num_protocol_cmds_coalesced;
242 uint8_t _reserved1[6];
243 uint64_t _reserved2[7]; /* Forces alignment. */
244 };
245
246 #define FIT_PROTOCOL_ID_FIT 1
247 #define FIT_PROTOCOL_ID_SSDI 2
248 #define FIT_PROTOCOL_ID_SOFIT 3
249
250
251 #define FIT_PROTOCOL_MINOR_VER(mtd_val) ((mtd_val >> 16) & 0xF)
252 #define FIT_PROTOCOL_MAJOR_VER(mtd_val) ((mtd_val >> 20) & 0xF)
253
254 #ifndef SKD_OMIT_FROM_SRC_DIST
255 /*
256 * Format of a completion entry. The completion queue is circular
257 * and must have at least as many entries as the maximum number
258 * of commands that may be issued to the device.
259 *
260 * There are no head/tail pointers. The cycle value is used to
261 * infer the presence of new completion records.
262 * Initially the cycle in all entries is 0, the index is 0, and
263 * the cycle value to expect is 1. When completions are added
264 * their cycle values are set to 1. When the index wraps the
265 * cycle value to expect is incremented.
266 *
267 * Command_context is opaque and taken verbatim from the SSDI command.
268 * All other fields are big endian.
269 */
270 #endif /* SKD_OMIT_FROM_SRC_DIST */
271 #define FIT_PROTOCOL_VERSION_0 0
272
273 /*
274 * Protocol major version 1 completion entry.
275 * The major protocol version is found in bits
276 * 20-23 of the FIT_MTD_FITFW_INIT response.
277 */
278 struct fit_completion_entry_v1
279 {
280 uint32_t num_returned_bytes;
281 uint16_t tag;
282 uint8_t status; /* SCSI status */
283 uint8_t cycle;
284 };
285
286 #define FIT_PROTOCOL_VERSION_1 1
287 #define FIT_PROTOCOL_VERSION_CURRENT FIT_PROTOCOL_VERSION_1
288
289 struct fit_comp_error_info {
290 uint8_t type : 7; /* 00: Bits0-6 indicates the type of sense data. */
291 uint8_t valid : 1; /* 00: Bit 7 := 1 ==> info field is valid. */
292 uint8_t reserved0; /* 01: Obsolete field */
293 uint8_t key : 4; /* 02: Bits0-3 indicate the sense key. */
294 uint8_t reserved2 : 1; /* 02: Reserved bit. */
295 uint8_t bad_length : 1; /* 02: Incorrect Length Indicator */
296 uint8_t end_medium : 1; /* 02: End of Medium */
297 uint8_t file_mark : 1; /* 02: Filemark */
298 uint8_t info[4]; /* 03: */
299 uint8_t reserved1; /* 07: Additional Sense Length */
300 uint8_t cmd_spec[4]; /* 08: Command Specific Information */
301 uint8_t code; /* 0C: Additional Sense Code */
302 uint8_t qual; /* 0D: Additional Sense Code Qualifier */
303 uint8_t fruc; /* 0E: Field Replaceable Unit Code */
304 uint8_t sks_high : 7; /* 0F: Sense Key Specific (MSB) */
305 uint8_t sks_valid : 1; /* 0F: Sense Key Specific Valid */
306 uint16_t sks_low; /* 10: Sense Key Specific (LSW) */
307 uint16_t reserved3; /* 12: Part of additional sense bytes (unused) */
308 uint16_t uec; /* 14: Additional Sense Bytes */
309 uint64_t per; /* 16: Additional Sense Bytes */
310 uint8_t reserved4[2]; /* 1E: Additional Sense Bytes (unused) */
311 };
312
313
314 /* Task management constants */
315 #define SOFT_TASK_SIMPLE 0x00
316 #define SOFT_TASK_HEAD_OF_QUEUE 0x01
317 #define SOFT_TASK_ORDERED 0x02
318
319
320 /*
321 * Version zero has the last 32 bits reserved,
322 * Version one has the last 32 bits sg_list_len_bytes;
323 */
324 struct skd_command_header
325 {
326 uint64_t sg_list_dma_address;
327 uint16_t tag;
328 uint8_t attribute;
329 uint8_t add_cdb_len; /* In 32 bit words */
330 uint32_t sg_list_len_bytes;
331 };
332
333 struct skd_scsi_request
334 {
335 struct skd_command_header hdr;
336 unsigned char cdb[16];
337 };
338
339 struct driver_inquiry_data {
340 uint8_t peripheralDeviceType : 5;
341 uint8_t qualifier : 3;
342 uint8_t pageCode;
343 uint16_t pageLength;
344 uint16_t pcieBusNumber;
345 uint8_t pcieDeviceNumber;
346 uint8_t pcieFunctionNumber;
347 uint8_t pcieLinkSpeed;
348 uint8_t pcieLinkLanes;
349 uint16_t pcieVendorId;
350 uint16_t pcieDeviceId;
351 uint16_t pcieSubsystemVendorId;
352 uint16_t pcieSubsystemDeviceId;
353 uint8_t reserved1[2];
354 uint8_t reserved2[3];
355 uint8_t driverVersionLength;
356 uint8_t driverVersion[0x14];
357 };
358
359 #endif /* _SKD_S1120_H */