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[unleashed/lotheac.git] / usr / src / uts / common / io / upf / adm8511reg.h
blob71fd41eeb0dc1c74eacc807721cebccdb0a60f62
1 /*
2 * @(#)adm8511reg.h 1.1 09/06/20
3 * Register dehinitsions of ADMtek ADM8511 Fast Ethernet to USB controller.
4 * Codeded by Masayuki Murayama(KHF04453@nifty.ne.jp)
5 * This file is public domain.
6 */
8 #ifndef __ADM8511_H__
9 #define __ADM8511_H__
11 #define EC0 0x00 /* B */
12 #define EC1 0x01 /* B */
13 #define EC2 0x02 /* B */
14 #define MA 0x08 /* 8byte array */
15 #define EID 0x10 /* B */
16 #define PAUSETIMER 0x18 /* B pause timer */
17 #define RPNBFC 0x1a /* B */
18 #define ORFBFC 0x1b /* B */
19 #define EP1C 0x1c /* B */
20 #define RXFC 0x1d /* B */
21 #define BIST 0x1e /* B */
22 #define EEOFFSET 0x20 /* B */
23 #define EEDATA 0x21 /* W */
24 #define EECTRL 0x23 /* B */
25 #define PHYA 0x25 /* B */
26 #define PHYD 0x26 /* W */
27 #define PHYAC 0x28 /* B */
28 #define USBSTAT 0x2a /* B */
29 #define ETHTXSTAT 0x2b /* W */
30 #define ETHRXSTAT 0x2d /* B */
31 #define LOSTCNT 0x2e /* W */
32 #define WF0MASK 0x30 /* 16byte array */
33 #define WF0OFFSET 0x40 /* W */
34 #define WF0CRC 0x41 /* W */
35 #define WF1MASK 0x48 /* 16byte array */
36 #define WF1OFFSET 0x58 /* W */
37 #define WF1CRC 0x59 /* W */
38 #define WF2MASK 0x60 /* 16byte array */
39 #define WF2OFFSET 0x70 /* W */
40 #define WF2CRC 0x71 /* W */
41 #define WCTRL 0x78 /* B */
42 #define WSTAT 0x7a /* B */
43 #define IPHYC 0x7b /* B */
44 #define GPIO54 0x7c /* B */
45 #define GPIO10 0x7e /* B */
46 #define GPIO32 0x7f /* B */
47 #define TEST 0x80 /* B */
48 #define TM 0x81 /* B */
49 #define RPN 0x82 /* B */
51 /* Ethernet control register 0: offset 0 */
52 #define EC0_TXE 0x80U
53 #define EC0_RXE 0x40U
54 #define EC0_RXFCE 0x20U
55 #define EC0_WOE 0x10U
56 #define EC0_RXSA 0x08U
57 #define EC0_SBO 0x04U
58 #define EC0_RXMA 0x02U
59 #define EC0_RXCS 0x01U
61 #define EC0_BITS \
62 "\020" \
63 "\010TXE" \
64 "\007RXE" \
65 "\006RXFCE" \
66 "\005WOE" \
67 "\004RXSA" \
68 "\003SBO" \
69 "\002RXMA" \
70 "\001RXCS"
72 /* Ethernet control register 1: offset 1 */
73 #define EC1_FD 0x20U
74 #define EC1_100M 0x10U /* 0:10Mbps 1:100Mbps */
75 #define EC1_RM 0x08U /* reset mac */
77 #define EC1_BITS \
78 "\020" \
79 "\006FD" \
80 "\005100M" \
81 "\004RM"
83 /* Ethernet control register 2: offset 2 */
84 #define EC2_MEPL 0x80U /* 8515: MTU 0:1528, 1:1638 */
85 #define EC2_RPNC 0x40U
86 #define EC2_LEEPRS 0x20U
87 #define EC2_EEPRW 0x10U
88 #define EC2_LB 0x08U
89 #define EC2_PROM 0x04U
90 #define EC2_RXBP 0x02U
91 #define EC2_EP3RC 0x01U
93 #define EC2_BITS \
94 "\020" \
95 "\010MEPS" \
96 "\007RPNC" \
97 "\006LEEPRS" \
98 "\005EEPRW" \
99 "\004LB" \
100 "\003PROM" \
101 "\002RXBP" \
102 "\001EP3RC"
104 /* Recieve Packet number based Flow Control register: offset 0x1a */
105 #define RPNBFC_PN 0x7eU /* */
106 #define RPNBFC_PN_SHIFT 1
107 #define RPNBFC_FCP 0x01U /* enable rx flow control */
109 /* Occupied Recieve FIFO based Flow Control register: offset 0x1b */
110 #define ORFBFC_RXS 0x7eU /* */
111 #define ORFBFC_RXS_SHIFT 1
112 #define ORFBFC_RXS_UNIT 1024U
113 #define ORFBFC_FCRXS 0x01U /* enable rx flow control */
115 /* EP1 control register: offset 0x1c */
116 #define EP1C_EP1S0E 0x80U /* send 0 enable */
117 #define EP1C_ITMA 0x60U /* internal test mode A */
118 #define EP1C_ITMB 0x1fU /* internal test mode B */
120 #define EP1C_BITS \
121 "\020" \
122 "\010EP1S0E"
124 /* Rx FIFO Control register: offset 0x1d */
125 #define RXFC_EXT_SRAM 0x02 /* enable external 32k sram */
126 #define RXFC_RX32PKT 0x01 /* max 32 packet */
128 /* EEPROM offset register: offset 0x20 */
129 #define EEOFFSET_MASK 0x3f /* eeprom offset address in word */
131 /* EEPROM access control register: offset 0x23 */
132 #define EECTRL_DONE 0x04
133 #define EECTRL_RD 0x02
134 #define EECTRL_WR 0x01
136 #define EECTRL_BITS \
137 "\020" \
138 "\003DONE" \
139 "\002RD" \
140 "\001WR"
142 /* PHY control register: offset 28 */
143 #define PHYAC_DO 0x80U /* Done */
144 #define PHYAC_RDPHY 0x40U /* read phy */
145 #define PHYAC_WRPHY 0x20U /* write phy */
146 #define PHYAC_PHYRA 0x1fU /* PHY register address */
148 #define PHYCTRL_BITS \
149 "\020" \
150 "\010DO" \
151 "\007RDPHY" \
152 "\006WRPHY"
154 /* Internal PHY control register: offset 7b */
155 #define IPHYC_EPHY 0x02
156 #define IPHYC_PHYR 0x01
158 #define IPHYC_BITS \
159 "\020" \
160 "\002EPHY" \
161 "\001PHYR"
163 /* GPIO45 register: offset 7c */
164 #define GPIO54_5OE 0x20
165 #define GPIO54_5O 0x10
166 #define GPIO54_5I 0x08
167 #define GPIO54_4OE 0x04
168 #define GPIO54_4O 0x02
169 #define GPIO54_4I 0x01
171 /* GPIO01 register: offset 7e */
172 #define GPIO10_1OE 0x20
173 #define GPIO10_1O 0x10
174 #define GPIO10_1I 0x08
175 #define GPIO10_0OE 0x04
176 #define GPIO10_0O 0x02
177 #define GPIO10_0I 0x01
179 /* GPIO23 register: offset 7f */
180 #define GPIO32_3OE 0x20
181 #define GPIO32_3O 0x10
182 #define GPIO32_3I 0x08
183 #define GPIO32_2OE 0x04
184 #define GPIO32_2O 0x02
185 #define GPIO32_2I 0x01
187 /* rx status at the end of received packets */
188 /* byte 0 and 1 is packet length in little endian */
189 /* byte 2 is receive status */
190 #define RSR_DRIBBLE 0x10
191 #define RSR_CRC 0x08
192 #define RSR_RUNT 0x04
193 #define RSR_LONG 0x02
194 #define RSR_MULTI 0x01
196 #define RSR_ERRORS \
197 (RSR_DRIBBLE | RSR_CRC | RSR_RUNT | RSR_LONG | RSR_MULTI)
199 #define RSR_BITS \
200 "\020" \
201 "\005DRIBBLE" \
202 "\004CRC" \
203 "\003RUNT" \
204 "\002LONG" \
205 "\001MULTI"
206 /* byte 3 is reserved */
208 /* TEST register: offset 80 */
210 #endif /* __ADM8511_H__ */