usr/src/uts/common/io/urf/rtl8150reg.h

   1 /*
   2  * @(#)rtl8150reg.h     1.1 04/09/16
   3  * Macro definitions for Realtek 8150 USB to fast ethernet controller
   4  * based on Realtek RTL8150 data sheet
   5  * This file is public domain. Coded by M.Murayama (KHF04453@nifty.com)
   6  */
   7
   8 #ifndef __RTL8150REG_H__
   9 #define __RTL8150REG_H__
  10
  11 /*
  12  * Register offset
  13  */
  14 #define IDR     0x0120  /* Base of ID registers */
  15 #define MAR     0x0126  /* Base of multicast registers */
  16 #define CR      0x012e  /* Command register */
  17 #define TCR     0x012f  /* Transmit Configuration register */
  18 #define RCR     0x0130  /* Receive Configuration register */
  19 #define TSR     0x0132  /* Transmit Status register */
  20 #define RSR     0x0133  /* Receive Status register */
  21 #define CON0    0x0135  /* Configuration register 0 */
  22 #define CON1    0x0136  /* Configuration register 1 */
  23 #define MSR     0x0137  /* Media Status register */
  24 #define PHYADD  0x0138  /* PHY address register */
  25 #define PHYDAT  0x0139  /* PHY data register */
  26 #define PHYCNT  0x013b  /* PHY control register */
  27 #define GPPC    0x013d  /* General purpose pin control */
  28 #define WAKECNT 0x013e  /* Wake up event control */
  29 #define BMCR    0x0140  /* Basic Mode Control register */
  30 #define BMSR    0x0142  /* Basic Mode Status register */
  31 #define ANAR    0x0144  /* Auto Negotiation Advertisement register */
  32 #define ANLP    0x0146  /* Auto Negotiation Link Partner register */
  33 #define ANER    0x0148  /* Auto Negotiation Expansion register */
  34 #define NWAYT   0x014a  /* Nway test register */
  35 #define CSCR    0x014c  /* CS configuration register */
  36 #define CRC0    0x014e  /* Power management register for wakeup frame0 */
  37 #define CRC1    0x0150  /* Power management register for wakeup frame1 */
  38 #define CRC2    0x0152  /* Power management register for wakeup frame2 */
  39 #define CRC3    0x0154  /* Power management register for wakeup frame3 */
  40 #define CRC4    0x0156  /* Power management register for wakeup frame4 */
  41 #define BYTEMASK0 0x0158        /* Power management wakeup frame0 bytemask */
  42 #define BYTEMASK1 0x0160        /* Power management wakeup frame1 bytemask */
  43 #define BYTEMASK2 0x0168        /* Power management wakeup frame2 bytemask */
  44 #define BYTEMASK3 0x0170        /* Power management wakeup frame3 bytemask */
  45 #define BYTEMASK4 0x0178        /* Power management wakeup frame4 bytemask */
  46 #define PHY1    0x0180  /* PHY parameter 1 */
  47 #define PHY2    0x0184  /* PHY parameter 2 */
  48 #define TW1     0x0186  /* Twister parameter 1 */
  49
  50 /*
  51  * Bit field definitions
  52  */
  53 /* CR : Command register (uint8_t) */
  54 #define CR_WEPROM       0x20    /* EEPROM write enable */
  55 #define CR_SOFT_RST     0x10    /* Reset */
  56 #define CR_RE           0x08    /* Ethernet receive enable */
  57 #define CR_TE           0x04    /* Ethernet transmit enable */
  58 #define CR_EP3CLREN     0x02    /* clear performance counter after EP3 */
  59 #define CR_AUTOLOAD     0x01    /* autoload contents of 93c46 */
  60
  61 #define CR_BITS "\020\006WEPROM\005SOFT_RST\004RE\003TE\002EP3CLREN\001AUTOLOAD"
  62
  63 /* TCR: Transmit Configuration register */
  64 #define TCR_TXRR        0xc0    /* Tx retry count */
  65 #define TCR_TXRR_SHIFT          6
  66 #define TCR_IFG         0x18    /* Interframe Gap */
  67 #define TCR_IFG_SHIFT           3
  68 #define TCR_IFG_802_3           (3 << TCR_IFG_SHIFT)    /* 802.3 standard */
  69 #define TCR_NOCRC       0x01    /* Inhibit Appending CRC */
  70
  71 #define TCR_BITS        "\020\001NOCRC"
  72
  73 /* Receive Configuration register */
  74 #define RCR_TAIL        0x0080  /* Rx header forward to host in CRC field */
  75 #define RCR_AER         0x0040  /* Accept Error packet */
  76 #define RCR_AR          0x0020  /* Accept runt */
  77 #define RCR_AM          0x0010  /* Accept multicast */
  78 #define RCR_AB          0x0008  /* Accept broadcast */
  79 #define RCR_AD          0x0004  /* Accept physical match */
  80 #define RCR_AAM         0x0002  /* Accept all Multicast */
  81 #define RCR_AAP         0x0001  /* Accept all physical */
  82
  83 #define RCR_ACCEPT_MODE         \
  84         (RCR_AER | RCR_AR | RCR_AM | RCR_AB | RCR_AD | RCR_AAM | RCR_AAP)
  85
  86 #define RCR_BITS        \
  87         "\020\010TAIL\007AER\006AR\005AM\004AB\003AD\002AAM\001AAP"
  88
  89 /* Transmit Status register */
  90
  91 #define TSR_ECOL        0x20    /* excessive collision indication */
  92 #define TSR_LCOL        0x10    /* late collision indication */
  93 #define TSR_LOSS_CRS    0x08    /* lost of carrier indication */
  94 #define TSR_JBR         0x04    /* jabber time out indication */
  95 #define TSR_BUF_EMPTY   0x02    /* Tx buffer is empty */
  96 #define TSR_BUF_FULL    0x01    /* Tx buffer is full */
  97
  98 #define TSR_BITS        \
  99         "\020"          \
 100         "\006ECOL"      \
 101         "\005LCOL"      \
 102         "\004LOSS_CRS"  \
 103         "\003JBR"       \
 104         "\002BUF_EMPTY" \
 105         "\001BUF_FULL"
 106
 107 /* Receive status register in Rx packet field */
 108 #define RSR_WEVENT      0x80    /* Wakeup event indication */
 109 #define RSR_RX_BUF_FULL 0x40    /* Receive buffer full indication */
 110 #define RSR_LKCHG       0x20    /* Link change indication */
 111 #define RSR_RUNT        0x10    /* short packet indication */
 112 #define RSR_LONG        0x08    /* Long packet indication */
 113 #define RSR_CRC         0x04    /* CRC error indication */
 114 #define RSR_FAE         0x02    /* Frame alignment error */
 115 #define RSR_ROK         0x01    /* Receive OK indication */
 116
 117 #define RSR_ERRS        (RSR_RUNT | RSR_LONG | RSR_CRC | RSR_FAE)
 118 #define RSR_BITS        \
 119         "\020"          \
 120         "\010WEVENT"    \
 121         "\007RX_BUF_FULL"       \
 122         "\006LKCHG"     \
 123         "\005RUNT"      \
 124         "\004LONG"      \
 125         "\003CRC"       \
 126         "\002FAE"       \
 127         "\001ROK"
 128
 129 /* Config 0 */
 130
 131 #define CON0_SUSLED     0x80
 132 #define CON0_PARM_EN    0x40    /* parameter enable */
 133 #define CON0_LDPS       0x08
 134 #define CON0_MSEL       0x04    /* media select 1:MII, 0:auto */
 135 #define CON0_LEDS       0x03    /* LED pattern */
 136
 137 /* Config 1 */
 138 #define CON0_BWF        0x40    /* Broadcast wakeup function 1:on 0:off */
 139 #define CON0_MWF        0x20    /* Multicast wakeup function 1:on 0:off */
 140 #define CON0_UWF        0x10    /* Unicast wakeup function 1:on 0:off */
 141 #define CON0_LONGWF1    0x02    /* */
 142 #define CON0_LONGWF0    0x01    /* */
 143
 144
 145 /* MSR : Media Status register */
 146 #define MSR_TXFCE       0x80    /* Tx Flow control enable */
 147 #define MSR_RXFCE       0x40    /* Rx Flow control enable */
 148 #define MSR_DUPLEX      0x10    /* full duplex */
 149 #define MSR_SPEED_100   0x08    /* 100Mbps mode */
 150 #define MSR_LINK        0x04    /* link status */
 151 #define MSR_TXPF        0x02    /* 8150 sends pause packet */
 152 #define MSR_RXPF        0x01    /* 8150 is in backoff state */
 153
 154 #define MSR_BITS        \
 155         "\020"          \
 156         "\010TXFCE"     \
 157         "\007RXFCE"     \
 158         "\005DUPLEX"    \
 159         "\004SPEED_100" \
 160         "\003LINK"      \
 161         "\002TXPF"      \
 162         "\001RXPF"
 163
 164 /* MII PHY Address */
 165 #define PHYADD_MASK     0x1f
 166
 167 /* MII PHY Data */
 168 #define PHYCNT_OWN      0x40    /* 8150 owns:1 not owns:0 */
 169 #define PHYCNT_RWCR     0x20    /* write:1 read:0 */
 170 #define PHYCNT_PHYOFF   0x1f
 171
 172 /* BMCR (almost same with MII_CONTROL register) */
 173 #define BMCR_RESET      0x8000  /* PHY reset */
 174 #define BMCR_Spd_Set    0x2000  /* 100Mbps */
 175 #define BMCR_ANE        0x1000  /* auto negotiation enable */
 176 #define BMCR_RSA        0x0200  /* restart auto negotiation */
 177 #define BMCR_duplex     0x0100  /* 100Mbps */
 178
 179 /* Basic mode status register */
 180 /* Auto-negotiation Advertisement register */
 181 /* Auto-negotiation Link Partner Ability register */
 182 /* Auto-negotiation Expansion register */
 183
 184 /* Nway test register */
 185 #define NWAYT_NWLPBK    0x0080
 186 #define NWAYT_ENNWLE    0x0008
 187 #define NWAYT_FLAGABD   0x0004
 188 #define NWAYT_FLAGPDF   0x0002
 189 #define NWAYT_FLAGLSC   0x0001
 190
 191 /* CS configuration register */
 192 #define CS_TESTFUN      0x8000  /* */
 193 #define CS_LD           0x0200  /* */
 194 #define CS_HEARTBEAT    0x0100  /* */
 195 #define CS_JBEN         0x0080  /* */
 196 #define CS_F_LINK100    0x0040  /* */
 197 #define CS_F_CONNECT    0x0020  /* */
 198 #define CS_CON_STATUS   0x0008  /* */
 199 #define CS_CON_STATUS_EN 0x0004 /* */
 200 #define CS_PASS_SCR     0x0001  /* bypass scramble function */
 201
 202 /*
 203  * header format of rx packet
 204  */
 205 #define RXHD_MULT       0x8000  /* multicast packet */
 206 #define RXHD_PHYS       0x4000  /* physical match packet */
 207 #define RXHD_RUNT       0x2000  /* too short */
 208 #define RXHD_VALID      0x1000  /* packet is ok */
 209 #define RXHD_BYTECNT    0x0fff  /* rx byte count */
 210
 211 #define RXHD_BITS       \
 212         "\020"          \
 213         "\020MULT"      \
 214         "\017PHYS"      \
 215         "\016RUNT"      \
 216         "\015VALID"
 217 /*
 218  * Offset to EPROM contents
 219  */
 220 #define URF_EEPROM_BASE         0x1200
 221 #define EPROM_EthernetID        0x0002
 222
 223 #endif /* __RTL8150REG_H__ */