usr/src/uts/intel/io/drm/radeon_irq.c

   1
   2 /*
   3  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
   4  * Use is subject to license terms.
   5  * Copyright (c) 2016 by Delphix. All rights reserved.
   6  */
   7 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
   8 /*
   9  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
  10  *
  11  * The Weather Channel (TM) funded Tungsten Graphics to develop the
  12  * initial release of the Radeon 8500 driver under the XFree86 license.
  13  * This notice must be preserved.
  14  *
  15  * Permission is hereby granted, free of charge, to any person obtaining a
  16  * copy of this software and associated documentation files (the "Software"),
  17  * to deal in the Software without restriction, including without limitation
  18  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  19  * and/or sell copies of the Software, and to permit persons to whom the
  20  * Software is furnished to do so, subject to the following conditions:
  21  *
  22  * The above copyright notice and this permission notice (including the next
  23  * paragraph) shall be included in all copies or substantial portions of the
  24  * Software.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  27  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  28  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  29  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  30  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  31  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  32  * DEALINGS IN THE SOFTWARE.
  33  *
  34  * Authors:
  35  *    Keith Whitwell <keith@tungstengraphics.com>
  36  *    Michel D�zer <michel@daenzer.net>
  37  */
  38
  39 #include "drmP.h"
  40 #include "radeon_drm.h"
  41 #include "radeon_drv.h"
  42 #include "radeon_io32.h"
  43
  44 static inline u32
  45 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 mask)
  46 {
  47         uint32_t irqs = RADEON_READ(RADEON_GEN_INT_STATUS) & mask;
  48         if (irqs)
  49                 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
  50         return (irqs);
  51 }
  52
  53 /*
  54  * Interrupts - Used for device synchronization and flushing in the
  55  * following circumstances:
  56  *
  57  * - Exclusive FB access with hw idle:
  58  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
  59  *
  60  * - Frame throttling, NV_fence:
  61  *    - Drop marker irq's into command stream ahead of time.
  62  *    - Wait on irq's with lock *not held*
  63  *    - Check each for termination condition
  64  *
  65  * - Internally in cp_getbuffer, etc:
  66  *    - as above, but wait with lock held???
  67  *
  68  * NOTE: These functions are misleadingly named -- the irq's aren't
  69  * tied to dma at all, this is just a hangover from dri prehistory.
  70  */
  71
  72 irqreturn_t
  73 radeon_driver_irq_handler(DRM_IRQ_ARGS)
  74 {
  75         drm_device_t *dev = (drm_device_t *)(uintptr_t)arg;
  76         drm_radeon_private_t *dev_priv =
  77             (drm_radeon_private_t *)dev->dev_private;
  78         u32 stat;
  79
  80         /*
  81          * Only consider the bits we're interested in - others could be used
  82          * outside the DRM
  83          */
  84         stat = radeon_acknowledge_irqs(dev_priv, (RADEON_SW_INT_TEST_ACK |
  85             RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT));
  86         if (!stat)
  87                 return (IRQ_NONE);
  88
  89         stat &= dev_priv->irq_enable_reg;
  90
  91         /* SW interrupt */
  92         if (stat & RADEON_SW_INT_TEST) {
  93                 DRM_WAKEUP(&dev_priv->swi_queue);
  94         }
  95
  96         /* VBLANK interrupt */
  97         if (stat & (RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT)) {
  98                 int vblank_crtc = dev_priv->vblank_crtc;
  99
 100                 if ((vblank_crtc &
 101                     (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) ==
 102                     (DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 103                         if (stat & RADEON_CRTC_VBLANK_STAT)
 104                                 atomic_inc(&dev->vbl_received);
 105                         if (stat & RADEON_CRTC2_VBLANK_STAT)
 106                                 atomic_inc(&dev->vbl_received2);
 107                 } else if (((stat & RADEON_CRTC_VBLANK_STAT) &&
 108                     (vblank_crtc & DRM_RADEON_VBLANK_CRTC1)) ||
 109                     ((stat & RADEON_CRTC2_VBLANK_STAT) &&
 110                     (vblank_crtc & DRM_RADEON_VBLANK_CRTC2)))
 111                         atomic_inc(&dev->vbl_received);
 112
 113                 DRM_WAKEUP(&dev->vbl_queue);
 114                 drm_vbl_send_signals(dev);
 115         }
 116
 117         return (IRQ_HANDLED);
 118 }
 119
 120 static int radeon_emit_irq(drm_device_t *dev)
 121 {
 122         drm_radeon_private_t *dev_priv = dev->dev_private;
 123         unsigned int ret;
 124         RING_LOCALS;
 125
 126         atomic_inc(&dev_priv->swi_emitted);
 127         ret = atomic_read(&dev_priv->swi_emitted);
 128
 129         BEGIN_RING(4);
 130         OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
 131         OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
 132         ADVANCE_RING();
 133         COMMIT_RING();
 134
 135         return (ret);
 136 }
 137
 138 static int radeon_wait_irq(drm_device_t *dev, int swi_nr)
 139 {
 140         drm_radeon_private_t *dev_priv =
 141             (drm_radeon_private_t *)dev->dev_private;
 142         int ret = 0;
 143
 144         if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
 145                 return (0);
 146
 147         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 148
 149         DRM_WAIT_ON(ret, &dev_priv->swi_queue, 3 * DRM_HZ,
 150             RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
 151
 152         return (ret);
 153 }
 154
 155 static int radeon_driver_vblank_do_wait(struct drm_device *dev,
 156                                         unsigned int *sequence, int crtc)
 157 {
 158         drm_radeon_private_t *dev_priv =
 159             (drm_radeon_private_t *)dev->dev_private;
 160         unsigned int cur_vblank;
 161         int ret = 0;
 162         atomic_t *counter;
 163         if (!dev_priv) {
 164                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 165                 return (EINVAL);
 166         }
 167
 168         /*
 169          * I don't know why reset Intr Status Register here,
 170          * it might miss intr. So, I remove the code which
 171          * exists in open source, and changes as follows:
 172          */
 173
 174         if (crtc == DRM_RADEON_VBLANK_CRTC1) {
 175                 counter = &dev->vbl_received;
 176         } else if (crtc == DRM_RADEON_VBLANK_CRTC2) {
 177                 counter = &dev->vbl_received2;
 178         } else
 179                 return (EINVAL);
 180
 181         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 182
 183         /*
 184          * Assume that the user has missed the current sequence number
 185          * by about a day rather than wanting to wait for years
 186          * using vertical blanks...
 187          */
 188         DRM_WAIT_ON(ret, &dev->vbl_queue, 3 * DRM_HZ,
 189             (((cur_vblank = atomic_read(counter)) - *sequence) <= (1 << 23)));
 190
 191         *sequence = cur_vblank;
 192
 193         return (ret);
 194 }
 195
 196 int
 197 radeon_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
 198 {
 199         return (radeon_driver_vblank_do_wait(dev, sequence,
 200             DRM_RADEON_VBLANK_CRTC1));
 201 }
 202
 203 int
 204 radeon_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
 205 {
 206         return (radeon_driver_vblank_do_wait(dev, sequence,
 207             DRM_RADEON_VBLANK_CRTC2));
 208 }
 209
 210 /*
 211  * Needs the lock as it touches the ring.
 212  */
 213 /*ARGSUSED*/
 214 int
 215 radeon_irq_emit(DRM_IOCTL_ARGS)
 216 {
 217         DRM_DEVICE;
 218         drm_radeon_private_t *dev_priv = dev->dev_private;
 219         drm_radeon_irq_emit_t emit;
 220         int result;
 221
 222         LOCK_TEST_WITH_RETURN(dev, fpriv);
 223
 224         if (!dev_priv) {
 225                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 226                 return (EINVAL);
 227         }
 228
 229 #ifdef _MULTI_DATAMODEL
 230         if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
 231                 drm_radeon_irq_emit_32_t emit32;
 232
 233                 DRM_COPYFROM_WITH_RETURN(&emit32, (void *) data,
 234                     sizeof (emit32));
 235                 emit.irq_seq = (void *)(uintptr_t)(emit32.irq_seq);
 236         } else {
 237 #endif
 238
 239                 DRM_COPYFROM_WITH_RETURN(&emit, (void *) data, sizeof (emit));
 240 #ifdef _MULTI_DATAMODEL
 241 }
 242 #endif
 243
 244         result = radeon_emit_irq(dev);
 245
 246         if (DRM_COPY_TO_USER(emit.irq_seq, &result, sizeof (int))) {
 247                 DRM_ERROR("copy_to_user\n");
 248                 return (EFAULT);
 249         }
 250
 251         return (0);
 252 }
 253
 254 /*
 255  * Doesn't need the hardware lock.
 256  */
 257 /*ARGSUSED*/
 258 int
 259 radeon_irq_wait(DRM_IOCTL_ARGS)
 260 {
 261         DRM_DEVICE;
 262         drm_radeon_private_t *dev_priv = dev->dev_private;
 263         drm_radeon_irq_wait_t irqwait;
 264
 265         if (!dev_priv) {
 266                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
 267                 return (EINVAL);
 268         }
 269
 270         DRM_COPYFROM_WITH_RETURN(&irqwait, (void *) data, sizeof (irqwait));
 271
 272         return (radeon_wait_irq(dev, irqwait.irq_seq));
 273 }
 274
 275 static void radeon_enable_interrupt(struct drm_device *dev)
 276 {
 277         drm_radeon_private_t *dev_priv;
 278
 279         dev_priv = (drm_radeon_private_t *)dev->dev_private;
 280         dev_priv->irq_enable_reg = RADEON_SW_INT_ENABLE;
 281
 282         if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC1) {
 283                 dev_priv->irq_enable_reg |= RADEON_CRTC_VBLANK_MASK;
 284         }
 285
 286         if (dev_priv->vblank_crtc & DRM_RADEON_VBLANK_CRTC2) {
 287                 dev_priv->irq_enable_reg |= RADEON_CRTC2_VBLANK_MASK;
 288         }
 289
 290         RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
 291         dev_priv->irq_enabled = 1;
 292 }
 293
 294
 295 /*
 296  * drm_dma.h hooks
 297  */
 298 int
 299 radeon_driver_irq_preinstall(drm_device_t *dev)
 300 {
 301         drm_radeon_private_t *dev_priv =
 302             (drm_radeon_private_t *)dev->dev_private;
 303
 304         if (!dev_priv->mmio)
 305                 return (EINVAL);
 306
 307         /* Disable *all* interrupts */
 308         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 309
 310         /* Clear bits if they're already high */
 311         (void) radeon_acknowledge_irqs(dev_priv,
 312             (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT |
 313             RADEON_CRTC2_VBLANK_STAT));
 314
 315         return (0);
 316 }
 317
 318 void
 319 radeon_driver_irq_postinstall(drm_device_t *dev)
 320 {
 321         drm_radeon_private_t *dev_priv =
 322             (drm_radeon_private_t *)dev->dev_private;
 323
 324         atomic_set(&dev_priv->swi_emitted, 0);
 325         DRM_INIT_WAITQUEUE(&dev_priv->swi_queue, DRM_INTR_PRI(dev));
 326
 327         radeon_enable_interrupt(dev);
 328 }
 329
 330 void
 331 radeon_driver_irq_uninstall(drm_device_t *dev)
 332 {
 333         drm_radeon_private_t *dev_priv =
 334             (drm_radeon_private_t *)dev->dev_private;
 335         if (!dev_priv)
 336                 return;
 337
 338         /* Disable *all* interrupts */
 339         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
 340         DRM_FINI_WAITQUEUE(&dev_priv->swi_queue);
 341 }
 342
 343 int
 344 radeon_vblank_crtc_get(drm_device_t *dev)
 345 {
 346         drm_radeon_private_t *dev_priv;
 347         u32 flag;
 348         u32 value;
 349
 350         dev_priv = (drm_radeon_private_t *)dev->dev_private;
 351         flag = RADEON_READ(RADEON_GEN_INT_CNTL);
 352         value = 0;
 353
 354         if (flag & RADEON_CRTC_VBLANK_MASK)
 355                 value |= DRM_RADEON_VBLANK_CRTC1;
 356
 357         if (flag & RADEON_CRTC2_VBLANK_MASK)
 358                 value |= DRM_RADEON_VBLANK_CRTC2;
 359         return (value);
 360 }
 361
 362 int
 363 radeon_vblank_crtc_set(drm_device_t *dev, int64_t value)
 364 {
 365         drm_radeon_private_t *dev_priv;
 366
 367         dev_priv = (drm_radeon_private_t *)dev->dev_private;
 368         if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
 369                 DRM_ERROR("called with invalid crtc 0x%x\n",
 370                     (unsigned int)value);
 371                 return (EINVAL);
 372         }
 373         dev_priv->vblank_crtc = (unsigned int)value;
 374         radeon_enable_interrupt(dev);
 375         return (0);
 376 }