8354 sync regcomp(3C) with upstream (fix make catalog)
[unleashed/tickless.git] / usr / src / uts / sun4u / serengeti / sys / sbdp_mem.h
blobc84e84d2428c52a8ebcb0aafd6f690d504a90c0a
1 /*
2 * CDDL HEADER START
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
19 * CDDL HEADER END
23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
27 #ifndef _SBDP_MEM_H
28 #define _SBDP_MEM_H
30 #pragma ident "%Z%%M% %I% %E% SMI"
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
36 #include <sys/sbd.h>
37 #include <sys/sbdp_priv.h>
39 #define SBDP_MAX_MCS_PER_NODE 4
40 #define SBDP_MAX_MEM_NODES_PER_BOARD 4
41 #define SBDP_MAX_CORES_PER_CMP 2
43 typedef uint64_t mc_dc_regs_t[SBDP_MAX_MCS_PER_NODE];
45 typedef struct {
46 int board;
47 pnode_t *nodes;
48 int nmem;
49 } mem_op_t;
51 typedef struct {
52 uint_t regspec_addr_hi;
53 uint_t regspec_addr_lo;
54 uint_t regspec_size_hi;
55 uint_t regspec_size_lo;
56 } mc_regspace;
58 typedef struct {
59 uint64_t mc_decode[SBDP_MAX_MCS_PER_NODE];
60 uint64_t mc_memctl;
61 } mc_regs_t;
64 * Memory controller register offsets
66 #define SG_MEM_TIMING1_CTL 0x400000
67 #define SG_MEM_TIMING2_CTL 0x400008
68 #define SG_MEM_TIMING3_CTL 0x400038
69 #define SG_MEM_TIMING4_CTL 0x400040
70 #define SG_MEM_DECODE0_ADR 0x400028
71 #define SG_MEM_DECODE1_ADR 0x400010
72 #define SG_MEM_DECODE2_ADR 0x400018
73 #define SG_MEM_DECODE3_ADR 0x400020
74 #define SG_MEM_CONTROL_ADR 0x400030
75 #define SG_EMU_ACTIVITY_STATUS 0x400050
78 * Bit fields for the decode registers
80 #define SG_DECODE_VALID 0x8000000000000000ull
81 #define SG_DECODE_UK 0x001ffe0000000000ull
82 #define SG_DECODE_UM 0x000001fffff00000ull
83 #define SG_DECODE_LK 0x00000000000fc000ull
84 #define SG_DECODE_LM 0x0000000000003f00ull
85 #define SG_INVAL_UM 0x0000000ffff00000ull
86 #define SG_SLICE_INFO 0x000001fc00000000ull
87 #define SG_ALIGNMENT 0x800000000ULL
91 * Memory Macros
93 #define MC_MEMDEC0(mc_addr) \
94 (mc_addr) | SG_MEM_DECODE0_ADR
95 #define MC_MEMDEC1(mc_addr) \
96 (mc_addr) | SG_MEM_DECODE1_ADR
97 #define MC_MEMDEC2(mc_addr) \
98 (mc_addr) | SG_MEM_DECODE2_ADR
99 #define MC_MEMDEC3(mc_addr) \
100 (mc_addr) | SG_MEM_DECODE3_ADR
101 #define MC_ACTIVITY_STATUS(mc_addr) \
102 (mc_addr) | SG_EMU_ACTIVITY_STATUS
106 * Mappings to the array for the decode registers only
108 #define SG_MC_DECODE_I 0
109 #define SG_MC_DECODE_II 1
110 #define SG_MC_DECODE_III 2
111 #define SG_MC_DECODE_IV 3
113 * Memory Macros
115 #define SG_REG_2_OFFSET(num) \
116 ((num) == SG_MC_DECODE_I ? (uint64_t)SG_MEM_DECODE0_ADR : \
117 (num) == SG_MC_DECODE_II ? (uint64_t)SG_MEM_DECODE1_ADR : \
118 (num) == SG_MC_DECODE_III ? (uint64_t)SG_MEM_DECODE2_ADR : \
119 (num) == SG_MC_DECODE_IV ? (uint64_t)SG_MEM_DECODE3_ADR : \
120 (uint64_t)-1)
122 #define MC_VALID_SHIFT 63
123 #define MC_UK_SHIFT 41
124 #define MC_UM_SHIFT 20
125 #define MC_LK_SHIFT 14
126 #define MC_LM_SHIFT 8
127 #define PHYS2UM_SHIFT 26
128 #define MC_UK(memdec) (((memdec) >> MC_UK_SHIFT) & 0xfffu)
129 #define MC_LK(memdec) (((memdec) >> MC_LK_SHIFT)& 0x3fu)
130 #define MC_INTLV(memdec) ((~(MC_LK(memdec)) & 0xfu) + 1)
131 #define MC_UK2SPAN(memdec) ((MC_UK(memdec) + 1) << PHYS2UM_SHIFT)
132 #define MC_SPANMB(memdec) (MC_UK2SPAN(memdec) >> 20)
133 #define MC_UM(memdec) (((memdec) >> MC_UM_SHIFT) & 0x1fffffu)
134 #define MC_LM(memdec) (((memdec) >> MC_LM_SHIFT) & 0x3f)
135 #define MC_BASE(memdec) (MC_UM(memdec) & ~(MC_UK(memdec)))
136 #define MC_BASE2UM(base) (((base) & 0x1fffffu) << MC_UM_SHIFT)
137 #define SAF_MASK 0x000007ffff800000ull
138 #define MC_OFFSET_MASK 0xffu
141 * Memory Slice information
143 #define SG_SLICE_16G_SIZE 0x400000000ULL
144 #define SG_SLICE_32G_SIZE 0x800000000ULL
145 #define SG_SLICE_64G_SIZE 0x1000000000ULL
148 * Copy-rename info
151 #define SBDP_RENAME_MAXOP (PAGESIZE / sizeof (sbdp_rename_script_t))
154 * Must be same size as sbdp_rename_script_t.
156 typedef struct {
157 uint64_t addr;
158 uint_t bd_id;
159 pnode_t node;
160 uint_t asi;
161 uint_t _filler;
162 } sbdp_mc_idle_script_t;
164 typedef struct {
165 uint64_t masr_addr;
166 uint64_t masr;
167 uint_t asi;
168 uint_t _filler;
169 } sbdp_rename_script_t;
171 typedef struct {
172 sbdp_bd_t *s_bdp; /* pointer to src bd info */
173 sbdp_bd_t *t_bdp; /* pointer to tgt bd info */
174 sbdp_rename_script_t *script; /* points to the actual script */
175 uint64_t ret;
176 sbdp_mc_idle_script_t *busy_mc;
177 } sbdp_cr_handle_t;
180 extern uint64_t lddsafaddr(uint64_t physaddr);
181 extern uint64_t lddmcdecode(uint64_t physaddr);
182 extern void stdmcdecode(uint64_t, uint64_t);
184 int sbdp_is_mem(pnode_t node, void *arg);
185 #ifdef DEBUG
186 int sbdp_passthru_readmem(sbdp_handle_t *hp, void *);
187 int sbdp_passthru_prep_script(sbdp_handle_t *hp, void *);
188 #endif
190 #ifdef __cplusplus
192 #endif
194 #endif /* _SBDP_MEM_H */