usr/src/uts/sun4u/sys/machcpuvar.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 #ifndef _SYS_MACHCPUVAR_H
  27 #define _SYS_MACHCPUVAR_H
  28
  29 #pragma ident   "%Z%%M% %I%     %E% SMI"
  30
  31 #include <sys/intr.h>
  32 #include <sys/clock.h>
  33 #include <sys/machparam.h>
  34 #include <sys/machpcb.h>
  35 #include <sys/privregs.h>
  36 #include <sys/machlock.h>
  37
  38 #ifdef  __cplusplus
  39 extern "C" {
  40 #endif
  41
  42 #ifndef _ASM
  43
  44 #include <sys/obpdefs.h>
  45 #include <sys/async.h>
  46 #include <sys/fm/protocol.h>
  47
  48 /*
  49  * CPU state ptl1_panic save.
  50  */
  51 typedef struct ptl1_trapregs {
  52         uint32_t        ptl1_tl;
  53         uint32_t        ptl1_tt;
  54         uint64_t        ptl1_tstate;
  55         uint64_t        ptl1_tpc;
  56         uint64_t        ptl1_tnpc;
  57 } ptl1_trapregs_t;
  58
  59 typedef struct ptl1_regs {
  60         ptl1_trapregs_t ptl1_trap_regs[PTL1_MAXTL];
  61         uint64_t        ptl1_g1;
  62         uint64_t        ptl1_g2;
  63         uint64_t        ptl1_g3;
  64         uint64_t        ptl1_g4;
  65         uint64_t        ptl1_g5;
  66         uint64_t        ptl1_g6;
  67         uint64_t        ptl1_g7;
  68         uint64_t        ptl1_tick;
  69         uint64_t        ptl1_dmmu_sfar;
  70         uint64_t        ptl1_dmmu_sfsr;
  71         uint64_t        ptl1_dmmu_tag_access;
  72         uint64_t        ptl1_immu_sfsr;
  73         uint64_t        ptl1_immu_tag_access;
  74         struct rwindow  ptl1_rwindow[MAXWIN];
  75         uint32_t        ptl1_softint;
  76         uint16_t        ptl1_pstate;
  77         uint8_t         ptl1_pil;
  78         uint8_t         ptl1_cwp;
  79         uint8_t         ptl1_wstate;
  80         uint8_t         ptl1_otherwin;
  81         uint8_t         ptl1_cleanwin;
  82         uint8_t         ptl1_cansave;
  83         uint8_t         ptl1_canrestore;
  84 } ptl1_regs_t;
  85
  86 typedef struct ptl1_state {
  87         ptl1_regs_t     ptl1_regs;
  88         uint32_t        ptl1_entry_count;
  89         uintptr_t       ptl1_stktop;
  90         ulong_t         ptl1_stk[1];
  91 } ptl1_state_t;
  92
  93 /*
  94  * Machine specific fields of the cpu struct
  95  * defined in common/sys/cpuvar.h.
  96  */
  97 struct  machcpu {
  98         struct machpcb  *mpcb;
  99         uint64_t        mpcb_pa;
 100         int             mutex_ready;
 101         int             in_prom;
 102         int             tl1_hdlr;
 103         uint16_t        divisor;        /* Estar %tick clock ratio */
 104         uint8_t         intrcnt;        /* number of back-to-back interrupts */
 105         u_longlong_t    tmp1;           /* per-cpu tmps */
 106         u_longlong_t    tmp2;           /*  used in trap processing */
 107         u_longlong_t    tmp3;
 108         u_longlong_t    tmp4;
 109
 110         label_t         *ofd[HIGH_LEVELS];      /* saved pil ofd */
 111         uintptr_t       lfd[HIGH_LEVELS];       /* saved ret PC */
 112         struct on_trap_data *otd[HIGH_LEVELS];  /* saved pil otd */
 113
 114         struct intr_vec *intr_head[PIL_LEVELS]; /* intr queue heads per pil */
 115         struct intr_vec *intr_tail[PIL_LEVELS]; /* intr queue tails per pil */
 116         boolean_t       poke_cpu_outstanding;
 117         /*
 118          * The cpu module allocates a private data structure for the
 119          * E$ data, which is needed for the specific cpu type.
 120          */
 121         void            *cpu_private;           /* ptr to cpu private data */
 122         /*
 123          * per-MMU ctxdom CPU data.
 124          */
 125         uint_t          cpu_mmu_idx;
 126         struct mmu_ctx  *cpu_mmu_ctxp;
 127
 128         ptl1_state_t    ptl1_state;
 129
 130         uint64_t        pil_high_start[HIGH_LEVELS];    /* high-level intrs */
 131
 132         /*
 133          * intrstat[][] is used to keep track of ticks used at a given pil
 134          * level. intrstat[pil][0] is cumulative and exported via kstats.
 135          * intrstat[pil][1] is used in intr_get_time() and is private.
 136          * 2-dimensional array improves cache locality.
 137          */
 138
 139         uint64_t        intrstat[PIL_MAX+1][2];
 140         kthread_t       *startup_thread;
 141 };
 142
 143 typedef struct machcpu  machcpu_t;
 144
 145 #define cpu_startup_thread      cpu_m.startup_thread
 146 #define CPU_MMU_IDX(cp)         ((cp)->cpu_m.cpu_mmu_idx)
 147 #define CPU_MMU_CTXP(cp)        ((cp)->cpu_m.cpu_mmu_ctxp)
 148 #define NINTR_THREADS   (LOCK_LEVEL)    /* number of interrupt threads */
 149
 150 /*
 151  * Macro to access the "cpu private" data structure.
 152  */
 153 #define CPU_PRIVATE(cp)         ((cp)->cpu_m.cpu_private)
 154
 155 /*
 156  * The OpenBoot Standalone Interface supplies the kernel with
 157  * implementation dependent parameters through the devinfo/property mechanism
 158  */
 159 #define MAXSYSNAME      20
 160
 161 /*
 162  * Used to indicate busy/idle state of a cpu.
 163  * msram field will be set with ECACHE_CPU_MIRROR if we are on
 164  * mirrored sram module.
 165  */
 166 #define ECACHE_CPU_IDLE         0x0             /* CPU is idle */
 167 #define ECACHE_CPU_BUSY         0x1             /* CPU is busy */
 168 #define ECACHE_CPU_MIRROR       0x2             /* E$ is mirrored */
 169 #define ECACHE_CPU_NON_MIRROR   0x3             /* E$ is not mirrored */
 170
 171 /*
 172  * A CPU FRU FMRI string minus the unum component.
 173  */
 174 #define CPU_FRU_FMRI            FM_FMRI_SCHEME_HC":///" \
 175     FM_FMRI_LEGACY_HC"="
 176
 177 struct cpu_node {
 178         char    name[MAXSYSNAME];
 179         char    fru_fmri[sizeof (CPU_FRU_FMRI) + UNUM_NAMLEN];
 180         int     implementation;
 181         int     version;
 182         int     portid;
 183         pnode_t nodeid;
 184         uint64_t        clock_freq;
 185         uint_t  tick_nsec_scale;
 186         union {
 187                 int     dummy;
 188         }       u_info;
 189         int     ecache_size;
 190         int     ecache_linesize;
 191         int     ecache_associativity;
 192         int     ecache_setsize;
 193         ushort_t        itlb_size;
 194         ushort_t        dtlb_size;
 195         int     msram;
 196         uint64_t        device_id;
 197 };
 198
 199 extern struct cpu_node cpunodes[];
 200
 201 #endif  /* _ASM */
 202
 203 #ifdef  __cplusplus
 204 }
 205 #endif
 206
 207 #endif  /* _SYS_MACHCPUVAR_H */