usr/src/uts/sun4u/sys/starfire.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright (c) 1996-2000 by Sun Microsystems, Inc.
  24  * All rights reserved.
  25  */
  26
  27 #ifndef _STARFIRE_H
  28 #define _STARFIRE_H
  29
  30 #pragma ident   "%Z%%M% %I%     %E% SMI"
  31
  32 #ifdef  __cplusplus
  33 extern "C" {
  34 #endif
  35
  36 /* I/O space definitions */
  37 #define STARFIRE_IO_BASE 0x10000000000ULL
  38
  39 /* UPA Port Space (UPS) definitions */
  40 #define STARFIRE_UPS_MID_SHIFT 33       /* MID is 7 bits */
  41 #define STARFIRE_UPS_BRD_SHIFT 36
  42 #define STARFIRE_UPS_BUS_SHIFT 6
  43
  44 /* Starfire Interconnect Space (IS) definitions */
  45 #define STARFIRE_IS_MC_BASE     0x10e80000000ULL /* MC Register Space */
  46
  47
  48 /* Port Specific Interconnect Space (PSI) */
  49 #define STARFIRE_PSI_BASE \
  50                 0x100f8000000ULL        /* put mid in [39:33] */
  51 #define STARFIRE_PSI_PCREG_OFF \
  52                 0x4000000ULL            /* PSI offset for PC regs */
  53 #define STARFIRE_BRD_TO_PSI(board) \
  54                 (STARFIRE_PSI_BASE | \
  55                         (((uint64_t)board) << STARFIRE_UPS_BRD_SHIFT))
  56
  57
  58 /* Starfire BootBus Space (BS) definitions */
  59 #define STARFIRE_PSI_BS_BASE \
  60                 STARFIRE_PSI_BASE       /* BS at start of PSI Space */
  61
  62 #define STARFIRE_UPAID2PSI_BS(upaid) \
  63                 (STARFIRE_PSI_BS_BASE | \
  64                 ((u_longlong_t)STARFIRE_UPAID2HWMID(upaid) << \
  65                         STARFIRE_UPS_MID_SHIFT))
  66
  67 #define STARFIRE_DEV2UPAID(b, p, i) \
  68                 ((((i) & 0x1) << 6) | \
  69                 (((b) & 0xf) << 2) | \
  70                 ((p) & 0x3))
  71
  72 /* Starfire Port Controller Register offsets */
  73 #define STARFIRE_PC_CONF                0x000000UL /* Configuration Reg */
  74 #define STARFIRE_PC_COMP_ID             0x000010UL /* Component ID Reg */
  75 #define STARFIRE_PC_BUS_CONF            0x000020UL /* Bus Configuration Reg */
  76 #define STARFIRE_PC_TO_HOLD_CONF        0x000030UL /* Timeout/Hold Config Reg */
  77 #define STARFIRE_PC_CIC_WRITE_DATA      0x000040UL /* CIC Write Data Reg */
  78 #define STARFIRE_PC_FORCE_PARITY_ERR    0x000050UL /* Force Parity Err Reg */
  79 #define STARFIRE_PC_ERR_0_MASK          0x000060UL /* Err 0 Mask Reg */
  80 #define STARFIRE_PC_ERR_1_MASK          0x000070UL /* Err 1 Mask Reg */
  81 #define STARFIRE_PC_ERR_0               0x000080UL /* Err 0 Reg */
  82 #define STARFIRE_PC_ERR_1               0x000090UL /* Err 1 Reg */
  83 #define STARFIRE_PC_ERR_DATA_SRC        0x0000a0UL /* Err Data Src Reg */
  84 #define STARFIRE_PC_ERR_DATA_LOW        0x0000b0UL /* Err Data Lower Reg */
  85 #define STARFIRE_PC_ERR_DATA_HI         0x0000c0UL /* Err Data Upper Reg */
  86 #define STARFIRE_PC_PORT_ID             0x0000d0UL
  87 #define STARFIRE_PC_PERF_COUNT_0        0x0000e0UL
  88 #define STARFIRE_PC_PERF_COUNT_1        0x0000f0UL
  89 #define STARFIRE_PC_PERF_COUNT_CNTRL    0x000100UL
  90 #define STARFIRE_PC_BLOCK               0x0001c0UL /* 512 Byte scr area */
  91 #define STARFIRE_PC_INT_MAP             0x000200UL /* 32 regs 00.0200-00.03f0 */
  92 #define STARFIRE_PC_MADR                0x000400UL /* 16 regs 00.0400-00.04f0 */
  93
  94 /* Starfire PC definitions/macros */
  95 #define STARFIRE_PC_MADR_BOARD_SHIFT    4
  96 #define STARFIRE_PC_MADR_ADDR(bb, rb, p) \
  97                 (STARFIRE_BRD_TO_PSI(bb) | \
  98                 ((uint64_t)(p) << STARFIRE_UPS_MID_SHIFT) | \
  99                 ((uint64_t)(rb) << STARFIRE_PC_MADR_BOARD_SHIFT) | \
 100                 STARFIRE_PSI_PCREG_OFF | \
 101                 STARFIRE_PC_MADR)
 102
 103 /* Starfire BB (BootBus) definitions/macros */
 104 #define STARFIRE_BB_SYSRESET_CNTRL      0x800000ULL
 105 #define STARFIRE_BB_PAUSE_FLUSH         0x800016ULL
 106
 107 #define STARFIRE_BB_PC_PAUSE(i)         ((uchar_t)(1 << (i)))
 108 #define STARFIRE_BB_PC_FLUSH(i)         ((uchar_t)(1 << ((i)+2)))
 109 #define STARFIRE_BB_PC_IDLE(i)          ((uchar_t)(1 << ((i)+4)))
 110
 111 #define STARFIRE_BB_SYSRESET(i)         ((uchar_t)(1 << (i)))
 112
 113 #define STARFIRE_BB_PC_ADDR(bb, p, io) \
 114                 (STARFIRE_UPAID2PSI_BS(STARFIRE_DEV2UPAID((bb), (p), (io))) | \
 115                 STARFIRE_BB_PAUSE_FLUSH)
 116 #define STARFIRE_BB_RESET_ADDR(bb, p) \
 117                 (STARFIRE_UPAID2PSI_BS(STARFIRE_DEV2UPAID((bb), (p), 0)) | \
 118                 STARFIRE_BB_SYSRESET_CNTRL)
 119
 120 /* Starfire Memory Controller Register offsets */
 121 #define STARFIRE_MC_ASR                 0x000400U       /* Addr Select Reg */
 122 #define STARFIRE_MC_DIMMTYPE            0x00c800U       /* DIMM Type Code Reg */
 123 #define STARFIRE_MC_IDLE                0x00cc00U       /* Idle MC Reg */
 124
 125 /* Starfire MC definitions/macros */
 126 #define STARFIRE_MC_MEM_PRESENT_MASK    0x80000000U
 127 #define STARFIRE_MC_MEM_BASEADDR_MASK   0x7fff0000U
 128 #define STARFIRE_MC_IDLE_MASK           0x00008000U
 129 #define STARFIRE_MC_MASK_MASK           0x00007f00U
 130 #define STARFIRE_MC_DIMMSIZE_MASK       0x0000001fU
 131 #define STARFIRE_MC_INTERLEAVE_MASK     0x00000001U
 132 #define STARFIRE_MC_MASK_SHIFT          18
 133 #define STARFIRE_MC_BASE_SHIFT          10
 134 #define STARFIRE_MC_ADDR_HIBITS         0x1fe00000000ULL
 135 #define STARFIRE_MC_ASR_ADDR(reg)       ((reg) | (uint64_t)STARFIRE_MC_ASR)
 136 #define STARFIRE_MC_IDLE_ADDR(reg)      ((reg) | (uint64_t)STARFIRE_MC_IDLE)
 137 #define STARFIRE_MC_DIMMTYPE_ADDR(reg)  ((reg) | (uint64_t)STARFIRE_MC_DIMMTYPE)
 138 #define STARFIRE_MC_ASR_ADDR_BOARD(b) \
 139                 (((uint64_t)(b) << STARFIRE_UPS_BRD_SHIFT) | \
 140                 STARFIRE_IS_MC_BASE | \
 141                 (uint64_t)STARFIRE_MC_ASR)
 142
 143 /*
 144  * Memory boards on Starfire are aligned on 8GB
 145  * boundaries, i.e. the physical address space
 146  * is not physically contiguous.
 147  */
 148 #define STARFIRE_MC_MEMBOARD_SHIFT      33
 149 #define STARFIRE_MC_MEMBOARD_ALIGNMENT  \
 150                 (UINT64_C(1) << STARFIRE_MC_MEMBOARD_SHIFT)
 151
 152 /*
 153  * Starfire has a special regspec for the "reg" property of the
 154  * mem-unit node since this node is homegrown.
 155  */
 156 struct sf_memunit_regspec {
 157         uint_t  regspec_addr_hi;
 158         uint_t  regspec_addr_lo;
 159         uint_t  regspec_size_hi;
 160         uint_t  regspec_size_lo;
 161 };
 162
 163 /*
 164  * Conversion macros
 165  */
 166
 167 /*
 168  * Starfire hardware version of the upaid (commonly known as
 169  * HWMID) is different from the software version (also known as upaid).
 170  *  HW version BBBBIPp   == SW version IBBBBPp
 171  */
 172 #define STARFIRE_UPAID2HWMID(upaid) (((upaid & 0x3C) << 1) | \
 173                                 ((upaid & 0x40) >> 4) | (upaid & 0x3))
 174
 175
 176 /* Xfire UPA ID to UPA Port Specific Space */
 177 #define STARFIRE_UPAID2UPS(upaid) \
 178                 (((u_longlong_t)STARFIRE_UPAID2HWMID(upaid) << \
 179                                 STARFIRE_UPS_MID_SHIFT) | STARFIRE_IO_BASE)
 180
 181 /*
 182  * Macro to convert our 7 bits HW MID to 7 bits SW MID
 183  * That is "BBBBIPp" to "IBBBBPp".
 184  */
 185 #define STARFIRE_HWMID2SWMID(mid) ((mid & 0x3) | ((mid & 0x78) >> 1) | \
 186                                         ((mid & 0x4) << 4))
 187
 188 /*
 189  * Macro to convert our 7 bits UPAid to Sun's 5 bit HW Interrupt
 190  * group number required in some hardware registers (sysios).
 191  * That is "IBBBBPp" to "BBBBp", where "BBBB" is the board number,
 192  * "IP" is the PC id and "p" is the port number.
 193  */
 194 #define STARFIRE_UPAID2HWIGN(upaid) \
 195                 (((upaid & 0x3C) >> 1) | (upaid & 0x1))
 196
 197 /*
 198  * Macro to convert our UPAid to a 7 bit Starfire version of the
 199  * interrupt group number. This so-called IGN is part of
 200  * the interrupt vector number read by the CPU serving this interrupt.
 201  * Thanks to the warp minds of our hardware guys, it is in this
 202  * convoluted weird format. Note that the interrupt vector number is
 203  * then used to index into the interrupt dispatch table to get its
 204  * interrupt handler.
 205  * Convert "IBBBBPp" to "XPBBBBp" where "BBBB" is the 4bit board #,
 206  * "IP" is the 2 bit PC id, "p" is the port # and "X" is ~I.
 207  */
 208 #define STARFIRE_UPAID2IGN(upaid)  (STARFIRE_UPAID2HWIGN(upaid) | \
 209                         ((upaid & 0x2) << 4) |  \
 210                         ((upaid & 0x40) ^ 0x40))
 211
 212 /*
 213  * Starfire platform specific routines currently only defined
 214  * in starfire.c and referenced by DR.
 215  */
 216 extern int      plat_max_boards();
 217 extern int      plat_max_cpu_units_per_board();
 218 extern int      plat_max_mem_units_per_board();
 219 extern int      plat_max_io_units_per_board();
 220
 221 /*
 222  * Starfire platform specific interrupt translation routines
 223  */
 224 extern void pc_ittrans_init(int, caddr_t *);
 225 extern void pc_ittrans_uninit(caddr_t);
 226 extern int pc_translate_tgtid(caddr_t, int, volatile uint64_t *);
 227 extern void pc_ittrans_cleanup(caddr_t, volatile uint64_t *);
 228
 229 /*
 230  * Maximum number of system boards supported in a Starfire.
 231  */
 232 #define STARFIRE_MAX_BOARDS     16
 233
 234 /*
 235  * We reserve some "fake" DMV values for Starfire IDN.  These are treated
 236  * as hardware interrupt numbers, but they don't correspond to an actual UPA
 237  * port; they can thus be allocated as "well-known" numbers for IDN purposes.
 238  */
 239 #define STARFIRE_DMV_EXTRA      4
 240 #define STARFIRE_DMV_HWINT      (MAX_UPA+STARFIRE_DMV_EXTRA)
 241 #define STARFIRE_DMV_IDN_BASE   (MAX_UPA)
 242
 243
 244 #ifdef  __cplusplus
 245 }
 246 #endif
 247
 248 #endif  /* _STARFIRE_H */