usr/src/uts/common/xen/public/hvm/params.h

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a copy
   3  * of this software and associated documentation files (the "Software"), to
   4  * deal in the Software without restriction, including without limitation the
   5  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
   6  * sell copies of the Software, and to permit persons to whom the Software is
   7  * furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  15  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  16  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  17  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  18  * DEALINGS IN THE SOFTWARE.
  19  */
  20
  21 #ifndef __XEN_PUBLIC_HVM_PARAMS_H__
  22 #define __XEN_PUBLIC_HVM_PARAMS_H__
  23
  24 #include "hvm_op.h"
  25
  26 /*
  27  * Parameter space for HVMOP_{set,get}_param.
  28  */
  29
  30 /*
  31  * How should CPU0 event-channel notifications be delivered?
  32  * val[63:56] == 0: val[55:0] is a delivery GSI (Global System Interrupt).
  33  * val[63:56] == 1: val[55:0] is a delivery PCI INTx line, as follows:
  34  *                  Domain = val[47:32], Bus  = val[31:16],
  35  *                  DevFn  = val[15: 8], IntX = val[ 1: 0]
  36  * If val == 0 then CPU0 event-channel notifications are not delivered.
  37  */
  38 #define HVM_PARAM_CALLBACK_IRQ 0
  39
  40 /*
  41  * These are not used by Xen. They are here for convenience of HVM-guest
  42  * xenbus implementations.
  43  */
  44 #define HVM_PARAM_STORE_PFN    1
  45 #define HVM_PARAM_STORE_EVTCHN 2
  46
  47 #define HVM_PARAM_PAE_ENABLED  4
  48
  49 #define HVM_PARAM_IOREQ_PFN    5
  50
  51 #define HVM_PARAM_BUFIOREQ_PFN 6
  52
  53 #ifdef __ia64__
  54
  55 #define HVM_PARAM_NVRAM_FD     7
  56 #define HVM_PARAM_VHPT_SIZE    8
  57 #define HVM_PARAM_BUFPIOREQ_PFN 9
  58
  59 #elif defined(__i386__) || defined(__x86_64__)
  60
  61 /* Expose Viridian interfaces to this HVM guest? */
  62 #define HVM_PARAM_VIRIDIAN     9
  63
  64 #endif
  65
  66 /*
  67  * Set mode for virtual timers (currently x86 only):
  68  *  delay_for_missed_ticks (default):
  69  *   Do not advance a vcpu's time beyond the correct delivery time for
  70  *   interrupts that have been missed due to preemption. Deliver missed
  71  *   interrupts when the vcpu is rescheduled and advance the vcpu's virtual
  72  *   time stepwise for each one.
  73  *  no_delay_for_missed_ticks:
  74  *   As above, missed interrupts are delivered, but guest time always tracks
  75  *   wallclock (i.e., real) time while doing so.
  76  *  no_missed_ticks_pending:
  77  *   No missed interrupts are held pending. Instead, to ensure ticks are
  78  *   delivered at some non-zero rate, if we detect missed ticks then the
  79  *   internal tick alarm is not disabled if the VCPU is preempted during the
  80  *   next tick period.
  81  *  one_missed_tick_pending:
  82  *   Missed interrupts are collapsed together and delivered as one 'late tick'.
  83  *   Guest time always tracks wallclock (i.e., real) time.
  84  */
  85 #define HVM_PARAM_TIMER_MODE   10
  86 #define HVMPTM_delay_for_missed_ticks    0
  87 #define HVMPTM_no_delay_for_missed_ticks 1
  88 #define HVMPTM_no_missed_ticks_pending   2
  89 #define HVMPTM_one_missed_tick_pending   3
  90
  91 /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
  92 #define HVM_PARAM_HPET_ENABLED 11
  93
  94 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */
  95 #define HVM_PARAM_IDENT_PT     12
  96
  97 /* Device Model domain, defaults to 0. */
  98 #define HVM_PARAM_DM_DOMAIN    13
  99
 100 /* ACPI S state: currently support S0 and S3 on x86. */
 101 #define HVM_PARAM_ACPI_S_STATE 14
 102
 103 /* TSS used on Intel when CR0.PE=0. */
 104 #define HVM_PARAM_VM86_TSS     15
 105
 106 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */
 107 #define HVM_PARAM_VPT_ALIGN    16
 108
 109 #define HVM_NR_PARAMS          17
 110
 111 #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */