usr/src/cmd/fm/dicts/SUN4V.dict

   1 #
   2 # Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
   3 # Use is subject to license terms.
   4 #
   5 # CDDL HEADER START
   6 #
   7 # The contents of this file are subject to the terms of the
   8 # Common Development and Distribution License (the "License").
   9 # You may not use this file except in compliance with the License.
  10 #
  11 # You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  12 # or http://www.opensolaris.org/os/licensing.
  13 # See the License for the specific language governing permissions
  14 # and limitations under the License.
  15 #
  16 # When distributing Covered Code, include this CDDL HEADER in each
  17 # file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  18 # If applicable, add the following below this CDDL HEADER, with the
  19 # fields enclosed by brackets "[]" replaced with your own identifying
  20 # information: Portions Copyright [yyyy] [name of copyright owner]
  21 #
  22 # CDDL HEADER END
  23 #
  24 # DO NOT EDIT -- this file is generated by the Event Registry.
  25 #
  26
  27 FMDICT: name=SUN4V version=1 maxkey=3 dictid=0x3456
  28
  29 fault.cpu.ultraSPARC-T1.ireg=1
  30 fault.cpu.ultraSPARC-T1.freg=2
  31 fault.cpu.ultraSPARC-T1.itlb=3
  32 fault.cpu.ultraSPARC-T1.dtlb=4
  33 fault.cpu.ultraSPARC-T1.icache=5
  34 fault.cpu.ultraSPARC-T1.dcache=6
  35 fault.cpu.ultraSPARC-T1.mau=7
  36 fault.cpu.ultraSPARC-T1.l2cachedata=8
  37 fault.cpu.ultraSPARC-T1.l2cachetag=9
  38 fault.cpu.ultraSPARC-T1.l2cachectl=10
  39 fault.memory.page=11
  40 fault.memory.dimm=12
  41 fault.memory.bank=13
  42 fault.memory.link-c=14
  43 fault.cpu.ultraSPARC-T2.ireg=15
  44 fault.cpu.ultraSPARC-T2.freg=16
  45 fault.cpu.ultraSPARC-T2.misc_reg=17
  46 fault.cpu.ultraSPARC-T2.itlb=18
  47 fault.cpu.ultraSPARC-T2.dtlb=19
  48 fault.cpu.ultraSPARC-T2.icache=20
  49 fault.cpu.ultraSPARC-T2.dcache=21
  50 fault.cpu.ultraSPARC-T2.mau=22
  51 fault.cpu.ultraSPARC-T2.l2data-c=23
  52 fault.cpu.ultraSPARC-T2.l2cachetag=24
  53 fault.cpu.ultraSPARC-T2.l2cachectl=25
  54 fault.memory.link-u=26
  55 fault.cpu.ultraSPARC-T2.l2data-u=27
  56 fault.cpu.ultraSPARC-T1.l2data-c=28
  57 fault.cpu.ultraSPARC-T1.l2data-u=29
  58 fault.memory.datapath=30
  59 fault.io.n2.ncu=31
  60 fault.io.n2.dmu=32
  61 fault.io.n2.niu=33
  62 fault.io.n2.siu=34
  63 fault.io.n2.soc=35
  64 fault.io.n2.crossbar=36
  65 fault.io.fire.fw-epkt fault.io.fire.sw-epkt fault.io.fire.sw-fw-mismatch=37
  66 fault.io.vf.ncx=38
  67 fault.memory.link-f=39
  68 fault.cpu.ultraSPARC-T2plus.ireg=40
  69 fault.cpu.ultraSPARC-T2plus.freg=41
  70 fault.cpu.ultraSPARC-T2plus.misc_reg=42
  71 fault.cpu.ultraSPARC-T2plus.itlb=43
  72 fault.cpu.ultraSPARC-T2plus.dtlb=44
  73 fault.cpu.ultraSPARC-T2plus.icache=45
  74 fault.cpu.ultraSPARC-T2plus.dcache=46
  75 fault.cpu.ultraSPARC-T2plus.mau=47
  76 fault.cpu.ultraSPARC-T2plus.l2data-c=48
  77 fault.cpu.ultraSPARC-T2plus.l2cachetag=49
  78 fault.cpu.ultraSPARC-T2plus.l2cachectl=50
  79 fault.cpu.ultraSPARC-T2plus.l2data-u=51
  80 fault.cpu.ultraSPARC-T2plus.lfu-f=52
  81 fault.cpu.ultraSPARC-T2plus.lfu-p=53
  82 fault.cpu.ultraSPARC-T2plus.lfu-u=54
  83 fault.asic.ultraSPARC-T2plus.interconnect.opu-u=55
  84 fault.asic.ultraSPARC-T2plus.interconnect.opu-c=56
  85 fault.cpu.ultraSPARC-T2plus.chip=57
  86 fault.asic.ultraSPARC-T2plus.interconnect.lfu-c fault.cpu.ultraSPARC-T2plus.chip=58
  87 fault.asic.ultraSPARC-T2plus.interconnect.lfu-f fault.cpu.ultraSPARC-T2plus.chip=59
  88 fault.asic.ultraSPARC-T2plus.interconnect.lfu-u fault.cpu.ultraSPARC-T2plus.chip=60
  89 fault.asic.ultraSPARC-T2plus.interconnect.lfu-u=61
  90 fault.asic.ultraSPARC-T2plus.interconnect.gpd-u fault.cpu.ultraSPARC-T2plus.chip=62
  91 fault.asic.ultraSPARC-T2plus.interconnect.gpd-c fault.cpu.ultraSPARC-T2plus.chip=63
  92 fault.asic.ultraSPARC-T2plus.interconnect.gpd-c=64
  93 fault.asic.fpga fault.asic.ultraSPARC-T2plus.interconnect.gpd-c=65
  94 fault.asic.ultraSPARC-T2plus.interconnect.asu=66
  95 fault.memory.dimm-page-retires-excessive=67
  96 fault.memory.dimm-ue-imminent=68
  97 fault.memory.dram-ue-imminent=69
  98 fault.cpu.generic-sparc.strand=70
  99 fault.cpu.generic-sparc.strand-nr=71
 100 fault.cpu.generic-sparc.strand-uc=72
 101 fault.cpu.generic-sparc.strand-uc-nr=73
 102 fault.cpu.generic-sparc.core=74
 103 fault.cpu.generic-sparc.core-nr=75
 104 fault.cpu.generic-sparc.core-uc=76
 105 fault.cpu.generic-sparc.core-uc-nr=77
 106 fault.cpu.generic-sparc.chip=78
 107 fault.cpu.generic-sparc.chip-nr=79
 108 fault.cpu.generic-sparc.chip-uc=80
 109 fault.cpu.generic-sparc.chip-uc-nr=81
 110 fault.cpu.generic-sparc.c2c=82
 111 fault.cpu.generic-sparc.c2c-failover=83
 112 fault.cpu.generic-sparc.c2c-uc=84
 113 fault.memory.memlink=85
 114 fault.memory.memlink-failover=86
 115 fault.memory.memlink-uc=87
 116 defect.fw.generic-sparc.addr-oob=88
 117 defect.fw.generic-sparc.erpt-gen=89
 118 fault.cpu.generic-sparc.bootbus=90
 119 fault.sp.failed=91