| blob | beb1296f579f39c94f796771d42ada5541b2bcf6 |
1 /*
2 *
3 * CDDL HEADER START
4 *
5 * The contents of this file are subject to the terms of the
6 * Common Development and Distribution License (the "License").
7 * You may not use this file except in compliance with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
24 * Copyright 2017 Joyent, Inc.
25 */
27 /*
28 * Copyright (c) 2010, Intel Corporation.
29 * All rights reserved.
30 */
32 /* Copyright (c) 1988 AT&T */
33 /* All Rights Reserved */
37 /* BEGIN CSTYLED */
39 /*
40 * Disassembly begins in dis_distable, which is equivalent to the One-byte
41 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The
42 * decoding loops then traverse out through the other tables as necessary to
43 * decode a given instruction.
44 *
45 * The behavior of this file can be controlled by one of the following flags:
46 *
47 * DIS_TEXT Include text for disassembly
48 * DIS_MEM Include memory-size calculations
49 *
50 * Either or both of these can be defined.
51 *
52 * This file is not, and will never be, cstyled. If anything, the tables should
53 * be taken out another tab stop or two so nothing overlaps.
54 */
56 /*
57 * These functions must be provided for the consumer to do disassembly.
58 */
59 #ifdef DIS_TEXT
65 #endif
69 /* field terminates - no pointer. */
71 /* Used to decode instructions. */
74 uchar_t it_adrmode;
75 #ifdef DIS_TEXT
78 #endif
79 #ifdef DIS_MEM
81 #endif
91 /*
92 * Instruction formats.
93 */
95 UNKNOWN,
96 MRw,
97 IMlw,
98 IMw,
99 IR,
100 OA,
101 AO,
102 MS,
103 SM,
104 Mv,
105 Mw,
110 PREF,
111 SWAPGS_RDTSCP,
112 MONITOR_MWAIT,
113 R,
114 RA,
115 SEG,
116 MR,
117 RM,
119 IA,
120 MA,
121 SD,
122 AD,
123 SA,
124 D,
125 INM,
126 SO,
127 BD,
128 I,
129 P,
130 V,
132 U,
133 OVERRIDE,
165 /*
166 * MMX/SIMD addressing modes.
167 */
217 XGETBV_XSETBV,
245 ADX /* ADX instructions, support REX.w, mod_rm->mod_reg */
246 };
248 /*
249 * VEX prefixes
250 */
256 /*
257 ** Register numbers for the i386
258 */
259 #define EAX_REGNO 0
260 #define ECX_REGNO 1
261 #define EDX_REGNO 2
262 #define EBX_REGNO 3
263 #define ESP_REGNO 4
264 #define EBP_REGNO 5
265 #define ESI_REGNO 6
266 #define EDI_REGNO 7
268 /*
269 * modes for immediate values
270 */
271 #define MODE_NONE 0
278 /*
279 * The letters used in these macros are:
280 * IND - indirect to another to another table
281 * "T" - means to Terminate indirections (this is the final opcode)
282 * "S" - means "operand length suffix required"
283 * "Sa" - means AVX2 suffix (d/q) required
284 * "NS" - means "no suffix" which is the operand length suffix of the opcode
285 * "Z" - means instruction size arg required
286 * "u" - means the opcode is invalid in IA32 but valid in amd64
287 * "x" - means the opcode is invalid in amd64, but not IA32
288 * "y" - means the operand size is always 64 bits in 64 bit mode
289 * "p" - means push/pop stack operation
290 * "vr" - means VEX instruction that operates on normal registers, not fpu
291 * "vo" - means VEX instruction that operates on opmask registers, not fpu
292 */
294 #if defined(DIS_TEXT) && defined(DIS_MEM)
297 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0}
298 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0}
299 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0}
300 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0}
301 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1}
302 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0}
303 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0}
304 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1}
305 #define TSavo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1, 1}
306 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1}
307 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0}
308 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0}
309 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0}
310 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1}
311 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0}
312 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 1}
313 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0}
314 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0}
316 #elif defined(DIS_TEXT)
319 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0}
320 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0}
321 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0}
322 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0}
323 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1}
324 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0}
325 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0}
326 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1}
327 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1}
328 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0}
329 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0}
330 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0}
331 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1}
332 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0}
333 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 1}
334 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0}
335 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0}
337 #elif defined(DIS_MEM)
338 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0}
339 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0}
340 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
341 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0}
342 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
343 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1}
344 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
345 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
346 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
347 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1}
348 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1}
349 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
350 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
351 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
352 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1}
353 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
354 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 1}
355 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0}
356 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
357 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0}
358 #else
359 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0}
360 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0}
361 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0}
362 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0}
363 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0}
364 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1}
365 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0}
366 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
367 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
368 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1}
369 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1}
370 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0}
371 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0}
372 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0}
373 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1}
374 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
375 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 1}
376 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0}
377 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
378 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0}
379 #endif
381 #ifdef DIS_TEXT
382 /*
383 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode
384 */
392 };
395 /*
396 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2
397 */
401 };
406 };
408 /*
409 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2
410 */
414 };
418 };
420 /*
421 * decode for scale from SIB byte
422 */
425 /*
426 * decode for scale from VSIB byte, note that we always include the scale factor
427 * to match gas.
428 */
431 /*
432 * register decoding for normal references to registers (ie. not addressing)
433 */
437 };
442 };
447 };
452 };
457 };
462 };
467 };
472 };
477 };
482 };
487 };
491 };
496 };
498 /*
499 * SIMD predicate suffixes
500 */
503 };
506 /*0 1 2 3 4 5 6 7*/
510 };
514 /*
515 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63)
516 */
519 /*
520 * "decode table" for pause and clflush instructions
521 */
524 /*
525 * Decode table for 0x0F00 opcodes
526 */
531 };
534 /*
535 * Decode table for 0x0F01 opcodes
536 */
539 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
541 };
543 /*
544 * Decode table for 0x0F18 opcodes -- SIMD prefetch
545 */
548 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF),
550 };
552 /*
553 * Decode table for 0x0FAE opcodes -- SIMD state save/restore
554 */
557 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
558 };
560 /*
561 * Decode table for 0x0FBA opcodes
562 */
568 };
570 /*
571 * Decode table for 0x0FC7 opcode (group 9)
572 */
578 };
580 /*
581 * Decode table for 0x0FC7 opcode (group 9) mode 3
582 */
588 };
590 /*
591 * Decode table for 0x0FC7 opcode with 0x66 prefix
592 */
598 };
600 /*
601 * Decode table for 0x0FC7 opcode with 0xF3 prefix
602 */
608 };
610 /*
611 * Decode table for 0x0FC8 opcode -- 486 bswap instruction
612 *
613 *bit pattern: 0000 1111 1100 1reg
614 */
617 };
619 /*
620 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions
621 */
623 {
626 }, {
629 }, {
632 }, {
635 } };
637 /*
638 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes.
639 */
652 };
654 /*
655 * SIMD instructions have been wedged into the existing IA32 instruction
656 * set through the use of prefixes. That is, while 0xf0 0x58 may be
657 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different
658 * instruction - addss. At present, three prefixes have been coopted in
659 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The
660 * following tables are used to provide the prefixed instruction names.
661 * The arrays are sparse, but they're fast.
662 */
664 /*
665 * Decode table for SIMD instructions with the address size (0x66) prefix.
666 */
673 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8),
674 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8),
680 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16),
681 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8),
694 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16),
695 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16),
696 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16),
698 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16),
699 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16),
700 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16),
701 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16),
706 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16),
733 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16),
734 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3),
735 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16),
736 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16),
738 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16),
739 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16),
740 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16),
741 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16),
744 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16),
745 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16),
747 };
755 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8),
756 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8),
762 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16),
771 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX),
776 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16),
777 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16),
778 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16),
780 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16),
781 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16),
782 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16),
783 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16),
785 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16),
786 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID,
788 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16),
795 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR),
811 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID,
815 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16),
816 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR),
817 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16),
818 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16),
820 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16),
821 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16),
822 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16),
823 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16),
825 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
826 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
827 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
828 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID,
829 };
831 /*
832 * Decode table for SIMD instructions with the repnz (0xf2) prefix.
833 */
914 };
922 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID,
944 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID,
945 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8),
996 };
1078 };
1157 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),
1160 };
1242 };
1243 /*
1244 * Decode table for SIMD instructions with the repz (0xf3) prefix.
1245 */
1274 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16),
1326 };
1334 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID,
1354 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4),
1356 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16),
1357 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4),
1408 };
1409 /*
1410 * The following two tables are used to encode crc32 and movbe
1411 * since they share the same opcodes.
1412 */
1416 };
1421 };
1423 /*
1424 * The following table is used to distinguish between adox and adcx which share
1425 * the same opcodes.
1426 */
1430 };
1433 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16),
1434 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16),
1435 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16),
1439 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16),
1443 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16),
1445 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16),
1448 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16),
1449 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16),
1450 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16),
1451 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16),
1495 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16),
1501 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16),
1511 };
1514 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16),
1515 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16),
1516 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16),
1517 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16),
1521 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID,
1524 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16),
1526 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16),
1527 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16),
1529 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16),
1530 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16),
1531 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16),
1532 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16),
1535 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16),
1541 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID,
1559 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16),
1561 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16),
1562 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16),
1566 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16),
1567 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16),
1571 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16),
1572 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16),
1582 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16),
1592 };
1597 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16),
1598 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16),
1601 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16),
1605 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID,
1615 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID,
1625 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16),
1674 };
1677 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID,
1678 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID,
1679 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16),
1680 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16),
1683 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16),
1687 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID,
1692 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI),
1697 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID,
1707 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16),
1756 };
1758 /*
1759 * Decode table for 0x0F0D which uses the first byte of the mod_rm to
1760 * indicate a sub-code.
1761 */
1765 };
1767 /*
1768 * Decode table for 0x0F opcodes
1769 */
1772 {
1777 }, {
1778 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8),
1779 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8),
1782 }, {
1785 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16),
1786 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4),
1787 }, {
1792 }, {
1797 }, {
1798 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16),
1799 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16),
1800 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16),
1801 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16),
1802 }, {
1803 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8),
1804 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8),
1805 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8),
1806 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8),
1807 }, {
1809 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM),
1812 }, {
1817 }, {
1822 }, {
1827 }, {
1832 }, {
1834 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7),
1837 }, {
1839 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3),
1840 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8),
1841 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8),
1842 }, {
1844 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8),
1845 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8),
1846 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8),
1847 }, {
1849 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8),
1852 } };
1855 {
1860 }, {
1861 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8),
1862 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8),
1865 }, {
1868 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16),
1870 }, {
1875 }, {
1877 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX),
1880 }, {
1881 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16),
1882 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16),
1883 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16),
1884 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16),
1885 }, {
1890 }, {
1895 }, {
1900 }, {
1901 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR),
1905 }, {
1910 }, {
1915 }, {
1920 }, {
1925 }, {
1930 }, {
1935 } };
1937 /*
1938 * Decode table for 0x80 opcodes
1939 */
1945 };
1948 /*
1949 * Decode table for 0x81 opcodes.
1950 */
1956 };
1959 /*
1960 * Decode table for 0x82 opcodes.
1961 */
1967 };
1968 /*
1969 * Decode table for 0x83 opcodes.
1970 */
1976 };
1978 /*
1979 * Decode table for 0xC0 opcodes.
1980 */
1986 };
1988 /*
1989 * Decode table for 0xD0 opcodes.
1990 */
1996 };
1998 /*
1999 * Decode table for 0xC1 opcodes.
2000 * 186 instruction set
2001 */
2007 };
2009 /*
2010 * Decode table for 0xD1 opcodes.
2011 */
2017 };
2020 /*
2021 * Decode table for 0xD2 opcodes.
2022 */
2028 };
2029 /*
2030 * Decode table for 0xD3 opcodes.
2031 */
2037 };
2040 /*
2041 * Decode table for 0xF6 opcodes.
2042 */
2048 };
2051 /*
2052 * Decode table for 0xF7 opcodes.
2053 */
2059 };
2062 /*
2063 * Decode table for 0xFE opcodes.
2064 */
2070 };
2071 /*
2072 * Decode table for 0xFF opcodes.
2073 */
2079 };
2081 /* for 287 instructions, which are a mess to decode */
2084 {
2085 /* bit pattern: 1101 1xxx MODxx xR/M */
2088 }, {
2091 }, {
2094 }, {
2097 }, {
2100 }, {
2103 }, {
2106 }, {
2109 } };
2112 {
2113 /* bit pattern: 1101 1xxx 11xx xREG */
2116 }, {
2119 }, {
2122 }, {
2125 }, {
2128 }, {
2131 }, {
2134 }, {
2137 } };
2140 {
2141 /* bit pattern: 1101 1001 111x xxxx */
2144 }, {
2147 }, {
2150 }, {
2153 } };
2156 /* bit pattern: 1101 1011 111x xxxx */
2159 };
2162 /* bit pattern: 1101 1011 11yy yxxx */
2165 };
2168 /* bit pattern: 1101 1010 11yy yxxx */
2171 };
2173 /*
2174 * Main decode table for the op codes. The first two nibbles
2175 * will be used as an index into the table. If there is a
2176 * a need to further decode an instruction, the array to be
2177 * referenced is indicated with the other two entries being
2178 * empty.
2179 */
2182 {
2187 }, {
2192 }, {
2197 }, {
2202 }, {
2207 }, {
2212 }, {
2213 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw),
2216 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4),
2217 }, {
2222 }, {
2227 }, {
2231 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM),
2232 }, {
2237 }, {
2242 }, {
2247 }, {
2251 /* 287 instructions. Note that although the indirect field */
2252 /* indicates opFP1n2 for further decoding, this is not necessarily */
2253 /* the case since the opFP arrays are not partitioned according to key1 */
2254 /* and key2. opFP1n2 is given only to indicate that we haven't */
2255 /* finished decoding the instruction. */
2258 }, {
2263 }, {
2268 } };
2270 /* END CSTYLED */
2272 /*
2273 * common functions to decode and disassemble an x86 or amd64 instruction
2274 */
2276 /*
2277 * These are the individual fields of a REX prefix. Note that a REX
2278 * prefix with none of these set is still needed to:
2279 * - use the MOVSXD (sign extend 32 to 64 bits) instruction
2280 * - access the %sil, %dil, %bpl, %spl registers
2281 */
2287 /*
2288 * These are the individual fields of a VEX prefix.
2289 */
2293 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */
2294 #define VEX_L 0x04
2300 /* VEX m-mmmm field, only used by three bytes prefix */
2305 /* VEX pp field, providing equivalent functionality of a SIMD prefix */
2306 #define VEX_p_66 0x01
2307 #define VEX_p_F3 0x02
2308 #define VEX_p_F2 0x03
2310 /*
2311 * Even in 64 bit mode, usually only 4 byte immediate operands are supported.
2312 */
2316 /*
2317 * Just a bunch of useful macros.
2318 */
2322 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1)
2323 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1)
2339 /*
2340 * The AVX2 gather instructions are a bit of a mess. While there's a pattern,
2341 * there's not really a consistent scheme that we can use to know what the mode
2342 * is supposed to be for a given type. Various instructions, like VPGATHERDD,
2343 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have
2344 * some registers match VEX_L, but the VSIB is always XMM.
2345 *
2346 * The simplest way to deal with this is to just define a table based on the
2347 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into
2348 * them.
2349 *
2350 * We further have to subdivide this based on the value of VEX_W and the value
2351 * of VEX_L. The array is constructed to be indexed as:
2352 * [opcode - 0x90][VEX_W][VEX_L].
2353 */
2354 /* w = 0, 0x90 */
2363 {
2364 /* op 0x90, W.0 */
2365 {
2368 },
2369 /* op 0x90, W.1 */
2370 {
2373 }
2374 },
2375 {
2376 /* op 0x91, W.0 */
2377 {
2380 },
2381 /* op 0x91, W.1 */
2382 {
2385 }
2386 },
2387 {
2388 /* op 0x92, W.0 */
2389 {
2392 },
2393 /* op 0x92, W.1 */
2394 {
2397 }
2398 },
2399 {
2400 /* op 0x93, W.0 */
2401 {
2404 },
2405 /* op 0x93, W.1 */
2406 {
2409 }
2410 }
2411 };
2413 /*
2414 * Get the next byte and separate the op code into the high and low nibbles.
2415 */
2416 static int
2418 {
2421 /*
2422 * x86 instructions have a maximum length of 15 bytes. Bail out if
2423 * we try to read more.
2424 */
2437 }
2439 /*
2440 * Get and decode an SIB (scaled index base) byte
2441 */
2442 static void
2444 {
2454 }
2460 }
2462 /*
2463 * Get the byte following the op code and separate it into the
2464 * mode, register, and r/m fields.
2465 */
2466 static void
2468 {
2474 }
2475 }
2477 /*
2478 * Adjust register selection based on any REX prefix bits present.
2479 */
2480 /*ARGSUSED*/
2481 static void
2483 {
2492 }
2493 }
2495 /*
2496 * Adjust register selection based on any VEX prefix bits present.
2497 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix
2498 */
2499 /*ARGSUSED*/
2500 static void
2502 {
2511 }
2512 }
2514 /*
2515 * Get an immediate operand of the given size, with sign extension.
2516 */
2517 static void
2519 {
2536 else
2551 }
2563 }
2566 }
2567 /* Do sign extension */
2572 }
2573 #ifdef DIS_TEXT
2577 #endif
2578 }
2580 /*
2581 * Get an ip relative operand of the given size, with sign extension.
2582 */
2583 static void
2585 {
2587 #ifdef DIS_TEXT
2589 #endif
2590 }
2592 /*
2593 * Check to see if there is a segment override prefix pending.
2594 * If so, print it in the current 'operand' location and set
2595 * the override flag back to false.
2596 */
2597 /*ARGSUSED*/
2598 static void
2600 {
2601 #ifdef DIS_TEXT
2605 }
2606 #endif
2608 }
2611 /*
2612 * Process a single instruction Register or Memory operand.
2613 *
2614 * mode = addressing mode from ModRM byte
2615 * r_m = r_m (or reg if mode == 3) field from ModRM byte
2616 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use.
2617 * o = index of operand that we are processing (0, 1 or 2)
2618 *
2619 * the value of reg or r_m must have already been adjusted for any REX prefix.
2620 */
2621 /*ARGSUSED*/
2622 static void
2624 {
2630 #ifdef DIS_TEXT
2632 #endif
2640 /*
2641 * first handle a simple register
2642 */
2644 #ifdef DIS_TEXT
2673 else
2684 else
2687 }
2690 }
2692 /*
2693 * if symbolic representation, skip override prefix, if any
2694 */
2697 /*
2698 * Handle 16 bit memory references first, since they decode
2699 * the mode values more simply.
2700 * mode 1 is r_m + 8 bit displacement
2701 * mode 2 is r_m + 16 bit displacement
2702 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp
2703 */
2709 #ifdef DIS_TEXT
2714 else
2717 #endif
2719 }
2721 /*
2722 * 32 and 64 bit addressing modes are more complex since they
2723 * can involve an SIB (scaled index and base) byte to decode.
2724 */
2737 }
2739 /*
2740 * Compute the displacement size and get its bytes
2741 */
2757 }
2759 #ifdef DIS_TEXT
2767 OPLEN);
2768 else
2770 OPLEN);
2774 OPLEN);
2777 MODE_RIPREL;
2778 }
2781 OPLEN);
2782 }
2783 }
2791 else
2797 else
2803 }
2805 /*
2806 * print the base (if any)
2807 */
2812 }
2817 }
2819 /*
2820 * print the index (if any)
2821 */
2829 }
2830 #endif
2831 }
2833 /*
2834 * Operand sequence for standard instruction involving one register
2835 * and one register/memory operand.
2836 * wbit indicates a byte(0) or opnd_size(1) operation
2837 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r")
2838 */
2839 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \
2840 dtrace_get_modrm(x, &mode, ®, &r_m); \
2841 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2842 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2843 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \
2844 }
2846 /*
2847 * Similar to above, but allows for the two operands to be of different
2848 * classes (ie. wbit).
2849 * wbit is for the r_m operand
2850 * w2 is for the reg operand
2851 */
2852 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \
2853 dtrace_get_modrm(x, &mode, ®, &r_m); \
2854 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2855 dtrace_get_operand(x, mode, r_m, wbit, vbit); \
2856 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \
2857 }
2859 /*
2860 * Similar, but for 2 operands plus an immediate.
2861 * vbit indicates direction
2862 * 0 for "opcode imm, r, r_m" or
2863 * 1 for "opcode imm, r_m, r"
2864 */
2865 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \
2866 dtrace_get_modrm(x, &mode, ®, &r_m); \
2867 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2868 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \
2869 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \
2870 dtrace_imm_opnd(x, wbit, immsize, 0); \
2871 }
2873 /*
2874 * Similar, but for 2 operands plus two immediates.
2875 */
2876 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \
2877 dtrace_get_modrm(x, &mode, ®, &r_m); \
2878 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2879 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2880 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \
2881 dtrace_imm_opnd(x, wbit, immsize, 1); \
2882 dtrace_imm_opnd(x, wbit, immsize, 0); \
2883 }
2885 /*
2886 * 1 operands plus two immediates.
2887 */
2888 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \
2889 dtrace_get_modrm(x, &mode, ®, &r_m); \
2890 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \
2891 dtrace_get_operand(x, mode, r_m, wbit, 2); \
2892 dtrace_imm_opnd(x, wbit, immsize, 1); \
2893 dtrace_imm_opnd(x, wbit, immsize, 0); \
2894 }
2896 /*
2897 * Dissassemble a single x86 or amd64 instruction.
2898 *
2899 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64)
2900 * for interpreting instructions.
2901 *
2902 * returns non-zero for bad opcode
2903 */
2904 int
2906 {
2908 #ifdef DIS_TEXT
2909 uint_t i;
2910 #endif
2911 #ifdef DIS_MEM
2913 #define NOMEM (nomem = 1)
2914 #else
2916 #endif
2921 uint_t vbit;
2935 /*
2936 * legacy prefixes come in 5 flavors, you should have only one of each
2937 */
2945 /*
2946 * Intel VEX instruction encoding prefix and fields
2947 */
2949 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */
2952 /*
2953 * VEX prefix byte 1, includes vex.r, vex.x and vex.b
2954 * (for 3 bytes prefix)
2955 */
2958 /*
2959 * For 32-bit mode, it should prefetch the next byte to
2960 * distinguish between AVX and les/lds
2961 */
2971 uint_t vex_L;
2974 #ifdef DIS_TEXT
2975 /* Instruction name for BLS* family of instructions */
2977 #endif
2981 instable_t dp_mmx;
2986 #ifdef DIS_TEXT
2996 }
2997 #endif
3012 }
3014 /*
3015 * Get one opcode byte and check for zero padding that follows
3016 * jump tables.
3017 */
3023 #ifdef DIS_TEXT
3025 #endif
3027 }
3029 /*
3030 * Gather up legacy x86 prefix bytes.
3031 */
3046 #ifdef DIS_TEXT
3048 #endif
3058 }
3064 }
3066 /*
3067 * Handle amd64 mode PREFIX values.
3068 * Some of the segment prefixes are no-ops. (only FS/GS actually work)
3069 * We might have a REX prefix (opcodes 0x40-0x4f)
3070 */
3082 /* AVX instructions */
3085 }
3087 /* LDS, LES or AVX */
3092 /* AVX */
3097 }
3098 }
3104 }
3109 /*
3110 * The vex.x and vex.b bits are not defined in two bytes
3111 * mode vex prefix, their default values are 1
3112 */
3138 }
3144 }
3168 /* Only these three vex_m values valid; others are reserved */
3180 &dis_opAVX660F
3184 &dis_opAVX660F38
3188 &dis_opAVX660F3A
3192 }
3197 &dis_opAVXF30F
3201 &dis_opAVXF30F38
3205 }
3210 &dis_opAVXF20F
3214 &dis_opAVXF20F3A
3218 &dis_opAVXF20F38
3222 }
3228 }
3229 }
3240 }
3241 }
3242 }
3244 /*
3245 * Deal with selection of operand and address size now.
3246 * Note that the REX.W bit being set causes opnd_size_prefix to be
3247 * ignored.
3248 */
3267 }
3268 /*
3269 * The pause instruction - a repz'd nop. This doesn't fit
3270 * with any of the other prefix goop added for SSE, so we'll
3271 * special-case it here.
3272 */
3276 }
3278 /*
3279 * Some 386 instructions have 2 bytes of opcode before the mod_r/m
3280 * byte so we may need to perform a table indirection.
3281 */
3287 uint_t subcode;
3305 #ifdef DIS_TEXT
3308 #endif
3317 }
3322 /* SSSE3 MMX instructions */
3326 #ifdef DIS_MEM
3328 #endif
3329 }
3333 }
3340 /*
3341 * Both crc32 and movbe have the same 3rd opcode
3342 * byte of either 0xF0 or 0xF1, so we use another
3343 * indirection to distinguish between the two.
3344 */
3350 /* It is movbe */
3351 dp++;
3352 }
3353 }
3355 /*
3356 * The adx family of instructions (adcx and adox)
3357 * continue the classic Intel tradition of abusing
3358 * arbitrary prefixes without actually meaning the
3359 * prefix bit. Therefore, if we find either the
3360 * opnd_size_prefix or rep_prefix we end up zeroing it
3361 * out after making our determination so as to ensure
3362 * that we don't get confused and accidentally print
3363 * repz prefixes and the like on these instructions.
3364 *
3365 * In addition, these instructions are actually much
3366 * closer to AVX instructions in semantics. Importantly,
3367 * they always default to having 32-bit operands.
3368 * However, if the CPU is in 64-bit mode, then and only
3369 * then, does it use REX.w promotes things to 64-bits
3370 * and REX.r allows 64-bit mode to use register r8-r15.
3371 */
3376 /* It is adox */
3377 dp++;
3380 /* It isn't adcx */
3382 }
3388 }
3390 #ifdef DIS_TEXT
3393 #endif
3403 }
3407 /* SSSE3 MMX instructions */
3411 #ifdef DIS_MEM
3413 #endif
3414 }
3419 }
3425 }
3429 }
3432 }
3433 }
3435 /*
3436 * If still not at a TERM decode entry, then a ModRM byte
3437 * exists and its fields further decode the instruction.
3438 */
3446 /*
3447 * decode 287 instructions (D8-DF) from opcodeN
3448 */
3461 else
3466 }
3467 }
3469 /*
3470 * In amd64 bit mode, ARPL opcode is changed to MOVSXD
3471 * (sign extend 32bit to 64 bit)
3472 */
3477 /*
3478 * at this point we should have a correct (or invalid) opcode
3479 */
3486 /*
3487 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do
3488 * need to include UNKNOWN below, as we may have instructions that
3489 * actually have a prefix, but don't exist in any other form.
3490 */
3509 /*
3510 * This is horrible. Some SIMD instructions take the
3511 * form 0x0F 0x?? ..., which is easily decoded using the
3512 * existing tables. Other SIMD instructions use various
3513 * prefix bytes to overload existing instructions. For
3514 * Example, addps is F0, 58, whereas addss is F3 (repz),
3515 * F0, 58. Presumably someone got a raise for this.
3516 *
3517 * If we see one of the instructions which can be
3518 * modified in this way (if we've got one of the SIMDO*
3519 * address modes), we'll check to see if the last prefix
3520 * was a repz. If it was, we strip the prefix from the
3521 * mnemonic, and we indirect using the dis_opSIMDrepz
3522 * table.
3523 */
3525 /*
3526 * Calculate our offset in dis_op0F
3527 */
3534 /*
3535 * Rewrite if this instruction used one of the magic prefixes.
3536 */
3540 else
3548 }
3552 /*
3553 * More horribleness: the group 9 (0xF0 0xC7) instructions are
3554 * allowed an optional prefix of 0x66 or 0xF3. This is similar
3555 * to the SIMD business described above, but with a different
3556 * addressing mode (and an indirect table), so we deal with it
3557 * separately (if similarly).
3558 *
3559 * Intel further complicated this with the release of Ivy Bridge
3560 * where they overloaded these instructions based on the ModR/M
3561 * bytes. The VMX instructions have a mode of 0 since they are
3562 * memory instructions but rdrand instructions have a mode of
3563 * 0b11 (REG_ONLY) because they only operate on registers. While
3564 * there are different prefix formats, for now it is sufficient
3565 * to use a single different table.
3566 */
3568 /*
3569 * Calculate our offset in dis_op0FC7 (the group 9 table)
3570 */
3577 /*
3578 * If we have a mode of 0b11 then we have to rewrite this.
3579 */
3584 }
3586 /*
3587 * Rewrite if this instruction used one of the magic prefixes.
3588 */
3592 else
3601 /*
3602 * We have xsavec (4) or xsaves (5), so rewrite.
3603 */
3606 }
3611 /*
3612 * As with the "normal" SIMD instructions, the MMX
3613 * shuffle instructions are overloaded. These
3614 * instructions, however, are special in that they use
3615 * an extra byte, and thus an extra table. As of this
3616 * writing, they only use the opnd_size prefix.
3617 */
3619 /*
3620 * Calculate our offset in dis_op0F7123
3621 */
3633 }
3639 /*
3640 * Calculate our offset in dis_op0F
3641 */
3653 }
3654 }
3656 }
3658 /*
3659 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64.
3660 */
3665 #ifdef DIS_TEXT
3666 /*
3667 * At this point most instructions can format the opcode mnemonic
3668 * including the prefixes.
3669 */
3689 OPLEN);
3691 /* opmask instructions */
3694 /* It's a kunpck. */
3699 /* vex_prefix == VEX_3bytes */
3702 }
3704 /* It's a kshift[l|r]. */
3711 /* W == 1 */
3715 }
3717 /* if (vex_prefix == VEX_2bytes) { */
3723 OPLEN);
3725 /* vex_prefix == VEX_3bytes */
3728 }
3729 }
3733 /* It's a cmovx.yy. Replace the suffix x */
3737 }
3742 /*
3743 * To handle PINSRD and PEXTRD
3744 */
3748 OPLEN);
3749 }
3750 }
3751 }
3752 #endif
3754 /*
3755 * Process operands based on the addressing modes.
3756 */
3758 /*
3759 * In vex mode the rex_prefix has no meaning
3760 */
3767 /*
3768 * amd64 instruction to sign extend 32 bit reg/mem operands
3769 * into 64 bit register values
3770 */
3772 #ifdef DIS_TEXT
3775 #endif
3785 /*
3786 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF)
3787 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7)
3788 * wbit lives in 2nd byte, note that operands
3789 * are different sized
3790 */
3793 /* target register size = 64 bit */
3795 }
3829 /* reg -> mem */
3833 /* mem -> reg */
3836 }
3839 /*
3840 * imul instruction, with either 8-bit or longer immediate
3841 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s)
3842 */
3849 /* memory or register operand to register, with 'w' bit */
3856 /* register to memory or register operand, with 'w' bit */
3857 /* arpl happens to fit here also because it is odd */
3861 else
3866 /* xaddb instruction */
3872 /* MMX register to memory or register operand */
3875 #ifdef DIS_TEXT
3877 #else
3879 #endif
3883 /* MMX register to memory */
3892 /* Double shift. Has immediate operand specifying the shift. */
3902 /*
3903 * Double shift. With no immediate operand, specifies using %cl.
3904 */
3910 /* immediate to memory or register operand */
3915 /*
3916 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83
3917 */
3921 /* immediate to memory or register operand with the */
3922 /* 'w' bit present */
3931 /* immediate to register with register in low 3 bits */
3932 /* of op code */
3934 /* w-bit here (with regs) is bit 3 */
3944 /* MMX immediate shift of register */
3950 /* SIMD immediate shift of register */
3953 mm_shift:
3958 NOMEM;
3961 /* accumulator to memory operand */
3964 /*FALLTHROUGH*/
3966 /* memory operand to accumulator */
3971 #ifdef DIS_TEXT
3973 #endif
3977 /* segment register to memory or register operand */
3980 /*FALLTHROUGH*/
3982 /* memory or register operand to segment register */
3990 /*
3991 * rotate or shift instructions, which may shift by 1 or
3992 * consult the cl register, depending on the 'v' bit
3993 */
3999 #ifdef DIS_TEXT
4006 }
4007 #endif
4009 /*
4010 * immediate rotate or shift instructions
4011 */
4014 normal_imm_mem:
4020 /* bit test instructions */
4025 /* single memory or register operand with 'w' bit present */
4028 just_mem:
4036 #ifdef DIS_TEXT
4038 #endif
4039 NOMEM;
4042 #ifdef DIS_TEXT
4044 #endif
4045 NOMEM;
4047 }
4049 /*FALLTHROUGH*/
4051 /* prefetch instruction - memory operand, but no memory acess */
4053 NOMEM;
4054 /*FALLTHROUGH*/
4056 /* single memory or register operand */
4062 /* single memory or register byte operand */
4069 #ifdef DIS_TEXT
4087 }
4090 #else
4093 #endif
4095 NOMEM;
4097 }
4098 /*FALLTHROUGH*/
4101 #if DIS_TEXT
4129 }
4132 #endif
4133 NOMEM;
4135 }
4136 /*FALLTHROUGH*/
4140 #ifdef DIS_TEXT
4142 #endif
4143 NOMEM;
4146 #ifdef DIS_TEXT
4148 #endif
4149 NOMEM;
4152 #ifdef DIS_TEXT
4154 #endif
4155 NOMEM;
4158 #ifdef DIS_TEXT
4160 #endif
4161 NOMEM;
4165 }
4166 }
4167 /*FALLTHROUGH*/
4171 #ifdef DIS_TEXT
4173 #endif
4174 NOMEM;
4177 #ifdef DIS_TEXT
4179 #endif
4180 NOMEM;
4184 }
4186 }
4187 /*FALLTHROUGH*/
4189 /* Similar to M, but only memory (no direct registers) */
4198 /* move special register to register or reverse if vbit */
4204 /*FALLTHROUGH*/
4211 /*FALLTHROUGH*/
4218 /*FALLTHROUGH*/
4223 }
4228 NOMEM;
4231 /*
4232 * single register operand with register in the low 3
4233 * bits of op code
4234 */
4238 else
4242 NOMEM;
4245 /*
4246 * register to accumulator with register in the low 3
4247 * bits of op code, xchg instructions
4248 */
4250 NOMEM;
4257 /*
4258 * single segment register operand, with register in
4259 * bits 3-4 of op code byte
4260 */
4262 NOMEM;
4267 /*
4268 * single segment register operand, with register in
4269 * bits 3-5 of op code
4270 */
4272 NOMEM;
4273 /* long seg reg from opcode */
4278 /* memory or register operand to register */
4292 /* MMX/SIMD-Int memory or mm reg to mm reg */
4295 #ifdef DIS_TEXT
4297 #else
4299 #endif
4304 #ifdef DIS_TEXT
4306 #else
4308 #endif
4319 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */
4325 xmm3p:
4332 NOMEM;
4340 /* MMX/SIMD-Int predicated r32/mem to mm reg */
4349 xmmprm:
4353 /* MMX/SIMD-Int predicated mm/mem to mm reg */
4359 /* MMX/SIMD-Int mm reg to r32 */
4361 NOMEM;
4369 /* SIMD memory or xmm reg operand to xmm reg */
4381 #ifdef DIS_TEXT
4382 /*
4383 * movlps and movhlps share opcodes. They differ in the
4384 * addressing modes allowed for their operands.
4385 * movhps and movlhps behave similarly.
4386 */
4392 }
4393 #endif
4398 /* SIMD xmm reg to memory or xmm reg */
4404 #ifdef DIS_TEXT
4410 #endif
4415 /* SIMD memory to xmm reg */
4421 #ifdef DIS_TEXT
4425 else
4427 }
4428 #endif
4432 /* SIMD memory or r32 to xmm reg */
4443 /* SIMD memory or mm reg to xmm reg */
4445 /* SIMD mm to xmm */
4451 /* SIMD memory or xmm reg to mm reg */
4460 /* SIMD memory or xmm reg to r32 */
4466 /* SIMD xmm to r32 */
4475 NOMEM;
4478 /* SIMD predicated memory or xmm reg with/to xmm reg */
4487 #ifdef DIS_TEXT
4488 /*
4489 * cmpps and cmpss vary their instruction name based
4490 * on the value of imm8. Other XMMP instructions,
4491 * such as shufps, require explicit specification of
4492 * the predicate.
4493 */
4505 OPLEN);
4508 OPLEN);
4512 }
4514 /*
4515 * The pclmulqdq instruction has a series of alternate names for
4516 * various encodings of the immediate byte. As such, if we
4517 * happen to find it and the immediate value matches, we'll
4518 * rewrite the mnemonic.
4519 */
4525 OPLEN);
4529 OPLEN);
4533 OPLEN);
4537 OPLEN);
4542 }
4549 }
4550 }
4551 #endif
4557 NOMEM;
4562 NOMEM;
4565 /* immediate operand to accumulator */
4570 NOMEM;
4573 /* memory or register operand to accumulator */
4580 /* si register to di register used to reference memory */
4582 #ifdef DIS_TEXT
4587 OPLEN);
4589 OPLEN);
4592 OPLEN);
4594 OPLEN);
4597 OPLEN);
4599 OPLEN);
4600 }
4601 #endif
4605 /* accumulator to di register */
4608 #ifdef DIS_TEXT
4614 OPLEN);
4617 OPLEN);
4618 else
4620 OPLEN);
4621 #endif
4624 /* si register to accumulator */
4627 #ifdef DIS_TEXT
4632 OPLEN);
4635 OPLEN);
4636 else
4638 OPLEN);
4640 #endif
4643 /*
4644 * single operand, a 16/32 bit displacement
4645 */
4649 NOMEM;
4652 /* jmp/call indirect to memory or register operand */
4654 #ifdef DIS_TEXT
4656 #endif
4662 /*
4663 * for long jumps and long calls -- a new code segment
4664 * register and an offset in IP -- stored in object
4665 * code in reverse order. Note - not valid in amd64
4666 */
4671 #ifdef DIS_TEXT
4673 #endif
4674 /* will now get segment operand */
4678 /*
4679 * jmp/call. single operand, 8 bit displacement.
4680 * added to current EIP in 'compofff'
4681 */
4684 NOMEM;
4687 /* single 32/16 bit immediate operand */
4693 /* single 8 bit immediate operand */
4713 }
4717 /* 16-bit immediate operand */
4723 /* single 8 bit port operand */
4727 NOMEM;
4730 /* single operand, dx register (variable port instruction) */
4734 #ifdef DIS_TEXT
4736 #endif
4737 NOMEM;
4740 /*
4741 * The int instruction, which has two forms:
4742 * int 3 (breakpoint) or
4743 * int n, where n is indicated in the subsequent
4744 * byte (format Ib). The int 3 instruction (opcode 0xCC),
4745 * where, although the 3 looks like an operand,
4746 * it is implied by the opcode. It must be converted
4747 * to the correct base and output.
4748 */
4750 #ifdef DIS_TEXT
4755 #endif
4756 NOMEM;
4759 /* single 8 bit immediate operand */
4762 NOMEM;
4765 /* an unused byte must be discarded */
4770 NOMEM;
4774 #ifdef DIS_TEXT
4779 else
4781 #endif
4783 NOMEM;
4787 #ifdef DIS_TEXT
4792 else
4794 #endif
4796 NOMEM;
4800 /*
4801 * sfence is sfence if mode is REG_ONLY. If mode isn't
4802 * REG_ONLY, mnemonic should be 'clflush'.
4803 */
4806 /* sfence doesn't take operands */
4807 #ifdef DIS_TEXT
4814 NOMEM;
4815 }
4816 #else
4820 NOMEM;
4821 }
4822 #endif
4825 /*
4826 * no disassembly, the mnemonic was all there was so go on
4827 */
4831 NOMEM;
4832 /*FALLTHROUGH*/
4837 /*
4838 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but
4839 * differ in mode and reg.
4840 */
4844 /*
4845 * Only the following exact byte sequences are allowed:
4846 *
4847 * 0f ae e8 lfence
4848 * 0f ae f0 mfence
4849 */
4854 #ifdef DIS_TEXT
4861 }
4862 #endif
4865 }
4868 /* float reg */
4870 #ifdef DIS_TEXT
4874 #endif
4875 NOMEM;
4878 /* float reg to float reg, with ret bit present */
4881 /*FALLTHROUGH*/
4883 #ifdef DIS_TEXT
4888 #endif
4889 NOMEM;
4892 /* AVX instructions */
4894 /* op(ModR/M.r/m) */
4897 #ifdef DIS_TEXT
4900 #endif
4906 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */
4911 /*
4912 * In classic Intel fashion, the opcodes for all of the FMA
4913 * instructions all have two possible mnemonics which vary by
4914 * one letter, which is selected based on the value of the wbit.
4915 * When wbit is one, they have the 'd' suffix and when 'wbit' is
4916 * 0, they have the 's' suffix. Otherwise, the FMA instructions
4917 * are all a standard VEX_RMrX.
4918 */
4919 #ifdef DIS_TEXT
4926 }
4927 }
4928 #endif
4933 /* vmovsd <m64>, <xmm> */
4934 /* or vmovss <m64>, <xmm> */
4937 }
4938 }
4941 /*
4942 * VEX prefix uses the 1's complement form to encode the
4943 * XMM/YMM regs
4944 */
4949 /*
4950 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>,
4951 * <xmm>, <xmm>
4952 */
4954 }
4955 #ifdef DIS_TEXT
4962 }
4963 #endif
4969 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */
4975 /*
4976 * VEX prefix uses the 1's complement form to encode the
4977 * XMM/YMM regs
4978 */
4985 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */
4989 /*
4990 * All instructions that use VSIB are currently a mess. See the
4991 * comment around the dis_gather_regs_t structure definition.
4992 */
4996 #ifdef DIS_TEXT
5000 #endif
5006 /*
5007 * VEX prefix uses the 1's complement form to encode the
5008 * XMM/YMM regs
5009 */
5016 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
5025 /* vmovsd <xmm>, <m64> */
5026 /* or vmovss <xmm>, <m64> */
5029 }
5030 }
5038 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */
5046 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */
5050 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */
5051 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */
5054 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */
5055 #ifdef DIS_TEXT
5058 #endif
5062 }
5064 /* one byte immediate number */
5067 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */
5071 #ifdef DIS_TEXT
5073 #endif
5075 #ifdef DIS_TEXT
5079 else
5082 #endif
5083 }
5087 /* ModR/M.reg := op(ModR/M.rm) */
5092 L_VEX_MX:
5097 /* vcvtpd2dq <ymm>, <xmm> */
5098 /* or vcvtpd2ps <ymm>, <xmm> */
5099 /* or vcvttpd2dq <ymm>, <xmm> */
5111 /* vcvtdq2pd <xmm>, <ymm> */
5112 /* or vcvtps2pd <xmm>, <ymm> */
5113 /* or vcvtph2ps <xmm>, <ymm> */
5114 /* or vbroadcasts* <xmm>, <ymm> */
5118 /* vmovd/q <reg/mem 32/64>, <xmm> */
5119 #ifdef DIS_TEXT
5122 #endif
5128 }
5133 /* ModR/M.reg := op(ModR/M.rm, imm8) */
5142 /* one byte immediate number */
5147 /* VEX.vvvv := op(ModR/M.rm, imm8) */
5151 #ifdef DIS_TEXT
5153 OPLEN);
5154 #endif
5160 /* one byte immediate number */
5165 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */
5167 /* vpextrw <imm8>, <xmm>, <reg> */
5173 }
5186 /* opmask: mod_rm := %k */
5195 /* opmask: mod_reg := mod_rm */
5204 }
5208 /* opmask: mod_reg := mod_rm */
5217 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */
5227 /* ModR/M.rm := op(ModR/M.reg) */
5228 /* vextractf128 || vcvtps2ph */
5239 /* one byte immediate number */
5242 }
5253 /* ModR/M.rm := op(ModR/M.reg) */
5260 /* vmovd/q <reg/mem 32/64>, <xmm> */
5261 #ifdef DIS_TEXT
5264 #endif
5273 /* ModR/M.rm := op(ModR/M.reg, imm) */
5279 #ifdef DIS_TEXT
5281 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */
5284 }
5285 #endif
5289 /* one byte immediate number */
5293 /* ModR/M.rm := op(ModR/M.reg, imm) */
5301 /* one byte immediate number */
5306 /* ModR/M.rm := op(ModR/M.reg) */
5315 /* one byte immediate number */
5318 }
5323 L_VEX_RM:
5331 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */
5337 /* VEX use the 1's complement form encode the XMM/YMM regs */
5343 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */
5354 #ifdef DIS_TEXT
5357 #endif
5361 /*
5362 * The BLS instructions are VEX instructions that are based on
5363 * VEX.0F38.F3; however, they are considered special group 17
5364 * and like everything else, they use the bits in 3-5 of the
5365 * MOD R/M to determine the sub instruction. Unlike many others
5366 * like the VMX instructions, these are valid both for memory
5367 * and register forms.
5368 */
5375 #ifdef DIS_TEXT
5377 #endif
5380 #ifdef DIS_TEXT
5382 #endif
5385 #ifdef DIS_TEXT
5387 #endif
5391 }
5394 #ifdef DIS_TEXT
5396 #endif
5400 }
5401 /* an invalid op code */
5407 NOMEM;
5414 done:
5415 #ifdef DIS_MEM
5416 /*
5417 * compute the size of any memory accessed by the instruction
5418 */
5432 }
5437 /*
5438 * In 64 bit mode descriptor table entries
5439 * go up to 10 bytes and popf/pushf are always 8 bytes
5440 */
5446 else
5457 else
5465 }
5466 #endif
5469 error:
5470 #ifdef DIS_TEXT
5472 #endif
5474 }
5476 #ifdef DIS_TEXT
5478 /*
5479 * Some instructions should have immediate operands printed
5480 * as unsigned integers. We compare against this table.
5481 */
5485 0
5486 };
5489 static int
5491 {
5496 /*
5497 * Work back to start of last mnemonic, since we may have
5498 * prefixes on some opcodes.
5499 */
5512 }
5514 }
5516 /*
5517 * Print a numeric immediate into end of buf, maximum length buflen.
5518 * The immediate may be an address or a displacement. Mask is set
5519 * for address size. If the immediate is a "small negative", or
5520 * if it's a negative displacement of any magnitude, print as -<absval>.
5521 * Respect the "octal" flag. "Small negative" is defined as "in the
5522 * interval [NEG_LIMIT, 0)".
5523 *
5524 * Also, "isunsigned_op()" instructions never print negatives.
5525 *
5526 * Return whether we decided to print a negative value or not.
5527 */
5529 #define NEG_LIMIT -255
5533 static int
5536 {
5553 else
5558 }
5559 }
5562 static int
5564 {
5570 }
5572 }
5574 /* ARGSUSED */
5575 void
5578 {
5592 /*
5593 * For PC-relative jumps, the pc is really the next pc after executing
5594 * this instruction, so increment it appropriately.
5595 */
5606 /*
5607 * sv is for the signed, possibly-truncated immediate or
5608 * displacement; usv retains the original size and
5609 * unsignedness for symbol lookup.
5610 */
5614 /*
5615 * About masks: for immediates that represent
5616 * addresses, the appropriate display size is
5617 * the effective address size of the instruction.
5618 * This includes MODE_OFFSET, MODE_IPREL, and
5619 * MODE_RIPREL. Immediates that are simply
5620 * immediate values should display in the operand's
5621 * size, however, since they don't represent addresses.
5622 */
5624 /* d86_addr_size is SIZEnn, which is log2(real size) */
5627 /* d86_value_size and d86_imm_bytes are in bytes */
5647 buflen);
5652 }
5659 /*
5660 * We printed a negative value for an
5661 * immediate that wasn't a
5662 * displacement. Note that fact so we can
5663 * print the positive value as an
5664 * annotation.
5665 */
5669 }
5686 }
5694 }
5695 }
5697 /*
5698 * The symbol lookups may result in false positives,
5699 * particularly on object files, where small numbers may match
5700 * the 0-relative non-relocated addresses of symbols.
5701 */
5712 }
5714 /*
5715 * If we printed a negative immediate above, print the
5716 * positive in case our heuristic was unhelpful
5717 */
5723 }
5724 }
5727 /* Print symbol or effective address for reltgt */
5734 }
5735 }