usr/src/uts/i86pc/os/pci_neptune.c

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 #pragma ident   "%Z%%M% %I%     %E% SMI"
  28
  29 /*
  30  * Support for Intel "Neptune" PCI chip set
  31  */
  32
  33 #include <sys/types.h>
  34 #include <sys/pci.h>
  35 #include <sys/pci_impl.h>
  36 #include <sys/sunddi.h>
  37 #include <sys/pci_cfgspace_impl.h>
  38
  39 /*
  40  * This variable is a place holder for the initial value in PCI_PMC register
  41  * of neptune chipset.
  42  */
  43 static unsigned char neptune_BIOS_cfg_method = 0;
  44
  45 /*
  46  * Special hack for Intel's Neptune chipset, 82433NX and 82434NX.
  47  *
  48  * The motherboards I've seen still use a version of the BIOS
  49  * that operates using Configuration Mechanism #2 like the older
  50  * Mercury BIOS and chipset (the 82433LX and 82434LX).
  51  *
  52  */
  53 boolean_t
  54 pci_check_neptune(void)
  55 {
  56         uint8_t         oldstatus;
  57         uint32_t        tmp;
  58
  59         /* enable the config address space, bus=0 function=0 */
  60         oldstatus = inb(PCI_CSE_PORT);
  61         outb(PCI_CSE_PORT, PCI_MECH2_CONFIG_ENABLE);
  62         outb(PCI_FORW_PORT, 0);
  63
  64         /*
  65          * First check the vendor and device ids of the Host to
  66          * PCI bridge. But it isn't sufficient just to do this check
  67          * because the same device ID can refer to either
  68          * the Neptune or Mercury chipset.
  69          */
  70
  71         /* check the vendor id, the device id, and the revision id */
  72         /* the Neptune revision ID == 0x11, allow 0x1? */
  73         if ((inl(PCI_CADDR2(0, PCI_CONF_VENID)) != 0x04a38086) ||
  74                 (inb(PCI_CADDR2(0, PCI_CONF_REVID)) & 0xf0) != 0x10) {
  75                 /* disable mechanism #2 config address space */
  76                 outb(PCI_CSE_PORT, oldstatus);
  77                 return (B_FALSE);
  78         }
  79
  80         /* disable mechanism #2 config address space */
  81         outb(PCI_CSE_PORT, oldstatus);
  82
  83         /*
  84          * Now I know that the bridge *might* be a Neptune (it could be
  85          * a Mercury chip.) Try enabling mechanism #1 to differentiate
  86          * between the two chipsets.
  87          */
  88
  89         /*
  90          * save the old value in case it's not Neptune (the Mercury
  91          * chip has the deturbo and reset bits in the 0xcf9 register
  92          * and the forward register at 0xcfa)
  93          */
  94         tmp = inl(PCI_CONFADD);
  95
  96         /*
  97          * The Intel Neptune chipset defines this extra register
  98          * to enable Config Mechanism #1.
  99          */
 100         neptune_BIOS_cfg_method = inb(PCI_PMC);
 101         outb(PCI_PMC, neptune_BIOS_cfg_method | 1);
 102
 103         /* make certain mechanism #1 works correctly */
 104         /* check the vendor and device id's of the Host to PCI bridge */
 105         outl(PCI_CONFADD, PCI_CADDR1(0, 0, 0, PCI_CONF_VENID));
 106         if (inl(PCI_CONFDATA) != ((0x04a3 << 16) | 0x8086)) {
 107                 outb(PCI_PMC, neptune_BIOS_cfg_method);
 108                 outl(PCI_CONFADD, tmp);
 109                 return (B_FALSE);
 110         }
 111         outb(PCI_PMC, neptune_BIOS_cfg_method);
 112         return (B_TRUE);
 113 }
 114
 115 static void
 116 pci_neptune_enable()
 117 {
 118         /*
 119          * Switch the chipset to use Mechanism 1.
 120          */
 121         mutex_enter(&pcicfg_chipset_mutex);
 122         outb(PCI_PMC, neptune_BIOS_cfg_method | 1);
 123 }
 124
 125 static void
 126 pci_neptune_disable()
 127 {
 128         /*
 129          * The Neptune chipset has a bug that if you write the PMC,
 130          * it erroneously looks at some of the bits in the latches for
 131          * adjacent registers... like, say, the "reset" bit.  We zero
 132          * out the config address register to work around this bug.
 133          */
 134         outl(PCI_CONFADD, PCI_CADDR1(0, 0, 0, 0));
 135         outb(PCI_PMC, neptune_BIOS_cfg_method);
 136         mutex_exit(&pcicfg_chipset_mutex);
 137 }
 138
 139 uint8_t
 140 pci_neptune_getb(int bus, int device, int function, int reg)
 141 {
 142         uint8_t val;
 143
 144         pci_neptune_enable();
 145
 146         val = pci_mech1_getb(bus, device, function, reg);
 147
 148         pci_neptune_disable();
 149         return (val);
 150 }
 151
 152 uint16_t
 153 pci_neptune_getw(int bus, int device, int function, int reg)
 154 {
 155         uint16_t val;
 156
 157         pci_neptune_enable();
 158
 159         val = pci_mech1_getw(bus, device, function, reg);
 160
 161         pci_neptune_disable();
 162         return (val);
 163 }
 164
 165 uint32_t
 166 pci_neptune_getl(int bus, int device, int function, int reg)
 167 {
 168         uint32_t val;
 169
 170         pci_neptune_enable();
 171
 172         val = pci_mech1_getl(bus, device, function, reg);
 173
 174         pci_neptune_disable();
 175         return (val);
 176 }
 177
 178 void
 179 pci_neptune_putb(int bus, int device, int function, int reg, uint8_t val)
 180 {
 181         pci_neptune_enable();
 182
 183         pci_mech1_putb(bus, device, function, reg, val);
 184
 185         pci_neptune_disable();
 186 }
 187
 188 void
 189 pci_neptune_putw(int bus, int device, int function, int reg, uint16_t val)
 190 {
 191         pci_neptune_enable();
 192
 193         pci_mech1_putw(bus, device, function, reg, val);
 194
 195         pci_neptune_disable();
 196 }
 197
 198 void
 199 pci_neptune_putl(int bus, int device, int function, int reg, uint32_t val)
 200 {
 201         pci_neptune_enable();
 202
 203         pci_mech1_putl(bus, device, function, reg, val);
 204
 205         pci_neptune_disable();
 206 }