usr/src/uts/sun/io/eri/eri_phy.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
  24  * All rights reserved.
  25  */
  26
  27 #ifndef _SYS_ERI_PHY_H
  28 #define _SYS_ERI_PHY_H
  29
  30 #pragma ident   "%Z%%M% %I%     %E% SMI"
  31
  32 #ifdef  __cplusplus
  33 extern "C" {
  34 #endif
  35
  36 /*
  37  * MII supports a 16-bit register stack of upto 32, addressable through the
  38  * MDIO and MDC serial port.
  39  */
  40 #define ERI_PHY_BMCR    00      /* Basic Mode Control Register */
  41 #define ERI_PHY_BMSR    01      /* Basic Mode Status Register */
  42 #define ERI_PHY_IDR1    02      /* PHY Identifier Register 1 */
  43 #define ERI_PHY_IDR2    03      /* PHY Identifier Register 2 */
  44 #define ERI_PHY_ANAR    04      /* Auto-Negotiation Advertisement Register */
  45 #define ERI_PHY_ANLPAR  05      /* Auto-Negotiation Link Partner Ability Reg */
  46 #define ERI_PHY_ANER    06      /* Auto-Negotiation Expansion Register */
  47
  48 /* Registers 7-15 are reserved for future assignments by MII working group */
  49 /* Do not write to these registers */
  50
  51 /* Registers 16-17 are reserved for future assignment by Vendor */
  52 /* Do not write to these registers */
  53
  54 #define ERI_PHY_DIS     18      /* Disconnect Counter */
  55 #define ERI_PHY_FCSC    19      /* False Carrier Sense Counter */
  56 #define ERI_PHY_NWAYTR  20      /* NWay Test Register */
  57 #define ERI_PHY_REC     21      /* RX_ER Counter */
  58 #define ERI_PHY_SRR     22      /* Silicon Revision Register */
  59 #define ERI_PHY_CSC     23      /* CS Configuration Register */
  60 #define ERI_PHY_LBREMR  24      /* Loopback, Bypass, Receiver Error Mask Reg */
  61 #define ERI_PHY_AR      25      /* PHY Address Register */
  62 #define ERI_PHY_VRES1   26      /* Reserverd for future assignement by vendor */
  63 #define ERI_PHY_TPISR   27      /* 10 Mbps TPI Status Register */
  64 #define ERI_PHY_NICR    28      /* 10 Mbps Network I/F Configuration Register */
  65
  66 /* Registers 29-31 are reserved for future assignment by Vendor */
  67 /* Do not write to these registers */
  68
  69
  70 /* ************************************************************************ */
  71 /*  Register 00  Basic Mode Control Register */
  72
  73 #define PHY_BMCR_RESET  (1 << 15)       /* Reset */
  74 #define PHY_BMCR_LPBK   (1 << 14)       /* Loopback of TXD<3:0> */
  75 #define PHY_BMCR_100M   (1 << 13)       /* Speed selection, 1=100Mbps */
  76 #define PHY_BMCR_ANE    (1 << 12)       /* Auto Negotiation Enable */
  77 #define PHY_BMCR_PWRDN  (1 << 11)       /* Power down */
  78 #define PHY_BMCR_ISOLATE (1 << 10)      /* Isolate PHY from MII */
  79 #define PHY_BMCR_RAN    (1 << 9)        /* Restart Auto Negotiation */
  80 #define PHY_BMCR_FDX    (1 << 8)        /* Full Duplex */
  81 #define PHY_BMCR_COLTST (1 << 7)        /* Collision Test */
  82 #define PHY_BMCR_RES1   (0x7f << 0)     /* 0-6 Reserved */
  83
  84 /* ************************************************************************ */
  85 /* Register 01   Basic Mode Status Register */
  86
  87 #define PHY_BMSR_100T4  (1 << 15)       /* PHY able to perform 100Base-T4 */
  88 #define PHY_BMSR_100FDX (1 << 14)       /* PHY able to perform 100Base-TX FDX */
  89 #define PHY_BMSR_100HDX (1 << 13)       /* PHY able to perform 100Base-TX HDX */
  90 #define PHY_BMSR_10FDX  (1 << 12)       /* PHY able to perform 10Base-T FDX */
  91 #define PHY_BMSR_10HDX  (1 << 11)       /* PHY able to perform 10Base-T HDX */
  92 #define PHY_BMSR_RES1   (0x1f << 6)     /* 6-10 reserved */
  93 #define PHY_BMSR_ANC    (1 << 5)        /* Auto Negotiation Completed */
  94 #define PHY_BMSR_REMFLT (1 << 4)        /* Remote Fault detected */
  95 #define PHY_BMSR_ACFG   (1 << 3)        /* Able to do Auto Link Negotiation */
  96 #define PHY_BMSR_LNKSTS (1 << 2)        /* Link Status */
  97 #define PHY_BMSR_JABDET (1 << 1)        /* Jabber Condition Detected */
  98 #define PHY_BMSR_EXTCAP (1 << 0)        /* Extended Register Capability */
  99
 100 #define PHY_CAPABILITY_MASK (PHY_BMSR_100FDX | PHY_BMSR_100HDX \
 101                                 | PHY_BMSR_10FDX | PHY_BMSR_10HDX)
 102
 103 /* ************************************************************************ */
 104 /*
 105  * Registers 2 and 3 provide a 32 bit value which is a unique identifier
 106  * for a particular type of PHY. A 24-bit Organizationally Unique Identifier
 107  * (OUI) is defined with bit 1 as the MSB and bit 24 as the LSB. Bits 3-18 of
 108  * the OUI are found in PHY Identifier Register 1 and bits 19-24 are found in
 109  * PHY Identifier Register 2.
 110  *
 111  * The hexadecimal OUI code for NSC is 0x080017 .
 112  */
 113 /* Register 02   PHY Identifier Register 1 */
 114
 115 /* Register 03   PHY Identifier Register 2 */
 116
 117 #define PHY_IDR2_OUILSB (0x3f << 10)    /* Bits 19-24 of OUI */
 118 #define PHY_IDR2_VNDMDL (0x3f << 4)     /* vendor Model no. */
 119 #define PHY_IDR2_MDLREV (0xf << 0)      /* Model revision no. */
 120
 121 /* ************************************************************************ */
 122 /*
 123  * Register 04  Auto-Negotiation Advertisement Register (nway1Reg)
 124  * This register will hold the different modes of operation to be advertised to
 125  * the far-end PHY.
 126  */
 127
 128 #define PHY_ANAR_NP     (1 << 15)       /* Next Page bit */
 129 #define PHY_ANAR_ACK    (1 << 14)       /* Acks reception of Link Partner */
 130                                         /* Capability word  */
 131 #define PHY_ANAR_RF     (1 << 13)       /* Advertise Remote Fault det. cap. */
 132 #define PHY_ANAR_RES1   (0x7 << 10)     /* 10-12 reserved */
 133 #define PHY_ANAR_T4     (1 << 9)        /* Advertise 100Base-T4 Capability */
 134 #define PHY_ANAR_TXFDX  (1 << 8)        /* Advertise 100Base-TX FDX Cap. */
 135 #define PHY_ANAR_TX     (1 << 7)        /* Advertise 100Base-TX Cap. */
 136 #define PHY_ANAR_10FDX  (1 << 6)        /* Advertise 10Base-T FDX Cap. */
 137 #define PHY_ANAR_10     (1 << 5)        /* Advertise 10Base-T Cap. */
 138 #define PHY_ANAR_SELECT (0x1f << 0)     /* Binary Encoded selector supported */
 139                                         /* this node. Currently only CSMA/CD */
 140                                         /* <00001> is specified  */
 141
 142 #define PHY_SELECTOR    1       /* Default selector for CSMA/CD */
 143 /*
 144  * Priority scheme (from highest to lowest) for Auto Link Negotiation:
 145  *      1 - 100Base-TX Full Duplex
 146  *      2 - 100Base-T4
 147  *      3 - 100Base-TX
 148  *      4 - 10Base-T Full Duplex
 149  *      5 - 10Base-T
 150  */
 151
 152 /* ************************************************************************ */
 153 /*
 154  * Register 05   Auto-Negotiation Link Partner Ability Reg
 155  * This register contains the Link Partners capabilities after NWay
 156  * Auto-Negotiation is complete.
 157  */
 158
 159 #define PHY_ANLPAR_NP   (1 << 15)       /* Next page Bit */
 160 #define PHY_ANLPAR_ACK  (1 << 14)       /* Link Partner acks reception of our */
 161                                         /* capability data word  */
 162 #define PHY_ANLPAR_RF   (1 << 13)       /* LP indicates Remote fault */
 163 #define PHY_ANLPAR_RES1 (0x7 << 10)     /* 10-12 reserved */
 164 #define PHY_ANLPAR_T4   (1 << 9)        /* 100Base-T4 supported by LP */
 165 #define PHY_ANLPAR_TXFDX (1 << 8)       /* 100Base-TX FDX supp. by LP */
 166 #define PHY_ANLPAR_TX   (1 << 7)        /* 100Base-TX supp. by LP */
 167 #define PHY_ANLPAR_10FDX (1 << 6)       /* 10Base-T FDX supp. by LP */
 168 #define PHY_ANLPAR_10   (1 << 5)        /* 10Base-T supp. by LP */
 169 #define PHY_ANLPAR_SELECT (0x1f << 0)   /* LP's binary encoded node selector */
 170                                         /* Currently only CSMA/CD is <00001> */
 171                                         /* is specified  */
 172
 173 /* ************************************************************************ */
 174 /*
 175  * Register 06   Auto-Negotiation Expansion Register
 176  * This register contains additional status for NWay Auto-Negotiation
 177  */
 178
 179 #define PHY_ANER_RES1   (0x7ff << 5)    /* 5-15 reserved */
 180 #define PHY_ANER_MLF    (1 << 4)        /* Multiple Link faults occured */
 181 #define PHY_ANER_LPNP   (1 << 3)        /* LP supports Next Page negotiation */
 182 #define PHY_ANER_NPABLE (1 << 2)        /* This node can send additional */
 183                                 /* Next Pages. Should be 0 for DP83840  */
 184 #define PHY_ANER_PAGERX (1 << 1)        /* new LINK Code Word Page recvd. */
 185 #define PHY_ANER_LPNW   (1 << 0)        /* LP supports NWay Auto-negotiation */
 186
 187
 188 /* ************************************************************************ */
 189
 190 /* Registers 7-15 are reserved for future assignments by MII working group */
 191 /* Do not write to these registers */
 192
 193 /* DP83840 - 10/100 Mbps Physical layer from National semiconductor */
 194 /* Registers 16-17 are reserved for future assignment by Vendor */
 195 /* Do not write to these registers */
 196
 197 /* ************************************************************************ */
 198
 199 /*
 200  * Register 18   Disconnect Counter
 201  * This 16-bit counter is incremented for every disconnect event. It rolls over
 202  * when full.
 203  */
 204
 205 /* ************************************************************************ */
 206 /*
 207  * Register 19   False Carrier Sense Counter
 208  * This 16-bit counter is incremented for each false carrier event (i.e. carrier
 209  * assertion without JK detect). It freezes when full.
 210  */
 211
 212 /* ************************************************************************ */
 213 /*
 214  * Register 20   NWay Test Register
 215  */
 216 #define PHY_NWAYTR_RES1 (0xff << 8)     /* 8-15 reserved */
 217 #define PHY_NWAYTR_LPBK (1 << 7)        /* Puts NWay into Loopback mode */
 218 #define PHY_NWAYTR_RES2 (0x7f << 0)     /* 0-6 reserved */
 219
 220 /* ************************************************************************ */
 221 /*
 222  * Register 21   RX_ER Counter
 223  * This 16-bit counter is incremented once per valid packet (i.e. no collision
 224  * occured during packet reception), if there is one or more receive error
 225  * condition during the packet reception. The counter is incremented at the end
 226  * of the packet reception.
 227  */
 228
 229 /* ************************************************************************ */
 230 /*
 231  * Register 22   Silicon Revision Register
 232  * Contains information on silicon revision
 233  * This register will be incremented for any change made to the device.
 234  */
 235 /* ************************************************************************ */
 236 /*
 237  * Register 23   CS Configuration Register
 238  */
 239
 240 #define PHY_CSCR_NRZIDIS (1 << 15)      /* NRZI disabled (for FDDI) */
 241 #define PHY_CSCR_RES1   (1 << 14)       /* reserved */
 242 #define PHY_CSCR_TOCDIS (1 << 13)       /* disable Timeout counter */
 243                                         /* in descrambler  */
 244 #define PHY_CSCR_REPTR  (1 << 12)       /* Mode1: Node = 0, repeater = 1 */
 245 #define PHY_CSCR_ENCSEL (1 << 11)       /* encoder: 0 = MLT-3, 1 = binary */
 246 #define PHY_CSCR_RES2   (0x7 << 8)      /* 8-10 reserved */
 247 #define PHY_CSCR_CLK25M (1 << 7)        /* Tristates CLK25M */
 248 #define PHY_CSCR_FLN100 (1 << 6)        /* 0 = force good link in 100Mbps */
 249 #define PHY_CSCR_FCONN  (1 << 5)        /* 1 = bypass disconnect function */
 250 #define PHY_CSCR_TXOFF  (1 << 4)        /* 1 = Pulls TD from phaser ckt low */
 251 #define PHY_CSCR_RES3   (1 << 3)        /* reserved */
 252 #define PHY_CSCR_CSTSEN (1 << 2)        /* LED1 pin for connection status */
 253 #define PHY_CSCR_10FDXE (1 << 1)        /* LED4 pin for 10Base-T FDX */
 254 #define PHY_CSCR_RES4   (1 << 0)        /* reserved */
 255
 256 /* ************************************************************************ */
 257 /*
 258  * Register 24   Loopback, Bypass, Receiver Error Mask Reg
 259  * The high byte of this register configures the DP83840 whilst its low byte
 260  * programs the receive error types to be reported in real time as a HEX code
 261  * across the MII RXD<3:0> interface.
 262  */
 263
 264 #define PHY_LBREMR_BPEB (1 << 15)       /* Bypass Elasticity buffer */
 265 #define PHY_LBREMR_BP4B5B (1 << 14)     /* Bypass 4B5B and 5B4B encoder */
 266 #define PHY_LBREMR_BPSCR (1 << 13)      /* Bypass scrambler/descrambler */
 267 #define PHY_LBREMR_BPALIGN (1 << 12)    /* Bypass symbol alignment ckt */
 268 #define PHY_LBREMR_EWRAP (1 << 11)      /* 10Base-T ENDEC Loopback */
 269 #define PHY_LBREMR_XWRAP (1 << 10)      /* 10Base-T Transceiver loopback */
 270 #define PHY_LBREMR_LB   (0x3 << 8)      /* Twister and remote loopback */
 271 #define PHY_LBREMR_RES1 (0x7 << 5)      /* Reserved */
 272 #define PHY_LBREMR_CODE (1 << 4)        /* Report det. of Code Error */
 273 #define PHY_LBREMR_PME  (1 << 3)        /* Report det. of Pre-mature End err */
 274 #define PHY_LBREMR_LINK (1 << 2)        /* Report det. of Link Error */
 275 #define PHY_LBREMR_PKT  (1 << 1)        /* Report det. of Packet error */
 276 #define PHY_LBREMR_EB   (1 << 0)        /* Report det. of Elasticty buf err */
 277
 278 /* ************************************************************************ */
 279 /*
 280  * Register 25   PHY Address Register
 281  */
 282
 283 #define PHY_AR_RES1     (0x1ff << 7)    /* reserved */
 284 #define PHY_AR_SPEED10  (1 << 6)        /* speed : 1 = 10 Mbps, 0 - 100 Mbps */
 285 #define PHY_AR_CONSTS   (1 << 5)        /* status of the disconnect function */
 286 #define PHY_AR_ADDR     (0x1f << 0)     /* PHY Address */
 287
 288 /*
 289  * The PHYAD<4:0> allow 32 unique PHY addresses. The PHYAD<4:0> share the RX_ER,
 290  * PHYAD3, CRS, ENCSEL ald LBEN pins of the PHY. By patching the PHYAD address
 291  * pins with a light pull-up or pull-down resistor, the PMD address can be
 292  * strobed and stored in these register location during Reset or Power-on reset
 293  * time.
 294  *
 295  * The first PHY address bit transmitted or received is the MSB of the address.
 296  * A PHY connected to a station management entity via an interface connector
 297  * shall always respond to PHY address < 00000 > . A station management entity
 298  * connected to multiple PHY entities must know the appropriate PHY address of
 299  * each PHY entity. PHY address should be set to < 00001 > for a single
 300  * PHY entity. A PHY address of < 00000 > will cause the Isolate bit 0: < 10 >
 301  * to be set to one.
 302  */
 303
 304 /* ************************************************************************ */
 305 /*
 306  * Register 26   Reserverd for future assignement by vendor
 307  */
 308
 309 /* ************************************************************************ */
 310 /*
 311  * Register 27   10 Mbps TPI Status Register
 312  */
 313
 314 #define PHY_TPISR_RES1  (0x3f << 10)    /* reserved */
 315 #define PHY_TPISR_10BTSER (1 << 9)      /* 10BASE-T Serial mode */
 316 #define PHY_TPISR_RES2  (0x1ff << 0)    /* reserved */
 317
 318 /* ************************************************************************ */
 319 /*
 320  * Register 28   10 Mbps Network I/F Configuration Register
 321  */
 322
 323 #define PHY_NICR_RES1   (0x3ff << 6)    /* reserved */
 324 #define PHY_NICR_LD     (1 << 5)        /* Link disable */
 325 #define PHY_NICR_HBE    (1 << 4)        /* Enable Heart beat function */
 326 #define PHY_NICR_UTP    (1 << 3)        /* 1 = UTP, 0 = STP */
 327 #define PHY_NICR_LSS    (1 << 2)        /* Low Squelch select */
 328 #define PHY_NICR_RES2   (1 << 1)        /* reserved */
 329 #define PHY_NICR_JBEN   (1 << 0)        /* Enables Jabber function  in FDX */
 330                                         /* or xwrap mode  */
 331
 332 /* ************************************************************************ */
 333
 334 /* Registers 29-31 are reserved for future assignment by Vendor */
 335 /* Do not write to these registers */
 336
 337 /* ************************************************************************ */
 338
 339 #ifdef  __cplusplus
 340 }
 341 #endif
 342
 343 #endif  /* _SYS_ERI_PHY_H */