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docs/how-to-build.md: use proper markup for directory names
[unleashed/tickless.git] / include / sys / ib / adapters / hermon / hermon_hw.h
blob111ea877edfaabb213de37b570d9f4b43bddfaba
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22 /*
23 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
24 */
25
26 #ifndef _SYS_IB_ADAPTERS_HERMON_HW_H
27 #define _SYS_IB_ADAPTERS_HERMON_HW_H
28
29 /*
30 * hermon_hw.h
31 * Contains all the structure definitions and #defines for all Hermon
32 * hardware resources and registers (as defined by the Hermon register
33 * specification). Wherever possible, the names in the Hermon spec
34 * have been preserved in the structure and field names below.
35 */
36
37 #include <sys/types.h>
38 #include <sys/conf.h>
39 #include <sys/ddi.h>
40 #include <sys/sunddi.h>
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46
47 /*
48 * PCI IDs for supported chipsets
49 */
50 #define PCI_VENID_MLX 0x15b3
51 #define PCI_DEVID_HERMON_SDR 0x6340 /* Mellanox MT25208-SDR PCIe Gen1 */
52 #define PCI_DEVID_HERMON_DDR 0x634A /* Mellanox MT25208-DDR PCIe Gen1 */
53 #define PCI_DEVID_HERMON_DDRG2 0x6732 /* Mellanox MT25208-DDR PCIe Gen2 */
54 #define PCI_DEVID_HERMON_QDRG2 0x673C /* Mellanox MT25208-QDR PCIe Gen2 */
55 #define PCI_DEVID_HERMON_QDRG2V 0x6746 /* Mellanox MT25208-QDR PCIe Gen2 */
56 #define PCI_DEVID_HERMON_MAINT 0x0191 /* Maintenance/Mem Controller Mode */
57
58 /*
59 * Native page size of the adapter
60 */
61 #define HERMON_PAGESIZE 0x1000 /* 4Kb */
62 #define HERMON_PAGEOFFSET (HERMON_PAGESIZE - 1)
63 #define HERMON_PAGEMASK (~HERMON_PAGEOFFSET)
64 #define HERMON_PAGESHIFT 0xC /* 12 */
65
66 /*
67 * Offsets into the CMD BAR (BAR 0) for many of the more interesting hardware
68 * registers. These registers include the HCR (more below), and the software
69 * reset register (SW_RESET).
70 */
71 #define HERMON_CMD_HCR_OFFSET 0x80680 /* PRM */
72 #define HERMON_CMD_SW_RESET_OFFSET 0xF0010 /* PRM */
73 #define HERMON_CMD_SW_SEMAPHORE_OFFSET 0xF03FC /* PRM */
74 #define HERMON_CMD_OFFSET_MASK 0xFFFFF /* per MLX instruction */
75
76
77 /*
78 * Ownership flags used to define hardware or software ownership for
79 * various Hermon resources
80 */
81 #define HERMON_HW_OWNER 0x1
82 #define HERMON_SW_OWNER 0x0
83
84 /*
85 * Determines whether or not virtual-to-physical address translation is
86 * required. Several of the Hermon hardware structures can be optionally
87 * accessed by Hermon without going through the TPT address translation
88 * tables.
89 */
90 #define HERMON_VA2PA_XLAT_ENABLED 0x1
91 #define HERMON_VA2PA_XLAT_DISABLED 0x0
92
93 /*
94 * HCA Command Register (HCR)
95 * The HCR command interface provides privileged access to the HCA in
96 * order to query, configure and modify HCA execution. It is the
97 * primary mechanism through which mailboxes may be posted to Hermon
98 * firmware. To use this interface software fills the HCR with pointers
99 * to input and output mailboxes. Some commands support immediate
100 * parameters, however, and for these commands the HCR will contain the
101 * input or output parameters. Command execution completion can be
102 * detected either by the software polling the HCR or by waiting for a
103 * command completion event.
104 */
105 struct hermon_hw_hcr_s {
106 uint32_t in_param0;
107 uint32_t in_param1;
108 uint32_t input_modifier;
109 uint32_t out_param0;
110 uint32_t out_param1;
111 uint32_t token;
112 uint32_t cmd;
113 };
114 #define HERMON_HCR_TOKEN_MASK 0xFFFF0000
115 #define HERMON_HCR_TOKEN_SHIFT 16
116
117 #define HERMON_HCR_CMD_STATUS_MASK 0xFF000000
118 #define HERMON_HCR_CMD_GO_MASK 0x00800000
119 #define HERMON_HCR_CMD_E_MASK 0x00400000
120 #define HERMON_HCR_CMD_T_MASK 0x00200000
121 #define HERMON_HCR_CMD_OPMOD_MASK 0x0000F000
122 #define HERMON_HCR_CMD_OPCODE_MASK 0x00000FFF
123 #define HERMON_HCR_CMD_STATUS_SHFT 24
124 #define HERMON_HCR_CMD_GO_SHFT 23
125 #define HERMON_HCR_CMD_E_SHFT 22
126 #define HERMON_HCR_CMD_T_SHFT 21
127 #define HERMON_HCR_CMD_OPMOD_SHFT 12
128
129 /*
130 * Arbel/tavor "QUERY_DEV_LIM" == Hermon "QUERY_DEV_CAP" - Same hex code
131 * same function as tavor/arbel QUERY_DEV_LIM, just renamed (whatever).
132 * The QUERY_DEV_LIM command returns the device limits and capabilities
133 * supported by the Hermon device. This command must be run before
134 * running the INIT_HCA command (below) in order to determine the maximum
135 * capabilities of the device and which optional features are supported.
136 */
137 #ifdef _LITTLE_ENDIAN
138 struct hermon_hw_querydevlim_s {
139 uint32_t rsrv0[4];
140
141 uint32_t log_max_scqs :4;
142 uint32_t :4;
143 uint32_t num_rsvd_scqs :6;
144 uint32_t :2;
145 uint32_t log_max_srq :5;
146 uint32_t :7;
147 uint32_t log_rsvd_srq :4;
148
149 uint32_t log_max_qp :5;
150 uint32_t :3;
151 uint32_t log_rsvd_qp :4;
152 uint32_t :4;
153 uint32_t log_max_qp_sz :8;
154 uint32_t log_max_srq_sz :8;
155
156 uint32_t log_max_eq :4;
157 uint32_t :4;
158 uint32_t num_rsvd_eq :4;
159 uint32_t :4;
160 uint32_t log_max_dmpt :6;
161 uint32_t :2;
162 uint32_t log_max_eq_sz :8;
163
164 uint32_t log_max_cq :5;
165 uint32_t :3;
166 uint32_t log_rsvd_cq :4;
167 uint32_t :4;
168 uint32_t log_max_cq_sz :8;
169 uint32_t :8;
170
171
172 uint32_t :32;
173
174 uint32_t log_max_mtt :6;
175 uint32_t :2;
176 uint32_t log_rsvd_dmpt :4;
177 uint32_t :4;
178 uint32_t log_max_mrw_sz :7;
179 uint32_t :5;
180 uint32_t log_rsvd_mtt :4;
181
182 uint32_t log_max_ra_glob :6;
183 uint32_t :2;
184 uint32_t log_max_rss_tbl_sz :4;
185 uint32_t rss_toep :1; /* rss toeplitz hashing */
186 uint32_t rss_xor :1; /* rss xor hashing */
187 uint32_t :2;
188 uint32_t log_max_gso_sz :5; /* Lge Send Offload */
189 uint32_t :11; /* new w/ 0.35, RSS info */
190
191 uint32_t log_max_ra_res_qp :6;
192 uint32_t :10;
193 uint32_t log_max_ra_req_qp :6;
194 uint32_t :10;
195
196 uint32_t num_ports :4;
197 uint32_t :12;
198 uint32_t ca_ack_delay :5;
199 uint32_t cqmep :3; /* cq moderation policies */
200 uint32_t :4;
201 uint32_t :1;
202 uint32_t :3;
203
204 uint32_t mod_wr_srq :1; /* resize SRQ supported */
205 uint32_t :31;
206
207 uint32_t :16;
208 uint32_t stat_rate_sup :16;
209
210 uint32_t :8;
211 uint32_t :4;
212 uint32_t :4;
213 uint32_t :8;
214 uint32_t log_max_msg :5;
215 uint32_t :3;
216
217 uint32_t rc :1; /* 0x44 */
218 uint32_t uc :1;
219 uint32_t ud :1;
220 uint32_t xrc :1;
221 uint32_t rcm :1;
222 uint32_t fcoib :1;
223 uint32_t srq :1;
224 uint32_t ipoib_cksm :1;
225 uint32_t pkey_v :1;
226 uint32_t qkey_v :1;
227 uint32_t vmm :1;
228 uint32_t fcoe :1;
229 uint32_t dpdp :1; /* dual port diff protocol */
230 uint32_t raw_etype :1;
231 uint32_t raw_ipv4 :1;
232 uint32_t blh :1; /* big LSO header, bit in WQE */
233 uint32_t mem_win :1;
234 uint32_t apm :1;
235 uint32_t atomic :1;
236 uint32_t raw_multi :1;
237 uint32_t avp :1;
238 uint32_t ud_multi :1;
239 uint32_t udm_ipv4 :1;
240 uint32_t dif :1; /* DIF supported */
241 uint32_t pg_on_demand :1;
242 uint32_t router :1;
243 uint32_t l2mc :1; /* lev 2 enet multicast */
244 uint32_t :1;
245 uint32_t ud_swp :1; /* sw parse for UD xport */
246 uint32_t ipv6_ex :1; /* offload w/ IPV6 ext hdrs */
247 uint32_t lle :1; /* low latency enet */
248 uint32_t fcoe_t11 :1; /* fcoenet T11 frame support */
249
250 /* 0x40 */
251 uint32_t eth_uc_lb :1; /* enet unicast loopback */
252 uint32_t :3;
253 uint32_t hdr_split :1;
254 uint32_t hdr_lookahead :1;
255 uint32_t :2;
256 uint32_t rss_udp :1;
257 uint32_t :7;
258 uint32_t :16;
259
260 uint32_t log_max_bf_page :6; /* 0x4c */
261 uint32_t :2;
262 uint32_t log_max_bf_req_ppg :6;
263 uint32_t :2;
264 uint32_t log_bf_reg_sz :5;
265 uint32_t :10;
266 uint32_t blu_flm :1;
267
268 uint32_t log_pg_sz :8; /* 0x48 */
269 uint32_t :8;
270 uint32_t log_max_uar_sz :6;
271 uint32_t :6;
272 uint32_t num_rsvd_uar :4;
273
274 uint32_t max_desc_sz_rq :16; /* 0x54 */
275 uint32_t max_sg_rq :8;
276 uint32_t :8;
277
278 uint32_t max_desc_sz_sq :16; /* 0x50 */
279 uint32_t max_sg_sq :8;
280 uint32_t :8;
281
282
283 uint32_t rsvd_fcoib; /* 0x5C */
284
285 uint32_t :1; /* 0x58 */
286 uint32_t fexch_base_mpt :7; /* FC exch base mpt num */
287 uint32_t fcp_ud_base_qp :16; /* RC UD base qp num */
288 uint32_t fexch_base_qp :8; /* FC exch base qp num */
289
290
291 uint32_t log_max_xrcd :5; /* 0x64 */
292 uint32_t :7;
293 uint32_t num_rsvd_xrcds :4;
294 uint32_t log_max_pd :5;
295 uint32_t :7;
296 uint32_t num_rsvd_pd :4;
297
298 uint32_t log_max_mcg :8; /* 0x60 */
299 uint32_t num_rsvd_mcg :4;
300 uint32_t :4;
301 uint32_t log_max_qp_mcg :8;
302 uint32_t :8;
303
304 uint32_t rsrv2[6];
305
306 uint32_t altc_entry_sz :16; /* 0x84 */
307 uint32_t aux_entry_sz :16;
308
309 uint32_t qpc_entry_sz :16; /* 0x80 */
310 uint32_t rdmardc_entry_sz :16;
311
312 uint32_t cmpt_entry_sz :16; /* 0x8C */
313 uint32_t srq_entry_sz :16;
314
315 uint32_t cqc_entry_sz :16; /* 0x88 */
316 uint32_t eqc_entry_sz :16;
317
318 uint32_t bmme :1; /* 0x94 */
319 uint32_t win_type :1;
320 uint32_t mps :1;
321 uint32_t bl :1;
322 uint32_t zb :1;
323 uint32_t lif :1;
324 uint32_t local_inv :1;
325 uint32_t remote_inv :1;
326 uint32_t :1;
327 uint32_t win_type2 :1;
328 uint32_t reserved_lkey :1;
329 uint32_t fast_reg_wr :1;
330 uint32_t :20;
331
332 uint32_t dmpt_entry_sz :16; /* 0x90 */
333 uint32_t mtt_entry_sz :16;
334
335 uint32_t :32;
336
337 uint32_t rsv_lkey;
338 /* 0xA0 */
339 uint64_t max_icm_size;
340
341 uint32_t rsrv3[22];
342 };
343
344 #else /* BIG ENDIAN */
345
346 struct hermon_hw_querydevlim_s {
347 uint32_t rsrv0[4];
348
349 uint32_t log_max_srq_sz :8;
350 uint32_t log_max_qp_sz :8;
351 uint32_t :4;
352 uint32_t log_rsvd_qp :4;
353 uint32_t :3;
354 uint32_t log_max_qp :5;
355
356 uint32_t log_rsvd_srq :4;
357 uint32_t :7;
358 uint32_t log_max_srq :5;
359 uint32_t :2;
360 uint32_t num_rsvd_scqs :6;
361 uint32_t :4;
362 uint32_t log_max_scqs :4;
363
364 uint32_t :8;
365 uint32_t log_max_cq_sz :8;
366 uint32_t :4;
367 uint32_t log_rsvd_cq :4;
368 uint32_t :3;
369 uint32_t log_max_cq :5;
370
371 uint32_t log_max_eq_sz :8;
372 uint32_t :2;
373 uint32_t log_max_dmpt :6;
374 uint32_t :4;
375 uint32_t num_rsvd_eq :4;
376 uint32_t :4;
377 uint32_t log_max_eq :4;
378
379 uint32_t log_rsvd_mtt :4;
380 uint32_t :5;
381 uint32_t log_max_mrw_sz :7;
382 uint32_t :4;
383 uint32_t log_rsvd_dmpt :4;
384 uint32_t :2;
385 uint32_t log_max_mtt :6;
386
387 uint32_t :32;
388
389 uint32_t :10;
390 uint32_t log_max_ra_req_qp :6;
391 uint32_t :10;
392 uint32_t log_max_ra_res_qp :6;
393
394 uint32_t :11; /* new w/ 0.35, RSS info */
395 uint32_t log_max_gso_sz :5; /* Lge Send Offload */
396 uint32_t :2;
397 uint32_t rss_xor :1; /* rss xor hashing */
398 uint32_t rss_toep :1; /* rss toeplitz hashing */
399 uint32_t log_max_rss_tbl_sz :4;
400 uint32_t :2;
401 uint32_t log_max_ra_glob :6;
402
403 uint32_t :31;
404 uint32_t mod_wr_srq :1; /* resize SRQ supported */
405
406 uint32_t :3;
407 uint32_t :1;
408 uint32_t :4;
409 uint32_t cqmep :3; /* cq moderation policies */
410 uint32_t ca_ack_delay :5;
411 uint32_t :12;
412 uint32_t num_ports :4;
413
414 uint32_t :3;
415 uint32_t log_max_msg :5;
416 uint32_t :8;
417 uint32_t :4;
418 uint32_t :4;
419 uint32_t :8;
420
421 uint32_t stat_rate_sup :16;
422 uint32_t :16;
423
424 uint32_t :16; /* 0x40 */
425 uint32_t :7;
426 uint32_t rss_udp :1;
427 uint32_t :2;
428 uint32_t hdr_lookahead :1;
429 uint32_t hdr_split :1;
430 uint32_t :3;
431 uint32_t eth_uc_lb :1; /* enet unicast loopback */
432 /* 0x44 */
433 uint32_t fcoe_t11 :1; /* fcoenet T11 frame support */
434 uint32_t lle :1; /* low latency enet */
435 uint32_t ipv6_ex :1; /* offload w/ IPV6 ext hdrs */
436 uint32_t ud_swp :1; /* sw parse for UD xport */
437 uint32_t :1;
438 uint32_t l2mc :1; /* lev 2 enet multicast */
439 uint32_t router :1;
440 uint32_t pg_on_demand :1;
441 uint32_t dif :1; /* DIF supported */
442 uint32_t udm_ipv4 :1;
443 uint32_t ud_multi :1;
444 uint32_t avp :1;
445 uint32_t raw_multi :1;
446 uint32_t atomic :1;
447 uint32_t apm :1;
448 uint32_t mem_win :1;
449 uint32_t blh :1; /* big LSO header, bit in WQE */
450 uint32_t raw_ipv4 :1;
451 uint32_t raw_etype :1;
452 uint32_t dpdp :1; /* dual port diff protocol */
453 uint32_t fcoe :1;
454 uint32_t vmm :1;
455 uint32_t qkey_v :1;
456 uint32_t pkey_v :1;
457 uint32_t ipoib_cksm :1;
458 uint32_t srq :1;
459 uint32_t fcoib :1;
460 uint32_t rcm :1;
461 uint32_t xrc :1;
462 uint32_t ud :1;
463 uint32_t uc :1;
464 uint32_t rc :1;
465
466 uint32_t num_rsvd_uar :4; /* 0x48 */
467 uint32_t :6;
468 uint32_t log_max_uar_sz :6;
469 uint32_t :8;
470 uint32_t log_pg_sz :8;
471
472 uint32_t blu_flm :1; /* 0x4c */
473 uint32_t :10;
474 uint32_t log_bf_reg_sz :5;
475 uint32_t :2;
476 uint32_t log_max_bf_req_ppg :6;
477 uint32_t :2;
478 uint32_t log_max_bf_page :6;
479
480 uint32_t :8; /* 0x50 */
481 uint32_t max_sg_sq :8;
482 uint32_t max_desc_sz_sq :16;
483
484 uint32_t :8; /* 0x54 */
485 uint32_t max_sg_rq :8;
486 uint32_t max_desc_sz_rq :16;
487
488 /* 0x58 */
489 uint32_t fexch_base_qp :8; /* FC exch base qp num */
490 uint32_t fcp_ud_base_qp :16; /* RC UD base qp num */
491 uint32_t fexch_base_mpt :7; /* FC exch base mpt num */
492 uint32_t :1;
493
494 uint32_t rsvd_fcoib; /* 0x5C */
495
496 uint32_t :8; /* 0x60 */
497 uint32_t log_max_qp_mcg :8;
498 uint32_t :4;
499 uint32_t num_rsvd_mcg :4;
500 uint32_t log_max_mcg :8;
501
502 uint32_t num_rsvd_pd :4; /* 0x64 */
503 uint32_t :7;
504 uint32_t log_max_pd :5;
505 uint32_t num_rsvd_xrcds :4;
506 uint32_t :7;
507 uint32_t log_max_xrcd :5;
508
509 uint32_t rsrv2[6];
510
511 uint32_t rdmardc_entry_sz :16; /* 0x80 */
512 uint32_t qpc_entry_sz :16;
513
514 uint32_t aux_entry_sz :16; /* 0x84 */
515 uint32_t altc_entry_sz :16;
516
517 uint32_t eqc_entry_sz :16; /* 0x88 */
518 uint32_t cqc_entry_sz :16;
519
520 uint32_t srq_entry_sz :16; /* 0x8C */
521 uint32_t cmpt_entry_sz :16;
522
523 uint32_t mtt_entry_sz :16; /* 0x90 */
524 uint32_t dmpt_entry_sz :16;
525
526 uint32_t :20; /* 0x94 */
527 uint32_t fast_reg_wr :1;
528 uint32_t reserved_lkey :1;
529 uint32_t win_type2 :1;
530 uint32_t :1;
531 uint32_t remote_inv :1;
532 uint32_t local_inv :1;
533 uint32_t lif :1;
534 uint32_t zb :1;
535 uint32_t bl :1;
536 uint32_t mps :1;
537 uint32_t win_type :1;
538 uint32_t bmme :1;
539
540 uint32_t rsv_lkey;
541
542 uint32_t :32;
543
544 uint64_t max_icm_size;
545 /* 0xA0 */
546 uint32_t rsrv3[22];
547 };
548 #endif
549
550
551
552 /*
553 * Hermon "QUERY_FW" command
554 * The QUERY_FW command retrieves the firmware revision and the Command
555 * Interface revision. The command also returns the HCA attached local
556 * memory area (DDR) which is used by the firmware. Below we also
557 * include some defines which are used to enforce a minimum firmware
558 * version check (see hermon_fw_version_check() for more details).
559 */
560
561 #ifdef _LITTLE_ENDIAN
562 struct hermon_hw_queryfw_s {
563 uint32_t fw_rev_minor :16;
564 uint32_t fw_rev_subminor :16;
565
566 uint32_t fw_rev_major :16;
567 uint32_t fw_pages :16;
568
569 uint32_t log_max_cmd :8;
570 uint32_t :23;
571 uint32_t dbg_trace :1;
572
573 uint32_t cmd_intf_rev :16;
574 uint32_t :16;
575
576 uint32_t fw_day :8;
577 uint32_t fw_month :8;
578 uint32_t fw_year :16;
579
580 uint32_t :1;
581 uint32_t ccq :1; /* currently not def'd */
582 uint32_t :6;
583 uint32_t fw_sec :8;
584 uint32_t fw_min :8;
585 uint32_t fw_hour :8;
586
587 uint32_t rsrv0[2];
588
589 uint64_t clr_intr_offs;
590
591 uint32_t :32;
592
593 uint32_t :30;
594 uint32_t clr_int_bar :2;
595
596 uint64_t error_buf_addr;
597
598 uint32_t :30;
599 uint32_t err_buf_bar :2;
600
601 uint32_t error_buf_sz;
602
603 uint64_t vf_com_ch_addr;
604
605 uint32_t :32;
606
607 uint32_t :30;
608 uint32_t vf_com_ch_bar :2;
609
610 uint32_t rsrv2[44];
611 };
612 #else /* BIG ENDIAN */
613 struct hermon_hw_queryfw_s {
614 uint32_t fw_pages :16;
615 uint32_t fw_rev_major :16;
616
617 uint32_t fw_rev_subminor :16;
618 uint32_t fw_rev_minor :16;
619
620 uint32_t :16;
621 uint32_t cmd_intf_rev :16;
622
623 uint32_t dbg_trace :1;
624 uint32_t :23;
625 uint32_t log_max_cmd :8;
626
627 uint32_t fw_hour :8;
628 uint32_t fw_min :8;
629 uint32_t fw_sec :8;
630 uint32_t :6;
631 uint32_t ccq :1; /* currently not def'd */
632 uint32_t :1;
633
634 uint32_t fw_year :16;
635 uint32_t fw_month :8;
636 uint32_t fw_day :8;
637
638 uint32_t rsrv1[2];
639
640 uint64_t clr_intr_offs;
641
642 uint32_t clr_int_bar :2;
643 uint32_t :30;
644
645 uint32_t :32;
646
647 uint64_t error_buf_addr;
648
649 uint32_t error_buf_sz;
650
651 uint32_t err_buf_bar :2;
652 uint32_t :30;
653
654 uint64_t vf_com_ch_addr;
655
656 uint32_t vf_com_ch_bar :2;
657 uint32_t :30;
658
659 uint32_t :32;
660
661 uint32_t rsrv2[44];
662 };
663 #endif
664
665 /*
666 * 2.6.000 is critical for some performance features, e.g., Reserved_Lkey,
667 * and 2.7.000 is needed for FRWR and FCoIB. Requiring 2.6.000 now so that
668 * existing customers get the performance, but are not required to upgrade
669 * to the latest. Less than 2.6.000 will cause the driver to attach in
670 * maintenance mode, and throw an FMA event about upgrading the firmware.
671 */
672
673 #define HERMON_FW_VER_MAJOR 0x0002
674 #define HERMON_FW_VER_MINOR 0x0006
675 #define HERMON_FW_VER_SUBMINOR 0x0000
676
677 /*
678 * Hermon "QUERY_ADAPTER" command
679 * The QUERY_ADAPTER command retrieves adapter specific parameters. The
680 * command also retrieves the PCI(X) interrupt pin routing for each of
681 * the INTx# pins supported by the device. This information is used by
682 * the driver during interrupt processing in order to clear the appropriate
683 * interrupt bit.
684 */
685 #ifdef _LITTLE_ENDIAN
686 struct hermon_hw_queryadapter_s {
687 uint32_t rsrv0[4];
688
689 uint32_t :32;
690
691 uint32_t :24;
692 uint32_t inta_pin :8;
693
694 uint32_t vsd_vend_id :16; /* added v35 hermon */
695 uint32_t :16;
696
697 uint32_t :32;
698
699 uint32_t vsd[52];
700 uint32_t psid[4];
701 };
702 #else
703 struct hermon_hw_queryadapter_s {
704 uint32_t rsrv0[4];
705
706 uint32_t inta_pin :8;
707 uint32_t :24;
708
709 uint32_t :32;
710
711 uint32_t :32;
712
713 uint32_t :16;
714 uint32_t vsd_vend_id :16; /* added v35 hermon */
715
716 uint32_t vsd[52];
717 uint32_t psid[4];
718 };
719 #endif
720 #define HERMON_REV_A0 0xA0
721 #define HERMON_REV_A1 0xA1
722
723 /*
724 * Virtual physical mapping structure for: MAP_FA, MAP_ICM_AUX, and
725 * MAP_ICM commands.
726 */
727
728 #ifdef _LITTLE_ENDIAN
729 struct hermon_hw_vpm_s {
730 uint32_t :12;
731 uint32_t vaddr_l :20;
732
733 uint32_t vaddr_h;
734
735 uint32_t log2sz :5; /* in 4KB pages */
736 uint32_t :7;
737 uint32_t paddr_l :20;
738
739 uint32_t paddr_h;
740 };
741 #else
742 struct hermon_hw_vpm_s {
743 uint32_t vaddr_h;
744
745 uint32_t vaddr_l :20;
746 uint32_t :12;
747
748 uint32_t paddr_h;
749
750 uint32_t paddr_l :20;
751 uint32_t :7;
752 uint32_t log2sz :5; /* in 4KB pages */
753 };
754 #endif
755
756
757
758
759 /*
760 * Hermon "INIT_HCA" and "QUERY_HCA" commands
761 * The INIT_HCA command configures all HCA resources in HCA attached local
762 * memory and some system relevant information. The same mailbox output
763 * format is used by the QUERY_HCA command. All parameters, which are
764 * specifically the output of the QUERY_HCA command are marked as
765 * "QUERY_HCA only". These parameters are not configurable through the
766 * INIT_HCA command, but can be retrieved as read-only through the
767 * QUERY_HCA command.
768 *
769 * Below we first define several structures which help make up the whole
770 * of the INIT_HCA/QUERY_HCA command. These are:
771 * hermon_hw_qp_ee_cq_eq_rdb_t for "QPC/EEC/CQC/EQC/RDB Parameters",
772 * hermon_udav_mem_param_t for "Memory Access Parameters for UDAV Table",
773 * hermon_multicast_param_t for "Multicast Support Parameters",
774 * hermon_tpt_param_t for "Translation and Protection Table Parameters",
775 * and hermon_uar_param_t for Hermon "UAR Parameters".
776 */
777
778 /*
779 * need to consider removing any ref to "ee", hermon doesn't support
780 * ee/rd stuff, and they've taken away the pretense
781 */
782
783
784 #ifdef _LITTLE_ENDIAN
785 typedef struct hermon_hw_qp_ee_cq_eq_rdb_s {
786 uint32_t rsrv0[4];
787
788 uint32_t log_num_qp :5;
789 uint32_t qpc_baseaddr_l :27;
790 uint32_t qpc_baseaddr_h;
791
792 uint32_t rsrv1[4];
793
794 uint32_t log_num_srq :5;
795 uint32_t srqc_baseaddr_l :27;
796 uint32_t srqc_baseaddr_h;
797
798 uint32_t log_num_cq :5;
799 uint32_t cqc_baseaddr_l :27;
800 uint32_t cqc_baseaddr_h;
801
802 uint32_t rsrv2[2];
803
804 uint64_t altc_baseaddr;
805
806 uint32_t rsrv3[2];
807
808 uint64_t auxc_baseaddr;
809
810 uint32_t rsrv4[2];
811
812 uint32_t log_num_eq :5;
813 uint32_t eqc_baseaddr_l :27;
814 uint32_t eqc_baseaddr_h;
815
816 uint32_t rsv5[2];
817
818 uint32_t log_num_rdmardc :3;
819 uint32_t :2;
820 uint32_t rdmardc_baseaddr_l :27;
821 uint32_t rdmardc_baseaddr_h;
822
823 uint32_t rsrv6[2];
824 } hermon_hw_qp_ee_cq_eq_rdb_t;
825 #else /* BIG ENDIAN */
826 typedef struct hermon_hw_qp_ee_cq_eq_rdb_s {
827 uint32_t rsrv0[4];
828
829 uint32_t qpc_baseaddr_h;
830 uint32_t qpc_baseaddr_l :27;
831 uint32_t log_num_qp :5;
832
833 uint32_t rsrv1[4];
834
835 uint32_t srqc_baseaddr_h;
836 uint32_t srqc_baseaddr_l :27;
837 uint32_t log_num_srq :5;
838
839 uint32_t cqc_baseaddr_h;
840 uint32_t cqc_baseaddr_l :27;
841 uint32_t log_num_cq :5;
842
843 uint32_t rsrv2[2];
844
845 uint64_t altc_baseaddr;
846
847 uint32_t rsrv3[2];
848
849 uint64_t auxc_baseaddr;
850
851 uint32_t rsrv4[2];
852
853 uint32_t eqc_baseaddr_h;
854 uint32_t eqc_baseaddr_l :27;
855 uint32_t log_num_eq :5;
856
857 uint32_t rsv5[2];
858
859 uint32_t rdmardc_baseaddr_h;
860 uint32_t rdmardc_baseaddr_l :27;
861 uint32_t :2;
862 uint32_t log_num_rdmardc :3;
863
864 uint32_t rsrv6[2];
865 } hermon_hw_qp_ee_cq_eq_rdb_t;
866 #endif
867
868
869
870
871 #ifdef _LITTLE_ENDIAN
872 typedef struct hermon_multicast_param_s {
873 uint64_t mc_baseaddr;
874
875 uint32_t rsrv0[2];
876
877 uint32_t log_mc_tbl_hash_sz :5;
878 uint32_t :27;
879
880 uint32_t log_mc_tbl_ent :5;
881 uint32_t :27;
882
883 uint32_t :32;
884
885 uint32_t log_mc_tbl_sz :5;
886 uint32_t :19;
887 uint32_t mc_hash_fn :3;
888 uint32_t :5;
889 } hermon_multicast_param_t;
890 #else /* BIG ENDIAN */
891 typedef struct hermon_multicast_param_s {
892 uint64_t mc_baseaddr;
893
894 uint32_t rsrv0[2];
895
896 uint32_t :27;
897 uint32_t log_mc_tbl_ent :5;
898
899 uint32_t :27;
900 uint32_t log_mc_tbl_hash_sz :5;
901
902 uint32_t :5;
903 uint32_t mc_hash_fn :3;
904 uint32_t :19;
905 uint32_t log_mc_tbl_sz :5;
906
907 uint32_t :32;
908 } hermon_multicast_param_t;
909 #endif
910
911 #define HERMON_MCG_DEFAULT_HASH_FN 0x0
912
913 #ifdef _LITTLE_ENDIAN
914 typedef struct hermon_tpt_param_s {
915 uint64_t dmpt_baseaddr;
916
917 uint32_t :32;
918
919 uint32_t log_dmpt_sz :6;
920 uint32_t :2;
921 uint32_t pgfault_rnr_to :5;
922 uint32_t :19;
923
924 uint64_t mtt_baseaddr;
925
926 uint64_t cmpt_baseaddr;
927 } hermon_tpt_param_t;
928 #else /* BIG ENDIAN */
929 typedef struct hermon_tpt_param_s {
930 uint64_t dmpt_baseaddr;
931
932 uint32_t :19;
933 uint32_t pgfault_rnr_to :5;
934 uint32_t :2;
935 uint32_t log_dmpt_sz :6;
936
937 uint32_t :32;
938
939 uint64_t mtt_baseaddr;
940
941 uint64_t cmpt_baseaddr;
942 } hermon_tpt_param_t;
943 #endif
944
945
946 #ifdef _LITTLE_ENDIAN
947 typedef struct hermon_uar_param_s {
948 uint32_t rsvd0[2];
949
950 uint32_t :32;
951
952 uint32_t uar_pg_sz :8;
953 uint32_t log_max_uars :4;
954 uint32_t :20;
955
956 uint32_t resvd1[4];
957 } hermon_uar_param_t;
958 #else
959 typedef struct hermon_uar_param_s {
960 uint32_t rsvd0[2];
961
962 uint32_t :20;
963 uint32_t log_max_uars :4;
964 uint32_t uar_pg_sz :8;
965
966 uint32_t :32;
967
968 uint32_t resvd1[4];
969 } hermon_uar_param_t;
970 #endif
971
972 /*
973 * NEW for Hermon
974 * QP Allocation Params
975 * NOTE: as of PRM v0.50 no longer needed (ccq not supported
976 * leave structure here, just in case ccq comes back )
977 * but adjust the overall structure
978 * not to use it
979 *
980 */
981
982 #ifdef _LITTLE_ENDIAN
983 typedef struct hermon_qp_alloc_param_s {
984 uint32_t :32;
985
986 uint32_t ccq_base :24;
987 uint32_t log2ccqs :5;
988 uint32_t :2;
989 uint32_t ccq_en :1;
990
991 uint32_t rsvd[6]; /* but 0x14 def'd for fibre channel */
992 } hermon_qp_alloc_param_t;
993 #else /* BIG ENDIAN */
994 typedef struct hermon_qp_alloc_param_s {
995 uint32_t ccq_en :1;
996 uint32_t :2;
997 uint32_t log2ccqs :5;
998 uint32_t ccq_base :24;
999
1000 uint32_t :32;
1001
1002 uint32_t rsvd[6]; /* but 0x14 def'd for fibre channel */
1003 } hermon_qp_alloc_param_t;
1004 #endif
1005
1006
1007 #ifdef _LITTLE_ENDIAN
1008 struct hermon_hw_initqueryhca_s {
1009 uint32_t :32;
1010
1011 uint32_t :24;
1012 uint32_t version :8;
1013
1014 uint32_t :13;
1015 uint32_t log2_cacheline :3;
1016 uint32_t hca_core_clock :16; /* QUERY_HCA only */
1017
1018 uint32_t :32;
1019
1020 uint32_t udav_port_chk :1;
1021 uint32_t big_endian :1;
1022 uint32_t qos :1;
1023 uint32_t chsum_en :1;
1024 uint32_t :12;
1025 uint32_t cqpm_short_pkt_lim :14; /* short pkt limit for qpm */
1026 uint32_t cqmp :2; /* cq moderation policy */
1027
1028 uint32_t router_qp :24;
1029 uint32_t :5;
1030 uint32_t ipr2 :1;
1031 uint32_t ipr1 :1;
1032 uint32_t router_en :1;
1033
1034 uint32_t rsrv1[2];
1035
1036 hermon_hw_qp_ee_cq_eq_rdb_t context;
1037
1038 uint32_t rsrv2[8];
1039
1040 hermon_multicast_param_t multi;
1041
1042 uint32_t rsrv3[4];
1043
1044 hermon_tpt_param_t tpt;
1045
1046 uint32_t rsrv4[4];
1047
1048 hermon_uar_param_t uar;
1049
1050 uint32_t rsrv5[36];
1051
1052 hermon_multicast_param_t enet_multi;
1053
1054 uint32_t rsrv6[24]; /* to 0x24C */
1055
1056 uint32_t :32;
1057
1058 uint32_t fcoe_t11 :1; /* fcoe t11 frame enable */
1059 uint32_t :31;
1060
1061 uint32_t rsrv7[42]; /* 0x254 - 0x2FC */
1062 };
1063 #else /* BIG ENDIAN */
1064 struct hermon_hw_initqueryhca_s {
1065 uint32_t version :8;
1066 uint32_t :24;
1067
1068 uint32_t :32;
1069
1070 uint32_t :32;
1071
1072 uint32_t hca_core_clock :16; /* QUERY_HCA only */
1073 uint32_t log2_cacheline :3;
1074 uint32_t :13;
1075
1076 uint32_t router_en :1;
1077 uint32_t ipr1 :1;
1078 uint32_t ipr2 :1;
1079 uint32_t :5;
1080 uint32_t router_qp :24;
1081
1082 uint32_t cqmp :2; /* cq moderation policy */
1083 uint32_t cqpm_short_pkt_lim :14; /* short pkt limit for qpm */
1084 uint32_t :12;
1085 uint32_t chsum_en :1;
1086 uint32_t qos :1;
1087 uint32_t big_endian :1;
1088 uint32_t udav_port_chk :1;
1089
1090 uint32_t rsrv1[2];
1091
1092 hermon_hw_qp_ee_cq_eq_rdb_t context;
1093
1094 uint32_t rsrv2[8];
1095
1096 hermon_multicast_param_t multi;
1097
1098 uint32_t rsrv3[4];
1099
1100 hermon_tpt_param_t tpt;
1101
1102 uint32_t rsrv4[4];
1103
1104 hermon_uar_param_t uar;
1105
1106 uint32_t rsrv5[36];
1107
1108 hermon_multicast_param_t enet_multi;
1109
1110 uint32_t rsrv6[24]; /* to 0x24C */
1111
1112 uint32_t :31;
1113 uint32_t fcoe_t11 :1; /* fcoe t11 frame enable */
1114
1115 uint32_t :32;
1116
1117 uint32_t rsrv7[42]; /* 0x254 - 0x2FC */
1118 };
1119 #endif
1120 #define HERMON_UDAV_PROTECT_DISABLED 0x0
1121 #define HERMON_UDAV_PROTECT_ENABLED 0x1
1122 #define HERMON_UDAV_PORTCHK_DISABLED 0x0
1123 #define HERMON_UDAV_PORTCHK_ENABLED 0x1
1124
1125
1126 /*
1127 * Hermon "INIT_IB"/"INIT_PORT" command
1128 * The INIT_IB/INIT_PORT command enables the physical layer of an IB port.
1129 * It provides control over the IB port attributes. The capabilities
1130 * requested here should not exceed the device limits, as retrieved by
1131 * the QUERY_DEV_LIM/CAP command (above). To query information about the IB
1132 * port or node, the driver may submit GetPortInfo or GetNodeInfo MADs
1133 * through the Hermon MAD_IFC command.
1134 *
1135 * Changed name to initport, but operates similar to initib - but as of
1136 * PRM v0.35c the initport just does that, and the params set previously
1137 * by initib are now set in SET_PORT
1138 */
1139
1140
1141
1142
1143 /*
1144 * HERMON query_port and set_port commands. QUERY_PORT is new for hermon,
1145 * doing some of what used to be done in the QUERY_DEV_CAP command. It is
1146 * introduced in PRM v0.35 and will need to be added to the list of
1147 * supported HCA commands
1148 *
1149 * SET_PORT is similar to the SET_IB command from tavor and arbel. Here,
1150 * tho, it's more extensive and will be easier to deal with I suspect by
1151 * making it a structure and filling it in and then doing the copy to the
1152 * mailbox (instead of just writing the minimal information to the mailbox
1153 * directly as was done for the previous HCAs).
1154 */
1155
1156 /*
1157 * PRM 0.4X and 0.50 changed the query_port to integrate the ethernet
1158 * stuff as well, so this is a signficant change to the structure
1159 */
1160
1161 #ifdef _LITTLE_ENDIAN
1162 struct hermon_hw_query_port_s {
1163 /* 0x04 */
1164 uint32_t log_max_pkey :4; /* pkey table size */
1165 uint32_t log_max_gid :4; /* max gids / port */
1166 uint32_t ib_port_wid :8;
1167 /*
1168 * Enet link speed - 0x0 10Gb XAUI, 0x01 10Gb XFI,
1169 * 0x02 1Gb, 0xF other
1170 */
1171 uint32_t eth_link_spd :4;
1172 uint32_t :4;
1173 /*
1174 * IB Link speed - bit 0 SDR, bit1 DDR, Bit 2 QDR
1175 */
1176 uint32_t ib_link_spd :8;
1177
1178 /* 0x00 */
1179 uint32_t eth_mtu :16; /* in bytes */
1180 /*
1181 * IB MTU - 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x4=2048, 0x5=4096
1182 */
1183 uint32_t ib_mtu :4;
1184 uint32_t :4;
1185 /*
1186 * for next two if link down
1187 * -> what port supports, if up
1188 * -> what port is running
1189 */
1190
1191 uint32_t ib_link :1;
1192 uint32_t eth_link :1;
1193 uint32_t :1;
1194 uint32_t vpi :1;
1195 uint32_t :3;
1196 uint32_t link_up :1;
1197
1198
1199 uint32_t :32; /* 0x0C */
1200
1201 /* max vl's supported (not incl vl_15) */
1202 uint32_t max_vl :4; /* 0x08 */
1203 uint32_t :4;
1204 uint32_t log_max_mac :4;
1205 uint32_t log_max_vlan :4;
1206 uint32_t :16;
1207
1208 uint32_t mac_lo;
1209
1210 uint32_t mac_hi :16;
1211 uint32_t :16;
1212
1213 uint32_t rsvd1[2];
1214 };
1215
1216 #else /* BIG ENDIAN */
1217 struct hermon_hw_query_port_s {
1218 /* 0x00 */
1219 uint32_t link_up :1;
1220 uint32_t :3;
1221 uint32_t vpi :1;
1222 uint32_t :1;
1223 /*
1224 * for next two if link down
1225 * -> what port supports, if up
1226 * -> what port is running
1227 */
1228 uint32_t eth_link :1;
1229 uint32_t ib_link :1;
1230 uint32_t :4;
1231 /*
1232 * IB MTU - 0x0 rsvd, 0x1=256, 0x2=512, 0x3=1024, 0x4=2048, 0x5=4096
1233 */
1234 uint32_t ib_mtu :4;
1235 uint32_t eth_mtu :16; /* in bytes */
1236
1237 /* 0x04 */
1238 /*
1239 * IB Link speed - bit 0 SDR, bit1 DDR, Bit 2 QDR
1240 */
1241 uint32_t ib_link_spd :8;
1242 uint32_t :4;
1243 /*
1244 * Enet link speed - 0x0 10Gb XAUI, 0x01 10Gb XFI,
1245 * 0x02 1Gb, 0xF other
1246 */
1247 uint32_t eth_link_spd :4;
1248 uint32_t ib_port_wid :8;
1249 uint32_t log_max_gid :4; /* max gids / port */
1250 uint32_t log_max_pkey :4; /* pkey table size */
1251
1252 uint32_t :16; /* 0x08 */
1253 uint32_t log_max_vlan :4;
1254 uint32_t log_max_mac :4;
1255 uint32_t :4;
1256 /* max vl's supported (not incl vl_15) */
1257 uint32_t max_vl :4;
1258
1259 uint32_t :32; /* 0x0C */
1260
1261 uint32_t :16;
1262 uint32_t mac_hi :16;
1263
1264 uint32_t mac_lo;
1265
1266 uint32_t rsvd1[2];
1267
1268 };
1269 #endif
1270
1271 /*
1272 * the following structure is used for IB set port
1273 * others following are for ethernet set port
1274 */
1275
1276 #define HERMON_HW_OPMOD_SETPORT_IB 0x0
1277 #define HERMON_HW_OPMOD_SETPORT_EN 0x1
1278 #define HERMON_HW_OPMOD_SETPORT_EXT 0x2
1279
1280
1281 #ifdef _LITTLE_ENDIAN
1282 struct hermon_hw_set_port_s {
1283 uint32_t cap_mask;
1284
1285 uint32_t rqk :1; /* reset qkey violation cntr */
1286 uint32_t rcm :1; /* reset capability mask */
1287 uint32_t :2;
1288 uint32_t vl_cap :4;
1289 uint32_t :4;
1290 uint32_t mtu_cap :4;
1291 uint32_t g0 :1; /* set port GUID0 */
1292 uint32_t ng :1; /* set node GUID (all ports) */
1293 uint32_t sig :1; /* set sys image */
1294 uint32_t mg :1; /* change GID table */
1295 uint32_t mp :1; /* change pkey table size */
1296 uint32_t mvc :1; /* change vl_cap */
1297 uint32_t mmc :1; /* change mtu_cap */
1298 uint32_t :9;
1299
1300 uint64_t sys_img_guid;
1301
1302 uint64_t guid0;
1303
1304 uint64_t node_guid;
1305
1306 uint32_t ingress_sniff_qpn :24;
1307 uint32_t ingress_sniff_mode :1;
1308 uint32_t :7;
1309
1310 uint32_t egress_sniff_qpn :24;
1311 uint32_t egress_sniff_mode :1;
1312 uint32_t :7;
1313
1314 uint32_t :32;
1315
1316 uint32_t max_gid :16; /* valid if noted above */
1317 uint32_t max_pkey :16; /* valid if noted above */
1318
1319 uint32_t rsrd0[500];
1320 };
1321 #else /* BIG ENDIAN */
1322 struct hermon_hw_set_port_s {
1323 uint32_t :9;
1324 uint32_t mmc :1; /* change mtu_cap */
1325 uint32_t mvc :1; /* change vl_cap */
1326 uint32_t mp :1; /* change pkey table size */
1327 uint32_t mg :1; /* change GID table size */
1328 uint32_t sig :1; /* set sys image GUID */
1329 uint32_t ng :1; /* set node GUID (all ports) */
1330 uint32_t g0 :1; /* set port GUID0 */
1331 uint32_t mtu_cap :4;
1332 uint32_t :4;
1333 uint32_t vl_cap :4;
1334 uint32_t :2;
1335 uint32_t rcm :1; /* reset capability mask */
1336 uint32_t rqk :1; /* reset qkey violation cntr */
1337
1338 uint32_t cap_mask;
1339
1340 uint64_t sys_img_guid;
1341
1342 uint64_t guid0;
1343
1344 uint64_t node_guid;
1345
1346 uint32_t :7;
1347 uint32_t egress_sniff_mode :1;
1348 uint32_t egress_sniff_qpn :24;
1349
1350 uint32_t :7;
1351 uint32_t ingress_sniff_mode :1;
1352 uint32_t ingress_sniff_qpn :24;
1353
1354
1355 uint32_t max_pkey :16; /* valid if noted above */
1356 uint32_t max_gid :16; /* valid if noted above */
1357
1358 uint32_t :32;
1359
1360 uint32_t rsrd0[500];
1361 };
1362 #endif
1363
1364 /*
1365 * structures for ethernet setport
1366 * Which structure is used depends on low-16 of opmod
1367 * Low 8 == port number, 15:8 == selector
1368 * Or the following with port number
1369 */
1370
1371 #define HERMON_HW_ENET_OPMOD_SELECT_GEN 0x0000 /* general params */
1372 #define HERMON_HW_ENET_OPMOD_SELECT_RQN 0x0100 /* rcv qpn calc */
1373 #define HERMON_HW_ENET_OPMOD_SELECT_MAC 0x0200 /* MAC table conf */
1374 #define HERMON_HW_ENET_OPMOD_SELECT_VLAN 0x0300 /* VLAN table conf */
1375 #define HERMON_HW_ENET_OPMOD_SELECT_PRIO 0x0400 /* Priority table */
1376 #define HERMON_HW_ENET_OPMOD_SELECT_GID 0x0500 /* GID Table */
1377
1378 /*
1379 * set port for enthernet, general parameters
1380 * Which structure
1381 */
1382
1383 #ifdef _LITTLE_ENDIAN
1384 struct hermon_hw_set_port_en_s {
1385 uint32_t mtu :16;
1386 uint32_t :16;
1387
1388 uint32_t v_mtu :1;
1389 uint32_t v_pprx :1;
1390 uint32_t v_pptx :1;
1391 uint32_t :29;
1392
1393 uint32_t :16;
1394 uint32_t pfcrx :8;
1395 uint32_t :7;
1396 uint32_t pprx :1;
1397
1398 uint32_t :16;
1399 uint32_t pfctx :8;
1400 uint32_t :7;
1401 uint32_t pptx :1;
1402
1403 uint32_t rsvd0[4];
1404 };
1405
1406 #else /* BIG ENDIAN */
1407 struct hermon_hw_set_port_en_s {
1408 uint32_t :29;
1409 uint32_t v_pptx :1;
1410 uint32_t v_pprx :1;
1411 uint32_t v_mtu :1;
1412
1413 uint32_t :16;
1414 uint32_t mtu :16;
1415
1416 uint32_t pptx :1;
1417 uint32_t :7;
1418 uint32_t pfctx :8;
1419 uint32_t :16;
1420
1421 uint32_t pprx :1;
1422 uint32_t :7;
1423 uint32_t pfcrx :8;
1424 uint32_t :16;
1425
1426 uint32_t rsvd0[4];
1427
1428 };
1429 #endif
1430
1431 /* set_port for enet, RX QPM calculations Parameters */
1432
1433 #ifdef _LITTLE_ENDIAN
1434 struct hermon_hw_set_port_en_rqpn_s {
1435 uint32_t n_p :2;
1436 uint32_t :6;
1437 uint32_t n_v :3;
1438 uint32_t :5;
1439 uint32_t n_m :4;
1440 uint32_t :12;
1441
1442 uint32_t base_qpn :24;
1443 uint32_t :8;
1444
1445 uint32_t vlan_miss_idx :7;
1446 uint32_t :8;
1447 uint32_t intra_vlan_miss :1;
1448 uint32_t no_vlan_idx :7;
1449 uint32_t :8;
1450 uint32_t intra_no_vlan :1;
1451
1452 uint32_t mac_miss_idx :8;
1453 uint32_t :24;
1454
1455 uint32_t promisc_qpn :24;
1456 uint32_t :7;
1457 uint32_t en_uc_promisc :1;
1458
1459 uint32_t no_vlan_prio :3;
1460 uint32_t :29;
1461
1462 uint32_t :32;
1463
1464 uint32_t def_mcast_qpn :24;
1465 uint32_t :5;
1466 uint32_t mc_by_vlan :1;
1467 uint32_t mc_promisc_mode :2;
1468
1469 uint32_t rsvd0[4];
1470 };
1471
1472 #else /* BIG ENDIAN */
1473 struct hermon_hw_set_port_en_rqpn_s {
1474 uint32_t :8;
1475 uint32_t base_qpn :24;
1476
1477 uint32_t :12;
1478 uint32_t n_m :4;
1479 uint32_t :5;
1480 uint32_t n_v :3;
1481 uint32_t :6;
1482 uint32_t n_p :2;
1483
1484 uint32_t :24;
1485 uint32_t mac_miss_idx :8;
1486
1487 uint32_t intra_no_vlan :1;
1488 uint32_t :8;
1489 uint32_t no_vlan_idx :7;
1490 uint32_t intra_vlan_miss :1;
1491 uint32_t :8;
1492 uint32_t vlan_miss_idx :7;
1493
1494 uint32_t :29;
1495 uint32_t no_vlan_prio :3;
1496
1497 uint32_t en_uc_promisc :1;
1498 uint32_t :7;
1499 uint32_t promisc_qpn :24;
1500
1501 uint32_t mc_promisc_mode :2;
1502 uint32_t mc_by_vlan :1;
1503 uint32_t :5;
1504 uint32_t def_mcast_qpn :24;
1505
1506 uint32_t :32;
1507
1508 uint32_t rsvd0[4];
1509 };
1510 #endif
1511
1512
1513 #ifdef _LITTLE_ENDIAN
1514 struct hermon_hw_set_port_mact_entry_s {
1515 uint32_t mac_lo :32;
1516
1517 uint32_t mac_hi :16;
1518 uint32_t :7;
1519 uint32_t mac_valid :1;
1520 };
1521 #else /* BIG ENDIAN */
1522 struct hermon_hw_set_port_mact_entry_s {
1523 uint32_t mac_valid :1;
1524 uint32_t :7;
1525 uint32_t mac_hi :16;
1526
1527 uint32_t mac_lo :32;
1528
1529 };
1530 #endif
1531
1532
1533 /* set_port for enet, MAC Table Configuration */
1534
1535 #ifdef _LITTLE_ENDIAN
1536 struct hermon_hw_set_port_en_mact_s {
1537 struct hermon_hw_set_port_mact_entry_s mtable[128];
1538 };
1539 #else /* BIG ENDIAN */
1540 struct hermon_hw_set_port_en_mact_s {
1541 struct hermon_hw_set_port_mact_entry_s mtable[128];
1542 };
1543 #endif
1544
1545
1546 /* set_port for enet, VLAN Table Configuration */
1547
1548 #ifdef _LITTLE_ENDIAN
1549 struct hermon_hw_set_port_vlant_entry_s {
1550 uint32_t vlan_id :12;
1551 uint32_t :18;
1552 uint32_t intra :1;
1553 uint32_t valid :1;
1554 };
1555 #else /* BIG ENDIAN */
1556 struct hermon_hw_set_port_vlant_entry_s {
1557 uint32_t valid :1;
1558 uint32_t intra :1;
1559 uint32_t :18;
1560 uint32_t vlan_id :12;
1561 };
1562 #endif
1563
1564 #ifdef _LITTLE_ENDIAN
1565 struct hermon_hw_set_port_en_vlant_s {
1566 uint32_t rsvd[2];
1567 struct hermon_hw_set_port_vlant_entry_s table[126];
1568 };
1569 #else /* BIG ENDIAN */
1570 struct hermon_hw_set_port_en_vlant_s {
1571 uint32_t rsvd[2];
1572 struct hermon_hw_set_port_vlant_entry_s table[126];
1573 };
1574 #endif
1575
1576 /* set_port for enet, Priority table Parameters */
1577
1578 #ifdef _LITTLE_ENDIAN
1579 struct hermon_hw_set_port_en_priot_s {
1580 uint32_t :32;
1581
1582 uint32_t prio0 :3;
1583 uint32_t :1;
1584 uint32_t prio1 :3;
1585 uint32_t :1;
1586 uint32_t prio2 :3;
1587 uint32_t :1;
1588 uint32_t prio3 :3;
1589 uint32_t :1;
1590 uint32_t prio4 :3;
1591 uint32_t :1;
1592 uint32_t prio5 :3;
1593 uint32_t :1;
1594 uint32_t prio6 :3;
1595 uint32_t :1;
1596 uint32_t prio7 :3;
1597 uint32_t :1;
1598
1599 uint32_t rsvd[2];
1600 };
1601 #else /* BIG ENDIAN */
1602 struct hermon_hw_set_port_en_priot_s {
1603 uint32_t :1;
1604 uint32_t prio7 :3;
1605 uint32_t :1;
1606 uint32_t prio6 :3;
1607 uint32_t :1;
1608 uint32_t prio5 :3;
1609 uint32_t :1;
1610 uint32_t prio4 :3;
1611 uint32_t :1;
1612 uint32_t prio3 :3;
1613 uint32_t :1;
1614 uint32_t prio2 :3;
1615 uint32_t :1;
1616 uint32_t prio1 :3;
1617 uint32_t :1;
1618 uint32_t prio0 :3;
1619
1620 uint32_t :32;
1621
1622 uint32_t rsvd[2];
1623
1624 };
1625 #endif
1626
1627
1628 /* note: GID table is same BIG or LITTLE ENDIAN */
1629
1630 struct hermon_hw_set_port_gidtable_s {
1631 uint64_t gid[128];
1632 };
1633
1634 #ifdef _LITTLE_ENDIAN
1635 struct hermon_hw_conf_int_mod_s {
1636 uint32_t :32;
1637
1638 uint32_t int_vect :16;
1639 uint32_t min_delay :16;
1640 };
1641 #else /* BIG ENDIAN */
1642 struct hermon_hw_conf_int_mod_s {
1643 uint32_t min_delay :16;
1644 uint32_t int_vect :16;
1645
1646 uint32_t :32;
1647 };
1648 #endif
1649
1650
1651
1652
1653 /*
1654 * Hermon Memory Protection Table (MPT) entries
1655 *
1656 * The Memory Protection Table (MPT) contains the information associated
1657 * with all the regions and windows. The MPT table resides in a virtually-
1658 * contiguous area in ICM, and the memory key (R_Key or L_Key) is used to
1659 * calculate the physical address for accessing the entries in the table.
1660 *
1661 *
1662 * The SW2HW_MPT command transfers ownership of an MPT entry from software
1663 * to hardware. The command takes the MPT entry from the input mailbox and
1664 * stores it in the MPT in the hardware. The command will fail if the
1665 * requested MPT entry is already owned by the hardware or if the MPT index
1666 * given in the command is inconsistent with the MPT entry memory key.
1667 * The QUERY_MPT command retrieves a snapshot of an MPT entry. The command
1668 * takes the current state of an MPT entry from the hardware and stores it
1669 * in the output mailbox. The command will fail if the requested MPT entry
1670 * is already owned by software.
1671 * Finally, the HW2SW_MPT command transfers ownership of an MPT entry from
1672 * the hardware to the software. The command takes the MPT entry from the
1673 * hardware, invalidates it, and stores it in the output mailbox. The
1674 * command will fail if the requested entry is already owned by software.
1675 * The command will also fail if the MPT entry in question is a Memory
1676 * Region which has Memory Windows currently bound to it.
1677 *
1678 * The following structure is used in the SW2HW_MPT, QUERY_MPT, and
1679 * HW2SW_MPT commands, and ONLY for the dMPT - for data.
1680 */
1681
1682 #ifdef _LITTLE_ENDIAN
1683 struct hermon_hw_dmpt_s {
1684 uint32_t :7;
1685 uint32_t bnd_qp :1;
1686 uint32_t qpn :24; /* dw 1, byte 4-7 */
1687
1688 uint32_t :8;
1689 uint32_t reg_win :1;
1690 uint32_t phys_addr :1;
1691 uint32_t lr :1;
1692 uint32_t lw :1;
1693 uint32_t rr :1;
1694 uint32_t rw :1;
1695 uint32_t atomic :1;
1696 uint32_t en_bind :1;
1697 uint32_t atc_req :1;
1698 uint32_t atc_xlat :1;
1699 uint32_t :1;
1700 uint32_t no_snoop :1;
1701 uint32_t :8;
1702 uint32_t status :4; /* dw 0, byte 0-3 */
1703
1704 uint32_t pd :24;
1705 uint32_t ren_inval :1;
1706 uint32_t en_inval :1;
1707 uint32_t net_cache :1;
1708 uint32_t fast_reg_en :1;
1709 uint32_t rem_acc_en :1;
1710 uint32_t w_dif :1;
1711 uint32_t m_dif :1;
1712 uint32_t :1; /* dw 2, byte 0xc-f */
1713
1714 uint32_t mem_key;
1715
1716 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */
1717
1718 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */
1719
1720 uint32_t win_cnt :24;
1721 uint32_t :8; /* dw 9, byte 0x24-27 */
1722
1723 uint32_t lkey; /* dw 8, byte 0x20-23 */
1724
1725 uint32_t mtt_addr_h :8;
1726 uint32_t :24; /* dw 11, byte 0x2c-2f */
1727
1728 uint32_t mtt_rep :4;
1729 uint32_t :17;
1730 uint32_t blk_mode :1;
1731 uint32_t len_b64 :1; /* bit 64 of length */
1732 uint32_t fbo_en :1;
1733 uint32_t :8; /* dw 10, byte 0x28-2b */
1734
1735 uint32_t mtt_size; /* dw 13, byte 0x34-37 */
1736
1737 uint32_t :3;
1738 uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */
1739
1740 uint32_t mtt_fbo :21;
1741 uint32_t :11; /* dw 15, byte 0x3c-3f */
1742
1743 uint32_t entity_sz :21;
1744 uint32_t :11; /* dw 14, byte 0x38-3b */
1745
1746 uint32_t dif_m_atag :16;
1747 uint32_t :16; /* dw 17, 0x44-47 */
1748
1749 uint32_t dif_a_msk :16;
1750 uint32_t dif_v_msk :2;
1751 uint32_t dif_rep :2;
1752 uint32_t :4;
1753 uint32_t dif_err :3;
1754 uint32_t :5; /* dw 16, 0x40-43 */
1755
1756 uint32_t dif_w_atag :16;
1757 uint32_t :16; /* dw 19, 0x4c-4f */
1758
1759 uint32_t dif_m_rtagb; /* dw 18, 0x48-4b */
1760
1761 uint32_t :32;
1762
1763 uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */
1764
1765 uint32_t rsvd[10];
1766
1767 };
1768
1769 #else /* BIG ENDIAN */
1770 struct hermon_hw_dmpt_s {
1771 uint32_t status :4;
1772 uint32_t :8;
1773 uint32_t no_snoop :1;
1774 uint32_t :1;
1775 uint32_t atc_xlat :1;
1776 uint32_t atc_req :1;
1777 uint32_t en_bind :1;
1778 uint32_t atomic :1;
1779 uint32_t rw :1;
1780 uint32_t rr :1;
1781 uint32_t lw :1;
1782 uint32_t lr :1;
1783 uint32_t phys_addr :1;
1784 uint32_t reg_win :1;
1785 uint32_t :8; /* dw 0, byte 0x0-3 */
1786
1787 uint32_t qpn :24;
1788 uint32_t bnd_qp :1;
1789 uint32_t :7; /* dw 1, byte 0x4-7 */
1790
1791 uint32_t mem_key; /* dw 2, byte 0x8-b */
1792
1793 uint32_t :1;
1794 uint32_t m_dif :1;
1795 uint32_t w_dif :1;
1796 uint32_t rem_acc_en :1;
1797 uint32_t fast_reg_en :1;
1798 uint32_t net_cache :1;
1799 uint32_t en_inval :1;
1800 uint32_t ren_inval :1;
1801 uint32_t pd :24; /* dw 3, byte 0xc-f */
1802
1803 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */
1804
1805 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */
1806
1807 uint32_t lkey; /* dw 8, bytd 0x20-23 */
1808
1809 uint32_t :8;
1810 uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */
1811
1812 uint32_t :8;
1813 uint32_t fbo_en :1;
1814 uint32_t len_b64 :1; /* bit 64 of length */
1815 uint32_t blk_mode :1;
1816 uint32_t :17;
1817 uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */
1818
1819 uint32_t :24;
1820 uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */
1821
1822 uint32_t mtt_addr_l :29;
1823 uint32_t :3; /* dw 12, byte 0x30-33 */
1824
1825 uint32_t mtt_size; /* dw 13, byte 0x34-37 */
1826
1827 uint32_t :11;
1828 uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */
1829
1830 uint32_t :11;
1831 uint32_t mtt_fbo :21; /* dw 15, byte 0x3c-3f */
1832
1833 uint32_t :5;
1834 uint32_t dif_err :3;
1835 uint32_t :4;
1836 uint32_t dif_rep :2;
1837 uint32_t dif_v_msk :2;
1838 uint32_t dif_a_msk :16; /* dw 16, 0x40-43 */
1839
1840 uint32_t :16;
1841 uint32_t dif_m_atag :16; /* dw 17, 0x44-47 */
1842
1843 uint32_t dif_m_rtagb; /* dw 18, 0x48-4b */
1844
1845 uint32_t :16;
1846 uint32_t dif_w_atag :16; /* dw 19, 0x4c-4f */
1847
1848 uint32_t dif_w_rtagb; /* dw 20, 0x50-53 */
1849
1850 uint32_t :32;
1851
1852 uint32_t rsvd[10];
1853
1854 };
1855 #endif
1856
1857 /*
1858 * The following structure is for the CMPTs. This is NEVER actually built and
1859 * passed to the hardware - we use it to track information needed for the
1860 * context entries, and to facilitate the alloc tracking. It differs from
1861 * the dMPT sturcture above in that it does not have/need the "dif" stuff.
1862 *
1863 */
1864
1865
1866
1867 #ifdef _LITTLE_ENDIAN
1868 struct hermon_hw_cmpt_s {
1869 uint32_t :7;
1870 uint32_t bnd_qp :1;
1871 uint32_t qpn :24; /* dw 1, byte 4-7 */
1872
1873 uint32_t :8;
1874 uint32_t reg_win :1;
1875 uint32_t phys_addr :1;
1876 uint32_t lr :1;
1877 uint32_t lw :1;
1878 uint32_t rr :1;
1879 uint32_t rw :1;
1880 uint32_t atomic :1;
1881 uint32_t en_bind :1;
1882 uint32_t atc_req :1;
1883 uint32_t atc_xlat :1;
1884 uint32_t :1;
1885 uint32_t no_snoop :1;
1886 uint32_t :8;
1887 uint32_t status :4; /* dw 0, byte 0-3 */
1888
1889 uint32_t pd :24;
1890 uint32_t ren_inval :1;
1891 uint32_t en_inval :1;
1892 uint32_t net_cache :1;
1893 uint32_t fast_reg_en :1;
1894 uint32_t rem_acc_en :1;
1895 uint32_t w_dif :1;
1896 uint32_t m_dif :1;
1897 uint32_t :1; /* dw 2, byte 0xc-f */
1898
1899 uint32_t mem_key;
1900 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */
1901
1902 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */
1903
1904 uint32_t win_cnt :24;
1905 uint32_t :8; /* dw 9, byte 0x24-27 */
1906
1907 uint32_t lkey; /* dw 8, byte 0x20-23 */
1908
1909 uint32_t mtt_addr_h :8;
1910 uint32_t :24; /* dw 11, byte 0x2c-2f */
1911
1912 uint32_t mtt_rep :4;
1913 uint32_t :17;
1914 uint32_t blk_mode :1;
1915 uint32_t len_b64 :1; /* bit 64 of length */
1916 uint32_t fbo_en :1;
1917 uint32_t :8; /* dw 10, byte 0x28-2b */
1918
1919 uint32_t mtt_size; /* dw 13, byte 0x34-37 */
1920
1921 uint32_t :3;
1922 uint32_t mtt_addr_l :29; /* dw 12, byte 0x30-33 */
1923
1924 uint32_t mtt_fbo :21;
1925 uint32_t :11; /* dw 15, byte 0x3c-3f */
1926
1927 uint32_t entity_sz :21;
1928 uint32_t :11; /* dw 14, byte 0x38-3b */
1929
1930 };
1931
1932
1933 #else /* BIG ENDIAN */
1934 struct hermon_hw_cmpt_s {
1935 uint32_t status :4;
1936 uint32_t :8;
1937 uint32_t no_snoop :1;
1938 uint32_t :1;
1939 uint32_t atc_xlat :1;
1940 uint32_t atc_req :1;
1941 uint32_t en_bind :1;
1942 uint32_t atomic :1;
1943 uint32_t rw :1;
1944 uint32_t rr :1;
1945 uint32_t lw :1;
1946 uint32_t lr :1;
1947 uint32_t phys_addr :1;
1948 uint32_t reg_win :1;
1949 uint32_t :8; /* dw 0, byte 0x0-3 */
1950
1951 uint32_t qpn :24;
1952 uint32_t bnd_qp :1;
1953 uint32_t :7; /* dw 1, byte 0x4-7 */
1954
1955 uint32_t mem_key; /* dw 2, byte 0x8-b */
1956
1957 uint32_t :1;
1958 uint32_t m_dif :1;
1959 uint32_t w_dif :1;
1960 uint32_t rem_acc_en :1;
1961 uint32_t fast_reg_en :1;
1962 uint32_t net_cache :1;
1963 uint32_t en_inval :1;
1964 uint32_t ren_inval :1;
1965 uint32_t pd :24; /* dw 3, byte 0xc-f */
1966
1967 uint64_t start_addr; /* dw 4-5, byte 0x10-17 */
1968
1969 uint64_t reg_win_len; /* dw 6-7, byte 0x18-1f */
1970
1971 uint32_t lkey; /* dw 8, bytd 0x20-23 */
1972
1973 uint32_t :8;
1974 uint32_t win_cnt :24; /* dw 9, byte 0x24-27 */
1975
1976 uint32_t :8;
1977 uint32_t fbo_en :1;
1978 uint32_t len_b64 :1; /* bit 64 of length */
1979 uint32_t blk_mode :1;
1980 uint32_t :17;
1981 uint32_t mtt_rep :4; /* dw 10, byte 0x28-2b */
1982
1983 uint32_t :24;
1984 uint32_t mtt_addr_h :8; /* dw 11, byte 0x2c-2f */
1985
1986 uint32_t mtt_addr_l :29;
1987 uint32_t :3; /* dw 12, byte 0x30-33 */
1988
1989 uint32_t mtt_size; /* dw 13, byte 0x34-37 */
1990
1991 uint32_t :11;
1992 uint32_t entity_sz :21; /* dw 14, byte 0x38-3b */
1993
1994 uint32_t :11; /* dw 15, byte 0x3c-3f */
1995 uint32_t mtt_fbo :21;
1996 };
1997 #endif
1998
1999
2000 #define HERMON_MEM_CYCLE_GENERATE 0x1
2001 #define HERMON_IO_CYCLE_GENERATE 0x0
2002
2003 #define HERMON_MPT_IS_WINDOW 0x0
2004 #define HERMON_MPT_IS_REGION 0x1
2005
2006 #define HERMON_MPT_DEFAULT_VERSION 0x0
2007
2008 #define HERMON_UNLIMITED_WIN_BIND 0x0
2009
2010 #define HERMON_PHYSADDR_ENABLED 0x1
2011 #define HERMON_PHYSADDR_DISABLED 0x0
2012
2013
2014 /*
2015 * Hermon Memory Translation Table (MTT) entries
2016 * After accessing the MPT table (above) and validating the access rights
2017 * to the region/window, Hermon address translation moves to the next step
2018 * where it translates the virtual address to a physical address. This
2019 * translation is performed using the Memory Translation Table entries
2020 * (MTT). Note: The MTT in hardware is organized into segments and each
2021 * segment contains multiple address translation pages (MTT entries).
2022 * Each memory region (MPT above) points to the first segment in the MTT
2023 * that corresponds to that region.
2024 */
2025
2026 #ifdef _LITTLE_ENDIAN
2027 struct hermon_hw_mtt_s {
2028 uint32_t present :1;
2029 uint32_t :2;
2030 uint32_t ptag_l :29;
2031
2032 uint32_t ptag_h;
2033 };
2034 #else /* BIG_ENDIAN */
2035 struct hermon_hw_mtt_s {
2036 uint32_t ptag_h;
2037
2038 uint32_t ptag_l :29;
2039 uint32_t :2;
2040 uint32_t present :1;
2041 };
2042
2043 #endif
2044 #define HERMON_MTT_ENTRY_NOTPRESENT 0x0
2045 #define HERMON_MTT_ENTRY_PRESENT 0x1
2046
2047
2048 /*
2049 * Hermon Event Queue Context Table (EQC) entries
2050 * Hermon supports 512 Event Queues, and the status of Event Queues is stored
2051 * in the Event Queue Context (EQC) table. The EQC table is a virtually-
2052 * contiguous memory structure in the ICM. Each EQC
2053 * table entry contains Event Queue status and information required by
2054 * the hardware in order to access the event queue.
2055 * NOTE that in Hermon (as opposed to earlier HCAs),
2056 * you have to allocate ICM for 2**32 (or about 16 M), even though
2057 * it doesn't support that many. See PRM v35. Also, some set of them
2058 * will be available for each domain in a virtual environment, needing to
2059 * rething the allocation and usage model for EQs - in the future.
2060 *
2061 * The following structure is used in the SW2HW_EQ, QUERY_EQ, and HW2SW_EQ
2062 * commands.
2063 * The SW2HW_EQ command transfers ownership of an EQ context from software
2064 * to hardware. The command takes the EQC entry from the input mailbox and
2065 * stores it in the EQC in the hardware. The command will fail if the
2066 * requested EQC entry is already owned by the hardware. NOTE: the
2067 * initialization of the cMPT for the EQC occurs implicitly as a result
2068 * of executing this command, and MR has/had to be adjusted for it.
2069 * The QUERY_EQ command retrieves a snapshot of an EQC entry. The command
2070 * stores the snapshot in the output mailbox. The EQC state and its values
2071 * are not affected by the QUERY_EQ command.
2072 * Finally, the HW2SW_EQ command transfers ownership of an EQC entry from
2073 * the hardware to the software. The command takes the EQC entry from the
2074 * hardware and stores it in the output mailbox. The EQC entry will be
2075 * invalidated as a result of the command. It is the responsibility of the
2076 * software to unmap all the events, which might have been previously
2077 * mapped to the EQ, prior to issuing the HW2SW_EQ command.
2078 */
2079
2080
2081 #ifdef _LITTLE_ENDIAN
2082 struct hermon_hw_eqc_s {
2083 uint32_t :32;
2084
2085 uint32_t :8;
2086 uint32_t state :4;
2087 uint32_t :5;
2088 uint32_t overrun_ignore :1;
2089 uint32_t ev_coalesc :1;
2090 uint32_t :9;
2091 uint32_t status :4;
2092
2093 uint32_t :24;
2094 uint32_t log_eq_sz :5;
2095 uint32_t :3;
2096
2097 uint32_t :5;
2098 uint32_t pg_offs :7;
2099 uint32_t :20;
2100
2101 uint32_t intr :10;
2102 uint32_t :22;
2103
2104 uint32_t eq_max_cnt :16;
2105 uint32_t eq_period :16;
2106
2107 uint32_t :3;
2108 uint32_t mtt_base_addrl :29;
2109
2110 uint32_t mtt_base_addrh :8;
2111 uint32_t :16;
2112 uint32_t log2_pgsz :6; /* in 4K pages */
2113 uint32_t :2;
2114
2115 uint32_t rsrv0[2];
2116
2117 uint32_t prod_indx :24;
2118 uint32_t :8;
2119
2120 uint32_t cons_indx :24;
2121 uint32_t :8;
2122
2123 uint64_t rsrv1[2]; /* force it to 8b alignment */
2124 };
2125 #else /* BIG ENDIAN */
2126 struct hermon_hw_eqc_s {
2127 uint32_t status :4;
2128 uint32_t :9;
2129 uint32_t ev_coalesc :1;
2130 uint32_t overrun_ignore :1;
2131 uint32_t :5;
2132 uint32_t state :4;
2133 uint32_t :8;
2134
2135 uint32_t :32;
2136
2137 uint32_t :20;
2138 uint32_t pg_offs :7;
2139 uint32_t :5;
2140
2141 uint32_t :3;
2142 uint32_t log_eq_sz :5;
2143 uint32_t :24;
2144
2145 uint32_t eq_period :16;
2146 uint32_t eq_max_cnt :16;
2147
2148 uint32_t :22;
2149 uint32_t intr :10;
2150
2151 uint32_t :2;
2152 uint32_t log2_pgsz :6; /* in 4K pages */
2153 uint32_t :16;
2154 uint32_t mtt_base_addrh :8;
2155
2156 uint32_t mtt_base_addrl :29;
2157 uint32_t :3;
2158
2159 uint32_t rsrv0[2];
2160
2161 uint32_t :8;
2162 uint32_t cons_indx :24;
2163
2164 uint32_t :8;
2165 uint32_t prod_indx :24;
2166
2167 uint64_t rsrv1[2]; /* force it to 8b alignment */
2168 };
2169 #endif
2170 #define HERMON_EQ_STATUS_OK 0x0
2171 #define HERMON_EQ_STATUS_OVERFLOW 0x9
2172 #define HERMON_EQ_STATUS_WRITE_FAILURE 0xA
2173
2174 #define HERMON_EQ_ARMED 0x9
2175 #define HERMON_EQ_FIRED 0xA
2176 #define HERMON_EQ_ALWAYS_ARMED 0xB
2177
2178
2179 /*
2180 * Hermon Event Queue Entries (EQE)
2181 * Each EQE contains enough information for the software to identify the
2182 * source of the event. The following structures are used to define each
2183 * of the various kinds of events that the Hermon hardware will generate.
2184 * Note: The hermon_hw_eqe_t below is the generic "Event Queue Entry". All
2185 * other EQEs differ only in the contents of their "event_data" field.
2186 *
2187 * Below we first define several structures which define the contents of
2188 * the "event_data" fields:
2189 * hermon_hw_eqe_cq_t for "Completion Queue Events"
2190 * hermon_hw_eqe_qp_evt_t for "Queue Pair Events" such as Path Migration
2191 * Succeeded, Path Migration Failed, Communication Established, Send
2192 * Queue Drained, Local WQ Catastrophic Error, Invalid Request Local
2193 * WQ Error, and Local Access Violation WQ Error.
2194 * hermon_hw_eqe_cqerr_t for "Completion Queue Error Events"
2195 * hermon_hw_eqe_portstate_t for "Port State Change Events"
2196 * hermon_hw_eqe_gpio_t for "GPIO State Change Events"
2197 * hermon_hw_eqe_cmdcmpl_t for "Command Interface Completion Events"
2198 * hermon_hw_eqe_operr_t for "Operational and Catastrophic Error Events"
2199 * such as EQ Overflow, Misbehaved UAR page, Internal Parity Error,
2200 * Uplink bus error, and DDR data error.
2201 * hermon_hw_eqe_pgflt_t for "Not-present Page Fault on WQE or Data
2202 * Buffer Access". (Note: Currently, this event is unsupported).
2203 *
2204 * Note also: The following structures are not #define'd with both
2205 * little-endian and big-endian definitions. This is because their
2206 * individual fields are not directly accessed except through the macros
2207 * defined below.
2208 */
2209
2210
2211 typedef struct hermon_hw_eqe_cq_s {
2212 uint32_t :8;
2213 uint32_t cqn :24;
2214 uint32_t rsrv0[5];
2215 } hermon_hw_eqe_cq_t;
2216
2217
2218
2219 typedef struct hermon_hw_eqe_qp_evt_s {
2220 uint32_t :8;
2221 uint32_t qpn :24;
2222
2223 uint32_t rsrv0[5];
2224 } hermon_hw_eqe_qpevt_t;
2225
2226
2227 typedef struct hermon_hw_eqe_cqerr_s {
2228 uint32_t :8;
2229 uint32_t cqn :24;
2230
2231 uint32_t :32;
2232
2233 uint32_t :24;
2234 uint32_t syndrome :8;
2235
2236 uint32_t rsrv0[3];
2237 } hermon_hw_eqe_cqerr_t;
2238 #define HERMON_CQERR_OVERFLOW 0x1
2239 #define HERMON_CQERR_ACCESS_VIOLATION 0x2
2240
2241
2242 typedef struct hermon_hw_eqe_portstate_s {
2243 uint32_t rsrv0[2];
2244
2245 uint32_t :2;
2246 uint32_t port :2;
2247 uint32_t :28;
2248
2249 uint32_t rsrv1[3];
2250 } hermon_hw_eqe_portstate_t;
2251 #define HERMON_PORT_LINK_ACTIVE 0x4
2252 #define HERMON_PORT_LINK_DOWN 0x1
2253
2254
2255 typedef struct hermon_hw_eqe_gpio_s {
2256 uint32_t rsrv0[3];
2257
2258 uint32_t gpio_ev0;
2259
2260 uint32_t gpio_ev1;
2261
2262 uint32_t :32;
2263 } hermon_hw_eqe_gpio_t;
2264
2265
2266 typedef struct hermon_hw_eqe_cmdcmpl_s {
2267 uint32_t :16;
2268 uint32_t token :16;
2269
2270 uint32_t :32;
2271
2272 uint32_t :24;
2273 uint32_t status :8;
2274
2275 uint32_t out_param0;
2276
2277 uint32_t out_param1;
2278
2279 uint32_t :32;
2280 } hermon_hw_eqe_cmdcmpl_t;
2281
2282
2283 typedef struct hermon_hw_eqe_operr_s {
2284 uint32_t rsrv0[2];
2285
2286 uint32_t :24;
2287 uint32_t error_type :8;
2288
2289 uint32_t data;
2290
2291 uint32_t rsrv1[2];
2292 } hermon_hw_eqe_operr_t;
2293 #define HERMON_ERREVT_EQ_OVERFLOW 0x1
2294 #define HERMON_ERREVT_BAD_UARPG 0x2
2295 #define HERMON_ERREVT_UPLINK_BUSERR 0x3
2296 #define HERMON_ERREVT_DDR_DATAERR 0x4
2297 #define HERMON_ERREVT_INTERNAL_PARITY 0x5
2298
2299
2300 typedef struct hermon_hw_eqe_fcerr_s {
2301 uint32_t :14;
2302 uint32_t port :2;
2303 uint32_t fexch :16; /* fexch number */
2304
2305 uint32_t :32;
2306
2307 uint32_t :24;
2308 uint32_t fcsyndrome :8;
2309
2310 uint32_t rsvd[3];
2311 } hermon_hw_eqe_fcerr_t;
2312
2313 #define HERMON_ERR_FC_BADIU 0x0
2314 #define HERMON_ERR_FC_SEQUENCE 0x01
2315
2316 typedef struct hermon_hw_eqe_pgflt_s {
2317 uint32_t rsrv0[2];
2318 uint32_t :24;
2319 uint32_t fault_type :4;
2320 uint32_t wqv :1;
2321 uint32_t wqe_data :1;
2322 uint32_t rem_loc :1;
2323 uint32_t snd_rcv :1;
2324 uint32_t vaddr_h;
2325 uint32_t vaddr_l;
2326 uint32_t mem_key;
2327 } hermon_hw_eqe_pgflt_t;
2328 #define HERMON_PGFLT_PG_NOTPRESENT 0x8
2329 #define HERMON_PGFLT_PG_WRACC_VIOL 0xA
2330 #define HERMON_PGFLT_UNSUP_NOTPRESENT 0xE
2331 #define HERMON_PGFLT_UNSUP_WRACC_VIOL 0xF
2332 #define HERMON_PGFLT_WQE_CAUSED 0x1
2333 #define HERMON_PGFLT_DATA_CAUSED 0x0
2334 #define HERMON_PGFLT_REMOTE_CAUSED 0x1
2335 #define HERMON_PGFLT_LOCAL_CAUSED 0x0
2336 #define HERMON_PGFLT_SEND_CAUSED 0x1
2337 #define HERMON_PGFLT_RECV_CAUSED 0x0
2338 #define HERMON_PGFLT_DESC_CONSUMED 0x1
2339 #define HERMON_PGFLT_DESC_NOTCONSUMED 0x0
2340
2341 struct hermon_hw_eqe_s {
2342 uint32_t :8;
2343 uint32_t event_type :8;
2344 uint32_t :8;
2345 uint32_t event_subtype :8;
2346 union {
2347 hermon_hw_eqe_cq_t eqe_cq;
2348 hermon_hw_eqe_qpevt_t eqe_qpevt;
2349 hermon_hw_eqe_cqerr_t eqe_cqerr;
2350 hermon_hw_eqe_portstate_t eqe_portstate;
2351 hermon_hw_eqe_gpio_t eqe_gpio;
2352 hermon_hw_eqe_cmdcmpl_t eqe_cmdcmpl;
2353 hermon_hw_eqe_operr_t eqe_operr;
2354 hermon_hw_eqe_pgflt_t eqe_pgflt;
2355 hermon_hw_eqe_fcerr_t eqe_fcerr;
2356 } event_data;
2357 uint32_t :24;
2358 uint32_t owner :1;
2359 uint32_t :7;
2360 };
2361 #define eqe_cq event_data.eqe_cq
2362 #define eqe_qpevt event_data.eqe_qpevt
2363 #define eqe_cqerr event_data.eqe_cqerr
2364 #define eqe_portstate event_data.eqe_portstate
2365 #define eqe_gpio event_data.eqe_gpio
2366 #define eqe_cmdcmpl event_data.eqe_cmdcmpl
2367 #define eqe_operr event_data.eqe_operr
2368 #define eqe_pgflt event_data.eqe_pgflt
2369 #define eqe_fcerr event_data.eqe_fcerr
2370
2371 /*
2372 * The following macros are used for extracting (and in some cases filling in)
2373 * information from EQEs
2374 */
2375 #define HERMON_EQE_CQNUM_MASK 0x00FFFFFF
2376 #define HERMON_EQE_CQNUM_SHIFT 0
2377 #define HERMON_EQE_QPNUM_MASK 0x00FFFFFF
2378 #define HERMON_EQE_QPNUM_SHIFT 0
2379 #define HERMON_EQE_PORTNUM_MASK 0x30
2380 #define HERMON_EQE_PORTNUM_SHIFT 4
2381 #define HERMON_EQE_OWNER_MASK 0x00000080
2382 #define HERMON_EQE_OWNER_SHIFT 7
2383
2384 #define HERMON_EQE_EVTTYPE_GET(eq, eqe) \
2385 (((uint8_t *)(eqe))[1])
2386 #define HERMON_EQE_EVTSUBTYPE_GET(eq, eqe) \
2387 (((uint8_t *)(eqe))[3])
2388 #define HERMON_EQE_CQNUM_GET(eq, eqe) \
2389 ((htonl(((uint32_t *)(eqe))[1]) & HERMON_EQE_CQNUM_MASK) >> \
2390 HERMON_EQE_CQNUM_SHIFT)
2391 #define HERMON_EQE_QPNUM_GET(eq, eqe) \
2392 ((htonl(((uint32_t *)(eqe))[1]) & HERMON_EQE_QPNUM_MASK) >> \
2393 HERMON_EQE_QPNUM_SHIFT)
2394 #define HERMON_EQE_PORTNUM_GET(eq, eqe) \
2395 (((((uint8_t *)(eqe))[12]) & HERMON_EQE_PORTNUM_MASK) >> \
2396 HERMON_EQE_PORTNUM_SHIFT)
2397 #define HERMON_EQE_CMDTOKEN_GET(eq, eqe) \
2398 htons(((uint16_t *)(eqe))[3])
2399 #define HERMON_EQE_CMDSTATUS_GET(eq, eqe) \
2400 (((uint8_t *)(eqe))[0xf])
2401 #define HERMON_EQE_CMDOUTP0_GET(eq, eqe) \
2402 htonl(((uint32_t *)(eqe))[4])
2403 #define HERMON_EQE_CMDOUTP1_GET(eq, eqe) \
2404 htonl(((uint32_t *)(eqe))[5])
2405 #define HERMON_EQE_OPERRTYPE_GET(eq, eqe) \
2406 (((uint8_t *)(eqe))[0xf])
2407 #define HERMON_EQE_OPERRDATA_GET(eq, eqe) \
2408 htonl(((uint32_t *)(eqe))[4])
2409 #define HERMON_EQE_FEXCH_PORTNUM_GET(eq, eqe) \
2410 (((uint8_t *)(eqe))[5] & 0x3)
2411 #define HERMON_EQE_FEXCH_FEXCH_GET(eq, eqe) \
2412 htons(((uint16_t *)(eqe))[3])
2413 #define HERMON_EQE_FEXCH_SYNDROME_GET(eq, eqe) \
2414 (((uint8_t *)(eqe))[15])
2415
2416 /*
2417 * Hermon does ownership of CQ and EQ differently from Arbel & Tavor.
2418 * Now, you keep track of the TOTAL number of CQE's or EQE's that have been
2419 * processed, and the sense of the ownership bit changes each time through.
2420 * That is, if the size of the queue is 16, so 4 bits [3:0] are the index
2421 * number, then bit [4] is the ownership bit in the count. So you mask that
2422 * bit and compare it to the owner bit in the entry - if the same, then the
2423 * entry is in SW onwership. Otherwise, it's in hardware and the driver
2424 * does not consume it.
2425 */
2426
2427 #define HERMON_EQE_OWNER_IS_SW(eq, eqe, consindx, shift) \
2428 ((((uint8_t *)(eqe))[0x1f] & HERMON_EQE_OWNER_MASK) == \
2429 (((consindx) & eq->eq_bufsz) >> (shift)))
2430
2431 /*
2432 * Hermon Completion Queue Context Table (CQC) entries
2433 * The CQC table is a virtually-contiguous memory area residing in HCA's
2434 * ICM. Each CQC table entry contains information
2435 * required by the hardware to access the completion queue to post
2436 * completions (CQE).
2437 *
2438 * The following structure is used in the SW2HW_CQ, QUERY_CQ, RESIZE_CQ,
2439 * and HW2SW_CQ commands.
2440 * The SW2HW_CQ command transfers ownership of an CQ context from software
2441 * to hardware. The command takes the CQC entry from the input mailbox and
2442 * stores it in the CQC in the hardware. The command will fail if the
2443 * requested CQC entry is already owned by the hardware.
2444 * The QUERY_CQ command retrieves a snapshot of a CQC entry. The command
2445 * stores the snapshot in the output mailbox. The CQC state and its values
2446 * are not affected by the QUERY_CQ command.
2447 * Finally, the HW2SW_CQ command transfers ownership of a CQC entry from
2448 * the hardware to the software. The command takes the CQC entry from the
2449 * hardware and stores it in the output mailbox. The CQC entry will be
2450 * invalidated as a result of the command.
2451 */
2452
2453
2454 #ifdef _LITTLE_ENDIAN
2455 struct hermon_hw_cqc_s {
2456 uint32_t :32;
2457
2458 uint32_t :8;
2459 uint32_t state :4;
2460 uint32_t :5;
2461 uint32_t overrun_ignore :1;
2462 uint32_t cqe_coalesc :1;
2463 uint32_t :9;
2464 uint32_t status :4;
2465
2466 uint32_t usr_page :24;
2467 uint32_t log_cq_sz :5;
2468 uint32_t :3;
2469
2470 uint32_t :5;
2471 uint32_t pg_offs :7;
2472 uint32_t :20;
2473
2474 uint32_t c_eqn :9;
2475 uint32_t :23;
2476
2477 uint32_t cq_max_cnt :16;
2478 uint32_t cq_period :16;
2479
2480 uint32_t :3;
2481 uint32_t mtt_base_addl :29;
2482
2483 uint32_t mtt_base_addh :8;
2484 uint32_t :16;
2485 uint32_t log2_pgsz :6;
2486 uint32_t :2;
2487
2488 uint32_t solicit_prod_indx :24;
2489 uint32_t :8;
2490
2491 uint32_t last_notified_indx :24;
2492 uint32_t :8;
2493
2494 uint32_t prod_cntr :24; /* producer counter */
2495 uint32_t :8;
2496
2497 uint32_t cons_cntr :24; /* consumer counter */
2498 uint32_t :8;
2499
2500 uint32_t rsrv0[2];
2501
2502 uint32_t :3;
2503 uint32_t dbr_addrl :29;
2504
2505 uint32_t dbr_addrh;
2506
2507 uint64_t rsrv1[8]; /* hermon, match DEV_CAP size */
2508 };
2509 #else
2510 struct hermon_hw_cqc_s {
2511 uint32_t status :4;
2512 uint32_t :9;
2513 uint32_t cqe_coalesc :1;
2514 uint32_t overrun_ignore :1;
2515 uint32_t :5;
2516 uint32_t state :4;
2517 uint32_t :8;
2518
2519 uint32_t :32;
2520
2521 uint32_t :20;
2522 uint32_t pg_offs :7;
2523 uint32_t :5;
2524
2525 uint32_t :3;
2526 uint32_t log_cq_sz :5;
2527 uint32_t usr_page :24;
2528
2529 uint32_t cq_period :16;
2530 uint32_t cq_max_cnt :16;
2531
2532 uint32_t :23;
2533 uint32_t c_eqn :9;
2534
2535 uint32_t :2;
2536 uint32_t log2_pgsz :6;
2537 uint32_t :16;
2538 uint32_t mtt_base_addh :8;
2539
2540 uint32_t mtt_base_addl :29;
2541 uint32_t :3;
2542
2543 uint32_t :8;
2544 uint32_t last_notified_indx :24;
2545
2546 uint32_t :8;
2547 uint32_t solicit_prod_indx :24;
2548
2549 uint32_t :8;
2550 uint32_t cons_cntr :24; /* consumer counter */
2551
2552 uint32_t :8;
2553 uint32_t prod_cntr :24; /* priducer counter */
2554
2555 uint32_t rsrv0[2];
2556
2557 uint32_t dbr_addrh;
2558
2559 uint32_t dbr_addrl :29;
2560 uint32_t :3;
2561
2562 uint64_t rsrv1[8]; /* hermon, match DEV_CAP size */
2563 };
2564 #endif
2565 #define HERMON_CQ_STATUS_OK 0x0
2566 #define HERMON_CQ_STATUS_OVERFLOW 0x9
2567 #define HERMON_CQ_STATUS_WRITE_FAILURE 0xA
2568
2569 #define HERMON_CQ_DISARMED 0x0
2570 #define HERMON_CQ_ARMED 0x1
2571 #define HERMON_CQ_ARMED_SOLICITED 0x4
2572 #define HERMON_CQ_FIRED 0xA
2573
2574 /*
2575 * Hermon Completion Queue Entries (CQE)
2576 * Each CQE contains enough information for the software to associate the
2577 * completion with the Work Queue Element (WQE) to which it corresponds.
2578 *
2579 * Note: The following structure is not #define'd with both little-endian
2580 * and big-endian definitions. This is because each CQE's individual
2581 * fields are not directly accessed except through the macros defined below.
2582 */
2583
2584
2585 struct hermon_hw_cqe_s {
2586 uint32_t dife :1;
2587 uint32_t vlan :2;
2588 uint32_t fl :1;
2589 uint32_t fcrc_sd :1;
2590 uint32_t d2s :1;
2591 uint32_t :2;
2592 uint32_t my_qpn :24;
2593
2594 uint32_t immed_rss_val_key;
2595
2596 uint32_t grh :1;
2597 uint32_t ml_path :7;
2598 uint32_t srq_rqpn :24;
2599
2600 uint32_t sl :4;
2601 uint32_t vid :12;
2602 uint32_t slid :16; /* SMAC 47:32 or SLID */
2603
2604 uint32_t ipoib_status; /* SMAC 31:0 or enet/ipoib/EoIB status */
2605
2606 uint32_t byte_cnt;
2607
2608 uint32_t wqe_cntr :16;
2609 uint32_t checksum :16;
2610
2611 uint32_t :8;
2612 uint32_t :16;
2613 uint32_t owner :1;
2614 uint32_t send_or_recv :1;
2615 uint32_t inline_scatter :1;
2616 uint32_t opcode :5;
2617 };
2618 #define HERMON_COMPLETION_RECV 0x0
2619 #define HERMON_COMPLETION_SEND 0x1
2620
2621 #define HERMON_CQE_DEFAULT_VERSION 0x0
2622
2623 /*
2624 * The following macros are used for extracting (and in some cases filling in)
2625 * information from CQEs
2626 */
2627 #define HERMON_CQE_QPNUM_MASK 0x00FFFFFF
2628 #define HERMON_CQE_QPNUM_SHIFT 0
2629
2630
2631 #define HERMON_CQE_DQPN_MASK 0x00FFFFFF
2632 #define HERMON_CQE_DQPN_SHIFT 0
2633
2634
2635 #define HERMON_CQE_SL_SHIFT 4
2636 #define HERMON_CQE_GRH_MASK 0x80
2637 #define HERMON_CQE_PATHBITS_MASK 0x7F
2638 #define HERMON_CQE_SLID_15_8 0xe
2639 #define HERMON_CQE_SLID_7_0 0xf
2640 #define HERMON_CQE_OPCODE_MASK 0x1F
2641 #define HERMON_CQE_SENDRECV_MASK 0x40
2642 #define HERMON_CQE_SENDRECV_SHIFT 6
2643 #define HERMON_CQE_OWNER_MASK 0x80
2644 #define HERMON_CQE_OWNER_SHIFT 7
2645 #define HERMON_CQE_WQECNTR_15_8 0x18
2646 #define HERMON_CQE_WQECNTR_7_0 0x19
2647 /* Byte offsets for IPoIB Checksum Offload fields */
2648 #define HERMON_CQE_CKSUM_15_8 0x1a
2649 #define HERMON_CQE_CKSUM_7_0 0x1b
2650 #define HERMON_CQE_IPOK 0x10 /* byte 0x10 in cqe */
2651 #define HERMON_CQE_IPOK_BIT 0x10 /* bitmask for OK bit */
2652
2653 #define HERMON_CQE_IS_IPOK(cq, cqe) \
2654 (((uint8_t *)(cqe))[HERMON_CQE_IPOK] & HERMON_CQE_IPOK_BIT)
2655
2656 #define HERMON_CQE_CKSUM(cq, cqe) \
2657 ((((uint8_t *)(cqe))[HERMON_CQE_CKSUM_15_8] << 8) | \
2658 (((uint8_t *)(cqe))[HERMON_CQE_CKSUM_7_0]))
2659
2660 #define HERMON_CQE_IPOIB_STATUS(cq, cqe) \
2661 htonl((((uint32_t *)(cqe)))[4])
2662
2663 #define HERMON_CQE_QPNUM_GET(cq, cqe) \
2664 ((htonl((((uint32_t *)(cqe)))[0]) & HERMON_CQE_QPNUM_MASK) >> \
2665 HERMON_CQE_QPNUM_SHIFT)
2666
2667 #define HERMON_CQE_IMM_ETH_PKEY_CRED_GET(cq, cqe) \
2668 htonl(((uint32_t *)(cqe))[1])
2669
2670 #define HERMON_CQE_DQPN_GET(cq, cqe) \
2671 ((htonl(((uint32_t *)(cqe))[2]) & HERMON_CQE_DQPN_MASK) >> \
2672 HERMON_CQE_DQPN_SHIFT)
2673
2674 #define HERMON_CQE_GRH_GET(cq, cqe) \
2675 (((uint8_t *)(cqe))[8] & HERMON_CQE_GRH_MASK)
2676
2677 #define HERMON_CQE_PATHBITS_GET(cq, cqe) \
2678 (((uint8_t *)(cqe))[8] & HERMON_CQE_PATHBITS_MASK)
2679
2680 #define HERMON_CQE_DLID_GET(cq, cqe) \
2681 ((((uint8_t *)(cqe))[HERMON_CQE_SLID_15_8] << 8) | \
2682 (((uint8_t *)(cqe))[HERMON_CQE_SLID_7_0]))
2683
2684 #define HERMON_CQE_SL_GET(cq, cqe) \
2685 ((((uint8_t *)(cqe))[12]) >> HERMON_CQE_SL_SHIFT)
2686
2687 #define HERMON_CQE_BYTECNT_GET(cq, cqe) \
2688 htonl(((uint32_t *)(cqe))[5])
2689
2690 #define HERMON_CQE_WQECNTR_GET(cq, cqe) \
2691 ((((uint8_t *)(cqe))[HERMON_CQE_WQECNTR_15_8] << 8) | \
2692 (((uint8_t *)(cqe))[HERMON_CQE_WQECNTR_7_0]))
2693
2694 #define HERMON_CQE_ERROR_SYNDROME_GET(cq, cqe) \
2695 (((uint8_t *)(cqe))[27])
2696
2697 #define HERMON_CQE_ERROR_VENDOR_SYNDROME_GET(cq, cqe) \
2698 (((uint8_t *)(cqe))[26])
2699
2700 #define HERMON_CQE_OPCODE_GET(cq, cqe) \
2701 ((((uint8_t *)(cqe))[31]) & HERMON_CQE_OPCODE_MASK)
2702
2703 #define HERMON_CQE_SENDRECV_GET(cq, cqe) \
2704 (((((uint8_t *)(cqe))[31]) & HERMON_CQE_SENDRECV_MASK) >> \
2705 HERMON_CQE_SENDRECV_SHIFT)
2706
2707 #define HERMON_CQE_FEXCH_SEQ_CNT(cq, cqe) \
2708 HERMON_CQE_CKSUM(cq, cqe)
2709
2710 #define HERMON_CQE_FEXCH_TX_BYTES(cq, cqe) \
2711 htonl(((uint32_t *)(cqe))[3])
2712
2713 #define HERMON_CQE_FEXCH_RX_BYTES(cq, cqe) \
2714 htonl(((uint32_t *)(cqe))[4])
2715
2716 #define HERMON_CQE_FEXCH_SEQ_ID(cq, cqe) \
2717 (((uint8_t *)(cqe))[8])
2718
2719 #define HERMON_CQE_FEXCH_DETAIL(cq, cqe) \
2720 htonl(((uint32_t *)(cqe))[0])
2721
2722 #define HERMON_CQE_FEXCH_DIFE(cq, cqe) \
2723 ((((uint8_t *)(cqe))[0]) & 0x80)
2724
2725 /* See Comment above for EQE - ownership of CQE is handled the same */
2726
2727 #define HERMON_CQE_OWNER_IS_SW(cq, cqe, considx, shift, mask) \
2728 (((((uint8_t *)(cqe))[31] & HERMON_CQE_OWNER_MASK) >> \
2729 HERMON_CQE_OWNER_SHIFT) == \
2730 (((considx) & (mask)) >> (shift)))
2731
2732 /*
2733 * Hermon Shared Receive Queue (SRQ) Context Entry Format
2734 */
2735
2736 #ifdef _LITTLE_ENDIAN
2737 struct hermon_hw_srqc_s {
2738 uint32_t xrc_domain :16;
2739 uint32_t :8;
2740 uint32_t log_rq_stride :3;
2741 uint32_t :5;
2742
2743 uint32_t srqn :24;
2744 uint32_t log_srq_size :4;
2745 uint32_t state :4;
2746
2747 uint32_t :32;
2748
2749 uint32_t cqn_xrc :24;
2750 uint32_t :2;
2751 uint32_t page_offs :6;
2752
2753 uint32_t :3;
2754 uint32_t mtt_base_addrl :29;
2755
2756 uint32_t mtt_base_addrh :8;
2757 uint32_t :16;
2758 uint32_t log2_pgsz :6;
2759 uint32_t :2;
2760
2761 uint32_t wqe_cnt :16;
2762 uint32_t lwm :16;
2763
2764 uint32_t pd :24;
2765 uint32_t :8;
2766
2767 uint32_t :32;
2768
2769 uint32_t srq_wqe_cntr :16;
2770 uint32_t :16;
2771
2772 uint32_t :2;
2773 uint32_t dbr_addrl :30;
2774
2775 uint32_t dbr_addrh;
2776
2777 uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */
2778
2779 };
2780 #else /* BIG ENDIAN */
2781 struct hermon_hw_srqc_s {
2782 uint32_t state :4;
2783 uint32_t log_srq_size :4;
2784 uint32_t srqn :24;
2785
2786 uint32_t :5;
2787 uint32_t log_rq_stride :3;
2788 uint32_t :8;
2789 uint32_t xrc_domain :16;
2790
2791 uint32_t page_offs :6;
2792 uint32_t :2;
2793 uint32_t cqn_xrc :24;
2794
2795 uint32_t :32;
2796
2797 uint32_t :2;
2798 uint32_t log2_pgsz :6;
2799 uint32_t :16;
2800 uint32_t mtt_base_addrh :8;
2801
2802 uint32_t mtt_base_addrl :29;
2803 uint32_t :3;
2804
2805 uint32_t :8;
2806 uint32_t pd :24;
2807
2808 uint32_t lwm :16;
2809 uint32_t wqe_cnt :16;
2810
2811 uint32_t :16;
2812 uint32_t srq_wqe_cntr :16;
2813
2814 uint32_t :32;
2815
2816 uint32_t dbr_addrh;
2817
2818 uint32_t dbr_addrl :30;
2819 uint32_t :2;
2820
2821 uint32_t rsrc0[80]; /* to match DEV_CAP size of 0x80 */
2822 };
2823 #endif
2824
2825 /*
2826 * Hermon MOD_STAT_CFG input mailbox structure
2827 */
2828
2829
2830 #ifdef _LITTLE_ENDIAN
2831 struct hermon_hw_mod_stat_cfg_s {
2832 uint32_t :16;
2833 uint32_t qdr_rx_op :4;
2834 uint32_t :3;
2835 uint32_t qdr_rx_opt_m :1;
2836 uint32_t qdr_tx_op :4;
2837 uint32_t :3;
2838 uint32_t qdr_tx_opt_m :1;
2839
2840 uint32_t log_pg_sz :8;
2841 uint32_t log_pg_sz_m :1;
2842 uint32_t :5;
2843 uint32_t dife :1;
2844 uint32_t dife_m :1;
2845 uint32_t rx_options :4;
2846 uint32_t :3;
2847 uint32_t rx_options_m :1;
2848 uint32_t tx_options :4;
2849 uint32_t :3;
2850 uint32_t tx_options_m :1;
2851
2852 uint32_t lid :16;
2853 uint32_t lid_m :1;
2854 uint32_t :3;
2855 uint32_t port_en :1;
2856 uint32_t port_en_m :1;
2857 uint32_t :10;
2858
2859 uint32_t :32;
2860
2861 uint32_t guid_hi;
2862
2863 uint32_t :31;
2864 uint32_t guid_hi_m :1;
2865
2866 uint32_t guid_lo;
2867
2868 uint32_t :31;
2869 uint32_t guid_lo_m :1;
2870
2871 uint32_t rsvd[4];
2872
2873 uint32_t inbuf_ind_en :3;
2874 uint32_t :1;
2875 uint32_t sd_main :4;
2876 uint32_t :4;
2877 uint32_t sd_equal :4;
2878 uint32_t :4;
2879 uint32_t sd_mux_main :2;
2880 uint32_t :2;
2881 uint32_t mux_eq :2;
2882 uint32_t :2;
2883 uint32_t sigdet_th :3;
2884 uint32_t :1;
2885
2886 uint32_t ob_preemp_pre :5;
2887 uint32_t :3;
2888 uint32_t op_preemp_post :5;
2889 uint32_t :3;
2890 uint32_t ob_preemp_main :5;
2891 uint32_t :3;
2892 uint32_t ob_preemp :5;
2893 uint32_t :2;
2894 uint32_t serdes_m :1;
2895
2896 uint32_t reserved[22];
2897
2898 uint32_t mac_lo :32;
2899
2900 uint32_t mac_hi :16;
2901 uint32_t :15;
2902 uint32_t mac_m :1;
2903 };
2904 #else /* BIG ENDIAN */
2905 struct hermon_hw_mod_stat_cfg_s {
2906 uint32_t tx_options_m :1;
2907 uint32_t :3;
2908 uint32_t tx_options :4;
2909 uint32_t rx_options_m :1;
2910 uint32_t :3;
2911 uint32_t rx_options :4;
2912 uint32_t dife_m :1;
2913 uint32_t dife :1;
2914 uint32_t :5;
2915 uint32_t log_pg_sz_m :1;
2916 uint32_t log_pg_sz :8;
2917
2918 uint32_t qdr_tx_opt_m :1;
2919 uint32_t :3;
2920 uint32_t qdr_tx_op :4;
2921 uint32_t qdr_rx_opt_m :1;
2922 uint32_t :3;
2923 uint32_t qdr_rx_op :4;
2924 uint32_t :16;
2925
2926 uint32_t :32;
2927
2928 uint32_t :10;
2929 uint32_t port_en_m :1;
2930 uint32_t port_en :1;
2931 uint32_t :3;
2932 uint32_t lid_m :1;
2933 uint32_t lid :16;
2934
2935 uint32_t guid_hi_m :1;
2936 uint32_t :31;
2937
2938 uint32_t guid_hi;
2939
2940 uint32_t guid_lo_m :1;
2941 uint32_t :31;
2942
2943 uint32_t guid_lo;
2944
2945 uint32_t rsvd[4];
2946
2947 uint32_t serdes_m :1;
2948 uint32_t :2;
2949 uint32_t ob_preemp :5;
2950 uint32_t :3;
2951 uint32_t ob_preemp_main :5;
2952 uint32_t :3;
2953 uint32_t op_preemp_post :5;
2954 uint32_t :3;
2955 uint32_t ob_preemp_pre :5;
2956
2957 uint32_t :1;
2958 uint32_t sigdet_th :3;
2959 uint32_t :2;
2960 uint32_t mux_eq :2;
2961 uint32_t :2;
2962 uint32_t sd_mux_main :2;
2963 uint32_t :4;
2964 uint32_t sd_equal :4;
2965 uint32_t :4;
2966 uint32_t sd_main :4;
2967 uint32_t :1;
2968 uint32_t inbuf_ind_en :3;
2969
2970 uint32_t reserved[22]; /* get to new enet stuff */
2971
2972 uint32_t mac_m :1;
2973 uint32_t :15;
2974 uint32_t mac_hi :16;
2975
2976 uint32_t mac_lo :32;
2977 };
2978 #endif
2979
2980 /*
2981 * Hermon MOD_STAT_CFG input modifier structure
2982 * NOTE: this might end up defined ONLY one way,
2983 * if usage is access via macros
2984 */
2985 struct hermon_hw_msg_in_mod_s {
2986 #ifdef _LITTLE_ENDIAN
2987 uint32_t offset :8;
2988 uint32_t port_num :8;
2989 uint32_t lane_num :4;
2990 uint32_t link_speed :3;
2991 uint32_t auto_neg :1;
2992 uint32_t :8;
2993 #else
2994 uint32_t :8;
2995 uint32_t auto_neg :1;
2996 uint32_t link_speed :3;
2997 uint32_t lane_num :4;
2998 uint32_t port_num :8;
2999 uint32_t offset :8;
3000 #endif
3001 };
3002
3003
3004 /*
3005 * Hermon UD Address Vector (UDAV)
3006 * Hermon UDAV are used in conjunction with Unreliable Datagram (UD) send
3007 * WQEs. Each UD send message contains an address vector in in the datagram
3008 * segment. The verbs consumer must use special verbs to create and modify
3009 * address handles, each of which contains a UDAV structure. When posting
3010 * send WQEs to UD QP, the verbs consumer must supply a valid address
3011 * handle/UDAV.
3012 */
3013
3014
3015 #ifdef _LITTLE_ENDIAN
3016 struct hermon_hw_udav_s {
3017 uint32_t rlid :16;
3018 uint32_t ml_path :7; /* mlid or SMAC idx */
3019 uint32_t grh :1;
3020 uint32_t :8;
3021
3022 uint32_t pd :24;
3023 uint32_t portnum :2;
3024 uint32_t :5;
3025 uint32_t force_lb :1;
3026
3027 uint32_t flow_label :20;
3028 uint32_t tclass :8;
3029 uint32_t sl :4;
3030
3031 uint32_t hop_limit :8;
3032 uint32_t max_stat_rate :4;
3033 uint32_t :4;
3034 uint32_t mgid_index :7;
3035 uint32_t :9;
3036
3037 uint64_t rgid_h;
3038 uint64_t rgid_l;
3039 };
3040 #else
3041 struct hermon_hw_udav_s {
3042 uint32_t force_lb :1;
3043 uint32_t :5;
3044 uint32_t portnum :2;
3045 uint32_t pd :24;
3046
3047 uint32_t :8;
3048 uint32_t grh :1;
3049 uint32_t ml_path :7; /* mlid or SMAC idx */
3050 uint32_t rlid :16;
3051
3052 uint32_t :9;
3053 uint32_t mgid_index :7;
3054 uint32_t :4;
3055 uint32_t max_stat_rate :4;
3056 uint32_t hop_limit :8;
3057
3058 uint32_t sl :4;
3059 uint32_t tclass :8;
3060 uint32_t flow_label :20;
3061
3062 uint64_t rgid_h;
3063 uint64_t rgid_l;
3064 };
3065 #endif
3066 #define HERMON_UDAV_MODIFY_MASK0 0xFCFFFFFFFF000000ULL
3067 #define HERMON_UDAV_MODIFY_MASK1 0xFF80F00000000000ULL
3068
3069 /* UDAV for enthernet */
3070
3071 #ifdef _LITTLE_ENDIAN
3072 struct hermon_hw_udav_enet_s {
3073 uint32_t :16;
3074 uint32_t smac_idx :7;
3075 uint32_t :9;
3076
3077 uint32_t pd :24;
3078 uint32_t portnum :2;
3079 uint32_t :3;
3080 uint32_t cv :1;
3081 uint32_t :1;
3082 uint32_t force_lb :1;
3083
3084 uint32_t flow_label :20;
3085 uint32_t tclass :8;
3086 uint32_t sl :4;
3087
3088 uint32_t hop_limit :8;
3089 uint32_t max_stat_rate :4;
3090 uint32_t :4;
3091 uint32_t mgid_index :7;
3092 uint32_t :9;
3093
3094 uint64_t rgid_h;
3095 uint64_t rgid_l;
3096
3097 uint32_t rsrv[2];
3098
3099 uint32_t dmac_lo;
3100
3101 uint32_t dmac_hi :16;
3102 uint32_t vlan :16;
3103 };
3104 #else
3105 struct hermon_hw_udav_enet_s {
3106 uint32_t force_lb :1;
3107 uint32_t :1;
3108 uint32_t cv :1;
3109 uint32_t :3;
3110 uint32_t portnum :2;
3111 uint32_t pd :24;
3112
3113 uint32_t :9;
3114 uint32_t smac_idx :7;
3115 uint32_t :16;
3116
3117 uint32_t :9;
3118 uint32_t mgid_index :7;
3119 uint32_t :4;
3120 uint32_t max_stat_rate :4;
3121 uint32_t hop_limit :8;
3122
3123 uint32_t sl :4;
3124 uint32_t tclass :8;
3125 uint32_t flow_label :20;
3126
3127 uint64_t rgid_h;
3128 uint64_t rgid_l;
3129
3130 uint32_t rsrv[2];
3131
3132 uint32_t vlan :16;
3133 uint32_t dmac_hi :16;
3134
3135 uint32_t dmac_low;
3136 };
3137 #endif
3138
3139 /*
3140 * Hermon Queue Pair Context Table (QPC) entries
3141 * The QPC table is a virtually-contiguous memory area residing in HCA
3142 * ICM. Each QPC entry is accessed for reads and writes
3143 * by the HCA while executing work requests on the associated QP.
3144 *
3145 * The following structure is used in the RST2INIT_QP, INIT2INIT_QP,
3146 * INIT2RTR_QP, RTR2RTS_QP, RTS2RTS_QP, SQERR2RTS_QP, TOERR_QP, RTS2SQD_QP,
3147 * SQD2RTS_QP, TORST_QP, and QUERY_QP commands.
3148 * With the exception of the QUERY_QP command, each of these commands reads
3149 * from some portion of the QPC in the input mailbox and modified the QPC
3150 * stored in the hardware. The QUERY_QP command retrieves a snapshot of a
3151 * QPC entry. The command stores the snapshot in the output mailbox. The
3152 * QPC state and its values are not affected by the QUERY_QP command.
3153 *
3154 * Below we first define the hermon_hw_addr_path_t or "Hermon Address Path"
3155 * structure. This structure is used to provide address path information
3156 * (both primary and secondary) for each QP context. Note: Since this
3157 * structure is _very_ similar to the hermon_hw_udav_t structure above,
3158 * we are able to leverage the similarity with filling in and reading from
3159 * the two types of structures. See hermon_get_addr_path() and
3160 * hermon_set_addr_path() in hermon_misc.c for more details.
3161 */
3162 #if (DATAMODEL_NATIVE == DATAMODEL_LP64)
3163 #pragma pack(4)
3164 #endif
3165
3166 #ifdef _LITTLE_ENDIAN
3167 struct hermon_hw_addr_path_s {
3168 uint32_t rlid :16;
3169 uint32_t mlid :7; /* mlid or SMAC idx */
3170 uint32_t grh :1;
3171 uint32_t cntr_idx :8;
3172
3173 uint32_t pkey_indx :7;
3174 uint32_t :22;
3175 uint32_t :1; /* but may be used for enet */
3176 uint32_t cv :1;
3177 uint32_t force_lb :1;
3178
3179 uint32_t flow_label :20;
3180 uint32_t tclass :8;
3181 uint32_t sniff_s_in :1;
3182 uint32_t sniff_s_out :1;
3183 uint32_t sniff_r_in :1;
3184 uint32_t sniff_r_out :1; /* sniff-rcv-egress */
3185
3186 uint32_t hop_limit :8;
3187 uint32_t max_stat_rate :4;
3188 uint32_t :4;
3189 uint32_t mgid_index :7;
3190 uint32_t :1;
3191 uint32_t link_type :3;
3192 uint32_t ack_timeout :5;
3193
3194 uint64_t rgid_h;
3195 uint64_t rgid_l;
3196
3197 uint32_t dmac_hi :16;
3198 uint32_t :16;
3199
3200 uint32_t :8; /* but may be used for enet */
3201 uint32_t sp :1;
3202 uint32_t :2;
3203 uint32_t fvl :1;
3204 uint32_t fsip :1;
3205 uint32_t fsm :1;
3206 uint32_t :2;
3207 uint32_t vlan_idx :7;
3208 uint32_t :1;
3209 uint32_t sched_q :8;
3210
3211 uint32_t dmac_lo :32;
3212 };
3213 #else
3214 struct hermon_hw_addr_path_s {
3215 uint32_t force_lb :1;
3216 uint32_t cv :1;
3217 uint32_t :1; /* but may be used for enet */
3218 uint32_t :22;
3219 uint32_t pkey_indx :7;
3220
3221 uint32_t cntr_idx :8;
3222 uint32_t grh :1;
3223 uint32_t mlid :7; /* mlid or SMAC idx */
3224 uint32_t rlid :16;
3225
3226 uint32_t ack_timeout :5;
3227 uint32_t link_type :3;
3228 uint32_t :1;
3229 uint32_t mgid_index :7;
3230 uint32_t :4;
3231 uint32_t max_stat_rate :4;
3232 uint32_t hop_limit :8;
3233
3234 uint32_t sniff_r_out :1; /* sniff-rcv-egress */
3235 uint32_t sniff_r_in :1;
3236 uint32_t sniff_s_out :1;
3237 uint32_t sniff_s_in :1;
3238 uint32_t tclass :8;
3239 uint32_t flow_label :20;
3240
3241 uint64_t rgid_h;
3242 uint64_t rgid_l;
3243
3244 uint32_t sched_q :8;
3245 uint32_t :1;
3246 uint32_t vlan_idx :7;
3247 uint32_t :2;
3248 uint32_t fsm :1;
3249 uint32_t fsip :1;
3250 uint32_t fvl :1;
3251 uint32_t :2;
3252 uint32_t sp :1;
3253 uint32_t :8; /* but may be used for enet */
3254
3255 uint32_t :16;
3256 uint32_t dmac_hi :16;
3257
3258 uint32_t dmac_lo :32;
3259 };
3260 #endif /* LITTLE ENDIAN */
3261
3262 /* The addr path includes RSS fields for RSS QPs */
3263 #ifdef _LITTLE_ENDIAN
3264 struct hermon_hw_rss_s {
3265 uint32_t rlid :16;
3266 uint32_t mlid :7;
3267 uint32_t grh :1;
3268 uint32_t cntr_idx :8;
3269
3270 uint32_t pkey_indx :7;
3271 uint32_t :22;
3272 uint32_t :1; /* but may be used for enet */
3273 uint32_t cv :1;
3274 uint32_t force_lb :1;
3275
3276 uint32_t flow_label :20;
3277 uint32_t tclass :8;
3278 uint32_t sniff_s_in :1;
3279 uint32_t sniff_s_out :1;
3280 uint32_t sniff_r_in :1;
3281 uint32_t sniff_r_out :1; /* sniff-rcv-egress */
3282
3283 uint32_t hop_limit :8;
3284 uint32_t max_stat_rate :4;
3285 uint32_t :4;
3286 uint32_t mgid_index :7;
3287 uint32_t :1;
3288 uint32_t link_type :3;
3289 uint32_t ack_timeout :5;
3290
3291 uint64_t rgid_h;
3292 uint64_t rgid_l;
3293
3294 uint32_t base_qpn :24;
3295 uint32_t log2_tbl_sz :4;
3296 uint32_t :4;
3297
3298 uint32_t :8; /* but may be used for enet */
3299 uint32_t sp :1;
3300 uint32_t :2;
3301 uint32_t fvl :1;
3302 uint32_t fsip :1;
3303 uint32_t fsm :1;
3304 uint32_t :2;
3305 uint32_t vlan_idx :7;
3306 uint32_t :1;
3307 uint32_t sched_q :8;
3308
3309 uint32_t :2;
3310 uint32_t tcp_ipv6 :1;
3311 uint32_t ipv6 :1;
3312 uint32_t tcp_ipv4 :1;
3313 uint32_t ipv4 :1;
3314 uint32_t :2;
3315 uint32_t hash_fn :2;
3316 uint32_t :22;
3317
3318 uint32_t default_qpn :24;
3319 uint32_t :8;
3320
3321 uint8_t rss_key[40];
3322 };
3323 #else /* BIG ENDIAN */
3324 struct hermon_hw_rss_s {
3325 uint32_t force_lb :1;
3326 uint32_t cv :1;
3327 uint32_t :1; /* but may be used for enet */
3328 uint32_t :22;
3329 uint32_t pkey_indx :7;
3330
3331 uint32_t cntr_idx :8;
3332 uint32_t grh :1;
3333 uint32_t mlid :7;
3334 uint32_t rlid :16;
3335
3336 uint32_t ack_timeout :5;
3337 uint32_t link_type :3;
3338 uint32_t :1;
3339 uint32_t mgid_index :7;
3340 uint32_t :4;
3341 uint32_t max_stat_rate :4;
3342 uint32_t hop_limit :8;
3343
3344 uint32_t sniff_r_out :1; /* sniff-rcv-egress */
3345 uint32_t sniff_r_in :1;
3346 uint32_t sniff_s_out :1;
3347 uint32_t sniff_s_in :1;
3348 uint32_t tclass :8;
3349 uint32_t flow_label :20;
3350
3351 uint64_t rgid_h;
3352 uint64_t rgid_l;
3353
3354 uint32_t sched_q :8;
3355 uint32_t :1;
3356 uint32_t vlan_idx :7;
3357 uint32_t :2;
3358 uint32_t fsm :1;
3359 uint32_t fsip :1;
3360 uint32_t fvl :1;
3361 uint32_t :2;
3362 uint32_t sp :1;
3363 uint32_t :8; /* but may be used for enet */
3364
3365 uint32_t :4;
3366 uint32_t log2_tbl_sz :4;
3367 uint32_t base_qpn :24;
3368
3369 uint32_t :8;
3370 uint32_t default_qpn :24;
3371
3372 uint32_t :22;
3373 uint32_t hash_fn :2;
3374 uint32_t :2;
3375 uint32_t ipv4 :1;
3376 uint32_t tcp_ipv4 :1;
3377 uint32_t ipv6 :1;
3378 uint32_t tcp_ipv6 :1;
3379 uint32_t :2;
3380
3381 uint8_t rss_key[40];
3382 };
3383 #endif /* LITTLE ENDIAN */
3384
3385 #if (DATAMODEL_NATIVE == DATAMODEL_LP64)
3386 #pragma pack()
3387 #endif
3388
3389 #if (DATAMODEL_NATIVE == DATAMODEL_LP64)
3390 #pragma pack(4)
3391 #endif
3392 #ifdef _LITTLE_ENDIAN
3393 struct hermon_hw_qpc_s {
3394 uint32_t pd :24;
3395 uint32_t :8;
3396
3397 uint32_t :11;
3398 uint32_t pm_state :2;
3399 uint32_t rss :1;
3400 uint32_t :2;
3401 uint32_t serv_type :8;
3402 uint32_t :4;
3403 uint32_t state :4;
3404
3405 uint32_t usr_page :24;
3406 uint32_t :8;
3407
3408 uint32_t :4;
3409 uint32_t rlky :1;
3410 uint32_t :3;
3411 uint32_t log_sq_stride :3;
3412 uint32_t log_sq_size :4;
3413 uint32_t sq_no_prefetch :1;
3414 uint32_t log_rq_stride :3;
3415 uint32_t log_rq_size :4;
3416 uint32_t :1;
3417 uint32_t msg_max :5;
3418 uint32_t mtu :3;
3419
3420 uint32_t rem_qpn :24;
3421 uint32_t :8;
3422
3423 uint32_t loc_qpn :24;
3424 uint32_t :8;
3425
3426 hermon_hw_addr_path_t pri_addr_path;
3427
3428 hermon_hw_addr_path_t alt_addr_path;
3429
3430 uint32_t :32;
3431
3432 uint32_t :5;
3433 uint32_t cur_retry_cnt :3;
3434 uint32_t cur_rnr_retry :3;
3435 uint32_t fre :1;
3436 uint32_t :1;
3437 uint32_t rnr_retry :3;
3438 uint32_t retry_cnt :3;
3439 uint32_t :2;
3440 uint32_t sra_max :3;
3441 uint32_t :4;
3442 uint32_t ack_req_freq :4;
3443
3444 uint32_t cqn_snd :24;
3445 uint32_t :8;
3446
3447 uint32_t next_snd_psn :24;
3448 uint32_t :8;
3449
3450 uint32_t :32;
3451
3452 uint32_t :32;
3453
3454 uint32_t ssn :24;
3455 uint32_t :8;
3456
3457 uint32_t last_acked_psn :24;
3458 uint32_t :8;
3459
3460 uint32_t next_rcv_psn :24;
3461 uint32_t min_rnr_nak :5;
3462 uint32_t :3;
3463
3464 uint32_t :4;
3465 uint32_t ric :1;
3466 uint32_t :1;
3467 uint32_t page_offs :6;
3468 uint32_t :1;
3469 uint32_t rae :1;
3470 uint32_t rwe :1;
3471 uint32_t rre :1;
3472 uint32_t :5;
3473 uint32_t rra_max :3;
3474 uint32_t :8;
3475
3476 uint32_t cqn_rcv :24;
3477 uint32_t :8;
3478
3479 uint32_t xrcd :16;
3480 uint32_t :16;
3481
3482 uint32_t :2;
3483 uint32_t dbr_addrl :30;
3484
3485 uint32_t dbr_addrh :32;
3486
3487 uint32_t srq_number :24;
3488 uint32_t srq_en :1;
3489 uint32_t :7;
3490
3491 uint32_t qkey;
3492
3493 uint32_t sq_wqe_counter :16;
3494 uint32_t rq_wqe_counter :16;
3495
3496 uint32_t rmsn :24;
3497 uint32_t :8;
3498
3499 uint32_t rsrv0[2];
3500
3501 /* new w/ hermon */
3502
3503 uint32_t base_mkey :24; /* bits 32-8, low 7 m/b 0 */
3504 uint32_t num_rmc_peers :8;
3505
3506 uint32_t rmc_parent_qpn :24;
3507 uint32_t header_sep :1;
3508 uint32_t inline_scatter :1; /* m/b 0 for srq */
3509 uint32_t :1;
3510 uint32_t rmc_enable :2;
3511 uint32_t :2; /* may use one bit for enet */
3512 uint32_t mkey_remap :1;
3513
3514 uint32_t :3;
3515 uint32_t mtt_base_addrl :29;
3516
3517 uint32_t mtt_base_addrh :8;
3518 uint32_t :16;
3519 uint32_t log2_pgsz :6;
3520 uint32_t :2;
3521
3522 uint32_t exch_base :16;
3523 uint32_t exch_size :4;
3524 uint32_t :12;
3525
3526 uint32_t vft_vf_id :12;
3527 uint32_t vft_prior :3;
3528 uint32_t :16;
3529 uint32_t ve :1;
3530
3531 uint32_t :32;
3532
3533 uint32_t :16;
3534 uint32_t my_fc_id_idx :8;
3535 uint32_t vft_hop_cnt :8;
3536
3537 uint32_t rsvd[8];
3538 };
3539 #else /* BIG ENDIAN */
3540 struct hermon_hw_qpc_s {
3541 uint32_t state :4;
3542 uint32_t :4;
3543 uint32_t serv_type :8;
3544 uint32_t :2;
3545 uint32_t rss :1;
3546 uint32_t pm_state :2;
3547 uint32_t :11;
3548
3549 uint32_t :8;
3550 uint32_t pd :24;
3551
3552 uint32_t mtu :3;
3553 uint32_t msg_max :5;
3554 uint32_t :1;
3555 uint32_t log_rq_size :4;
3556 uint32_t log_rq_stride :3;
3557 uint32_t sq_no_prefetch :1;
3558 uint32_t log_sq_size :4;
3559 uint32_t log_sq_stride :3;
3560 uint32_t :3;
3561 uint32_t rlky :1;
3562 uint32_t :4;
3563
3564 uint32_t :8;
3565 uint32_t usr_page :24;
3566
3567 uint32_t :8;
3568 uint32_t loc_qpn :24;
3569
3570 uint32_t :8;
3571 uint32_t rem_qpn :24;
3572
3573 hermon_hw_addr_path_t pri_addr_path;
3574
3575 hermon_hw_addr_path_t alt_addr_path;
3576
3577 uint32_t ack_req_freq :4;
3578 uint32_t :4;
3579 uint32_t sra_max :3;
3580 uint32_t :2;
3581 uint32_t retry_cnt :3;
3582 uint32_t rnr_retry :3;
3583 uint32_t :1;
3584 uint32_t fre :1;
3585 uint32_t cur_rnr_retry :3;
3586 uint32_t cur_retry_cnt :3;
3587 uint32_t :5;
3588
3589 uint32_t :32;
3590
3591 uint32_t :8;
3592 uint32_t next_snd_psn :24;
3593
3594 uint32_t :8;
3595 uint32_t cqn_snd :24;
3596
3597 uint32_t :32;
3598
3599 uint32_t :32;
3600
3601 uint32_t :8;
3602 uint32_t last_acked_psn :24;
3603
3604 uint32_t :8;
3605 uint32_t ssn :24;
3606
3607 uint32_t :8;
3608 uint32_t rra_max :3;
3609 uint32_t :5;
3610 uint32_t rre :1;
3611 uint32_t rwe :1;
3612 uint32_t rae :1;
3613 uint32_t :1;
3614 uint32_t page_offs :6;
3615 uint32_t :1;
3616 uint32_t ric :1;
3617 uint32_t :4;
3618
3619 uint32_t :3;
3620 uint32_t min_rnr_nak :5;
3621 uint32_t next_rcv_psn :24;
3622
3623 uint32_t :16;
3624 uint32_t xrcd :16;
3625
3626 uint32_t :8;
3627 uint32_t cqn_rcv :24;
3628
3629 uint32_t dbr_addrh :32;
3630
3631 uint32_t dbr_addrl :30;
3632 uint32_t :2;
3633
3634 uint32_t qkey;
3635
3636 uint32_t :7;
3637 uint32_t srq_en :1;
3638 uint32_t srq_number :24;
3639
3640 uint32_t :8;
3641 uint32_t rmsn :24;
3642
3643 uint32_t rq_wqe_counter :16;
3644 uint32_t sq_wqe_counter :16;
3645
3646 uint32_t rsrv0[2];
3647
3648 /* new w/ hermon */
3649
3650 uint32_t mkey_remap :1;
3651 uint32_t :2; /* may use one bit for enet */
3652 uint32_t rmc_enable :2;
3653 uint32_t :1;
3654 uint32_t inline_scatter :1; /* m/b 0 for srq */
3655 uint32_t header_sep :1;
3656 uint32_t rmc_parent_qpn :24;
3657
3658 uint32_t num_rmc_peers :8;
3659 uint32_t base_mkey :24; /* bits 32-8, low 7 m/b 0 */
3660
3661 uint32_t :2;
3662 uint32_t log2_pgsz :6;
3663 uint32_t :16;
3664 uint32_t mtt_base_addrh :8;
3665
3666 uint32_t mtt_base_addrl :29;
3667 uint32_t :3;
3668
3669 uint32_t ve :1;
3670 uint32_t :16;
3671 uint32_t vft_prior :3;
3672 uint32_t vft_vf_id :12;
3673
3674 uint32_t :12;
3675 uint32_t exch_size :4;
3676 uint32_t exch_base :16;
3677
3678 uint32_t vft_hop_cnt :8;
3679 uint32_t my_fc_id_idx :8;
3680 uint32_t :16;
3681
3682 uint32_t :32;
3683
3684 uint32_t rsvd[8];
3685 };
3686 #endif /* LITTLE ENDIAN */
3687
3688 #if (DATAMODEL_NATIVE == DATAMODEL_LP64)
3689 #pragma pack()
3690 #endif
3691
3692 #define HERMON_QP_RESET 0x0
3693 #define HERMON_QP_INIT 0x1
3694 #define HERMON_QP_RTR 0x2
3695 #define HERMON_QP_RTS 0x3
3696 #define HERMON_QP_SQERR 0x4
3697 #define HERMON_QP_SQD 0x5
3698 #define HERMON_QP_ERR 0x6
3699 #define HERMON_QP_SQDRAINING 0x7
3700
3701 #define HERMON_QP_RC 0x0
3702 #define HERMON_QP_UC 0x1
3703 #define HERMON_QP_UD 0x3
3704 #define HERMON_QP_FCMND 0x4
3705 #define HERMON_QP_FEXCH 0x5
3706 #define HERMON_QP_XRC 0x6
3707 #define HERMON_QP_MLX 0x7
3708 #define HERMON_QP_RFCI 0x9
3709
3710 #define HERMON_QP_PMSTATE_MIGRATED 0x3
3711 #define HERMON_QP_PMSTATE_ARMED 0x0
3712 #define HERMON_QP_PMSTATE_REARM 0x1
3713
3714 #define HERMON_QP_DESC_EVT_DISABLED 0x0
3715 #define HERMON_QP_DESC_EVT_ENABLED 0x1
3716
3717 #define HERMON_QP_FLIGHT_LIM_UNLIMITED 0xF
3718
3719 #define HERMON_QP_SQ_ALL_SIGNALED 0x1
3720 #define HERMON_QP_SQ_WR_SIGNALED 0x0
3721 #define HERMON_QP_RQ_ALL_SIGNALED 0x1
3722 #define HERMON_QP_RQ_WR_SIGNALED 0x0
3723
3724 #define HERMON_QP_SRQ_ENABLED 0x1
3725 #define HERMON_QP_SRQ_DISABLED 0x0
3726
3727 #define HERMON_QP_WQE_BASE_SHIFT 0x6
3728
3729 /*
3730 * Hermon Multicast Group Member (MCG)
3731 * Hermon MCG are organized in a virtually-contiguous memory table (the
3732 * Multicast Group Table) in the ICM. This table is
3733 * actually comprised of two consecutive tables: the Multicast Group Hash
3734 * Table (MGHT) and the Additional Multicast Group Members Table (AMGM).
3735 * Each such entry contains an MGID and a list of QPs that are attached to
3736 * the multicast group. Each such entry may also include an index to an
3737 * Additional Multicast Group Member Table (AMGM) entry. The AMGMs are
3738 * used to form a linked list of MCG entries that all map to the same hash
3739 * value. The MCG entry size is configured through the INIT_HCA command.
3740 * Note: An MCG actually consists of a single hermon_hw_mcg_t and some
3741 * number of hermon_hw_mcg_qp_list_t (such that the combined structure is a
3742 * power-of-2).
3743 *
3744 * The following structures are used in the READ_MGM and WRITE_MGM commands.
3745 * The READ_MGM command reads an MCG entry from the multicast table and
3746 * returns it in the output mailbox. Note: This operation does not affect
3747 * the MCG entry state or values.
3748 * The WRITE_MGM command retrieves an MCG entry from the input mailbox and
3749 * stores it in the multicast group table at the index specified in the
3750 * command. Once the command has finished execution, the multicast group
3751 * table is updated. The old entry contents are lost.
3752 */
3753 #ifdef _LITTLE_ENDIAN
3754 struct hermon_hw_mcg_s {
3755 uint32_t member_cnt :24;
3756 uint32_t :6;
3757 uint32_t protocol :2;
3758
3759 uint32_t :6;
3760 uint32_t next_gid_indx :26;
3761
3762 uint32_t :32;
3763 uint32_t :32;
3764
3765 uint64_t mgid_h;
3766 uint64_t mgid_l;
3767 };
3768 #else
3769 struct hermon_hw_mcg_s {
3770 uint32_t next_gid_indx :26;
3771 uint32_t :6;
3772
3773 uint32_t protocol :2;
3774 uint32_t :6;
3775 uint32_t member_cnt :24;
3776
3777 uint32_t :32;
3778 uint32_t :32;
3779
3780 uint64_t mgid_h;
3781 uint64_t mgid_l;
3782 };
3783 #endif
3784
3785 #ifdef _LITTLE_ENDIAN
3786 struct hermon_hw_mcg_en_s {
3787 uint32_t member_cnt :24;
3788 uint32_t :6;
3789 uint32_t protocol :2;
3790
3791 uint32_t :6;
3792 uint32_t next_gid_indx :26;
3793
3794 uint32_t :32;
3795 uint32_t :32;
3796
3797 uint32_t vlan_present :1;
3798 uint32_t :31;
3799
3800 uint32_t :32;
3801
3802 uint32_t mac_lo :32;
3803
3804 uint32_t mac_hi :16;
3805 uint32_t vlan_id :12;
3806 uint32_t vlan_cfi :1;
3807 uint32_t vlan_prior :3;
3808
3809 };
3810 #else
3811 struct hermon_hw_mcg_en_s {
3812 uint32_t next_gid_indx :26;
3813 uint32_t :6;
3814
3815 uint32_t protocol :2;
3816 uint32_t :6;
3817 uint32_t member_cnt :24;
3818
3819 uint32_t :32;
3820 uint32_t :32;
3821
3822 uint32_t :32;
3823
3824 uint32_t :31;
3825 uint32_t vlan_present :1;
3826
3827 uint32_t vlan_prior :3;
3828 uint32_t vlan_cfi :1;
3829 uint32_t vlan_id :12;
3830 uint32_t mac_hi :16;
3831
3832 uint32_t mac_lo :32;
3833
3834 };
3835 #endif
3836
3837
3838 /* Multicast Group Member - QP List entries */
3839 #ifdef _LITTLE_ENDIAN
3840 struct hermon_hw_mcg_qp_list_s {
3841 uint32_t qpn :24;
3842 uint32_t :6;
3843 uint32_t blk_lb :1;
3844 uint32_t :1;
3845 };
3846 #else
3847 struct hermon_hw_mcg_qp_list_s {
3848 uint32_t :1;
3849 uint32_t blk_lb :1;
3850 uint32_t :6;
3851 uint32_t qpn :24;
3852 };
3853 #endif
3854
3855 #define HERMON_MCG_QPN_BLOCK_LB 0x40000000
3856
3857 /*
3858 * ETHERNET ONLY Commands
3859 * The follow are new commands, used only for an Ethernet Port
3860 */
3861
3862 #ifdef _LITTLE_ENDIAN
3863 struct hermon_hw_set_mcast_fltr_s {
3864 uint32_t mac_lo;
3865
3866 uint32_t mac_hi :16;
3867 uint32_t :15;
3868 uint32_t sfs :1;
3869 };
3870 #else /* BIG ENDIAN */
3871 struct hermon_hw_set_mcast_fltr_s {
3872 uint32_t sfs :1;
3873 uint32_t :15;
3874 uint32_t mac_hi :16;
3875
3876 uint32_t mac_lo;
3877 };
3878 #endif
3879
3880 /* opmod for set_mcast_fltr */
3881 #define HERMON_SET_MCAST_FLTR_CONF 0x0
3882 #define HERMON_SET_MCAST_FLTR_DIS 0x1
3883 #define HERMON_SET_MCAST_FLTR_EN 0x2
3884
3885
3886 /*
3887 * FC Command structures
3888 */
3889
3890
3891
3892 #ifdef _LITTLE_ENDIAN
3893 struct hermon_hw_config_fc_basic_s {
3894 uint32_t n_p :2;
3895 uint32_t :6;
3896 uint32_t n_v :3;
3897 uint32_t :5;
3898 uint32_t n_m :4;
3899 uint32_t :12;
3900
3901 uint32_t :16;
3902 uint32_t fexch_base_hi :8;
3903 uint32_t :8;
3904
3905 uint32_t rfci_base :24;
3906 uint32_t log2_num_rfci :3;
3907 uint32_t :5;
3908
3909 uint32_t fx_base_mpt_lo :8;
3910 uint32_t :17;
3911 uint32_t fx_base_mpt_hi :7;
3912
3913 uint32_t fcoe_prom_qpn :24;
3914 uint32_t uint32_t :8;
3915
3916 uint32_t :32;
3917
3918 uint32_t rsrv[58];
3919 };
3920 #else
3921 struct hermon_hw_config_fc_basic_s {
3922 uint32_t :8;
3923 uint32_t fexch_base_hi :8;
3924 uint32_t :16;
3925
3926 uint32_t :12;
3927 uint32_t n_m :4;
3928 uint32_t :5;
3929 uint32_t n_v :3;
3930 uint32_t :6;
3931 uint32_t n_p :2;
3932
3933 uint32_t fx_base_mpt_hi :7;
3934 uint32_t :17;
3935 uint32_t fx_base_mpt_lo :8;
3936
3937 uint32_t :5;
3938 uint32_t log2_num_rfci :3;
3939 uint32_t rfci_base :24;
3940
3941 uint32_t :32;
3942
3943 uint32_t uint32_t :8;
3944 uint32_t fcoe_prom_qpn :24;
3945
3946 uint32_t rsrv[58];
3947 };
3948 #endif
3949
3950 #define HERMON_HW_FC_PORT_ENABLE 0x0
3951 #define HERMON_HW_FC_PORT_DISABLE 0x1
3952 #define HERMON_HW_FC_CONF_BASIC 0x0000
3953 #define HERMON_HW_FC_CONF_NPORT 0x0100
3954
3955 #ifdef _LITTLE_ENDIAN
3956 struct hermon_hw_query_fc_s {
3957 uint32_t :32;
3958
3959 uint32_t log2_max_rfci :3;
3960 uint32_t :5;
3961 uint32_t log2_max_fexch :5;
3962 uint32_t :3;
3963 uint32_t log2_max_nports :3;
3964 uint32_t :13;
3965
3966 uint32_t rsrv[62];
3967 };
3968 #else
3969 struct hermon_hw_query_fc_s {
3970 uint32_t :13;
3971 uint32_t log2_max_nports :3;
3972 uint32_t :3;
3973 uint32_t log2_max_fexch :5;
3974 uint32_t :5;
3975 uint32_t log2_max_rfci :3;
3976
3977 uint32_t :32;
3978
3979 uint32_t rsrv[62];
3980 };
3981 #endif
3982
3983
3984
3985
3986 /* ARM_RQ - limit water mark for srq & rq */
3987 #ifdef _LITTLE_ENDIAN
3988 struct hermon_hw_arm_req_s {
3989 uint32_t lwm :16;
3990 uint32_t :16;
3991
3992 uint32_t :32;
3993 };
3994 #else
3995 struct hermon_hw_arm_req_s {
3996 uint32_t :32;
3997
3998 uint32_t :16;
3999 uint32_t lwm :16;
4000 };
4001 #endif
4002
4003 /*
4004 * Structure for getting the peformance counters from the HCA
4005 */
4006
4007 #ifdef _LITTLE_ENDIAN
4008 struct hermon_hw_sm_perfcntr_s {
4009 uint32_t linkdown :8;
4010 uint32_t linkerrrec :8;
4011 uint32_t symerr :16;
4012
4013 uint32_t cntrsel :16;
4014 uint32_t portsel :8;
4015 uint32_t :8;
4016
4017 uint32_t portxmdiscard :16;
4018 uint32_t portrcvswrelay :16;
4019
4020 uint32_t portrcvrem :16;
4021 uint32_t portrcv :16;
4022
4023 uint32_t vl15drop :16;
4024 uint32_t :16;
4025
4026 uint32_t xsbuffovrun :4;
4027 uint32_t locallinkint :4;
4028 uint32_t :8;
4029 uint32_t portrcconstr :8;
4030 uint32_t portxmconstr :8;
4031
4032 uint32_t portrcdata;
4033
4034 uint32_t portxmdata;
4035
4036 uint32_t portrcpkts;
4037
4038 uint32_t portxmpkts;
4039
4040 uint32_t reserved;
4041
4042 uint32_t portxmwait;
4043 };
4044 #else /* BIG ENDIAN */
4045 struct hermon_hw_sm_perfcntr_s {
4046 uint32_t :8;
4047 uint32_t portsel :8;
4048 uint32_t cntrsel :16;
4049
4050 uint32_t symerr :16;
4051 uint32_t linkerrrec :8;
4052 uint32_t linkdown :8;
4053
4054 uint32_t portrcv :16;
4055 uint32_t portrcvrem :16;
4056
4057 uint32_t portrcvswrelay :16;
4058 uint32_t portxmdiscard :16;
4059
4060 uint32_t portxmconstr :8;
4061 uint32_t portrcconstr :8;
4062 uint32_t :8;
4063 uint32_t locallinkint :4;
4064 uint32_t xsbuffovrun :4;
4065
4066 uint32_t :16;
4067 uint32_t vl15drop :16;
4068
4069 uint32_t portxmdata;
4070
4071 uint32_t portrcdata;
4072
4073 uint32_t portxmpkts;
4074
4075 uint32_t portrcpkts;
4076
4077 uint32_t portxmwait;
4078
4079 uint32_t reserved;
4080 };
4081 #endif
4082
4083 /*
4084 * Structure for getting the extended peformance counters from the HCA
4085 */
4086
4087 #ifdef _LITTLE_ENDIAN
4088 struct hermon_hw_sm_extperfcntr_s {
4089 uint32_t rsvd;
4090 uint32_t cntrsel :16;
4091 uint32_t portsel :8;
4092 uint32_t :8;
4093
4094 uint64_t portxmdata;
4095
4096 uint64_t portrcdata;
4097
4098 uint64_t portxmpkts;
4099
4100 uint64_t portrcpkts;
4101
4102 uint64_t portunicastxmpkts;
4103
4104 uint64_t portunicastrcpkts;
4105
4106 uint64_t portmulticastxmpkts;
4107
4108 uint64_t portmulticastrcpkts;
4109 };
4110 #else /* BIG ENDIAN */
4111 struct hermon_hw_sm_extperfcntr_s {
4112 uint32_t :8;
4113 uint32_t portsel :8;
4114 uint32_t cntrsel :16;
4115 uint32_t rsvd;
4116
4117 uint64_t portxmdata;
4118
4119 uint64_t portrcdata;
4120
4121 uint64_t portxmpkts;
4122
4123 uint64_t portrcpkts;
4124
4125 uint64_t portunicastxmpkts;
4126
4127 uint64_t portunicastrcpkts;
4128
4129 uint64_t portmulticastxmpkts;
4130
4131 uint64_t portmulticastrcpkts;
4132 };
4133 #endif
4134
4135
4136 /*
4137 * Hermon User Access Region (UAR)
4138 *
4139 * JBDB : writeup on the UAR for memfree
4140 *
4141 * JBDB : writeup on the structures
4142 * UAR page
4143 * DB register
4144 * DB record
4145 * UCE
4146 *
4147 * [es] and change it even further for hermon
4148 * the whole UAR and doorbell record (dbr) approach is changed again
4149 * from arbel, and needs commenting
4150 *
4151 * -- Tavor comment
4152 *
4153 *
4154 * Tavor doorbells are each rung by writing to the doorbell registers that
4155 * form a User Access Region (UAR). A doorbell is a write-only hardware
4156 * register which enables passing information from software to hardware
4157 * with minimum software latency. A write operation from the host software
4158 * to these doorbell registers passes information about the HCA resources
4159 * and initiates processing of the doorbell data. There are 6 types of
4160 * doorbells in Tavor.
4161 *
4162 * "Send Doorbell" for synchronizing the attachment of a WQE (or a chain
4163 * of WQEs) to the send queue.
4164 * "RD Send Doorbell" (Same as above, except for RD QPs) is not supported.
4165 * "Receive Doorbell" for synchronizing the attachment of a WQE (or a chain
4166 * of WQEs) to the receive queue.
4167 * "CQ Doorbell" for updating the CQ consumer index and requesting
4168 * completion notifications.
4169 * "EQ Doorbell" for updating the EQ consumer index, arming interrupt
4170 * triggering, and disarming CQ notification requests.
4171 * "InfiniBlast" (which would have enabled access to the "InfiniBlast
4172 * buffer") is not supported.
4173 *
4174 * Note: The tavor_hw_uar_t below is the container for all of the various
4175 * doorbell types. Below we first define several structures which make up
4176 * the contents of those doorbell types.
4177 *
4178 * Note also: The following structures are not #define'd with both little-
4179 * endian and big-endian definitions. This is because each doorbell type
4180 * is not directly accessed except through a single ddi_put64() operation
4181 * (see tavor_qp_send_doorbell, tavor_qp_recv_doorbell, tavor_cq_doorbell,
4182 * or tavor_eq_doorbell)
4183 */
4184
4185 /*
4186 * Send doorbell register structure
4187 */
4188 typedef struct hermon_hw_send_db_reg_s {
4189 uint32_t :32;
4190
4191 uint32_t snd_q_num :24;
4192 uint32_t :8;
4193 } hermon_hw_send_db_reg_t;
4194
4195 #define HERMON_QPSNDDB_QPN_SHIFT 0x8
4196
4197 /* Max descriptors per Hermon doorbell */
4198 #define HERMON_QP_MAXDESC_PER_DB 256
4199
4200 /*
4201 * CQ doorbell register structure
4202 */
4203 typedef struct hermon_hw_cq_db_reg_s {
4204 uint32_t :2;
4205 uint32_t cmd_sn :2;
4206 uint32_t :2;
4207 uint32_t cmd :2;
4208 uint32_t cqn :24;
4209
4210 uint32_t :8;
4211 /* consumer cntr of last polled completion */
4212 uint32_t cq_ci :24;
4213 } hermon_hw_cq_db_reg_t;
4214
4215 #define HERMON_CQDB_CMD_SHIFT 0x18 /* dec 24 */
4216 #define HERMON_CQDB_CMDSN_SHIFT 0x1C /* dec 28 */
4217
4218
4219 #define HERMON_CQDB_NOTIFY_CQ 0x02
4220 #define HERMON_CQDB_NOTIFY_CQ_SOLICIT 0x01
4221
4222 /* Default value for use in NOTIFY_CQ doorbell */
4223 #define HERMON_CQDB_DEFAULT_PARAM 0xFFFFFFFF
4224
4225 typedef struct hermon_hw_guest_eq_ci_s { /* guest op eq consumer index */
4226 uint32_t armed :1;
4227 uint32_t :7;
4228 uint32_t guestos_ci :24;
4229
4230 uint32_t :32;
4231 } hermon_hw_guest_eq_ci_t;
4232
4233
4234
4235 /*
4236 * UAR page structure, containing all doorbell registers
4237 */
4238 struct hermon_hw_uar_s {
4239 uint32_t rsrv0[4];
4240
4241 hermon_hw_send_db_reg_t send;
4242
4243 uint32_t rsrv1[2];
4244
4245 hermon_hw_cq_db_reg_t cq;
4246
4247 uint32_t rsrv2[502]; /* next is at offset 0x800 */
4248
4249 hermon_hw_guest_eq_ci_t g_eq0;
4250 hermon_hw_guest_eq_ci_t g_eq1;
4251 hermon_hw_guest_eq_ci_t g_eq2;
4252 hermon_hw_guest_eq_ci_t g_eq3;
4253
4254 uint32_t rsrv3[504]; /* end of page */
4255 };
4256
4257 /*
4258 * QP (RQ, SRQ) doorbell record-specific data
4259 * Note that this structure is NOT in ICM, but just kept in host memory
4260 * and managed independently of PRM or other constraints. Also, though
4261 * the qp/srq doorbell need to be only 4 bytes, it is 8 bytes in memory for
4262 * ease of management. Hermon defines its usage in the QP chapter.
4263 */
4264 typedef struct hermon_hw_qp_db_s {
4265 uint32_t :16;
4266 uint32_t rcv_wqe_cntr :16; /* wqe_counter */
4267
4268 uint32_t :32;
4269 } hermon_hw_qp_db_t;
4270
4271 /*
4272 * CQ (ARM and SET_CI) doorbell record-specific data
4273 * See comment above re: QP doorbell. This dbr is 8 bytes long, and its
4274 * usage is defined in PRM chapter on Completion Queues
4275 */
4276 typedef struct hermon_hw_cq_arm_db_s {
4277 uint32_t :8;
4278 uint32_t update_ci :24;
4279
4280 uint32_t :2;
4281 /* sequence number of the doorbell ring % 4 */
4282 uint32_t cmd_sn :2;
4283 uint32_t :1;
4284 uint32_t cmd :3; /* command */
4285 uint32_t cq_ci :24;
4286 } hermon_hw_cq_db_t;
4287
4288 #define HERMON_CQ_DB_CMD_SOLICTED 0x01
4289 #define HERMON_CQ_DB_CMD_NEXT 0x02
4290
4291
4292 /*
4293 * Hermon Blue Flame (BF)
4294 * Hermon has the ability to do a low-latency write of successive WQEs
4295 * for the HCA. This utilizes part of the memory area behind the
4296 * same BAR as the UAR page (see above) - half the area is devoted to
4297 * UAR pages, the other half to BlueFlame (though in fairness, the return
4298 * information from QUERY_DEV_CAP should be consulted _in case_ they ever
4299 * decide to change it.
4300 *
4301 * We define the structures to access them below.
4302 */
4303
4304
4305 /*
4306 * Hermon Send Work Queue Element (WQE)
4307 * A Hermon Send WQE is built of the following segments, each of which is a
4308 * multiple of 16 bytes. Note: Each individual WQE may contain only a
4309 * subset of these segments described below (according to the operation type
4310 * and transport type of the QP).
4311 *
4312 * The first 16 bytes of ever WQE are formed from the "Ctrl" segment.
4313 * This segment contains the address of the next WQE to be executed and the
4314 * information required in order to allocate the resources to execute the
4315 * next WQE. The "Ctrl" part of this segment contains the control
4316 * information required to execute the WQE, including the opcode and other
4317 * control information.
4318 * The "Datagram" segment contains address information required in order to
4319 * form a UD message.
4320 * The "Bind" segment contains the parameters required for a Bind Memory
4321 * Window operation.
4322 * The "Remote Address" segment is present only in RDMA or Atomic WQEs and
4323 * specifies remote virtual addresses and RKey, respectively. Length of
4324 * the remote access is calculated from the scatter/gather list (for
4325 * RDMA-write/RDMA-read) or set to eight (for Atomic).
4326 * The "Atomic" segment is present only in Atomic WQEs and specifies
4327 * Swap/Add and Compare data.
4328 *
4329 * Note: The following structures are not #define'd with both little-endian
4330 * and big-endian definitions. This is because their individual fields are
4331 * not directly accessed except through macros defined below.
4332 */
4333
4334
4335 struct hermon_hw_snd_wqe_ctrl_s {
4336 uint32_t owner :1;
4337 uint32_t :1;
4338 uint32_t nec :1;
4339 uint32_t :5;
4340 uint32_t fceof :8;
4341 uint32_t :9;
4342 uint32_t rr :1;
4343 uint32_t :1;
4344 uint32_t opcode :5;
4345
4346 uint32_t vlan :16;
4347 uint32_t :1;
4348 uint32_t cv :1;
4349 uint32_t :7;
4350 uint32_t fence :1;
4351 uint32_t ds :6; /* WQE size in octowords */
4352
4353 /*
4354 * XRC remote buffer if impl
4355 * XRC 23:0, or DMAC 47:32& 8 bits of pad
4356 */
4357 uint32_t xrc_rem_buf :24;
4358 uint32_t so :1;
4359 uint32_t fcrc :1; /* fc crc calc */
4360 uint32_t tcp_udp :1; /* Checksumming */
4361 uint32_t ip :1; /* Checksumming */
4362 uint32_t cq_gen :2; /* 00=no cqe, 11= gen cqe */
4363 /* s-bit set means solicit bit in last packet */
4364 uint32_t s :1;
4365 uint32_t force_lb :1;
4366
4367 /*
4368 * immediate OR invalidation key OR DMAC 31:0 depending
4369 */
4370 uint32_t immediate :32;
4371 };
4372
4373 struct hermon_hw_srq_wqe_next_s {
4374 uint32_t :16;
4375 uint32_t next_wqe_idx :16;
4376
4377 uint32_t rsvd[3];
4378 };
4379
4380
4381 struct hermonw_hw_fcp3_ctrl_s {
4382 uint32_t owner :1;
4383 uint32_t :1;
4384 uint32_t nec :1;
4385 uint32_t :24;
4386 uint32_t opcode :5;
4387
4388 uint32_t :24;
4389 uint32_t sit :1;
4390 uint32_t :1;
4391 uint32_t ds :6;
4392
4393 uint32_t seq_id :8;
4394 uint32_t info :4;
4395 uint32_t :3;
4396 uint32_t ls :1;
4397 uint32_t :8;
4398 uint32_t so :1;
4399 uint32_t :3;
4400 uint32_t cq_gen :2;
4401 uint32_t :2;
4402
4403 uint32_t param :32;
4404 };
4405
4406 struct hermon_hw_fcp3_init_s {
4407 uint32_t :8;
4408 uint32_t pe :1;
4409 uint32_t :23;
4410
4411 uint32_t csctl_prior :8;
4412 uint32_t seqid_tx :8;
4413 uint32_t :6;
4414 uint32_t mtu :10;
4415
4416 uint32_t rem_id :24;
4417 uint32_t abort :2;
4418 uint32_t :1;
4419 uint32_t op :2;
4420 uint32_t :1;
4421 uint32_t org :1;
4422 uint32_t :1;
4423
4424 uint32_t rem_exch :16;
4425 uint32_t loc_exch_idx :16;
4426 };
4427
4428 struct hermon_hw_fcmd_o_enet_s {
4429 uint32_t :4;
4430 uint32_t stat_rate :4;
4431 uint32_t :24;
4432
4433 uint32_t :32;
4434
4435 uint32_t :16;
4436 uint32_t dmac_hi :16;
4437
4438 uint32_t dmac_lo :32;
4439 };
4440
4441 struct hermon_hw_fcmd_o_ib_s {
4442 uint32_t :32;
4443
4444 uint32_t :8;
4445 uint32_t grh :1;
4446 uint32_t :7;
4447 uint32_t rlid :16;
4448
4449 uint32_t :20;
4450 uint32_t stat_rate :4;
4451 uint32_t hop_limit :8;
4452
4453 uint32_t sl :4;
4454 uint32_t tclass :8;
4455 uint32_t flow_label :20;
4456
4457 uint64_t rgid_hi;
4458
4459 uint64_t rgid_lo;
4460
4461 uint32_t :8;
4462 uint32_t rqp :24;
4463
4464 uint32_t rsrv[3];
4465 };
4466
4467
4468
4469
4470
4471 #define HERMON_WQE_SEND_FENCE_MASK 0x40
4472
4473 #define HERMON_WQE_SEND_NOPCODE_NOP 0x00
4474 #define HERMON_WQE_SEND_NOPCODE_SND_INV 0x01
4475 #define HERMON_WQE_SEND_NOPCODE_RDMAW 0x8
4476 #define HERMON_WQE_SEND_NOPCODE_RDMAWI 0x9
4477 #define HERMON_WQE_SEND_NOPCODE_SEND 0xA
4478 #define HERMON_WQE_SEND_NOPCODE_SENDI 0xB
4479 #define HERMON_WQE_SEND_NOPCODE_INIT_AND_SEND 0xD
4480 #define HERMON_WQE_SEND_NOPCODE_LSO 0xE
4481 #define HERMON_WQE_SEND_NOPCODE_RDMAR 0x10
4482 #define HERMON_WQE_SEND_NOPCODE_ATMCS 0x11
4483 #define HERMON_WQE_SEND_NOPCODE_ATMFA 0x12
4484 #define HERMON_WQE_SEND_NOPCODE_ATMCSE 0x14
4485 #define HERMON_WQE_SEND_NOPCODE_ATMFAE 0x15
4486 #define HERMON_WQE_SEND_NOPCODE_BIND 0x18
4487 #define HERMON_WQE_SEND_NOPCODE_FRWR 0x19
4488 #define HERMON_WQE_SEND_NOPCODE_LCL_INV 0x1B
4489 #define HERMON_WQE_SEND_NOPCODE_CONFIG 0x1F /* for ccq only */
4490
4491 #define HERMON_WQE_FCP_OPCODE_INIT_AND_SEND 0xD
4492 #define HERMON_WQE_FCP_OPCODE_INIT_FEXCH 0xC
4493
4494 #define HERMON_WQE_SEND_SIGNALED_MASK 0x0000000C00000000ull
4495 #define HERMON_WQE_SEND_SOLICIT_MASK 0x0000000200000000ull
4496 #define HERMON_WQE_SEND_IMMEDIATE_MASK 0x0000000100000000ull
4497
4498 struct hermon_hw_snd_wqe_ud_s {
4499 struct hermon_hw_udav_s ud_addr_v;
4500
4501 uint32_t :8;
4502 uint32_t dest_qp :24;
4503
4504 uint32_t qkey :32;
4505
4506 uint32_t vlan :16;
4507 uint32_t dmac_hi :16;
4508
4509 uint32_t dmac_lo :32;
4510 };
4511 #define HERMON_WQE_SENDHDR_UD_AV_MASK 0xFFFFFFFFFFFFFFE0ull
4512 #define HERMON_WQE_SENDHDR_UD_DQPN_MASK 0xFFFFFF
4513
4514 struct hermon_hw_snd_wqe_bind_s {
4515 uint32_t ae :1;
4516 uint32_t rw :1;
4517 uint32_t rr :1;
4518 uint32_t :3;
4519 uint32_t l_64 :1;
4520 uint32_t :25;
4521
4522 uint32_t win_t :1;
4523 uint32_t z_base :1;
4524 uint32_t :30;
4525
4526 uint32_t new_rkey;
4527 uint32_t reg_lkey;
4528 uint64_t addr;
4529 uint64_t len;
4530 };
4531 #define HERMON_WQE_SENDHDR_BIND_ATOM 0x8000000000000000ull
4532 #define HERMON_WQE_SENDHDR_BIND_WR 0x4000000000000000ull
4533 #define HERMON_WQE_SENDHDR_BIND_RD 0x2000000000000000ull
4534
4535 struct hermon_hw_snd_wqe_lso_s {
4536 uint32_t mss :16;
4537 uint32_t :6;
4538 uint32_t hdr_size :10;
4539 };
4540
4541 struct hermon_hw_snd_wqe_remaddr_s {
4542 uint64_t vaddr;
4543 uint32_t rkey;
4544 uint32_t :32;
4545 };
4546
4547 struct hermon_hw_snd_wqe_atomic_s {
4548 uint64_t swap_add;
4549 uint64_t compare;
4550 };
4551
4552 struct hermon_hw_snd_wqe_atomic_ext_s {
4553 uint64_t swap_add;
4554 uint64_t compare;
4555 uint64_t swapmask;
4556 uint64_t cmpmask;
4557 };
4558
4559 struct hermon_hw_snd_wqe_local_inv_s {
4560 uint32_t :6;
4561 uint32_t atc_shoot :1;
4562 uint32_t :25;
4563
4564 uint32_t :32;
4565
4566 uint32_t mkey;
4567
4568 uint32_t rsrv0;
4569
4570 uint32_t rsrv1;
4571 uint32_t :25;
4572 uint32_t guest_id :7; /* for atc shootdown */
4573
4574 uint32_t p_addrh;
4575 uint32_t p_addrl :23;
4576 uint32_t :9;
4577 };
4578
4579 struct hermon_hw_snd_rem_addr_s {
4580 uint64_t rem_vaddr;
4581
4582 uint32_t rkey;
4583 uint32_t rsrv;
4584 };
4585
4586
4587 struct hermon_hw_snd_wqe_frwr_s {
4588 uint32_t rem_atomic :1;
4589 uint32_t rem_write :1;
4590 uint32_t rem_read :1;
4591 uint32_t loc_write :1;
4592 uint32_t loc_read :1;
4593 uint32_t fbo_en :1;
4594 uint32_t len_64 :1;
4595 uint32_t :2;
4596 uint32_t dif :1; /* FCoIB */
4597 uint32_t bind_en :1;
4598 uint32_t blk_pg_mode :1;
4599 uint32_t mtt_rep :4;
4600 uint32_t :16;
4601
4602 uint32_t mkey; /* swapped w/ addrh relative to arbel */
4603
4604 uint64_t pbl_addr;
4605
4606 uint64_t start_addr;
4607
4608 uint64_t reg_len; /* w/ len_64 allows 65 bits of length */
4609
4610 uint32_t :11;
4611 uint32_t fbo :21;
4612
4613 uint32_t :11;
4614 uint32_t pge_blk_sz :21;
4615
4616 uint32_t rsrv0[2];
4617 };
4618
4619 struct hermon_hw_snd_wqe_frwr_ext_s {
4620 uint32_t dif_in_mem :1;
4621 uint32_t dif_on_wire :1;
4622 uint32_t valid_ref :1;
4623 uint32_t valid_crc :1;
4624 uint32_t repl_ref_tag :1;
4625 uint32_t repl_app_tag :1;
4626 uint32_t :10;
4627 uint32_t app_mask :16;
4628
4629 uint32_t wire_app_tag :16;
4630 uint32_t mem_app_tag :16;
4631
4632 uint32_t wire_ref_tag_base;
4633
4634 uint32_t mem_ref_tag_base;
4635 };
4636
4637
4638
4639 /*
4640 * Hermon "MLX transport" Work Queue Element (WQE)
4641 * The format of the MLX WQE is similar to that of the Send WQE (above)
4642 * with the following exceptions. MLX WQEs are used for sending MADs on
4643 * special QPs 0 and 1. Everything following the "Next/Ctrl" header
4644 * (defined below) consists of scatter-gather list entries. The contents
4645 * of these SGLs (also defined below) will be put on the wire exactly as
4646 * they appear in the buffers. In addition, the VCRC and the ICRC of each
4647 * sent packet can be modified by changing values in the following header
4648 * or in the payload of the packet itself.
4649 */
4650
4651
4652 struct hermon_hw_mlx_wqe_nextctrl_s {
4653 uint32_t owner :1;
4654 uint32_t :23;
4655 uint32_t :3;
4656 uint32_t opcode :5; /* is 0x0A (send) for MLX */
4657
4658 uint32_t :26;
4659 uint32_t ds :6; /* WQE size in octowords */
4660
4661 uint32_t :14;
4662 uint32_t vl15 :1;
4663 uint32_t slr :1;
4664 uint32_t max_srate :4;
4665 uint32_t sl :4;
4666 uint32_t :3; /* FCoIB usage */
4667 uint32_t icrc :1; /* 1==don't replace icrc fld */
4668 uint32_t cq_gen :2; /* 00= no cqe, 11==cqe */
4669 uint32_t :1;
4670 uint32_t force_lb :1;
4671
4672 uint32_t rlid :16;
4673 uint32_t :16;
4674 };
4675
4676
4677 #define HERMON_WQE_MLXHDR_VL15_MASK 0x0002000000000000ull
4678 #define HERMON_WQE_MLXHDR_SLR_MASK 0x0001000000000000ull
4679 #define HERMON_WQE_MLXHDR_SRATE_SHIFT 44
4680 #define HERMON_WQE_MLXHDR_SL_SHIFT 40
4681 #define HERMON_WQE_MLXHDR_SIGNALED_MASK 0x0000000800000000ull
4682 #define HERMON_WQE_MLXHDR_RLID_SHIFT 16
4683
4684
4685 /*
4686 * Hermon Receive Work Queue Element (WQE)
4687 * Unlike the Send WQE, the Receive WQE is built ONLY of 16-byte segments. A
4688 * "Next/Ctrl" segment is no longer needed, because of the fixed
4689 * receive queue stride (RQ.STRIDE). It contains just
4690 * some number of scatter list entries for the incoming message.
4691 *
4692 * The format of the scatter-gather list entries is shown below. For
4693 * Receive WQEs the "inline_data" field must be cleared (i.e. data segments
4694 * cannot contain inline data).
4695 */
4696
4697
4698 struct hermon_hw_wqe_sgl_s {
4699 uint32_t inline_data :1;
4700 uint32_t byte_cnt :31;
4701
4702 uint32_t lkey;
4703
4704 uint64_t addr;
4705 };
4706 #define HERMON_WQE_SGL_BYTE_CNT_MASK 0x7FFFFFFF
4707 #define HERMON_WQE_SGL_INLINE_MASK 0x80000000
4708
4709 /*
4710 * The following defines are used when building descriptors for special QP
4711 * work requests (i.e. MLX transport WQEs). Note: Because Hermon MLX transport
4712 * requires the driver to build actual IB packet headers, we use these defines
4713 * for the most common fields in those headers.
4714 */
4715
4716
4717 #define HERMON_MLX_VL15_LVER 0xF0000000
4718 #define HERMON_MLX_VL0_LVER 0x00000000
4719 #define HERMON_MLX_IPVER_TC_FLOW 0x60000000
4720 #define HERMON_MLX_TC_SHIFT 20
4721 #define HERMON_MLX_DEF_PKEY 0xFFFF
4722 #define HERMON_MLX_GSI_QKEY 0x80010000
4723 #define HERMON_MLX_UDSEND_OPCODE 0x64000000
4724 #define HERMON_MLX_DQPN_MASK 0xFFFFFF
4725
4726 /*
4727 * The following macros are used for building each of the individual
4728 * segments that can make up a Hermon WQE. Note: We try not to use the
4729 * structures (with their associated bitfields) here, instead opting to
4730 * build and put 64-bit or 32-bit chunks to the WQEs as appropriate,
4731 * primarily because using the bitfields appears to force more read-modify-
4732 * write operations.
4733 *
4734 * HERMON_WQE_BUILD_UD - Builds Unreliable Datagram Segment
4735 *
4736 * HERMON_WQE_BUILD_REMADDR - Builds Remote Address Segment using
4737 * RDMA info from the work request
4738 * HERMON_WQE_BUILD_RC_ATOMIC_REMADDR - Builds Remote Address Segment
4739 * for RC Atomic work requests
4740 * HERMON_WQE_BUILD_ATOMIC - Builds Atomic Segment using atomic
4741 * info from the work request
4742 * HERMON_WQE_BUILD_BIND - Builds the Bind Memory Window
4743 * Segment using bind info from the
4744 * work request
4745 * HERMON_WQE_BUILD_DATA_SEG - Builds the individual Data Segments
4746 * for Send, Receive, and MLX WQEs
4747 * HERMON_WQE_BUILD_INLINE - Builds an "inline" Data Segment
4748 * (primarily for MLX transport)
4749 * HERMON_WQE_BUILD_INLINE_ICRC - Also builds an "inline" Data Segment
4750 * (but used primarily in the ICRC
4751 * portion of MLX transport WQEs)
4752 * HERMON_WQE_LINKNEXT - Links the current WQE to the
4753 * previous one
4754 * HERMON_WQE_LINKFIRST - Links the first WQE on the current
4755 * chain to the previous WQE
4756 * HERMON_WQE_BUILD_MLX_LRH - Builds the inline LRH header for
4757 * MLX transport MADs
4758 * HERMON_WQE_BUILD_MLX_GRH - Builds the inline GRH header for
4759 * MLX transport MADs
4760 * HERMON_WQE_BUILD_MLX_BTH - Builds the inline BTH header for
4761 * MLX transport MADs
4762 * HERMON_WQE_BUILD_MLX_DETH - Builds the inline DETH header for
4763 * MLX transport MADs
4764 */
4765 #define HERMON_WQE_BUILD_UD(qp, ud, ah, dest) \
4766 { \
4767 uint64_t *tmp; \
4768 uint64_t *udav; \
4769 \
4770 tmp = (uint64_t *)(ud); \
4771 udav = (uint64_t *)(ah)->ah_udav; \
4772 tmp[0] = ntohll(udav[0]); \
4773 tmp[1] = ntohll(udav[1]); \
4774 tmp[2] = ntohll(udav[2]); \
4775 tmp[3] = ntohll(udav[3]); \
4776 tmp[4] = ntohll((((uint64_t)((dest)->ud_dst_qpn & \
4777 HERMON_WQE_SENDHDR_UD_DQPN_MASK) << 32) | \
4778 (dest)->ud_qkey)); \
4779 tmp[5] = 0; \
4780 }
4781
4782 #define HERMON_WQE_BUILD_LSO(qp, ds, mss, hdr_sz) \
4783 *(uint32_t *)(ds) = htonl(((mss) << 16) | hdr_sz);
4784
4785 #define HERMON_WQE_BUILD_REMADDR(qp, ra, wr_rdma) \
4786 { \
4787 uint64_t *tmp; \
4788 \
4789 tmp = (uint64_t *)(ra); \
4790 tmp[0] = htonll((wr_rdma)->rdma_raddr); \
4791 tmp[1] = htonll((uint64_t)(wr_rdma)->rdma_rkey << 32); \
4792 }
4793
4794 #define HERMON_WQE_BUILD_RC_ATOMIC_REMADDR(qp, rc, wr) \
4795 { \
4796 uint64_t *tmp; \
4797 \
4798 tmp = (uint64_t *)(rc); \
4799 tmp[0] = htonll((wr)->wr.rc.rcwr.atomic->atom_raddr); \
4800 tmp[1] = htonll((uint64_t)(wr)->wr.rc.rcwr.atomic->atom_rkey << 32); \
4801 }
4802
4803 #define HERMON_WQE_BUILD_ATOMIC(qp, at, wr_atom) \
4804 { \
4805 uint64_t *tmp; \
4806 \
4807 tmp = (uint64_t *)(at); \
4808 tmp[0] = htonll((wr_atom)->atom_arg2); \
4809 tmp[1] = htonll((wr_atom)->atom_arg1); \
4810 }
4811
4812 #define HERMON_WQE_BUILD_BIND(qp, bn, wr_bind) \
4813 { \
4814 uint64_t *tmp; \
4815 uint64_t bn0_tmp; \
4816 ibt_bind_flags_t bind_flags; \
4817 \
4818 tmp = (uint64_t *)(bn); \
4819 bind_flags = (wr_bind)->bind_flags; \
4820 bn0_tmp = (bind_flags & IBT_WR_BIND_ATOMIC) ? \
4821 HERMON_WQE_SENDHDR_BIND_ATOM : 0; \
4822 bn0_tmp |= (bind_flags & IBT_WR_BIND_WRITE) ? \
4823 HERMON_WQE_SENDHDR_BIND_WR : 0; \
4824 bn0_tmp |= (bind_flags & IBT_WR_BIND_READ) ? \
4825 HERMON_WQE_SENDHDR_BIND_RD : 0; \
4826 tmp[0] = htonll(bn0_tmp); \
4827 tmp[1] = htonll(((uint64_t)(wr_bind)->bind_rkey_out << 32) | \
4828 (wr_bind)->bind_lkey); \
4829 tmp[2] = htonll((wr_bind)->bind_va); \
4830 tmp[3] = htonll((wr_bind)->bind_len); \
4831 }
4832
4833 #define HERMON_WQE_BUILD_FRWR(qp, frwr_arg, pmr_arg) \
4834 { \
4835 ibt_mr_flags_t flags; \
4836 ibt_lkey_t lkey; \
4837 ibt_wr_reg_pmr_t *pmr = (pmr_arg); \
4838 uint64_t *frwr64 = (uint64_t *)(frwr_arg); \
4839 \
4840 flags = pmr->pmr_flags; \
4841 ((uint32_t *)frwr64)[0] = htonl(0x08000000 | \
4842 ((flags & IBT_MR_ENABLE_REMOTE_ATOMIC) ? 0x80000000 : 0) | \
4843 ((flags & IBT_MR_ENABLE_REMOTE_WRITE) ? 0x40000000 : 0) | \
4844 ((flags & IBT_MR_ENABLE_REMOTE_READ) ? 0x20000000 : 0) | \
4845 ((flags & IBT_MR_ENABLE_LOCAL_WRITE) ? 0x10000000 : 0) | \
4846 ((flags & IBT_MR_ENABLE_WINDOW_BIND) ? 0x00200000 : 0)); \
4847 lkey = (pmr->pmr_lkey & ~0xff) | pmr->pmr_key; \
4848 pmr->pmr_rkey = pmr->pmr_lkey = lkey; \
4849 ((uint32_t *)frwr64)[1] = htonl(lkey); \
4850 frwr64[1] = htonll(pmr->pmr_addr_list->p_laddr); \
4851 frwr64[2] = htonll(pmr->pmr_iova); \
4852 frwr64[3] = htonll(pmr->pmr_len); \
4853 ((uint32_t *)frwr64)[8] = htonl(pmr->pmr_offset); \
4854 ((uint32_t *)frwr64)[9] = htonl(pmr->pmr_buf_sz); \
4855 frwr64[5] = 0; \
4856 }
4857
4858 #define HERMON_WQE_BUILD_LI(qp, li_arg, wr_li) \
4859 { \
4860 uint64_t *li64 = (uint64_t *)(void *)(li_arg); \
4861 \
4862 li64[0] = 0; \
4863 ((uint32_t *)li64)[2] = htonl((wr_li)->li_rkey); \
4864 ((uint32_t *)li64)[3] = 0; \
4865 li64[2] = 0; \
4866 li64[3] = 0; \
4867 }
4868
4869 #define HERMON_WQE_BUILD_FCP3_INIT(ds, fctl, cs_pri, seq_id, mtu, \
4870 dest_id, op, rem_exch, local_exch_idx) \
4871 { \
4872 uint32_t *fc_init; \
4873 \
4874 fc_init = (uint32_t *)ds; \
4875 fc_init[1] = htonl((cs_pri) << 24 | (seq_id) << 16 | (mtu)); \
4876 fc_init[2] = htonl((dest_id) << 8 | \
4877 IBT_FCTL_GET_ABORT_FIELD(fctl) << 6 | (op) << 3 | 0x2); \
4878 fc_init[3] = htonl((rem_exch) << 16 | (local_exch_idx)); \
4879 membar_producer(); /* fc_init[0] is where the stamping is */ \
4880 fc_init[0] = htonl(((fctl) & IBT_FCTL_PRIO) << 6); \
4881 }
4882
4883 #define HERMON_WQE_BUILD_DATA_SEG_RECV(ds, sgl) \
4884 { \
4885 uint64_t *tmp; \
4886 \
4887 tmp = (uint64_t *)(ds); \
4888 tmp[0] = htonll((((uint64_t)((sgl)->ds_len & \
4889 HERMON_WQE_SGL_BYTE_CNT_MASK) << 32) | (sgl)->ds_key)); \
4890 tmp[1] = htonll((sgl)->ds_va); \
4891 }
4892
4893 #define HERMON_WQE_BUILD_DATA_SEG_SEND(ds, sgl) \
4894 { \
4895 ((uint64_t *)(ds))[1] = htonll((sgl)->ds_va); \
4896 ((uint32_t *)(ds))[1] = htonl((sgl)->ds_key); \
4897 membar_producer(); \
4898 ((uint32_t *)(ds))[0] = \
4899 htonl((sgl)->ds_len & HERMON_WQE_SGL_BYTE_CNT_MASK); \
4900 }
4901
4902 #define HERMON_WQE_BUILD_INLINE(qp, ds, sz) \
4903 *(uint32_t *)(ds) = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz))
4904
4905 #define HERMON_WQE_BUILD_INLINE_ICRC(qp, ds, sz, icrc) \
4906 { \
4907 uint32_t *tmp; \
4908 \
4909 tmp = (uint32_t *)(ds); \
4910 tmp[1] = htonl(icrc); \
4911 membar_producer(); \
4912 tmp[0] = htonl(HERMON_WQE_SGL_INLINE_MASK | (sz)); \
4913 }
4914
4915 #define HERMON_WQE_SET_CTRL_SEGMENT(desc, desc_sz, fence, \
4916 imm, sol, sig, cksum, qp, strong, fccrc) \
4917 { \
4918 uint32_t *tmp; \
4919 uint32_t cntr_tmp; \
4920 \
4921 /* do not set the first dword (owner/opcode) here */ \
4922 tmp = (uint32_t *)desc; \
4923 cntr_tmp = (fence << 6) | desc_sz; \
4924 tmp[1] = ntohl(cntr_tmp); \
4925 cntr_tmp = strong | fccrc | sol | sig | cksum; \
4926 tmp[2] = ntohl(cntr_tmp); \
4927 tmp[3] = ntohl(imm); \
4928 }
4929
4930 #define HERMON_WQE_SET_MLX_CTRL_SEGMENT(desc, desc_sz, sig, maxstat, \
4931 lid, qp, sl) \
4932 { \
4933 uint32_t *tmp; \
4934 uint32_t cntr_tmp; \
4935 \
4936 tmp = (uint32_t *)desc; \
4937 cntr_tmp = htonl(tmp[0]); \
4938 cntr_tmp &= 0x80000000; \
4939 cntr_tmp |= HERMON_WQE_SEND_NOPCODE_SEND; \
4940 tmp[0] = ntohl(cntr_tmp); \
4941 tmp[1] = ntohl(desc_sz); \
4942 cntr_tmp = (((maxstat << 4) | (sl & 0xff)) << 8) | sig; \
4943 if (qp->qp_is_special == HERMON_QP_SMI) \
4944 cntr_tmp |= (0x02 << 16); \
4945 if (lid == IB_LID_PERMISSIVE) \
4946 cntr_tmp |= (0x01 << 16); \
4947 tmp[2] = ntohl(cntr_tmp); \
4948 tmp[3] = ntohl((lid) << 16); \
4949 }
4950
4951 #define HERMON_WQE_BUILD_MLX_LRH(lrh, qp, udav, pktlen) \
4952 { \
4953 uint32_t *tmp; \
4954 uint32_t lrh_tmp; \
4955 \
4956 tmp = (uint32_t *)(void *)(lrh); \
4957 \
4958 if ((qp)->qp_is_special == HERMON_QP_SMI) { \
4959 lrh_tmp = HERMON_MLX_VL15_LVER; \
4960 } else { \
4961 lrh_tmp = HERMON_MLX_VL0_LVER | ((udav)->sl << 20); \
4962 } \
4963 if ((udav)->grh) { \
4964 lrh_tmp |= (IB_LRH_NEXT_HDR_GRH << 16); \
4965 } else { \
4966 lrh_tmp |= (IB_LRH_NEXT_HDR_BTH << 16); \
4967 } \
4968 lrh_tmp |= (udav)->rlid; \
4969 tmp[0] = htonl(lrh_tmp); \
4970 \
4971 lrh_tmp = (pktlen) << 16; \
4972 if ((udav)->rlid == IB_LID_PERMISSIVE) { \
4973 lrh_tmp |= IB_LID_PERMISSIVE; \
4974 } else { \
4975 lrh_tmp |= (udav)->ml_path; \
4976 } \
4977 tmp[1] = htonl(lrh_tmp); \
4978 }
4979
4980 /*
4981 * Note: The GRH payload length, calculated below, is the overall packet
4982 * length (in bytes) minus LRH header and GRH headers.
4983 *
4984 * Also note: Filling in the GIDs in the way we do below is helpful because
4985 * it avoids potential alignment restrictions and/or conflicts.
4986 */
4987 #define HERMON_WQE_BUILD_MLX_GRH(state, grh, qp, udav, pktlen) \
4988 { \
4989 uint32_t *tmp; \
4990 uint32_t grh_tmp; \
4991 ib_gid_t sgid; \
4992 \
4993 tmp = (uint32_t *)(grh); \
4994 \
4995 grh_tmp = HERMON_MLX_IPVER_TC_FLOW; \
4996 grh_tmp |= (udav)->tclass << HERMON_MLX_TC_SHIFT; \
4997 grh_tmp |= (udav)->flow_label; \
4998 tmp[0] = htonl(grh_tmp); \
4999 \
5000 grh_tmp = (((pktlen) << 2) - (sizeof (ib_lrh_hdr_t) + \
5001 sizeof (ib_grh_t))) << 16; \
5002 grh_tmp |= (IB_GRH_NEXT_HDR_BTH << 8); \
5003 grh_tmp |= (udav)->hop_limit; \
5004 tmp[1] = htonl(grh_tmp); \
5005 \
5006 sgid.gid_prefix = (state)->hs_sn_prefix[(qp)->qp_portnum]; \
5007 sgid.gid_guid = (state)->hs_guid[(qp)->qp_portnum] \
5008 [(udav)->mgid_index]; \
5009 bcopy(&sgid, &tmp[2], sizeof (ib_gid_t)); \
5010 bcopy(&(udav)->rgid_h, &tmp[6], sizeof (ib_gid_t)); \
5011 }
5012
5013 #define HERMON_WQE_BUILD_MLX_BTH(state, bth, qp, wr) \
5014 { \
5015 uint32_t *tmp; \
5016 uint32_t bth_tmp; \
5017 \
5018 tmp = (uint32_t *)(bth); \
5019 \
5020 bth_tmp = HERMON_MLX_UDSEND_OPCODE; \
5021 if ((wr)->wr_flags & IBT_WR_SEND_SOLICIT) { \
5022 bth_tmp |= (IB_BTH_SOLICITED_EVENT_MASK << 16); \
5023 } \
5024 if (qp->qp_is_special == HERMON_QP_SMI) { \
5025 bth_tmp |= HERMON_MLX_DEF_PKEY; \
5026 } else { \
5027 bth_tmp |= (state)->hs_pkey[(qp)->qp_portnum] \
5028 [(qp)->qp_pkeyindx]; \
5029 } \
5030 tmp[0] = htonl(bth_tmp); \
5031 tmp[1] = htonl((wr)->wr.ud.udwr_dest->ud_dst_qpn & \
5032 HERMON_MLX_DQPN_MASK); \
5033 tmp[2] = 0x0; \
5034 }
5035
5036 #define HERMON_WQE_BUILD_MLX_DETH(deth, qp) \
5037 { \
5038 uint32_t *tmp; \
5039 \
5040 tmp = (uint32_t *)(deth); \
5041 \
5042 if ((qp)->qp_is_special == HERMON_QP_SMI) { \
5043 tmp[0] = 0x0; \
5044 tmp[1] = 0x0; \
5045 } else { \
5046 tmp[0] = htonl(HERMON_MLX_GSI_QKEY); \
5047 tmp[1] = htonl(0x1); \
5048 } \
5049 }
5050
5051
5052 /*
5053 * Flash interface:
5054 * Below we have PCI config space space offsets for flash interface
5055 * access, offsets within Hermon CR space for accessing flash-specific
5056 * information or settings, masks used for flash settings, and
5057 * timeout values for flash operations.
5058 */
5059 #define HERMON_HW_FLASH_CFG_HWREV 8
5060 #define HERMON_HW_FLASH_CFG_ADDR 88
5061 #define HERMON_HW_FLASH_CFG_DATA 92
5062
5063 #define HERMON_HW_FLASH_RESET_AMD 0xF0
5064 #define HERMON_HW_FLASH_RESET_INTEL 0xFF
5065 #define HERMON_HW_FLASH_CPUMODE 0xF0150
5066 #define HERMON_HW_FLASH_ADDR 0xF01A4
5067 #define HERMON_HW_FLASH_DATA 0xF01A8
5068 #define HERMON_HW_FLASH_GPIO_SEMA 0xF03FC
5069 #define HERMON_HW_FLASH_WRCONF_SEMA 0xF0380
5070 #define HERMON_HW_FLASH_GPIO_DATA 0xF0040
5071 #define HERMON_HW_FLASH_GPIO_MOD1 0xF004C
5072 #define HERMON_HW_FLASH_GPIO_MOD0 0xF0050
5073 #define HERMON_HW_FLASH_GPIO_DATACLEAR 0xF00D4
5074 #define HERMON_HW_FLASH_GPIO_DATASET 0xF00DC
5075 #define HERMON_HW_FLASH_GPIO_LOCK 0xF0048
5076 #define HERMON_HW_FLASH_GPIO_UNLOCK_VAL 0xD42F
5077 #define HERMON_HW_FLASH_GPIO_PIN_ENABLE 0x1E000000
5078
5079 #define HERMON_HW_FLASH_CPU_MASK 0xC0000000
5080 #define HERMON_HW_FLASH_CPU_SHIFT 30
5081 #define HERMON_HW_FLASH_ADDR_MASK 0x0007FFFC
5082 #define HERMON_HW_FLASH_CMD_MASK 0xE0000000
5083 #define HERMON_HW_FLASH_BANK_MASK 0xFFF80000
5084
5085 #define HERMON_HW_FLASH_SPI_BUSY 0x40000000
5086 #define HERMON_HW_FLASH_SPI_WIP 0x01000000
5087 #define HERMON_HW_FLASH_SPI_READ_OP 0x00000001
5088 #define HERMON_HW_FLASH_SPI_USE_INSTR 0x00000040
5089 #define HERMON_HW_FLASH_SPI_NO_ADDR 0x00000020
5090 #define HERMON_HW_FLASH_SPI_NO_DATA 0x00000010
5091 #define HERMON_HW_FLASH_SPI_TRANS_SZ_4B 0x00000200
5092
5093 #define HERMON_HW_FLASH_SPI_SECTOR_ERASE 0xD8
5094 #define HERMON_HW_FLASH_SPI_READ 0x03
5095 #define HERMON_HW_FLASH_SPI_PAGE_PROGRAM 0x02
5096 #define HERMON_HW_FLASH_SPI_READ_STATUS_REG 0x05
5097 #define HERMON_HW_FLASH_SPI_WRITE_ENABLE 0x06
5098 #define HERMON_HW_FLASH_SPI_READ_ESIGNATURE 0xAB
5099
5100 #define HERMON_HW_FLASH_SPI_GW 0xF0400
5101 #define HERMON_HW_FLASH_SPI_ADDR 0xF0404
5102 #define HERMON_HW_FLASH_SPI_DATA 0xF0410
5103 #define HERMON_HW_FLASH_SPI_DATA4 0xF0414
5104 #define HERMON_HW_FLASH_SPI_DATA8 0xF0418
5105 #define HERMON_HW_FLASH_SPI_DATA12 0xF041C
5106 #define HERMON_HW_FLASH_SPI_ADDR_MASK 0x00FFFFFF
5107 #define HERMON_HW_FLASH_SPI_INSTR_PHASE_OFF 0x04
5108 #define HERMON_HW_FLASH_SPI_ADDR_PHASE_OFF 0x08
5109 #define HERMON_HW_FLASH_SPI_DATA_PHASE_OFF 0x10
5110 #define HERMON_HW_FLASH_SPI_ENABLE_OFF 0x2000
5111 #define HERMON_HW_FLASH_SPI_CS_OFF 0x800
5112 #define HERMON_HW_FLASH_SPI_INSTR_OFF 0x10000
5113 #define HERMON_HW_FLASH_SPI_INSTR_SHIFT 0x10
5114 #define HERMON_HW_FLASH_SPI_BOOT_ADDR_REG 0xF0000
5115
5116 #define HERMON_HW_FLASH_TIMEOUT_WRITE 300
5117 #define HERMON_HW_FLASH_TIMEOUT_ERASE 1000000
5118 #define HERMON_HW_FLASH_TIMEOUT_GPIO_SEMA 1000
5119 #define HERMON_HW_FLASH_TIMEOUT_CONFIG 50
5120
5121 #define HERMON_HW_FLASH_ICS_ERASE 0x20
5122 #define HERMON_HW_FLASH_ICS_ERROR 0x3E
5123 #define HERMON_HW_FLASH_ICS_WRITE 0x40
5124 #define HERMON_HW_FLASH_ICS_STATUS 0x70
5125 #define HERMON_HW_FLASH_ICS_READY 0x80
5126 #define HERMON_HW_FLASH_ICS_CONFIRM 0xD0
5127 #define HERMON_HW_FLASH_ICS_READ 0xFF
5128
5129 #ifdef __cplusplus
5130 }
5131 #endif
5132
5133 #endif /* _SYS_IB_ADAPTERS_HERMON_HW_H */
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