include/sys/lom_ebuscodes.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright 1999-2002 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 #ifndef _SYS_LOM_EBUSCODES_H
  28 #define _SYS_LOM_EBUSCODES_H
  29
  30 #pragma ident   "%Z%%M% %I%     %E% SMI"
  31
  32 /*
  33  * This file enumerates the virtual registers exported by the microcontroller.
  34  * It cannot be changed without also revising the firwmare.
  35  */
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #define EBUS_CMD_SPACE_GENERIC  0x00    /* generic space */
  42 #define EBUS_CMD_SPACE1         0x01    /* space 1 - console buffer or  */
  43                                         /* boot script                  */
  44 #define EBUS_CMD_SPACE2         0x02    /* space 2 - supply rail data */
  45 #define EBUS_CMD_SPACE3         0x03    /* space 3 - circuit breaker data */
  46 #define EBUS_CMD_SPACE4         0x04    /* space 4 - fan data */
  47 #define EBUS_CMD_SPACE5         0x05    /* space 5 - temp/otemp sensor data */
  48 #define EBUS_CMD_SPACE6         0x06    /* space 6 - phone-home config */
  49 #define EBUS_CMD_SPACE_PROGRAM  0x07    /* space 7 - send a program */
  50 #define EBUS_CMD_SPACE_EEPROM   0x08    /* space 8 - eeprom/event-log access */
  51 #define EBUS_CMD_SPACE_SELFTEST 0x09    /* space 9 - selftest control */
  52 #define EBUS_CMD_SPACE_LEDS     0x0a    /* space 10 - LED name access */
  53
  54 /*
  55  * Read only values
  56  */
  57 #define EBUS_IDX_FW_REV         0x01    /* Firmware Revision */
  58 #define EBUS_IDX_CHECK_HI       0x02    /* Firmware checksum high */
  59 #define EBUS_IDX_CHECK_LO       0x03    /* Firmware checksum low */
  60 #define EBUS_IDX_FAN1_SPEED     0x04    /* Fan 1 current speed % of max */
  61 #define EBUS_IDX_FAN2_SPEED     0x05    /* Fan 2 current speed % of max */
  62 #define EBUS_IDX_FAN3_SPEED     0x06    /* Fan 3 current speed % of max */
  63 #define EBUS_IDX_FAN4_SPEED     0x07    /* Fan 4 current speed % of max */
  64 #define EBUS_IDX_PSU1_STAT      0x08    /* PSU 1 status */
  65 #define EBUS_IDX_PSU2_STAT      0x09    /* PSU 2 status */
  66 #define EBUS_IDX_PSU3_STAT      0x0a    /* PSU 3 status */
  67 #define EBUS_IDX_STATE_CHNG     0x0b    /* State change flags */
  68 #define EBUS_IDX_GPIP           0x0c    /* General purpose inputs */
  69
  70 /* RESERVED                     0x0d    */
  71 /* RESERVED                     0x0e    */
  72 /* RESERVED                     0x0f    */
  73 #define EBUS_IDX_LOG_START_HI   0x10    /* MSB of start of eventlog in eeprom */
  74 #define EBUS_IDX_LOG_START_LO   0x11    /* LSB of start of eventlog in eeprom */
  75 #define EBUS_IDX_LOG_PTR_HI     0x12    /* MSB of current position in log */
  76 #define EBUS_IDX_LOG_PTR_LO     0x13    /* LSB of current position in log */
  77
  78 /*
  79  * We currently don't have a virtual register to indicate the end of the log.
  80  * We cannot assume the log runs to the end of the EEPROM because the EEPROM
  81  * is logically partitioned into a Log portion (first 8K) and then a FRUID
  82  * portion (next 8K).  For the moment we therefore need to use a hardcoded
  83  * value to represent the end of the event log.
  84  */
  85 #define EBUS_LOG_END            0x2000
  86
  87 #define EBUS_IDX_EEPROM_SIZE_KB 0x14    /* Size of eeprom in kilobytes */
  88 #define EBUS_IDX_UNREAD_EVENTS  0x15    /* Number of events (un)read by host */
  89 /* RESERVED                     0x16    */
  90 /* RESERVED                     0x17    */
  91
  92 #define EBUS_IDX_TEMP1          0x18    /* Temperature sensors */
  93 #define EBUS_IDX_TEMP2          0x19
  94 #define EBUS_IDX_TEMP3          0x1A
  95 #define EBUS_IDX_TEMP4          0x1B
  96 #define EBUS_IDX_TEMP5          0x1C
  97 #define EBUS_IDX_TEMP6          0x1D
  98 #define EBUS_IDX_TEMP7          0x1E
  99 #define EBUS_IDX_TEMP8          0x1F
 100
 101 #define EBUS_IDX_ALARMNEW       0x20
 102 #define EBUS_IDX_SUPPLY_LO      0x21    /* 1 bit per voltage line status */
 103 #define EBUS_IDX_SUPPLY_HI      0x22    /* whether faulty or not; 1=>faulty */
 104 #define EBUS_IDX_CBREAK_STATUS  0x23
 105 #define EBUS_IDX_OTEMP_STATUS   0x24
 106
 107 #define EBUS_IDX_LED1_STATUS    0x25
 108 #define EBUS_IDX_LED2_STATUS    0x26
 109 #define EBUS_IDX_LED3_STATUS    0x27
 110 #define EBUS_IDX_LED4_STATUS    0x28
 111 #define EBUS_IDX_LED5_STATUS    0x29
 112 #define EBUS_IDX_LED6_STATUS    0x2a
 113 #define EBUS_IDX_LED7_STATUS    0x2b
 114 #define EBUS_IDX_LED8_STATUS    0x2c
 115 /* RESERVED                     0x2d    */
 116
 117 #define EBUS_IDX_CPU_IDENT      0x2e
 118 #define EBUS_IDX_EVENT_DETAIL   0x2f
 119
 120 /*
 121  * Read/write access registers
 122  */
 123 #define EBUS_IDX_ALARM          0x30    /* Alarm control/status */
 124 #define EBUS_IDX_WDOG_CTRL      0x31    /* Watchdog control */
 125 #define EBUS_IDX_WDOG_TIME      0x32    /* Watchdog timeout */
 126
 127 #define EBUS_IDX_SER_BAUD       0x33
 128 #define EBUS_IDX_SER_CHARMODE   0x34
 129 #define EBUS_IDX_SER_FLOWCTL    0x35
 130 #define EBUS_IDX_SER_MODEMTYPE  0x36
 131 #define EBUS_IDX_EEPROM_PAGESEL 0x37
 132
 133 #define EBUS_IDX_HNAME_LENGTH   0x38
 134 #define EBUS_IDX_HNAME_CHAR     0x39
 135
 136 #define EBUS_IDX_CONFIG_MISC    0x3a    /* Host specific configuration */
 137
 138 #define EBUS_IDX_TIME0          0x3b
 139 #define EBUS_IDX_TIME1          0x3c
 140 #define EBUS_IDX_TIME2          0x3d
 141 #define EBUS_IDX_TIME3          0x3e
 142
 143 #define EBUS_IDX_ESCAPE         0x3f    /* Escape character, default '#' */
 144 #define EBUS_IDX_EVENT_CNT      0x40    /* Number of unread (via EBus) events */
 145
 146 #define EBUS_IDX_SELFTEST0      0x41
 147 #define EBUS_IDX_SELFTEST1      0x42
 148 #define EBUS_IDX_SELFTEST2      0x43
 149 #define EBUS_IDX_SELFTEST3      0x44
 150 #define EBUS_IDX_SELFTEST4      0x45
 151 #define EBUS_IDX_SELFTEST5      0x46
 152 #define EBUS_IDX_SELFTEST6      0x47
 153 #define EBUS_IDX_SELFTEST7      0x48
 154
 155 #define EBUS_IDX_ESCAPE_LEN     0x49
 156 #define EBUS_IDX_SER_TIMEOUT    0x4a
 157 #define EBUS_IDX_EVENT_FILTER   0x4b
 158 #define EBUS_IDX_POWERON_DELAY  0x4c
 159
 160 #define EBUS_IDX_BOOTMODE       0x4d    /* boot-mode for PROM */
 161
 162 #define EBUS_IDX_I2C_HOLDOFF    0x4e    /* hold off i2c bus while obp starts */
 163 /* RESERVED                     0x4f    */
 164
 165 #define EBUS_IDX_MODEL_ID1      0x50    /* Model identifier */
 166 #define EBUS_IDX_MODEL_ID2      0x51
 167 #define EBUS_IDX_MODEL_ID3      0x52
 168 #define EBUS_IDX_MODEL_ID4      0x53
 169 #define EBUS_IDX_MODEL_ID5      0x54
 170 #define EBUS_IDX_MODEL_ID6      0x55
 171 #define EBUS_IDX_MODEL_ID7      0x56
 172 #define EBUS_IDX_MODEL_ID8      0x57
 173 #define EBUS_IDX_MODEL_ID9      0x58
 174 #define EBUS_IDX_MODEL_ID10     0x59
 175 #define EBUS_IDX_MODEL_ID11     0x5a
 176 #define EBUS_IDX_MODEL_ID12     0x5b
 177 #define EBUS_IDX_MODEL_REV      0x5c    /* Model Revision */
 178
 179 #define EBUS_IDX_CONFIG         0x5d    /* Model specific configuration */
 180 #define EBUS_IDX_FAN1_CAL       0x5e    /* Fan 1 calibration value */
 181 #define EBUS_IDX_FAN2_CAL       0x5f    /* Fan 2 calibration value */
 182 #define EBUS_IDX_FAN3_CAL       0x60    /* Fan 3 calibration value */
 183 #define EBUS_IDX_FAN4_CAL       0x61    /* Fan 4 calibration value */
 184 #define EBUS_IDX_FAN1_LOW       0x62    /* Fan 1 low limit */
 185 #define EBUS_IDX_FAN2_LOW       0x63    /* Fan 2 low limit */
 186 #define EBUS_IDX_FAN3_LOW       0x64    /* Fan 3 low limit */
 187 #define EBUS_IDX_FAN4_LOW       0x65    /* Fan 4 low limit */
 188
 189 #define EBUS_IDX_CONFIG2        0x66    /* Model specific configuration */
 190 #define EBUS_IDX_CONFIG3        0x67    /* Model specific configuration */
 191
 192 #define EBUS_IDX_HOSTID1        0X68    /* Host ID, MSB */
 193 #define EBUS_IDX_HOSTID2        0X69    /* Host ID */
 194 #define EBUS_IDX_HOSTID3        0X6a    /* Host ID */
 195 #define EBUS_IDX_HOSTID4        0X6b    /* Host ID */
 196
 197 /* RESERVED                     0x6c    */
 198 /* RESERVED                     0x6d    */
 199 /* RESERVED                     0x6e    */
 200 /* RESERVED                     0x6f    */
 201 /* RESERVED                     0x70    */
 202 /* RESERVED                     0x71    */
 203 /* RESERVED                     0x72    */
 204 /* RESERVED                     0x73    */
 205 /* RESERVED                     0x74    */
 206 /* RESERVED                     0x75    */
 207 /* RESERVED                     0x76    */
 208 /* RESERVED                     0x77    */
 209 /* RESERVED                     0x78    */
 210 /* RESERVED                     0x79    */
 211 /* RESERVED                     0x7a    */
 212
 213 /*
 214  * Capability bits:
 215  *
 216  * Register starting from 0x7e and downward are used to describe various
 217  * capabilities that the LOM firmware has.  A capability is present if the
 218  * corresponding bit returns '1'.
 219  */
 220 #define EBUS_IDX_CAP2           0x7b    /* Capabilities - Read only */
 221 #define EBUS_IDX_CAP1           0x7c    /* Capabilities - Read only */
 222 #define EBUS_IDX_CAP0           0x7d    /* Capabilities - Read only */
 223
 224 #define EBUS_IDX_PROBE55        0x7e    /* Always returns 0x55 */
 225 #define EBUS_IDX_PROBEAA        0x7f    /* Always returns 0xaa */
 226
 227 #define EBUS_FIRST_READONLY     EBUS_IDX_FW_REV
 228 #define EBUS_LAST_READONLY      EBUS_IDX_EVENT_DETAIL
 229 #define EBUS_FIRST_MODELLOCKED  EBUS_IDX_MODEL_ID1
 230 #define EBUS_LAST_MODELLOCKED   EBUS_IDX_CONFIG3
 231
 232 /*
 233  * Register for special address spaces
 234  */
 235 #define EBUS_IDX1_CONS_BUF_START        0x00
 236 #define EBUS_IDX1_CONS_BUF_END          0xff
 237
 238 #define EBUS_IDX2_SUPPLY_ENABLE_MASK1   0x01
 239 #define EBUS_IDX2_SUPPLY_ENABLE_MASK2   0x02
 240 #define EBUS_IDX2_SUPPLY_FATAL_MASK1    0x03
 241 #define EBUS_IDX2_SUPPLY_FATAL_MASK2    0x04
 242 #define EBUS_IDX2_SUPPLY_FINE_TOL       0x05
 243 #define EBUS_IDX2_SUPPLY_GROSS_TOL      0x06
 244 #define EBUS_IDX2_SUPPLY_READING1       0x10
 245 #define EBUS_IDX2_SUPPLY_READING2       0x11
 246 #define EBUS_IDX2_SUPPLY_READING3       0x12
 247 #define EBUS_IDX2_SUPPLY_READING4       0x13
 248 #define EBUS_IDX2_SUPPLY_READING5       0x14
 249 #define EBUS_IDX2_SUPPLY_READING6       0x15
 250 #define EBUS_IDX2_SUPPLY_READING7       0x16
 251 #define EBUS_IDX2_SUPPLY_READING8       0x17
 252 #define EBUS_IDX2_SUPPLY_READING9       0x18
 253 #define EBUS_IDX2_SUPPLY_READING10      0x19
 254 #define EBUS_IDX2_SUPPLY_READING11      0x1a
 255 #define EBUS_IDX2_SUPPLY_READING12      0x1b
 256 #define EBUS_IDX2_SUPPLY_READING13      0x1c
 257 #define EBUS_IDX2_SUPPLY_READING14      0x1d
 258 #define EBUS_IDX2_SUPPLY_READING15      0x1e
 259 #define EBUS_IDX2_SUPPLY_READING16      0x1f
 260 #define EBUS_IDX2_SUPPLY_CAL1           0x20
 261 #define EBUS_IDX2_SUPPLY_CAL2           0x21
 262 #define EBUS_IDX2_SUPPLY_CAL3           0x22
 263 #define EBUS_IDX2_SUPPLY_CAL4           0x23
 264 #define EBUS_IDX2_SUPPLY_CAL5           0x24
 265 #define EBUS_IDX2_SUPPLY_CAL6           0x25
 266 #define EBUS_IDX2_SUPPLY_CAL7           0x26
 267 #define EBUS_IDX2_SUPPLY_CAL8           0x27
 268 #define EBUS_IDX2_SUPPLY_CAL9           0x28
 269 #define EBUS_IDX2_SUPPLY_CAL10          0x29
 270 #define EBUS_IDX2_SUPPLY_CAL11          0x2a
 271 #define EBUS_IDX2_SUPPLY_CAL12          0x2b
 272 #define EBUS_IDX2_SUPPLY_CAL13          0x2c
 273 #define EBUS_IDX2_SUPPLY_CAL14          0x2d
 274 #define EBUS_IDX2_SUPPLY_CAL15          0x2e
 275 #define EBUS_IDX2_SUPPLY_CAL16          0x2f
 276 #define EBUS_IDX2_SUPPLY_NAME_START     0x40
 277 #define EBUS_IDX2_SUPPLY_NAME_END       0xff
 278
 279 #define EBUS_IDX3_BREAKER_ENABLE_MASK   0x01
 280 #define EBUS_IDX3_BREAKER_NAME_START    0x40
 281 #define EBUS_IDX3_BREAKER_NAME_END      0xff
 282
 283 #define EBUS_IDX4_TEMP_ENABLE_MASK      0x01
 284 #define EBUS_IDX4_OTEMP_ENABLE_MASK     0x02
 285 #define EBUS_IDX4_TEMP_FATAL_MASK       0x03
 286 #define EBUS_IDX4_OTEMP_FATAL_MASK      0x04
 287 #define EBUS_IDX4_TEMP_HYSTERESIS       0x05
 288 #define EBUS_IDX4_TEMP_FAN_LINK_MASK    0x06
 289 #define EBUS_IDX4_TEMP_WARN1            0x10    /* Temp warning levels */
 290 #define EBUS_IDX4_TEMP_WARN2            0x11
 291 #define EBUS_IDX4_TEMP_WARN3            0x12
 292 #define EBUS_IDX4_TEMP_WARN4            0x13
 293 #define EBUS_IDX4_TEMP_WARN5            0x14
 294 #define EBUS_IDX4_TEMP_WARN6            0x15
 295 #define EBUS_IDX4_TEMP_WARN7            0x16
 296 #define EBUS_IDX4_TEMP_WARN8            0x17
 297 #define EBUS_IDX4_TEMP_SDOWN1           0x18    /* Temp shutdown levels */
 298 #define EBUS_IDX4_TEMP_SDOWN2           0x19
 299 #define EBUS_IDX4_TEMP_SDOWN3           0x1a
 300 #define EBUS_IDX4_TEMP_SDOWN4           0x1b
 301 #define EBUS_IDX4_TEMP_SDOWN5           0x1c
 302 #define EBUS_IDX4_TEMP_SDOWN6           0x1d
 303 #define EBUS_IDX4_TEMP_SDOWN7           0x1e
 304 #define EBUS_IDX4_TEMP_SDOWN8           0x1f
 305 #define EBUS_IDX4_TEMP_CORRECT1         0x20    /* Temp warning levels */
 306 #define EBUS_IDX4_TEMP_CORRECT2         0x21
 307 #define EBUS_IDX4_TEMP_CORRECT3         0x22
 308 #define EBUS_IDX4_TEMP_CORRECT4         0x23
 309 #define EBUS_IDX4_TEMP_CORRECT5         0x24
 310 #define EBUS_IDX4_TEMP_CORRECT6         0x25
 311 #define EBUS_IDX4_TEMP_CORRECT7         0x26
 312 #define EBUS_IDX4_TEMP_CORRECT8         0x27
 313 #define EBUS_IDX4_TEMP_NAME_START       0x40
 314 #define EBUS_IDX4_TEMP_NAME_END         0xff
 315
 316 #define EBUS_IDX5_FAN_ENABLE_CONFIG     0x01
 317 #define EBUS_IDX5_FAN_NAME_START        0x40
 318 #define EBUS_IDX5_FAN_NAME_END          0xff
 319
 320 #define EBUS_IDX10_LED_NAME_START       0x40
 321 #define EBUS_IDX10_LED_NAME_END         0xff
 322
 323 /*
 324  * This arrangement for CPU signatures allows only one CPU to generate a
 325  * CPU Signature at a time.  Since the signature won't fit into one byte
 326  * it is recommended to datafill the MSB, LSB, STATE, SUBSTATE first, and
 327  * then write the ID.  A one byte ID limits the number of CPUs to 255.
 328  * CPU 255 is handled specially; it denotes that the signature applies to
 329  * "all", or rather "any" CPU ID.
 330  */
 331
 332 #define EBUS_ANY_CPU_ID         255
 333
 334 #define EBUS_IDX11_CPU_ID       0x01    /* CPU with signature pending */
 335 #define EBUS_IDX11_CPU_SIG_MSB  0x02    /* MSB of sig */
 336 #define EBUS_IDX11_CPU_SIG_LSB  0x03    /* LSB of sig */
 337 #define EBUS_IDX11_CPU_STATE    0x04    /* state of sig */
 338 #define EBUS_IDX11_CPU_SUBSTATE 0x05    /* sub-state of sig */
 339
 340 /*
 341  * OBP-defined reset reasons.  Solaris never generates these.
 342  */
 343 #define EBUS_IDX11_HOST_RESET_REASON    0x07
 344 #define RESET_REASON_HOST       0x01    /* host reset itself */
 345 #define RESET_REASON_LOM        0x02    /* lom CLI or SSP request */
 346 #define RESET_REASON_ASR        0x04    /* watchdog or cpusig timeout */
 347
 348 /*
 349  * I2C Transfers can be done using the BSC as a proxy.  We transfer data at
 350  * the conceptual level of struct i2c_transfer defined by the i2c services
 351  * framework in Solaris.
 352  */
 353
 354 /*
 355  * TRANSFER_TYPE mirrors the i2c_transfer.i2c_flags used in Solaris i2c
 356  * services framework.
 357  */
 358 #define EBUS_I2C_WR             0x01 /* write */
 359 #define EBUS_I2C_RD             0x02 /* read */
 360 #define EBUS_I2C_WR_RD          0x04 /* write then read */
 361
 362 /*
 363  * RESULT mirrors the i2c_transfer.i2c_result used the Solaris i2c services
 364  * framework.
 365  */
 366 #define EBUS_I2C_SUCCESS                0x00
 367 #define EBUS_I2C_FAILURE                0xFF
 368 #define EBUS_I2C_INCOMPLETE             0xFE
 369
 370
 371 #define EBUS_IDX12_MAX_TRANSFER_SZ      0x01
 372 #define EBUS_IDX12_BUS_ADDRESS          0x02
 373 #define EBUS_IDX12_CLIENT_ADDRESS       0x03
 374 #define EBUS_IDX12_WR_RD_BOUNDARY       0x04
 375 #define EBUS_IDX12_TRANSFER_TYPE        0x05
 376 #define EBUS_IDX12_RESIDUAL_DATA        0x06
 377 #define EBUS_IDX12_DATA_INOUT           0x07
 378 #define EBUS_IDX12_RESULT               0x08
 379
 380 #define EBUS_IDX12_TRANSACTION_LOCK     0x09    /* 1=> lock out i2c devices  */
 381                                                 /* so multi i2c transactions */
 382                                                 /* can complete atomically   */
 383
 384 #define EBUS_PROGRAM_PCSR                       0x01
 385 #define EBUS_PROGRAM_PCR_RSVD                   0x00
 386 #define EBUS_PROGRAM_PCR_READ                   0x02
 387 #define EBUS_PROGRAM_PCR_PRGMODE_ON             0x03
 388 #define EBUS_PROGRAM_PCR_ERASE                  0x04
 389 #define EBUS_PROGRAM_PCR_PROGRAM                0x05
 390 #define EBUS_PROGRAM_PCR_PRSVD                  0x06
 391 #define EBUS_PROGRAM_PCR_PRGMODE_OFF            0x07
 392 #define EBUS_PROGRAM_PCR_PROGOFF_JUMPTOADDR     0x08
 393 #define EBUS_PROGRAM_PSR_SUCCESS                0x00
 394 #define EBUS_PROGRAM_PSR_PROGRAM_FAIL           0x01
 395 #define EBUS_PROGRAM_PSR_ERASE_FAIL             0x02
 396 #define EBUS_PROGRAM_PSR_INVALID_AREA           0x03
 397 #define EBUS_PROGRAM_PSR_INCORRECT_CSUM         0x04
 398 #define EBUS_PROGRAM_PSR_INCORRECT_COUNT        0x05
 399 #define EBUS_PROGRAM_PSR_INVALID_OPERATION      0x06
 400 #define EBUS_PROGRAM_PSR_STATUS_MASK            0x7f
 401 #define EBUS_PROGRAM_PSR_PROG_MODE              0x80
 402 #define EBUS_PROGRAM_DATA                       0x02
 403 #define EBUS_PROGRAM_PCSM0                      0x03 /* MSB of checksum data */
 404 #define EBUS_PROGRAM_PCSM1                      0x04
 405 #define EBUS_PROGRAM_PADR0                      0x05 /* MSB of addr */
 406 #define EBUS_PROGRAM_PADR1                      0x06
 407 #define EBUS_PROGRAM_PADR2                      0x07
 408 #define EBUS_PROGRAM_PADR3                      0x08
 409 #define EBUS_PROGRAM_PSIZ0                      0x09 /* MSB of size */
 410 #define EBUS_PROGRAM_PSIZ1                      0x0a
 411 #define EBUS_PROGRAM_PSIZ2                      0x0b
 412 #define EBUS_PROGRAM_PSIZ3                      0x0c
 413 #define EBUS_PROGRAM_PAGE0                      0x0d /* MSB of ROM page size */
 414 #define EBUS_PROGRAM_PAGE1                      0x0e
 415 #define EBUS_PROGRAM_PAGE2                      0x0f
 416 #define EBUS_PROGRAM_PAGE3                      0x10
 417
 418 /*
 419  * Command register and codes
 420  */
 421
 422 #define EBUS_IDX_CMD_RES        0x00    /* Command/Result register */
 423 #define EBUS_CMD_CODE_CHK       'C'     /* Recheck alarm conditions */
 424 #define EBUS_CMD_CODE_CLR       'E'     /* Clear event log */
 425 #define EBUS_CMD_UNLOCK1        'M'     /* Model Unlock step 1 */
 426 #define EBUS_CMD_UNLOCK2        'u'     /* Model Unlock step 2 */
 427 #define EBUS_CMD_POWERINGOFF    'P'     /* host sends before powering off */
 428 #define EBUS_CMD_RESETTING      'R'     /* host sends before resetting self */
 429 #define EBUS_CMD_CONLOG_ON      'F'
 430 #define EBUS_CMD_CONLOG_OFF     'D'
 431 #define EBUS_CMD_INTERRUPTS_ON  'i'
 432 #define EBUS_CMD_INTERRUPTS_OFF 'I'
 433 #define EBUS_CMD_DOG_PAT        'W'      /* Host pats it's watchdog */
 434 #define EBUS_CMD_PROG_START     'z'
 435
 436
 437 /*
 438  * space 11 - CPU signatures and OBP reset information.
 439  */
 440 #define EBUS_CMD_SPACE_CPUSIG   0x0b
 441 #define EBUS_CMD_SPACE_I2C      0x0c    /* space 12 - I2C transfers */
 442 #define EBUS_CMD_SPACE13        0x0d
 443 #define EBUS_CMD_SPACE14        0x0e
 444 #define EBUS_CMD_SPACE15        0x0f
 445
 446 #define EBUS_MAX_ADDRESS_SPACES 64  /* as defined by the protocol elsewhere */
 447
 448 /*
 449  * Number of unread events flag
 450  */
 451 #define EBUS_EVENT_CNT_CLEAR    0x80    /* Event log cleared since last read */
 452
 453 /*
 454  * Prom boot mode parameters
 455  */
 456 #define EBUS_BOOTMODE_FORCE_CONSOLE     0x01
 457 #define EBUS_BOOTMODE_FORCE_NOBOOT      0x02
 458 #define EBUS_BOOTMODE_RESET_DEFAULT     0x04
 459 #define EBUS_BOOTMODE_FULLDIAG          0x08
 460 #define EBUS_BOOTMODE_SKIPDIAG          0x10
 461
 462 /*
 463  * Configuration register
 464  */
 465 #define EBUS_CONFIG_NFAN_DEC(n) (((n)>>5)&0x7)  /* Extract no. of fans */
 466 #define EBUS_CONFIG_NFAN_ENC(n) (((n)&0x7)<<5)  /* Insert no. of fans */
 467 #define EBUS_CONFIG_NPSU_DEC(n) (((n)>>3)&0x3)  /* Extract no. of PSUs */
 468 #define EBUS_CONFIG_NPSU_ENC(n) (((n)&0x3)<<3)  /* Insert no. of PSUs */
 469 #define EBUS_CONFIG_TTY_CON     0x04    /* Set if TTY/LOM switchable */
 470 #define EBUS_CONFIG_STEADY_LED  0x02    /* Set to stop LED flashing */
 471 #define EBUS_CONFIG_USER_LOG    0x01    /* log user operations */
 472
 473 /*
 474  * Configuration register 2
 475  */
 476 #define EBUS_CONFIG2_NTEMP_DEC(n)       (((n)>>4)&0xf)
 477 #define EBUS_CONFIG2_NTEMP_ENC(n)       (((n)&0xf)<<4)
 478 #define EBUS_CONFIG2_NSUPPLY_DEC(n)     ((n)&0xf)
 479 #define EBUS_CONFIG2_NSUPPLY_ENC(n)     ((n)&0xf)
 480
 481 /*
 482  * Configuration register 3
 483  */
 484 #define EBUS_CONFIG3_NOTEMP_DEC(n)      (((n)>>4)&0xf)
 485 #define EBUS_CONFIG3_NOTEMP_ENC(n)      (((n)&0xf)<<4)
 486 #define EBUS_CONFIG3_NBREAKERS_DEC(n)   ((n)&0xf)
 487 #define EBUS_CONFIG3_NBREAKERS_ENC(n)   ((n)&0xf)
 488
 489 /*
 490  * Miscellaneous host configuration register
 491  */
 492 #define EBUS_CONFIG_MISC_PSUIPFAILEVENTS        0x80
 493 #define EBUS_CONFIG_MISC_DELAYED_STARTUP        0x40
 494 #define EBUS_CONFIG_MISC_RANDOM_DELAY           0x20
 495 #define EBUS_CONFIG_MISC_DECLINE_STARTUP        0x10
 496 #define EBUS_CONFIG_MISC_ALARM0_ENABLED         0x08
 497 #define EBUS_CONFIG_MISC_PHONEHOME_ENABLED      0x04
 498 #define EBUS_CONFIG_MISC_SECURITY_ENABLED       0x02
 499 #define EBUS_CONFIG_MISC_AUTO_CONSOLE           0x01
 500
 501 /*
 502  * Alarm control/status register
 503  */
 504 #define EBUS_ALARM_LED_DEC(n)   (((n)>>4)&0xf)  /* Extract LED Hz */
 505 #define EBUS_ALARM_LED_ENC(n)   (((n)&0xf)<<4)  /* Insert LED Hz */
 506 #define EBUS_ALARM_NOEVENTS     0x08    /* No serial event reports */
 507 #define EBUS_ALARM_ENABLE3      0x04    /* Alarm 3 enable */
 508 #define EBUS_ALARM_ENABLE2      0x02    /* Alarm 2 enable */
 509 #define EBUS_ALARM_ENABLE1      0x01    /* Alarm 1 enable */
 510
 511 /*
 512  * General Channel Watchdog control
 513  */
 514 #define EBUS_WDOG_BREAK_DISABLE 0x10    /* Set if wdog disabled if break seen */
 515 #define EBUS_WDOG_AL3_FANPSU    0x08    /* Set if fan/PSU errors set AL3 */
 516 #define EBUS_WDOG_AL3_WDOG      0x04    /* Set if wdog timeouts set AL3 */
 517 #define EBUS_WDOG_RST           0x02    /* Reset host on expiry */
 518 #define EBUS_WDOG_ENABLE        0x01    /* Enable host WDOG */
 519
 520 /*
 521  * Watchdog channel non-blocking byte
 522  * Top nibble command, bottom nibble data
 523  */
 524 #define EBUS_WDOG_NB_PAT                0x00
 525 #define EBUS_WDOG_NB_PAT_SEQ_MASK       0x0F    /* Sequence number */
 526 #define EBUS_WDOG_NB_CFG                0x10
 527 #define EBUS_WDOG_NB_CFG_ENB            0x01    /* enable/disable wdog */
 528
 529 /*
 530  * PSU status
 531  */
 532 #define EBUS_PSU_INPUTA         0x01    /* Input A OK */
 533 #define EBUS_PSU_INPUTB         0x02    /* Input B OK */
 534 #define EBUS_PSU_OUTPUT         0x04    /* Output OK */
 535 #define EBUS_PSU_PRESENT        0x08    /* PSU is present */
 536 #define EBUS_PSU_STANDBY        0x10    /* PSU is in standby */
 537
 538 /*
 539  * State change flags
 540  */
 541 #define EBUS_STATE_TEMPERATURE  0x80    /* a temperature was exceeded */
 542 #define EBUS_STATE_RAIL         0x40    /* a supply rail failed */
 543 #define EBUS_STATE_EVENT        0x20    /* An event has been logged */
 544 #define EBUS_STATE_CB           0x10    /* A circuit breaker failed */
 545 #define EBUS_STATE_GP           0x08    /* A GP input has changed */
 546 #define EBUS_STATE_PSU          0x04    /* A PSU state has changed */
 547 #define EBUS_STATE_FAN          0x02    /* A fan speed has changed */
 548
 549
 550 /*
 551  * Bit-0 is overloaded.  It is used by the BSC to notify of a status change
 552  * The detail field will then be one of EBUS_DETAIL_XXXX.  Otherwise, it's used
 553  * to indicate that an Alarm state has changed.  The detail field would then
 554  * be the alarm number.
 555  */
 556 #define EBUS_STATE_ALARM        0x01    /* An alarm state has changed */
 557 #define EBUS_STATE_NOTIFY       0x01    /* BSC state changes */
 558
 559 /*
 560  * State Notify detail values
 561  */
 562 #define EBUS_DETAIL_FLASH       0xff    /* CSSP going to program BSC */
 563 #define EBUS_DETAIL_RESET       0xfe    /* BSC has been reset */
 564
 565 #define EBUS_STATE_MASK         0xff    /* All state changes */
 566
 567 /*
 568  * Alarm config bytes for register $20
 569  */
 570 #define ALARM_0                 0x01
 571 #define ALARM_0_ENABLE          0x02
 572
 573 /*
 574  * Phone home configuration information
 575  */
 576 #define PHONEHOME_CONFIG_REG            0x01
 577 #define PHONEHOME_SCRIPT_START_REG      0x02
 578
 579 #define PHONEHOME_CONFIG_ON_UNXPOWEROFF 0x01
 580 #define PHONEHOME_CONFIG_ON_WATCHDOGTRG 0x02
 581 #define PHONEHOME_CONFIG_ON_DEMAND      0x04
 582
 583 /*
 584  * CPU type ident codes.  This determines the programming mode.
 585  */
 586 #define CPU_IDENT_UNKNOWN               0x80
 587 #define CPU_IDENT_H8_3434               0x81
 588 #define CPU_IDENT_H8_3436               0x82
 589 #define CPU_IDENT_H8_3437               0x83
 590 #define CPU_IDENT_H8_3437SF             0x84
 591 #define CPU_IDENT_H8S_2148              0x85
 592 #define CPU_IDENT_H8S_2148A             0x86
 593 #define CPU_IDENT_H8S_BSC               0x87
 594
 595 /*
 596  * Capability codes
 597  */
 598 #define EBUS_CAP0_ASYNC_DOG             0x01 /* EBUS_CMD_DOGPAT implemented */
 599 #define EBUS_CAP0_SYNC_EVENTS           0x02 /* event report at command end */
 600 #define EBUS_CAP0_NEW_EVENTLOG_SPACE    0x04 /* new implementation of space8 */
 601 #define EBUS_CAP0_NEW_SELFTESTS         0x08 /* new implementation of tests */
 602 #define EBUS_CAP0_NEW_PROGRAMMING       0x10 /* new flash programming scheme */
 603 #define EBUS_CAP0_LED_INFORMATION       0x20 /* new LED modelling scheme */
 604 #define EBUS_CAP0_CPU_SIG               0x40 /* understands CPU signatures */
 605 #define EBUS_CAP0_I2C_PROXY             0x80 /* implements i2c proxy service */
 606 #define EBUS_CAP1_H8_SETS_IDX_TIME      0x01 /* H8 writes IDX_TIME values */
 607 #define EBUS_CAP1_SPACE1_IS_BOOTSCRIPT  0x02 /* SPACE1 used for Boot Script */
 608 #define EBUS_CAP1_FRUID_OFFSET          0x04 /* i2c reads are already offset */
 609
 610 /*  Error codes as returned via the EBUS interface */
 611
 612 #define EBUS_ERROR_NONE         0   /* no error occured */
 613 #define EBUS_ERROR_NOREAD       1   /* this register cannot be read */
 614 #define EBUS_ERROR_NOWRITE      2   /* this register cannot be written */
 615 #define EBUS_ERROR_PROTO_CMD    3   /* command sent unexpected */
 616 #define EBUS_ERROR_PROTO_DATA   4   /* data sent unexpected */
 617 #define EBUS_ERROR_INVALID_BIT  5   /* invalid bit was set in data passed */
 618 #define EBUS_ERROR_VALUE_BAD    6   /* data passed was plain bad */
 619 #define EBUS_ERROR_NOX_SPECCMD  7   /* no such special command exists */
 620 #define EBUS_ERROR_NOTUNLOCKED  8   /* need model-lock unlocked to do this */
 621 #define EBUS_ERROR_TIMEOUT      9   /* too long between cmd and data */
 622 #define EBUS_ERROR_DEVICEFAIL   10  /* Some device (e.g. eeprom) didn't work */
 623 #define EBUS_ERROR_STALEDATA    11  /* Data has changed - host must reread */
 624 #define EBUS_ERROR_NOX_DEVICE   12  /* Device doesn't exist */
 625 #define EBUS_ERROR_RESETNEEDED  13  /* host must reset the LOM */
 626 #define EBUS_ERROR_PROTO_PARAM  14  /* incorrect parameter count for command */
 627 #define EBUS_ERROR_PROTO_SEQ    15  /* Sequence number from host incorrect */
 628 #define EBUS_ERROR_IN_PROG_MODE 16  /* not supported in programming mode */
 629 #define EBUS_ERROR_NOT_PROG_MODE 17 /* must be in prog mode first */
 630
 631 /* Magic values for specific registers. */
 632 #define LOM_TEMP_MAX_VALUE              0x7c
 633 #define LOM_TEMP_STATE_INACCESSIBLE     0x7d /* can't tell - i2c faulted */
 634 #define LOM_TEMP_STATE_STANDBY          0x7e /* standby mode */
 635 #define LOM_TEMP_STATE_NOT_PRESENT      0x7f /* not fitted/present */
 636
 637 #define LOM_FAN_MAX_SPEED       0xfb    /* protects folllowing special cases */
 638 #define LOM_FAN_RECOUNT         0xfc    /* last access failed */
 639 #define LOM_FAN_NOACCESS        0xfd    /* can't tell - i2c/lm80 faulted */
 640 #define LOM_FAN_STANDBY         0xfe    /* standby mode */
 641 #define LOM_FAN_NOT_PRESENT     0xff    /* no fan fitted */
 642
 643 #ifdef __cplusplus
 644 }
 645 #endif
 646
 647 #endif /* _SYS_LOM_EBUSCODES_H */