include/sys/mpt/mpi_cnfg.h

   1 /*
   2  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
   3  * Use is subject to license terms.
   4  */
   5
   6 #ifndef _SYS_MPI_CNFG_H
   7 #define _SYS_MPI_CNFG_H
   8
   9 #ifdef  __cplusplus
  10 extern "C" {
  11 #endif
  12
  13 /*
  14  * Config Message and Structures
  15  */
  16 typedef struct config_page_header {
  17         uint8_t         PageVersion;
  18         uint8_t         PageLength;
  19         uint8_t         PageNumber;
  20         uint8_t         PageType;
  21 } config_page_header_t;
  22
  23 typedef union config_page_header_union {
  24         config_page_header_t    Struct;
  25         uint8_t                 Bytes[4];
  26         uint16_t                Word16[2];
  27         uint32_t                Word32;
  28 } config_page_header_union_t;
  29
  30 /*
  31  * The extended header is used for 1064 and on
  32  */
  33 typedef struct config_extended_page_header {
  34         uint8_t                 PageVersion;
  35         uint8_t                 Reserved1;
  36         uint8_t                 PageNumber;
  37         uint8_t                 PageType;
  38         uint16_t                ExtPageLength;
  39         uint8_t                 ExtPageType;
  40         uint8_t                 Reserved2;
  41 } config_extended_page_header_t;
  42
  43 /*
  44  * PageType field values
  45  */
  46 #define MPI_CONFIG_PAGEATTR_READ_ONLY           0x00
  47 #define MPI_CONFIG_PAGEATTR_CHANGEABLE          0x10
  48 #define MPI_CONFIG_PAGEATTR_PERSISTENT          0x20
  49 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT       0x30
  50 #define MPI_CONFIG_PAGEATTR_MASK                0xF0
  51
  52 #define MPI_CONFIG_PAGETYPE_IO_UNIT             0x00
  53 #define MPI_CONFIG_PAGETYPE_IOC                 0x01
  54 #define MPI_CONFIG_PAGETYPE_BIOS                0x02
  55 #define MPI_CONFIG_PAGETYPE_SCSI_PORT           0x03
  56 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE         0x04
  57 #define MPI_CONFIG_PAGETYPE_FC_PORT             0x05
  58 #define MPI_CONFIG_PAGETYPE_FC_DEVICE           0x06
  59 #define MPI_CONFIG_PAGETYPE_LAN                 0x07
  60 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME         0x08
  61 #define MPI_CONFIG_PAGETYPE_MANUFACTURING       0x09
  62 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK       0x0A
  63 #define MPI_CONFIG_PAGETYPE_INBAND              0x0B
  64 #define MPI_CONFIG_PAGETYPE_EXTENDED            0x0F
  65 #define MPI_CONFIG_PAGETYPE_MASK                0x0F
  66
  67 #define MPI_CONFIG_TYPENUM_MASK                 0x0FFF
  68
  69 /*
  70  * ExtPageType field values
  71  */
  72 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT      0x10
  73 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER     0x11
  74 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE       0x12
  75 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY          0x13
  76
  77 /*
  78  * Page Address field values
  79  */
  80 #define MPI_SCSI_PORT_PGAD_PORT_MASK            0x000000FF
  81
  82 #define MPI_SCSI_DEVICE_TARGET_ID_MASK          0x000000FF
  83 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT         0
  84 #define MPI_SCSI_DEVICE_BUS_MASK                0x0000FF00
  85 #define MPI_SCSI_DEVICE_BUS_SHIFT               8
  86
  87 #define MPI_FC_PORT_PGAD_PORT_MASK              0xF0000000
  88 #define MPI_FC_PORT_PGAD_PORT_SHIFT             28
  89 #define MPI_FC_PORT_PGAD_FORM_MASK              0x0F000000
  90 #define MPI_FC_PORT_PGAD_FORM_INDEX             0x01000000
  91 #define MPI_FC_PORT_PGAD_INDEX_MASK             0x0000FFFF
  92 #define MPI_FC_PORT_PGAD_INDEX_SHIFT            0
  93
  94 #define MPI_FC_DEVICE_PGAD_PORT_MASK            0xF0000000
  95 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT           28
  96 #define MPI_FC_DEVICE_PGAD_FORM_MASK            0x0F000000
  97 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID        0x00000000
  98 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK         0xF0000000
  99 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT        28
 100 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK          0x00FFFFFF
 101 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT         0
 102 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID         0x01000000
 103 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK          0x0000FF00
 104 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT         8
 105 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK          0x000000FF
 106 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT         0
 107
 108 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK      0x000000FF
 109 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT     0
 110
 111 #define MPI_SAS_EXPAND_PGAD_FORM_MASK                   0xF0000000
 112 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT                  28
 113 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE        0x00000000
 114 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM         0x00000001
 115 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE                 0x00000002
 116 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE             0x0000FFFF
 117 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE            0
 118 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY                0x00FF0000
 119 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY               16
 120 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE             0x0000FFFF
 121 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE            0
 122 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE               0x0000FFFF
 123 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE              0
 124
 125 #define MPI_SAS_DEVICE_PGAD_FORM_MASK                   0xF0000000
 126 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT                  28
 127 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE        0x00000000
 128 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID          0x00000001
 129 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE                 0x00000002
 130 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK             0x0000FFFF
 131 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT            0
 132 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK                 0x0000FF00
 133 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT                8
 134 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK                 0x000000FF
 135 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT                0
 136 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK               0x0000FFFF
 137 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT              0
 138
 139 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK                0x000000FF
 140 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT               0
 141
 142 /*
 143  * Config Message
 144  */
 145 typedef struct msg_config {
 146         uint8_t                 Action;
 147         uint8_t                 Reserved;
 148         uint8_t                 ChainOffset;
 149         uint8_t                 Function;
 150         uint16_t                ExtPageLength; /* 1064 only */
 151         uint8_t                 ExtPageType; /* 1064 only */
 152         uint8_t                 MsgFlags;
 153         uint32_t                MsgContext;
 154         uint8_t                 Reserved2[8];
 155         config_page_header_t    Header;
 156         uint32_t                PageAddress;
 157         sge_io_union_t          PageBufferSGE;
 158 } msg_config_t;
 159
 160 /*
 161  * Action field values
 162  */
 163 #define MPI_CONFIG_ACTION_PAGE_HEADER           0x00
 164 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT     0x01
 165 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT    0x02
 166 #define MPI_CONFIG_ACTION_PAGE_DEFAULT          0x03
 167 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM      0x04
 168 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT     0x05
 169 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM       0x06
 170
 171 /*
 172  * Config Reply Message
 173  */
 174 typedef struct msg_config_reply {
 175         uint8_t                 Action;
 176         uint8_t                 Reserved;
 177         uint8_t                 MsgLength;
 178         uint8_t                 Function;
 179         uint16_t                ExtPageLength;
 180         uint8_t                 ExtPageType;
 181         uint8_t                 MsgFlags;
 182         uint32_t                MsgContext;
 183         uint8_t                 Reserved2[2];
 184         uint16_t                IOCStatus;
 185         uint32_t                IOCLogInfo;
 186         config_page_header_t    Header;
 187 } msg_config_reply_t;
 188
 189 /*
 190  * Manufacturing Config pages
 191  */
 192 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC      0x1000
 193 #define MPI_MANUFACTPAGE_DEVICEID_FC909         0x0621
 194 #define MPI_MANUFACTPAGE_DEVICEID_FC919         0x0624
 195 #define MPI_MANUFACTPAGE_DEVICEID_FC929         0x0622
 196 #define MPI_MANUFACTPAGE_DEVICEID_FC919X        0x0628
 197 #define MPI_MANUFACTPAGE_DEVICEID_FC929X        0x0626
 198 #define MPI_MANUFACTPAGE_DEVID_53C1030          0x0030
 199 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC        0x0031
 200 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035     0x0032
 201 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035   0x0033
 202 #define MPI_MANUFACTPAGE_DEVID_53C1035          0x0040
 203 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC        0x0041
 204 #define MPI_MANUFACTPAGE_DEVID_SAS1064          0x0050
 205
 206 typedef struct config_page_manufacturing_0 {
 207         config_page_header_t    Header;
 208         uint8_t                 ChipName[16];
 209         uint8_t                 ChipRevision[8];
 210         uint8_t                 BoardName[16];
 211         uint8_t                 BoardAssembly[16];
 212         uint8_t                 BoardTracerNumber[16];
 213 } config_page_manufacturing_0_t;
 214
 215 #define MPI_MANUFACTURING0_PAGEVERSION          0x00
 216
 217 typedef struct config_page_manufacturing_1 {
 218         config_page_header_t    Header;
 219         uint8_t                 VPD[256];
 220 } config_page_manufacturing_1_t;
 221
 222 #define MPI_MANUFACTURING1_PAGEVERSION          0x00
 223
 224 typedef struct mpi_chip_revision_id {
 225         uint16_t                DeviceID;
 226         uint8_t                 PCIRevisionID;
 227         uint8_t                 Reserved;
 228 } mpi_chip_revision_id_t;
 229
 230 /*
 231  * Host code (drivers, BIOS, utilities, etc.) should leave this
 232  * define set to one and check Header.PageLength at runtime.
 233  */
 234 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
 235 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS        1
 236 #endif
 237
 238 typedef struct config_page_manufacturing_2 {
 239         config_page_header_t    Header;
 240         mpi_chip_revision_id_t  ChipId;
 241         uint32_t                HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];
 242 } config_page_manufacturing_2_t;
 243
 244 #define MPI_MANUFACTURING2_PAGEVERSION          0x00
 245
 246 /*
 247  * Host code (drivers, BIOS, utilities, etc.) should leave this
 248  * define set to one and check Header.PageLength at runtime.
 249  */
 250 #ifndef MPI_MAN_PAGE_3_INFO_WORDS
 251 #define MPI_MAN_PAGE_3_INFO_WORDS               1
 252 #endif
 253
 254 typedef struct config_page_manufacturing_3 {
 255         config_page_header_t    Header;
 256         mpi_chip_revision_id_t  ChipId;
 257         uint32_t                Info[MPI_MAN_PAGE_3_INFO_WORDS];
 258 } config_page_manufacturing_3_t;
 259
 260 #define MPI_MANUFACTURING3_PAGEVERSION          0x00
 261
 262 typedef struct config_page_manufacturing_4 {
 263         config_page_header_t    Header;
 264         uint32_t                Reserved1;
 265         uint8_t                 InfoOffset0;
 266         uint8_t                 InfoSize0;
 267         uint8_t                 InfoOffset1;
 268         uint8_t                 InfoSize1;
 269         uint8_t                 InquirySize;
 270         uint8_t                 Flags;
 271         uint16_t                Reserved2;
 272         uint8_t                 InquiryData[56];
 273         uint32_t                ISVolumeSettings;
 274         uint32_t                IMEVolumeSettings;
 275         uint32_t                IMVolumeSettings;
 276 } config_page_manufacturing_4_t;
 277
 278 #define MPI_MANUFACTURING4_PAGEVERSION          0x01
 279 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA         0x01
 280
 281 typedef struct config_page_manufacturing_5 {
 282         config_page_header_t    Header;
 283         uint64_t                BaseWWID;
 284 } config_page_manufacturing_5_t;
 285
 286 #define MPI_MANUFACTURING5_PAGEVERSION          0x00
 287
 288 typedef struct config_page_manufacturing_6 {
 289         config_page_header_t    Header;
 290         uint32_t                ProductSpecificInfo;
 291 } config_page_manufacturing_6_t;
 292
 293 #define MPI_MANUFACTURING6_PAGEVERSION          0x00
 294
 295 /*
 296  * IO Unit Config Pages
 297  */
 298 typedef struct config_page_io_unit_0 {
 299         config_page_header_t    Header;
 300         uint64_t                UniqueValue;
 301 } config_page_io_unit_0_t;
 302
 303 #define MPI_IOUNITPAGE0_PAGEVERSION             0x00
 304
 305 typedef struct config_page_io_unit_1 {
 306         config_page_header_t    Header;
 307         uint32_t                Flags;
 308 } config_page_io_unit_1_t;
 309
 310 #define MPI_IOUNITPAGE1_PAGEVERSION             0x01
 311
 312 #define MPI_IOUNITPAGE1_MULTI_FUNCTION                  0x00000000
 313 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION                 0x00000001
 314 #define MPI_IOUNITPAGE1_MULTI_PATHING                   0x00000002
 315 #define MPI_IOUNITPAGE1_SINGLE_PATHING                  0x00000000
 316 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID         0x00000004
 317 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING     0x00000020
 318 #define MPI_IOUNITPAGE1_DISABLE_IR                      0x00000040
 319 #define MPI_IOUNITPAGE1_FORCE_32                        0x00000080
 320 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE        0x00000100
 321
 322 typedef struct mpi_adapter_info {
 323         uint8_t                 PciBusNumber;
 324         uint8_t                 PciDeviceAndFunctionNumber;
 325         uint16_t                AdapterFlags;
 326 } mpi_adapter_info_t;
 327
 328 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED         0x0001
 329 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS      0x0002
 330
 331 typedef struct config_page_io_unit_2 {
 332         config_page_header_t    Header;
 333         uint32_t                Flags;
 334         uint32_t                BiosVersion;
 335         mpi_adapter_info_t      AdapterOrder[4];
 336 } config_page_io_unit_2_t;
 337
 338 #define MPI_IOUNITPAGE2_PAGEVERSION             0x00
 339
 340 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR    0x00000002
 341 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE    0x00000004
 342 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE 0x00000008
 343 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40  0x00000010
 344
 345 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK     0x000000E0
 346 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY     0x00000000
 347 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY           0x00000020
 348 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY       0x00000040
 349
 350 /*
 351  * Host code (drivers, BIOS, utilities, etc.) should leave this
 352  * define set to one and check Header.PageLength at runtime.
 353  */
 354 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
 355 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX         1
 356 #endif
 357
 358 typedef struct config_page_io_unit_3 {
 359         config_page_header_t    Header;
 360         uint8_t                 GPIOCount;
 361         uint8_t                 Reserved1;
 362         uint16_t                Reserved2;
 363         uint16_t                GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX];
 364 } config_page_io_unit_3_t;
 365
 366 #define MPI_IOUNITPAGE3_PAGEVERSION             0x01
 367
 368 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK      0xFC
 369 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT     2
 370 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF        0x00
 371 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON         0x01
 372
 373 /*
 374  * IOC Config Pages
 375  */
 376 typedef struct config_page_ioc_0 {
 377         config_page_header_t    Header;
 378         uint32_t                TotalNVStore;
 379         uint32_t                FreeNVStore;
 380         uint16_t                VendorID;
 381         uint16_t                DeviceID;
 382         uint8_t                 RevisionID;
 383         uint8_t                 Reserved[3];
 384         uint32_t                ClassCode;
 385         uint16_t                SubsystemVendorID;
 386         uint16_t                SubsystemID;
 387 } config_page_ioc_0_t;
 388
 389 #define MPI_IOCPAGE0_PAGEVERSION                0x01
 390
 391 typedef struct config_page_ioc_1 {
 392         config_page_header_t    Header;
 393         uint32_t                Flags;
 394         uint32_t                CoalescingTimeout;
 395         uint8_t                 CoalescingDepth;
 396         uint8_t                 PCISlotNum;
 397         uint8_t                 Reserved[2];
 398 } config_page_ioc_1_t;
 399
 400 #define MPI_IOCPAGE1_PAGEVERSION                0x01
 401 #define MPI_IOCPAGE1_EEDP_HOST_SUPPORTS_DIF     0x08000000
 402 #define MPI_IOCPAGE1_EEDP_MODE_MASK             0x07000000
 403 #define MPI_IOCPAGE1_EEDP_MODE_OFF              0x00000000
 404 #define MPI_IOCPAGE1_EEDP_MODE_T10              0x01000000
 405 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1            0x02000000
 406 #define MPI_IOCPAGE1_EEDP_MODE_LSI_2            0x03000000
 407 #define MPI_IOCPAGE1_REPLY_COALESCING           0x00000001
 408 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN         0xFF
 409
 410 typedef struct config_page_ioc_2_raid_vol {
 411         uint8_t                 VolumeID;
 412         uint8_t                 VolumeBus;
 413         uint8_t                 VolumeIOC;
 414         uint8_t                 VolumePageNumber;
 415         uint8_t                 VolumeType;
 416         uint8_t                 Flags;
 417         uint16_t                Reserved3;
 418 } config_page_ioc_2_raid_vol_t;
 419
 420 #define MPI_RAID_VOL_TYPE_IS                    0x00
 421 #define MPI_RAID_VOL_TYPE_IME                   0x01
 422 #define MPI_RAID_VOL_TYPE_IM                    0x02
 423 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE       0x08
 424
 425 /*
 426  * Host code (drivers, BIOS, utilities, etc.) should leave this
 427  * define set to one and check Header.PageLength at runtime.
 428  */
 429 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
 430 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX          1
 431 #endif
 432
 433 typedef struct config_page_ioc_2 {
 434         config_page_header_t    Header;
 435         uint32_t                CapabilitiesFlags;
 436         uint8_t                 NumActiveVolumes;
 437         uint8_t                 MaxVolumes;
 438         uint8_t                 NumActivePhysDisks;
 439         uint8_t                 MaxPhysDisks;
 440         config_page_ioc_2_raid_vol_t RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];
 441 } config_page_ioc_2_t;
 442
 443 #define MPI_IOCPAGE2_PAGEVERSION                0x02
 444
 445 /*
 446  * IOC Page 2 Capabilities flags
 447  */
 448 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT       0x00000001
 449 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT      0x00000002
 450 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT       0x00000004
 451 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT      0x20000000
 452 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT    0x40000000
 453 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT 0x80000000
 454 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING   0x10000000
 455
 456 typedef struct ioc_3_phys_disk {
 457         uint8_t                 PhysDiskID;
 458         uint8_t                 PhysDiskBus;
 459         uint8_t                 PhysDiskIOC;
 460         uint8_t                 PhysDiskNum;
 461 } ioc_3_phys_disk_t;
 462
 463 /*
 464  * Host code (drivers, BIOS, utilities, etc.) should leave this
 465  * define set to one and check Header.PageLength at runtime.
 466  */
 467 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
 468 #define MPI_IOC_PAGE_3_PHYSDISK_MAX             1
 469 #endif
 470
 471 typedef struct config_page_ioc_3 {
 472         config_page_header_t    Header;
 473         uint8_t                 NumPhysDisks;
 474         uint8_t                 Reserved1;
 475         uint16_t                Reserved2;
 476         ioc_3_phys_disk_t       PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX];
 477 } config_page_ioc_3_t;
 478
 479 #define MPI_IOCPAGE3_PAGEVERSION                0x00
 480
 481 typedef struct ioc_4_sep {
 482         uint8_t                 SEPTargetID;
 483         uint8_t                 SEPBus;
 484         uint16_t                Reserved;
 485 } ioc_4_sep_t;
 486
 487 /*
 488  * Host code (drivers, BIOS, utilities, etc.) should leave this
 489  * define set to one and check Header.PageLength at runtime.
 490  */
 491 #ifndef MPI_IOC_PAGE_4_SEP_MAX
 492 #define MPI_IOC_PAGE_4_SEP_MAX                  1
 493 #endif
 494
 495 typedef struct config_page_ioc_4 {
 496         config_page_header_t    Header;
 497         uint8_t                 ActiveSEP;
 498         uint8_t                 MaxSEP;
 499         uint16_t                Reserved1;
 500         ioc_4_sep_t             SEP[MPI_IOC_PAGE_4_SEP_MAX];
 501 } config_page_ioc_4_t;
 502
 503 #define MPI_IOCPAGE4_PAGEVERSION                0x00
 504
 505 /*
 506  * SCSI Port Config Pages
 507  */
 508 typedef struct config_page_scsi_port_0 {
 509         config_page_header_t    Header;
 510         uint32_t                Capabilities;
 511         uint32_t                PhysicalInterface;
 512 } config_page_scsi_port_0_t;
 513
 514 #define MPI_SCSIPORTPAGE0_PAGEVERSION                   0x01
 515
 516 /*
 517  * Capabilities
 518  */
 519 #define MPI_SCSIPORTPAGE0_CAP_IU                        0x00000001
 520 #define MPI_SCSIPORTPAGE0_CAP_DT                        0x00000002
 521 #define MPI_SCSIPORTPAGE0_CAP_QAS                       0x00000004
 522 #define MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS          0x00000008
 523 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK      0x0000FF00
 524 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK      0x00FF0000
 525 #define MPI_SCSIPORTPAGE0_CAP_WIDE                      0x20000000
 526 #define MPI_SCSIPORTPAGE0_CAP_AIP                       0x80000000
 527
 528 /*
 529  * Physical Interface
 530  */
 531 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK          0x00000003
 532 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD                0x01
 533 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE                 0x02
 534 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD                0x03
 535
 536 typedef struct config_page_scsi_port_1 {
 537         config_page_header_t    Header;
 538         uint32_t                Configuration;
 539         uint32_t                OnBusTimerValue;
 540 } config_page_scsi_port_1_t;
 541
 542 #define MPI_SCSIPORTPAGE1_PAGEVERSION                   0x02
 543
 544 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK         0x000000FF
 545 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK     0xFFFF0000
 546
 547 typedef struct mpi_device_info {
 548         uint8_t                 Timeout;
 549         uint8_t                 SyncFactor;
 550         uint16_t                DeviceFlags;
 551 } mpi_device_info_t;
 552
 553 typedef struct config_page_scsi_port_2 {
 554         config_page_header_t    Header;
 555         uint32_t                PortFlags;
 556         uint32_t                PortSettings;
 557         mpi_device_info_t       DeviceSettings[16];
 558 } config_page_scsi_port_2_t;
 559
 560 #define MPI_SCSIPORTPAGE2_PAGEVERSION                   0x01
 561
 562 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW   0x00000001
 563 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET   0x00000004
 564 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS      0x00000008
 565 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE 0x00000010
 566
 567 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK             0x0000000F
 568 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA            0x00000030
 569 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA         0x00000000
 570 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA            0x00000010
 571 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA              0x00000020
 572 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA         0x00000030
 573 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA          0x000000C0
 574 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK        0x00000F00
 575 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS 0x00003000
 576 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS     0x00000000
 577 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS     0x00001000
 578 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS      0x00003000
 579
 580 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE      0x0001
 581 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE         0x0002
 582 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE        0x0004
 583 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE       0x0008
 584 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE           0x0010
 585 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE            0x0020
 586
 587 /*
 588  * SCSI Target Device Config Pages
 589  */
 590 typedef struct config_page_scsi_device_0 {
 591         config_page_header_t    Header;
 592         uint32_t                NegotiatedParameters;
 593         uint32_t                Information;
 594 } config_page_scsi_device_0_t;
 595
 596 #define MPI_SCSIDEVPAGE0_PAGEVERSION                    0x02
 597
 598 #define MPI_SCSIDEVPAGE0_NP_IU                          0x00000001
 599 #define MPI_SCSIDEVPAGE0_NP_DT                          0x00000002
 600 #define MPI_SCSIDEVPAGE0_NP_QAS                         0x00000004
 601 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK        0x0000FF00
 602 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK        0x00FF0000
 603 #define MPI_SCSIDEVPAGE0_NP_WIDE                        0x20000000
 604 #define MPI_SCSIDEVPAGE0_NP_AIP                         0x80000000
 605 #define MPI_SCSIDEVPAGE0_NP_IDP                         0x08000000
 606
 607 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED         0x00000001
 608 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED             0x00000002
 609 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED             0x00000004
 610 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED              0x00000008
 611
 612 typedef struct config_page_scsi_device_1 {
 613         config_page_header_t    Header;
 614         uint32_t                RequestedParameters;
 615         uint32_t                Reserved;
 616         uint32_t                Configuration;
 617 } config_page_scsi_device_1_t;
 618
 619 #define MPI_SCSIDEVPAGE1_PAGEVERSION                    0x03
 620
 621 #define MPI_SCSIDEVPAGE1_RP_IU                          0x00000001
 622 #define MPI_SCSIDEVPAGE1_RP_DT                          0x00000002
 623 #define MPI_SCSIDEVPAGE1_RP_QAS                         0x00000004
 624 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK        0x0000FF00
 625 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK        0x00FF0000
 626 #define MPI_SCSIDEVPAGE1_RP_WIDE                        0x20000000
 627 #define MPI_SCSIDEVPAGE1_RP_AIP                         0x80000000
 628 #define MPI_SCSIDEVPAGE1_RP_IDP                         0x08000000
 629
 630 #define MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK     0x00000003
 631 #define MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK           0x00000300
 632
 633 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED           0x00000002
 634 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED           0x00000004
 635
 636 typedef struct config_page_scsi_device_2 {
 637         config_page_header_t    Header;
 638         uint32_t                DomainValidation;
 639         uint32_t                ParityPipeSelect;
 640         uint32_t                DataPipeSelect;
 641 } config_page_scsi_device_2_t;
 642
 643 #define MPI_SCSIDEVPAGE2_PAGEVERSION                    0x00
 644
 645 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE                  0x00000010
 646 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE     0x00000020
 647 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL              0x00000380
 648 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL         0x00001C00
 649 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL       0x0000E000
 650 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST                    0x10000000
 651 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST                    0x20000000
 652 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT                    0x40000000
 653 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT                    0x80000000
 654
 655 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK                   0x00000003
 656
 657 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK       0x00000003
 658 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK       0x0000000C
 659 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK       0x00000030
 660 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK       0x000000C0
 661 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK       0x00000300
 662 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK       0x00000C00
 663 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK       0x00003000
 664 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK       0x0000C000
 665 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK       0x00030000
 666 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK       0x000C0000
 667 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK      0x00300000
 668 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK      0x00C00000
 669 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK      0x03000000
 670 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK      0x0C000000
 671 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK      0x30000000
 672 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK      0xC0000000
 673
 674 /*
 675  * FC Port Config Pages
 676  */
 677 typedef struct config_page_fc_port_0 {
 678         config_page_header_t    Header;
 679         uint32_t                Flags;
 680         uint8_t                 MPIPortNumber;
 681         uint8_t                 Reserved[3];
 682         uint32_t                PortIdentifier;
 683         uint64_t                WWNN;
 684         uint64_t                WWPN;
 685         uint32_t                SupportedServiceClass;
 686         uint32_t                SupportedSpeeds;
 687         uint32_t                CurrentSpeed;
 688         uint32_t                MaxFrameSize;
 689         uint64_t                FabricWWNN;
 690         uint64_t                FabricWWPN;
 691         uint32_t                DiscoveredPortsCount;
 692         uint32_t                MaxInitiators;
 693 } config_page_fc_port_0_t;
 694
 695 #define MPI_FCPORTPAGE0_PAGEVERSION                     0x01
 696
 697 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK                 0x0000000F
 698 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT \
 699                                         MPI_PORTFACTS_PROTOCOL_INITIATOR
 700 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG \
 701                                         MPI_PORTFACTS_PROTOCOL_TARGET
 702 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN \
 703                                         MPI_PORTFACTS_PROTOCOL_LAN
 704 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR \
 705                                         MPI_PORTFACTS_PROTOCOL_LOGBUSADDR
 706
 707 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED      0x00000010
 708 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED       0x00000020
 709 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID          0x00000030
 710
 711 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK          0x00000F00
 712 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT            0x00000000
 713 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT     0x00000100
 714 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP       0x00000200
 715 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT      0x00000400
 716 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP        0x00000800
 717
 718 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK          0x00000F00
 719 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT            0x00000000
 720 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT     0x00000100
 721 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP       0x00000200
 722 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT      0x00000400
 723 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP        0x00000800
 724
 725 #define MPI_FCPORTPAGE0_LTYPE_RESERVED                  0x00
 726 #define MPI_FCPORTPAGE0_LTYPE_OTHER                     0x01
 727 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN                   0x02
 728 #define MPI_FCPORTPAGE0_LTYPE_COPPER                    0x03
 729 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300               0x04
 730 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500               0x05
 731 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI            0x06
 732 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI              0x07
 733 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI            0x08
 734 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI              0x09
 735 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE           0x0A
 736 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE          0x0B
 737 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE          0x0C
 738 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE            0x0D
 739 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE            0x0E
 740 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE            0x0F
 741
 742 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN               0x01
 743 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE                0x02
 744 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE               0x03
 745 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED              0x04
 746 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST              0x05
 747 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN              0x06
 748 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR                 0x07
 749 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK              0x08
 750
 751 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1                 0x00000001
 752 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2                 0x00000002
 753 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3                 0x00000004
 754
 755 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED             0x00000001
 756 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED             0x00000002
 757 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED            0x00000004
 758
 759 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT \
 760                         MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
 761 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT \
 762                         MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
 763 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT \
 764                         MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
 765
 766 typedef struct config_page_fc_port_1 {
 767         config_page_header_t    Header;
 768         uint32_t                Flags;
 769         uint64_t                NoSEEPROMWWNN;
 770         uint64_t                NoSEEPROMWWPN;
 771         uint8_t                 HardALPA;
 772         uint8_t                 LinkConfig;
 773         uint8_t                 TopologyConfig;
 774         uint8_t                 Reserved;
 775 } config_page_fc_port_1_t;
 776
 777 #define MPI_FCPORTPAGE1_PAGEVERSION                     0x02
 778
 779 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN         0x08000000
 780 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY     0x04000000
 781 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID               0x00000001
 782 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN               0x00000000
 783
 784 /*
 785  *  Flags used for programming protocol modes in NVStore
 786  */
 787 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK                 0xF0000000
 788 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT                28
 789 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT \
 790         ((uint32_t)MPI_PORTFACTS_PROTOCOL_INITIATOR << \
 791                 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
 792 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG \
 793         ((uint32_t)MPI_PORTFACTS_PROTOCOL_TARGET << \
 794                 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
 795 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN \
 796         ((uint32_t)MPI_PORTFACTS_PROTOCOL_LAN << \
 797                 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
 798 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR \
 799         ((uint32_t)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << \
 800                 MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
 801
 802 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED              0xFF
 803
 804 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK              0x0F
 805 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG              0x00
 806 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG              0x01
 807 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG              0x02
 808 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG             0x03
 809 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO              0x0F
 810
 811 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK                   0x0F
 812 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT                 0x01
 813 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT                  0x02
 814 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO                   0x0F
 815
 816 typedef struct config_page_fc_port_2 {
 817         config_page_header_t    Header;
 818         uint8_t                 NumberActive;
 819         uint8_t                 ALPA[127];
 820 } config_page_fc_port_2_t;
 821
 822 #define MPI_FCPORTPAGE2_PAGEVERSION                     0x01
 823
 824 typedef struct wwn_format {
 825         uint64_t                WWNN;
 826         uint64_t                WWPN;
 827 } wwn_format_t;
 828
 829 typedef union fc_port_persistent_physical_id {
 830         wwn_format_t            WWN;
 831         uint32_t                Did;
 832 } fc_port_persistent_physical_id_t;
 833
 834 typedef struct fc_port_persistent {
 835         fc_port_persistent_physical_id_t PhysicalIdentifier;
 836         uint8_t                 TargetID;
 837         uint8_t                 Bus;
 838         uint16_t                Flags;
 839 } fc_port_persistent_t;
 840
 841 #define MPI_PERSISTENT_FLAGS_SHIFT                      16
 842 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID                0x0001
 843 #define MPI_PERSISTENT_FLAGS_SCAN_ID                    0x0002
 844 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS                  0x0004
 845 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE                0x0008
 846 #define MPI_PERSISTENT_FLAGS_BY_DID                     0x0080
 847
 848 /*
 849  * Host code (drivers, BIOS, utilities, etc.) should leave this
 850  * define set to one and check Header.PageLength at runtime.
 851  */
 852 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
 853 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX                    1
 854 #endif
 855
 856 typedef struct config_page_fc_port_3 {
 857         config_page_header_t    Header;
 858         fc_port_persistent_t    Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX];
 859 } config_page_fc_port_3_t;
 860
 861 #define MPI_FCPORTPAGE3_PAGEVERSION                     0x01
 862
 863 typedef struct config_page_fc_port_4 {
 864         config_page_header_t    Header;
 865         uint32_t                PortFlags;
 866         uint32_t                PortSettings;
 867 } config_page_fc_port_4_t;
 868
 869 #define MPI_FCPORTPAGE4_PAGEVERSION                     0x00
 870
 871 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS        0x00000008
 872
 873 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA              0x00000030
 874 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA           0x00000000
 875 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA              0x00000010
 876 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA                0x00000020
 877 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA           0x00000030
 878 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA            0x000000C0
 879 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK          0x00000F00
 880
 881 typedef struct config_page_fc_port_5_alias_info {
 882         uint8_t                 Flags;
 883         uint8_t                 AliasAlpa;
 884         uint16_t                Reserved;
 885         uint64_t                AliasWWNN;
 886         uint64_t                AliasWWPN;
 887 } config_page_fc_port_5_alias_info_t;
 888
 889 /*
 890  * Host code (drivers, BIOS, utilities, etc.) should leave this
 891  * define set to one and check Header.PageLength at runtime.
 892  */
 893 #ifndef MPI_FC_PORT_PAGE_5_ALIAS_MAX
 894 #define MPI_FC_PORT_PAGE_5_ALIAS_MAX                    1
 895 #endif
 896
 897 typedef struct config_page_fc_port_5 {
 898         config_page_header_t    Header;
 899         config_page_fc_port_5_alias_info_t
 900                         AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX];
 901 } config_page_fc_port_5_t;
 902
 903 #define MPI_FCPORTPAGE5_PAGEVERSION                     0x00
 904
 905 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID          0x01
 906 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID           0x02
 907
 908 typedef struct config_page_fc_port_6 {
 909         config_page_header_t    Header;
 910         uint32_t                Reserved;
 911         uint64_t                TimeSinceReset;
 912         uint64_t                TxFrames;
 913         uint64_t                RxFrames;
 914         uint64_t                TxWords;
 915         uint64_t                RxWords;
 916         uint64_t                LipCount;
 917         uint64_t                NosCount;
 918         uint64_t                ErrorFrames;
 919         uint64_t                DumpedFrames;
 920         uint64_t                LinkFailureCount;
 921         uint64_t                LossOfSyncCount;
 922         uint64_t                LossOfSignalCount;
 923         uint64_t                PrimativeSeqErrCount;
 924         uint64_t                InvalidTxWordCount;
 925         uint64_t                InvalidCrcCount;
 926         uint64_t                FcpInitiatorIoCount;
 927 } config_page_fc_port_6_t;
 928
 929 #define MPI_FCPORTPAGE6_PAGEVERSION                     0x00
 930
 931 typedef struct config_page_fc_port_7 {
 932         config_page_header_t    Header;
 933         uint32_t                Reserved;
 934         uint8_t                 PortSymbolicName[256];
 935 } config_page_fc_port_7_t;
 936
 937 #define MPI_FCPORTPAGE7_PAGEVERSION                     0x00
 938
 939 typedef struct config_page_fc_port_8 {
 940         config_page_header_t    Header;
 941         uint32_t                BitVector[8];
 942 } config_page_fc_port_8_t;
 943
 944 #define MPI_FCPORTPAGE8_PAGEVERSION                     0x00
 945
 946 typedef struct config_page_fc_port_9 {
 947         config_page_header_t    Header;
 948         uint32_t                Reserved;
 949         uint64_t                GlobalWWPN;
 950         uint64_t                GlobalWWNN;
 951         uint32_t                UnitType;
 952         uint32_t                PhysicalPortNumber;
 953         uint32_t                NumAttachedNodes;
 954         uint16_t                IPVersion;
 955         uint16_t                UDPPortNumber;
 956         uint8_t                 IPAddress[16];
 957         uint16_t                Reserved1;
 958         uint16_t                TopologyDiscoveryFlags;
 959 } config_page_fc_port_9_t;
 960
 961 #define MPI_FCPORTPAGE9_PAGEVERSION                     0x00
 962
 963 /*
 964  * FC Device Config Pages
 965  */
 966 typedef struct config_page_fc_device_0 {
 967         config_page_header_t    Header;
 968         uint64_t                WWNN;
 969         uint64_t                WWPN;
 970         uint32_t                PortIdentifier;
 971         uint8_t                 Protocol;
 972         uint8_t                 Flags;
 973         uint16_t                BBCredit;
 974         uint16_t                MaxRxFrameSize;
 975         uint8_t                 Reserved1;
 976         uint8_t                 PortNumber;
 977         uint8_t                 FcPhLowestVersion;
 978         uint8_t                 FcPhHighestVersion;
 979         uint8_t                 CurrentTargetID;
 980         uint8_t                 CurrentBus;
 981 } config_page_fc_device_0_t;
 982
 983 #define MPI_FC_DEVICE_PAGE_0_PAGEVERSION                0x02
 984
 985 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID    0x01
 986
 987 #define MPI_FC_DEVICE_PAGE_0_PROT_IP                    0x01
 988 #define MPI_FC_DEVICE_PAGE_0_PROT_FCP_TARGET            0x02
 989 #define MPI_FC_DEVICE_PAGE_0_PROT_FCP_INITIATOR         0x04
 990
 991 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK \
 992                         (MPI_FC_DEVICE_PGAD_PORT_MASK)
 993 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK \
 994                         (MPI_FC_DEVICE_PGAD_FORM_MASK)
 995 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID \
 996                         (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
 997 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID \
 998                         (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
 999 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK \
1000                         (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
1001 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK \
1002                         (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
1003 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT \
1004                         (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
1005 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK \
1006                         (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
1007
1008 /*
1009  *  RAID Volume Config Pages
1010  */
1011 typedef struct raid_vol0_phys_disk {
1012         uint16_t                Reserved;
1013         uint8_t                 PhysDiskMap;
1014         uint8_t                 PhysDiskNum;
1015 } raid_vol0_phys_disk_t;
1016
1017 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY                   0x01
1018 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY                 0x02
1019
1020 typedef struct raid_vol0_status {
1021         uint8_t                 Flags;
1022         uint8_t                 State;
1023         uint16_t                Reserved;
1024 } raid_vol0_status_t;
1025
1026 /*
1027  * RAID Volume Page 0 VolumeStatus defines
1028  */
1029 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED                0x01
1030 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED               0x02
1031 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS     0x04
1032 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE        0x08
1033
1034 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL               0x00
1035 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED              0x01
1036 #define MPI_RAIDVOL0_STATUS_STATE_FAILED                0x02
1037 #define MPI_RAIDVOL0_STATUS_STATE_MISSING               0x03
1038
1039 typedef struct raid_vol0_settings {
1040         uint16_t                Settings;
1041         uint8_t                 HotSparePool;
1042         uint8_t                 Reserved;
1043 } raid_vol0_settings_t;
1044
1045 /*
1046  * RAID Volume Page 0 VolumeSettings defines
1047  */
1048 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE       0x0001
1049 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART           0x0002
1050 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE             0x0004
1051 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC            0x0008
1052 #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE         0x00C0
1053 #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE         0x0000
1054 #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE        0x0040
1055 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX      0x0010
1056 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS               0x8000
1057
1058 /*
1059  * RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk
1060  */
1061 #define MPI_RAID_HOT_SPARE_POOL_0                       0x01
1062 #define MPI_RAID_HOT_SPARE_POOL_1                       0x02
1063 #define MPI_RAID_HOT_SPARE_POOL_2                       0x04
1064 #define MPI_RAID_HOT_SPARE_POOL_3                       0x08
1065 #define MPI_RAID_HOT_SPARE_POOL_4                       0x10
1066 #define MPI_RAID_HOT_SPARE_POOL_5                       0x20
1067 #define MPI_RAID_HOT_SPARE_POOL_6                       0x40
1068 #define MPI_RAID_HOT_SPARE_POOL_7                       0x80
1069
1070 /*
1071  * Host code (drivers, BIOS, utilities, etc.) should leave this
1072  * define set to one and check Header.PageLength at runtime.
1073  */
1074 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
1075 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX                1
1076 #endif
1077
1078 typedef struct config_page_raid_vol_0 {
1079         config_page_header_t    Header;
1080         uint8_t                 VolumeID;
1081         uint8_t                 VolumeBus;
1082         uint8_t                 VolumeIOC;
1083         uint8_t                 VolumeType;
1084         raid_vol0_status_t      VolumeStatus;
1085         raid_vol0_settings_t    VolumeSettings;
1086         uint32_t                MaxLBA;
1087         uint32_t                MaxLBAHigh;
1088         uint32_t                StripeSize;
1089         uint32_t                Reserved2;
1090         uint32_t                Reserved3;
1091         uint8_t                 NumPhysDisks;
1092         uint8_t                 Reserved4;
1093         uint8_t                 ResyncRate;
1094         uint8_t                 Reserved5;
1095         raid_vol0_phys_disk_t   PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];
1096 } config_page_raid_vol_0_t;
1097
1098 #define MPI_RAIDVOLPAGE0_PAGEVERSION                    0x00
1099
1100 typedef struct config_page_raid_vol_1
1101 {
1102         config_page_header_t    Header;         /* 00h */
1103         uint8_t                 VolumeID;       /* 04h */
1104         uint8_t                 VolumeBus;      /* 05h */
1105         uint8_t                 VolumeIOC;      /* 06h */
1106         uint8_t                 Reserved0;      /* 07h */
1107         uint8_t                 GUID[24];       /* 08h */
1108         uint8_t                 Name[32];       /* 20h */
1109         uint64_t                WWID;           /* 40h */
1110         uint8_t                 Reserved1;      /* 48h */
1111         uint8_t                 Reserved2;      /* 4Ch */
1112 } config_page_raid_vol_1_t;
1113
1114 #define MPI_RAIDVOLPAGE1_PAGEVERSION                    0x01
1115
1116 /*
1117  * RAID Physical Disk Config Pages
1118  */
1119 typedef struct raid_phys_disk0_error_data {
1120         uint8_t                 ErrorCdbByte;
1121         uint8_t                 ErrorSenseKey;
1122         uint16_t                Reserved;
1123         uint16_t                ErrorCount;
1124         uint8_t                 ErrorASC;
1125         uint8_t                 ErrorASCQ;
1126         uint16_t                SmartCount;
1127         uint8_t                 SmartASC;
1128         uint8_t                 SmartASCQ;
1129 } raid_phys_disk0_error_data_t;
1130
1131 typedef struct raid_phys_disk_inquiry_data {
1132         uint8_t                 VendorID[8];
1133         uint8_t                 ProductID[16];
1134         uint8_t                 ProductRevLevel[4];
1135         uint8_t                 Info[32];
1136 } raid_phys_disk0_inquiry_data_t;
1137
1138 typedef struct raid_phys_disk0_settings {
1139         uint8_t                 SepID;
1140         uint8_t                 SepBus;
1141         uint8_t                 HotSparePool;
1142         uint8_t                 PhysDiskSettings;
1143 } raid_phys_disk0_settings_t;
1144
1145 typedef struct raid_phys_disk0_status {
1146         uint8_t                 Flags;
1147         uint8_t                 State;
1148         uint16_t                Reserved;
1149 } raid_phys_disk0_status_t;
1150
1151 /*
1152  * RAID Volume 2 IM Physical Disk DiskStatus flags
1153  */
1154 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC           0x01
1155 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED              0x02
1156
1157 #define MPI_PHYSDISK0_STATUS_ONLINE                     0x00
1158 #define MPI_PHYSDISK0_STATUS_MISSING                    0x01
1159 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE             0x02
1160 #define MPI_PHYSDISK0_STATUS_FAILED                     0x03
1161 #define MPI_PHYSDISK0_STATUS_INITIALIZING               0x04
1162 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED          0x05
1163 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED           0x06
1164 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE              0xFF
1165
1166 typedef struct config_page_raid_phys_disk_0 {
1167         config_page_header_t    Header;
1168         uint8_t                 PhysDiskID;
1169         uint8_t                 PhysDiskBus;
1170         uint8_t                 PhysDiskIOC;
1171         uint8_t                 PhysDiskNum;
1172         raid_phys_disk0_settings_t PhysDiskSettings;
1173         uint32_t                Reserved1;
1174         uint32_t                Reserved2;
1175         uint32_t                Reserved3;
1176         uint8_t                 DiskIdentifier[16];
1177         raid_phys_disk0_inquiry_data_t InquiryData;
1178         raid_phys_disk0_status_t PhysDiskStatus;
1179         uint32_t                MaxLBA;
1180         raid_phys_disk0_error_data_t ErrorData;
1181 } config_page_raid_phys_disk_0_t;
1182
1183 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION               0x00
1184
1185 typedef struct raid_phys_disk1_path {
1186         uint8_t                 PhysDiskID;
1187         uint8_t                 PhysDiskBus;
1188         uint16_t                Reserved1;
1189         uint64_t                WWID;
1190         uint64_t                OwnerWWID;
1191         uint8_t                 OwnerIdentifier;
1192         uint8_t                 Reserved2;
1193         uint16_t                Flags;
1194 } raid_phys_disk1_path_t;
1195
1196 /* RAID Physical Disk Page 1 Flags field defines */
1197
1198 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN          0x0002
1199 #define MPI_RAID_PHYSDISK1_FLAG_INVALID         0x0001
1200
1201 #ifndef MPI_RAID_PHYS_DISK1_PATH_MAX
1202 #define MPI_RAID_PHYS_DISK1_PATH_MAX            1
1203 #endif
1204
1205 typedef struct config_page_raid_phys_disk_1 {
1206         config_page_header_t    Header;
1207         uint8_t                 NumPhysDiskPaths;
1208         uint8_t                 PhysDiskNum;
1209         uint16_t                Reserved2;
1210         uint32_t                Reserved1;
1211         raid_phys_disk1_path_t  Path[MPI_RAID_PHYS_DISK1_PATH_MAX];
1212 } config_page_raid_phys_disk_1_t;
1213
1214 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION               0x01
1215 /*
1216  * LAN Config Pages
1217  */
1218 typedef struct config_page_lan_0 {
1219         config_page_header_t    Header;
1220         uint16_t                TxRxModes;
1221         uint16_t                Reserved;
1222         uint32_t                PacketPrePad;
1223 } config_page_lan_0_t;
1224
1225 #define MPI_LAN_PAGE0_PAGEVERSION                       0x01
1226
1227 #define MPI_LAN_PAGE0_RETURN_LOOPBACK                   0x0000
1228 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK                 0x0001
1229 #define MPI_LAN_PAGE0_LOOPBACK_MASK                     0x0001
1230
1231 typedef struct config_page_lan_1 {
1232         config_page_header_t    Header;
1233         uint16_t                Reserved;
1234         uint8_t                 CurrentDeviceState;
1235         uint8_t                 Reserved1;
1236         uint32_t                MinPacketSize;
1237         uint32_t                MaxPacketSize;
1238         uint32_t                HardwareAddressLow;
1239         uint32_t                HardwareAddressHigh;
1240         uint32_t                MaxWireSpeedLow;
1241         uint32_t                MaxWireSpeedHigh;
1242         uint32_t                BucketsRemaining;
1243         uint32_t                MaxReplySize;
1244         uint32_t                NegWireSpeedLow;
1245         uint32_t                NegWireSpeedHigh;
1246 } config_page_lan_1_t;
1247
1248 #define MPI_LAN_PAGE1_PAGEVERSION                       0x03
1249
1250 #define MPI_LAN_PAGE1_DEV_STATE_RESET                   0x00
1251 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL             0x01
1252
1253 /*
1254  * Inband config pages
1255  */
1256 typedef struct config_page_inband_0 {
1257         config_page_header_t    Header;
1258         mpi_version_format_t    InbandVersion;
1259         uint16_t                MaximumBuffers;
1260         uint16_t                Reserved1;
1261 } config_page_inband_0_t;
1262
1263 /*
1264  * SAS IO Unit config pages
1265  */
1266 typedef struct mpi_sas_io_unit0_phy_data {
1267         uint8_t                 Port;
1268         uint8_t                 PortFlags;
1269         uint8_t                 PhyFlags;
1270         uint8_t                 NegotiatedLinkRate;
1271         uint32_t                ControllerPhyDeviceInfo;
1272         uint16_t                AttachedDeviceHandle;
1273         uint16_t                ControllerDevHandle;
1274         uint32_t                Reserved2;
1275 } mpi_sas_io_unit0_phy_data_t;
1276
1277 /*
1278  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1279  * one and check Header.PageLength at runtime.
1280  */
1281 #ifndef MPI_SAS_IOUNIT0_PHY_MAX
1282 #define MPI_SAS_IOUNIT0_PHY_MAX         1
1283 #endif
1284
1285 typedef struct config_page_sas_io_unit_0 {
1286         config_extended_page_header_t   Header;
1287         uint16_t                        NvdataVersionDefault;
1288         uint16_t                        NvdataVersionPersistent;
1289         uint8_t                         NumPhys;
1290         uint8_t                         Reserved2;
1291         uint16_t                        Reserved3;
1292         mpi_sas_io_unit0_phy_data_t     PhyData[MPI_SAS_IOUNIT0_PHY_MAX];
1293 } config_page_sas_io_unit_0_t;
1294
1295 #define MPI_SASIOUNITPAGE0_PAGEVERSION          0x00
1296
1297 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS        0x08
1298 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM             0x00
1299 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM             0x04
1300 #define MPI_SAS_IOUNIT0_PORT_FLAGS_WAIT_FOR_PORTENABLE          0x02
1301 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG             0x01
1302
1303 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED                  0x04
1304 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT                     0x02
1305 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT                     0x01
1306
1307 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN                            0x00
1308 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED                       0x01
1309 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION           0x02
1310 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE                  0x03
1311 #define MPI_SAS_IOUNIT0_RATE_1_5                                0x08
1312 #define MPI_SAS_IOUNIT0_RATE_3_0                                0x09
1313
1314 typedef struct mpi_sas_io_unit1_phy_data {
1315         uint8_t                         Port;
1316         uint8_t                         PortFlags;
1317         uint8_t                         PhyFlags;
1318         uint8_t                         MaxMinLinkRate;
1319         uint32_t                        ControllerPhyDeviceInfo;
1320         uint32_t                        Reserved1;
1321 } mpi_sas_io_unit1_phy_data_t;
1322
1323 /*
1324  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1325  * one and check Header.PageLength at runtime.
1326  */
1327 #ifndef MPI_SAS_IOUNIT1_PHY_MAX
1328 #define MPI_SAS_IOUNIT1_PHY_MAX         1
1329 #endif
1330
1331 typedef struct config_page_sas_io_unit_1 {
1332         config_extended_page_header_t   Header;
1333         uint16_t                        ControlFlags;
1334         uint16_t                        MaxNumSATATargets;
1335         uint16_t                        AdditionalControlFlags;
1336         uint16_t                        Reserved1;
1337         uint8_t                         NumPhys;
1338         uint8_t                         SATAMaxQDepth;
1339         uint8_t                         ReportMissingDeviceDelay;
1340         uint8_t                         IODeviceMissingDelay;
1341         mpi_sas_io_unit1_phy_data_t     PhyData[MPI_SAS_IOUNIT1_PHY_MAX];
1342 } config_page_sas_io_unit_1_t;
1343
1344 #define MPI_SASIOUNITPAGE1_PAGEVERSION          0x00
1345
1346 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM             0x00
1347 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM             0x04
1348 #define MPI_SAS_IOUNIT1_PORT_FLAGS_WAIT_FOR_PORTENABLE          0x02
1349 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG             0x01
1350
1351 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE                   0x04
1352 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT                     0x02
1353 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT                     0x01
1354
1355 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK                           0xF0
1356 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5                            0x80
1357 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0                            0x90
1358 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK                           0x0F
1359 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5                            0x08
1360 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0                            0x09
1361
1362 typedef struct config_page_sas_io_unit_2 {
1363         config_extended_page_header_t           Header;
1364         uint32_t                                Reserved1;
1365         uint16_t                                MaxPersistentIDs;
1366         uint16_t                                NumPersistentIDsUsed;
1367         uint8_t                                 Status;
1368         uint8_t                                 Flags;
1369         uint16_t                                Reserved2;
1370 } config_page_sas_io_unit_2_t;
1371
1372 #define MPI_SASIOUNITPAGE2_PAGEVERSION          0x00
1373
1374 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS     0x02
1375 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS         0x01
1376
1377 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS       0x01
1378
1379 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE                0x0E
1380 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE               1
1381 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP                       0x00
1382 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP            0x01
1383 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP           0x02
1384 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP            0x07
1385
1386 typedef struct config_page_sas_io_unit_3 {
1387         config_extended_page_header_t           Header;
1388         uint32_t                                Reserved1;
1389         uint32_t                                MaxInvalidDwordCount;
1390         uint32_t                                InvalidDwordCountTime;
1391         uint32_t                                MaxRunningDisparityErrorCount;
1392         uint32_t                                RunningDisparityErrorTime;
1393         uint32_t                                MaxLossDwordSynchCount;
1394         uint32_t                                LossDwordSynchCountTime;
1395         uint32_t                                MaxPhyResetProblemCount;
1396         uint32_t                                PhyResetProblemTime;
1397 } config_page_sas_io_unit_3_t;
1398
1399 #define MPI_SASIOUNITPAGE3_PAGEVERSION          0x00
1400
1401 typedef struct config_page_sas_expander_0 {
1402         config_extended_page_header_t   Header;
1403         uint8_t                         PhysicalPort;
1404         uint8_t                         Reserved1;
1405         uint16_t                        EnclosureHandle;
1406         uint64_t                        SASAddress;
1407         uint32_t                        Reserved2;
1408         uint16_t                        DevHandle;
1409         uint16_t                        ParentDevHandle;
1410         uint16_t                        ExpanderChangeCount;
1411         uint16_t                        ExpanderRouteIndexes;
1412         uint8_t                         NumPhys;
1413         uint8_t                         SASLevel;
1414         uint8_t                         Flags;
1415         uint8_t                         Reserved3;
1416 } config_page_sas_expander_0_t;
1417
1418 #define MPI_SASEXPANDER0_PAGEVERSION            0x00
1419
1420 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG      0x02
1421 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS      0x01
1422
1423
1424 typedef struct config_page_sas_expander_1 {
1425         config_extended_page_header_t   Header;
1426         uint32_t                        Reserved1;
1427         uint8_t                         NumPhys;
1428         uint8_t                         Phy;
1429         uint16_t                        Reserved2;
1430         uint8_t                         ProgrammedLinkRate;
1431         uint8_t                         HwLinkRate;
1432         uint16_t                        AttachedDevHandle;
1433         uint32_t                        PhyInfo;
1434         uint32_t                        AttachedDeviceInfo;
1435         uint16_t                        OwnerDevHandle;
1436         uint8_t                         ChangeCount;
1437         uint8_t                         Reserved3;
1438         uint8_t                         PhyIdentifier;
1439         uint8_t                         AttachedPhyIdentifier;
1440         uint8_t                         NumTableEntriesProg;
1441         uint8_t                         DiscoveryInfo;
1442         uint32_t                        Reserved4;
1443 } config_page_sas_expander_1_t;
1444
1445 #define MPI_SASEXPANDER1_PAGEVERSION            0x00
1446
1447 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
1448
1449 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
1450
1451 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
1452
1453 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
1454
1455 /* values for SAS Expander Page 1 DiscoveryInfo field */
1456 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE   0x02
1457 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES   0x01
1458
1459 typedef struct config_page_sas_device_0 {
1460         config_extended_page_header_t   Header;
1461         uint16_t                        Slot;
1462         uint16_t                        EnclosureHandle;
1463         uint64_t                        SASAddress;
1464         uint16_t                        ParentDevHandle;
1465         uint8_t                         PhyNum;
1466         uint8_t                         AccessStatus;
1467         uint16_t                        DevHandle;
1468         uint8_t                         TargetID;
1469         uint8_t                         Bus;
1470         uint32_t                        DeviceInfo;
1471         uint16_t                        Flags;
1472         uint8_t                         PhysicalPort;
1473         uint8_t                         Reserved2;
1474 } config_page_sas_device_0_t;
1475
1476 #define MPI_SASDEVICE0_PAGEVERSION              0x00
1477
1478 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT        0x04
1479 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED             0x02
1480 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT            0x01
1481
1482 typedef struct config_page_sas_device_1 {
1483         config_extended_page_header_t   Header;
1484         uint32_t                        Reserved1;
1485         uint64_t                        SASAddress;
1486         uint32_t                        Reserved2;
1487         uint16_t                        DevHandle;
1488         uint8_t                         TargetID;
1489         uint8_t                         Bus;
1490         uint8_t                         InitialRegDeviceFIS[20];
1491 } config_page_sas_device_1_t;
1492
1493 #define MPI_SASDEVICE1_PAGEVERSION              0x00
1494
1495 typedef struct config_page_sas_phy_0 {
1496         config_extended_page_header_t   Header;
1497         uint32_t                        Reserved1;
1498         uint64_t                        SASAddress;
1499         uint16_t                        AttachedDevHandle;
1500         uint8_t                         AttachedPhyIdentifier;
1501         uint8_t                         Reserved2;
1502         uint32_t                        AttachedDeviceInfo;
1503         uint8_t                         ProgrammedLinkRate;
1504         uint8_t                         HwLinkRate;
1505         uint8_t                         ChangeCount;
1506         uint8_t                         Reserved3;
1507         uint32_t                        PhyInfo;
1508 } config_page_sas_phy_0_t;
1509
1510 #define MPI_SASPHY0_PAGEVERSION         0x00
1511
1512 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK                0xF0
1513 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE    0x00
1514 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5                 0x80
1515 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0                 0x90
1516 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK                0x0F
1517 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE    0x00
1518 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5                 0x08
1519 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0                 0x09
1520
1521 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK               0xF0
1522 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5                0x80
1523 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0                0x90
1524 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK               0x0F
1525 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5                0x08
1526 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0                0x09
1527
1528 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE           0x00004000
1529 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR         0x00002000
1530 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY                0x00001000
1531
1532 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME  0x00000F00
1533 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME 8
1534
1535 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE     0x000000F0
1536 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING             0x00000000
1537 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING        0x00000010
1538 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING              0x00000020
1539
1540 #define MPI_SAS_PHY0_DEVINFO_SATA_DEVICE                0x00000080
1541
1542 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE             0x0000000F
1543 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE          0x00000000
1544 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED               0x00000001
1545 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED         0x00000002
1546 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE          0x00000003
1547 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5                   0x00000008
1548 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0                   0x00000009
1549
1550 typedef struct config_page_sas_phy_1 {
1551         config_extended_page_header_t   Header;
1552         uint32_t                        Reserved1;
1553         uint32_t                        InvalidDwordCount;
1554         uint32_t                        RunningDisparityErrorCount;
1555         uint32_t                        LossDwordSynchCount;
1556         uint32_t                        PhyResetProblemCount;
1557 } config_page_sas_phy_1_t;
1558
1559 #define MPI_SASPHY1_PAGEVERSION         0x00
1560
1561 #ifdef  __cplusplus
1562 }
1563 #endif
1564
1565 #endif  /* _SYS_MPI_CNFG_H */