include/sys/nxge/nxge_defs.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 #ifndef _SYS_NXGE_NXGE_DEFS_H
  27 #define _SYS_NXGE_NXGE_DEFS_H
  28
  29 #ifdef  __cplusplus
  30 extern "C" {
  31 #endif
  32
  33 /*
  34  * Block Address Assignment (24-bit base address)
  35  * (bits [23:20]: block  [19]: set to 1 for FZC )
  36  */
  37 #define PIO                     0x000000
  38 #define FZC_PIO                 0x080000
  39 #define RESERVED_1              0x100000
  40 #define FZC_MAC                 0x180000
  41 #define RESERVED_2              0x200000
  42 #define FZC_IPP                 0x280000
  43 #define FFLP                    0x300000
  44 #define FZC_FFLP                0x380000
  45 #define PIO_VADDR               0x400000
  46 #define RESERVED_3              0x480000
  47 #define ZCP                     0x500000
  48 #define FZC_ZCP                 0x580000
  49 #define DMC                     0x600000
  50 #define FZC_DMC                 0x680000
  51 #define TXC                     0x700000
  52 #define FZC_TXC                 0x780000
  53 #define PIO_LDSV                0x800000
  54 #define RESERVED_4              0x880000
  55 #define PIO_LDGIM               0x900000
  56 #define RESERVED_5              0x980000
  57 #define PIO_IMASK0              0xa00000
  58 #define RESERVED_6              0xa80000
  59 #define PIO_IMASK1              0xb00000
  60 #define RESERVED_7_START        0xb80000
  61 #define RESERVED_7_END          0xc00000
  62 #define FZC_PROM                0xc80000
  63 #define RESERVED_8              0xd00000
  64 #define FZC_PIM                 0xd80000
  65 #define RESERVED_9_START        0xe00000
  66 #define RESERVED_9_END          0xf80000
  67
  68 /* PIO          (0x000000) */
  69
  70
  71 /* FZC_PIO      (0x080000) */
  72 #define LDGITMRES               (FZC_PIO + 0x00008)     /* timer resolution */
  73 #define SID                     (FZC_PIO + 0x10200)     /* 64 LDG, INT data */
  74 #define LDG_NUM                 (FZC_PIO + 0x20000)     /* 69 LDs */
  75
  76
  77
  78 /* FZC_IPP      (0x280000) */
  79
  80
  81 /* FFLP         (0x300000), Header Parser */
  82
  83 /* PIO_VADDR    (0x400000), PIO Virtaul DMA Address */
  84 /* ?? how to access DMA via PIO_VADDR? */
  85 #define VADDR                   (PIO_VADDR + 0x00000) /* ?? not for driver */
  86
  87
  88 /* ZCP          (0x500000), Neptune Only */
  89
  90
  91 /* FZC_ZCP      (0x580000), Neptune Only */
  92
  93
  94 /* DMC          (0x600000), register offset (32 DMA channels) */
  95
  96 /* Transmit Ring Register Offset (32 Channels) */
  97 #define TX_RNG_CFIG             (DMC + 0x40000)
  98 #define TX_RING_HDH             (DMC + 0x40008)
  99 #define TX_RING_HDL             (DMC + 0x40010)
 100 #define TX_RING_KICK            (DMC + 0x40018)
 101 /* Transmit Operations (32 Channels) */
 102 #define TX_ENT_MSK              (DMC + 0x40020)
 103 #define TX_CS                   (DMC + 0x40028)
 104 #define TXDMA_MBH               (DMC + 0x40030)
 105 #define TXDMA_MBL               (DMC + 0x40038)
 106 #define TX_DMA_PRE_ST           (DMC + 0x40040)
 107 #define TX_RNG_ERR_LOGH         (DMC + 0x40048)
 108 #define TX_RNG_ERR_LOGL         (DMC + 0x40050)
 109 #if OLD
 110 #define SH_TX_RNG_ERR_LOGH      (DMC + 0x40058)
 111 #define SH_TX_RNG_ERR_LOGL      (DMC + 0x40060)
 112 #endif
 113
 114 /* FZC_DMC RED Initial Random Value register offset (global) */
 115 #define RED_RAN_INIT            (FZC_DMC + 0x00068)
 116
 117 #define RX_ADDR_MD              (FZC_DMC + 0x00070)
 118
 119 /* FZC_DMC Ethernet Timeout Countue register offset (global) */
 120 #define EING_TIMEOUT            (FZC_DMC + 0x00078)
 121
 122 /* RDC Table */
 123 #define RDC_TBL                 (FZC_DMC + 0x10000)     /* 256 * 8 */
 124
 125 /* FZC_DMC partitioning support register offset (32 channels) */
 126
 127 #define TX_LOG_PAGE_VLD         (FZC_DMC + 0x40000)
 128 #define TX_LOG_MASK1            (FZC_DMC + 0x40008)
 129 #define TX_LOG_VAL1             (FZC_DMC + 0x40010)
 130 #define TX_LOG_MASK2            (FZC_DMC + 0x40018)
 131 #define TX_LOG_VAL2             (FZC_DMC + 0x40020)
 132 #define TX_LOG_PAGE_RELO1       (FZC_DMC + 0x40028)
 133 #define TX_LOG_PAGE_RELO2       (FZC_DMC + 0x40030)
 134 #define TX_LOG_PAGE_HDL         (FZC_DMC + 0x40038)
 135
 136 #define TX_ADDR_MOD             (FZC_DMC + 0x41000) /* only one? */
 137
 138
 139 /* FZC_DMC RED Parameters register offset (32 channels) */
 140 #define RDC_RED_PARA1           (FZC_DMC + 0x30000)
 141 #define RDC_RED_PARA2           (FZC_DMC + 0x30008)
 142 /* FZC_DMC RED Discard Cound Register offset (32 channels) */
 143 #define RED_DIS_CNT             (FZC_DMC + 0x30010)
 144
 145 #if OLD /* This has been moved to TXC */
 146 /* Transmit Ring Scheduler (per port) */
 147 #define TX_DMA_MAP0             (FZC_DMC + 0x50000)
 148 #define TX_DMA_MAP1             (FZC_DMC + 0x50008)
 149 #define TX_DMA_MAP2             (FZC_DMC + 0x50010)
 150 #define TX_DMA_MAP3             (FZC_DMC + 0x50018)
 151 #endif
 152
 153 /* Transmit Ring Scheduler: DRR Weight (32 Channels) */
 154 #define DRR_WT                  (FZC_DMC + 0x51000)
 155 #if OLD
 156 #define TXRNG_USE               (FZC_DMC + 0x51008)
 157 #endif
 158
 159 /* TXC          (0x700000)??    */
 160
 161
 162 /* FZC_TXC      (0x780000)??    */
 163
 164
 165 /*
 166  * PIO_LDSV     (0x800000)
 167  * Logical Device State Vector 0, 1, 2.
 168  * (69 logical devices, 8192 apart, partitioning control)
 169  */
 170 #define LDSV0                   (PIO_LDSV + 0x00000)    /* RO (64 - 69) */
 171 #define LDSV1                   (PIO_LDSV + 0x00008)    /* RO (32 - 63) */
 172 #define LDSV2                   (PIO_LDSV + 0x00010)    /* RO ( 0 - 31) */
 173
 174 /*
 175  * PIO_LDGIM    (0x900000)
 176  * Logical Device Group Interrupt Management (64 groups).
 177  * (count 64, step 8192)
 178  */
 179 #define LDGIMGN                 (PIO_LDGIMGN + 0x00000) /* RW */
 180
 181 /*
 182  * PIO_IMASK0   (0xA000000)
 183  *
 184  * Logical Device Masks 0, 1.
 185  * (64 logical devices, 8192 apart, partitioning control)
 186  */
 187 #define LD_IM0                  (PIO_IMASK0 + 0x00000)  /* RW ( 0 - 63) */
 188
 189 /*
 190  * PIO_IMASK0   (0xB000000)
 191  *
 192  * Logical Device Masks 0, 1.
 193  * (5 logical devices, 8192 apart, partitioning control)
 194  */
 195 #define LD_IM1                  (PIO_IMASK1 + 0x00000)  /* RW (64 - 69) */
 196
 197
 198 /* DMC/TMC CSR size */
 199 #define DMA_CSR_SLL             9       /* Used to calculate VR addresses */
 200 #define DMA_CSR_SIZE            (1 << DMA_CSR_SLL) /* 512 */
 201 #define DMA_CSR_MASK            0xff    /* Used to calculate VR addresses */
 202         /*
 203          * That is, each DMA CSR set must fit into a 512 byte space.
 204          * If you subtract DMC (0x60000) from each DMA register definition,
 205          * what you have left over is currently less than 255 (0xff)
 206          */
 207 #define DMA_CSR_MIN_PAGE_SIZE   (2 * DMA_CSR_SIZE) /* 1024 */
 208         /*
 209          * There are 2 subpages per page in a VR.
 210          */
 211 #define VDMA_CSR_SIZE           (8 * DMA_CSR_MIN_PAGE_SIZE) /* 0x2000 */
 212         /*
 213          * There are 8 pages in a VR.
 214          */
 215
 216 /*
 217  * Define the Default RBR, RCR
 218  */
 219 #define RBR_DEFAULT_MAX_BLKS    8192    /* each entry (16 blockaddr/64B) */
 220 #define RBR_NBLK_PER_LINE       16      /* 16 block addresses per 64 B line */
 221 #define RBR_DEFAULT_MAX_LEN     (RBR_DEFAULT_MAX_BLKS)
 222 #define RBR_DEFAULT_MIN_LEN     1
 223 #define RCR_DEFAULT_MAX         8192
 224
 225 #define SW_OFFSET_NO_OFFSET             0
 226 #define SW_OFFSET_64                    1       /* 64 bytes */
 227 #define SW_OFFSET_128                   2       /* 128 bytes */
 228 /* The following additional offsets are defined for Neptune-L and RF-NIU */
 229 #define SW_OFFSET_192                   3
 230 #define SW_OFFSET_256                   4
 231 #define SW_OFFSET_320                   5
 232 #define SW_OFFSET_384                   6
 233 #define SW_OFFSET_448                   7
 234
 235 #define TDC_DEFAULT_MAX         8192
 236 /*
 237  * RBR block descriptor is 32 bits (bits [43:12]
 238  */
 239 #define RBR_BKADDR_SHIFT        12
 240
 241
 242 #define RCR_DEFAULT_MAX_BLKS    4096    /* each entry (8 blockaddr/64B) */
 243 #define RCR_NBLK_PER_LINE       8       /* 8 block addresses per 64 B line */
 244 #define RCR_DEFAULT_MAX_LEN     (RCR_DEFAULT_MAX_BLKS)
 245 #define RCR_DEFAULT_MIN_LEN     1
 246
 247 /*  DMA Channels.  */
 248 #define NXGE_MAX_DMCS           (NXGE_MAX_RDCS + NXGE_MAX_TDCS)
 249 #define NXGE_MAX_RDCS           16
 250 #define NXGE_MAX_TDCS           24
 251 #define NXGE_MAX_TDCS_NIU       16
 252 /*
 253  * original mapping from Hypervisor
 254  */
 255 #ifdef  ORIGINAL
 256 #define NXGE_N2_RXDMA_START_LDG 0
 257 #define NXGE_N2_TXDMA_START_LDG 16
 258 #define NXGE_N2_MIF_LDG         32
 259 #define NXGE_N2_MAC_0_LDG       33
 260 #define NXGE_N2_MAC_1_LDG       34
 261 #define NXGE_N2_SYS_ERROR_LDG   35
 262 #endif
 263
 264 #define NXGE_N2_RXDMA_START_LDG 19
 265 #define NXGE_N2_TXDMA_START_LDG 27
 266 #define NXGE_N2_MIF_LDG         17
 267 #define NXGE_N2_MAC_0_LDG       16
 268 #define NXGE_N2_MAC_1_LDG       35
 269 #define NXGE_N2_SYS_ERROR_LDG   18
 270 #define NXGE_N2_LDG_GAP         17
 271
 272 #define NXGE_MAX_RDC_GRPS       8
 273
 274 /*
 275  * Max. ports per Neptune and NIU
 276  */
 277 #define NXGE_MAX_PORTS                  4
 278 #define NXGE_PORTS_NEPTUNE              4
 279 #define NXGE_PORTS_NIU                  2
 280
 281 /*
 282  * Virtualization Regions.
 283  */
 284 #define NXGE_MAX_VRS                    8
 285
 286 /*
 287  * TDC groups are used exclusively for the purpose of Hybrid I/O
 288  * TX needs one group for each VR
 289  */
 290 #define NXGE_MAX_TDC_GROUPS             (NXGE_MAX_VRS)
 291
 292 /* Max. RDC table groups */
 293 #define NXGE_MAX_RDC_GROUPS             8
 294 #define NXGE_MAX_RDCS                   16
 295 #define NXGE_MAX_DMAS                   32
 296
 297 #define NXGE_MAX_MACS_XMACS             16
 298 #define NXGE_MAX_MACS_BMACS             8
 299 #define NXGE_MAX_MACS                   (NXGE_MAX_PORTS * NXGE_MAX_MACS_XMACS)
 300
 301 #define NXGE_MAX_VLANS                  4096
 302 #define VLAN_ETHERTYPE                  (0x8100)
 303
 304
 305 /* Scaling factor for RBR (receive block ring) */
 306 #define RBR_SCALE_1             0
 307 #define RBR_SCALE_2             1
 308 #define RBR_SCALE_3             2
 309 #define RBR_SCALE_4             3
 310 #define RBR_SCALE_5             4
 311 #define RBR_SCALE_6             5
 312 #define RBR_SCALE_7             6
 313 #define RBR_SCALE_8             7
 314
 315
 316 #define MAX_PORTS_PER_NXGE      4
 317 #define MAX_MACS                32
 318
 319 #define TX_GATHER_POINTER_SZ    8
 320 #define TX_GP_PER_BLOCK         8
 321 #define TX_DEFAULT_MAX_GPS      1024    /* Max. # of gather pointers */
 322 #define TX_DEFAULT_JUMBO_MAX_GPS 4096   /* Max. # of gather pointers */
 323 #define TX_DEFAULT_MAX_LEN      (TX_DEFAULT_MAX_GPS/TX_GP_PER_BLOCK)
 324 #define TX_DEFAULT_JUMBO_MAX_LEN (TX_DEFAULT_JUMBO_MAX_GPS/TX_GP_PER_BLOCK)
 325
 326 #define TX_RING_THRESHOLD               (TX_DEFAULT_MAX_GPS/4)
 327 #define TX_RING_JUMBO_THRESHOLD         (TX_DEFAULT_JUMBO_MAX_GPS/4)
 328
 329 #define TRANSMIT_HEADER_SIZE            16      /* 16 B frame header */
 330
 331 #define TX_DESC_SAD_SHIFT       0
 332 #define TX_DESC_SAD_MASK        0x00000FFFFFFFFFFFULL   /* start address */
 333 #define TX_DESC_TR_LEN_SHIFT    44
 334 #define TX_DESC_TR_LEN_MASK     0x00FFF00000000000ULL   /* Transfer Length */
 335 #define TX_DESC_NUM_PTR_SHIFT   58
 336 #define TX_DESC_NUM_PTR_MASK    0x2C00000000000000ULL   /* gather pointers */
 337 #define TX_DESC_MASK_SHIFT      62
 338 #define TX_DESC_MASK_MASK       0x4000000000000000ULL   /* Mark bit */
 339 #define TX_DESC_SOP_SHIF        63
 340 #define TX_DESC_NUM_MASK        0x8000000000000000ULL   /* Start of packet */
 341
 342 #define TCAM_FLOW_KEY_MAX_CLASS         12
 343 #define TCAM_L3_MAX_USER_CLASS          4
 344 #define TCAM_MAX_ENTRY                  256
 345 #define TCAM_NIU_TCAM_MAX_ENTRY         128
 346 #define TCAM_NXGE_TCAM_MAX_ENTRY        256
 347 #define NXGE_L2_PROG_CLS                2
 348 #define NXGE_L3_PROG_CLS                4
 349
 350
 351
 352 /* TCAM entry formats */
 353 #define TCAM_IPV4_5TUPLE_FORMAT 0x00
 354 #define TCAM_IPV6_5TUPLE_FORMAT 0x01
 355 #define TCAM_ETHERTYPE_FORMAT   0x02
 356
 357
 358 /* TCAM */
 359 #define TCAM_SELECT_IPV6        0x01
 360 #define TCAM_LOOKUP             0x04
 361 #define TCAM_DISCARD            0x08
 362
 363 /* FLOW Key */
 364 #define FLOW_L4_1_34_BYTES      0x10
 365 #define FLOW_L4_1_78_BYTES      0x11
 366 #define FLOW_L4_0_12_BYTES      (0x10 << 2)
 367 #define FLOW_L4_0_56_BYTES      (0x11 << 2)
 368 #define FLOW_PROTO_NEXT         0x10
 369 #define FLOW_IPDA               0x20
 370 #define FLOW_IPSA               0x40
 371 #define FLOW_VLAN               0x80
 372 #define FLOW_L2DA               0x100
 373 #define FLOW_PORT               0x200
 374
 375 /* TCAM */
 376 #define MAX_EFRAME      11
 377
 378 #define TCAM_USE_L2RDC_FLOW_LOOKUP      0x00
 379 #define TCAM_USE_OFFSET_DONE            0x01
 380 #define TCAM_OVERRIDE_L2_FLOW_LOOKUP    0x02
 381 #define TCAM_OVERRIDE_L2_USE_OFFSET     0x03
 382
 383 /*
 384  * FCRAM (Hashing):
 385  *      1. IPv4 exact match
 386  *      2. IPv6 exact match
 387  *      3. IPv4 Optimistic match
 388  *      4. IPv6 Optimistic match
 389  *
 390  */
 391 #define FCRAM_IPV4_EXT_MATCH    0x00
 392 #define FCRAM_IPV6_EXT_MATCH    0x01
 393 #define FCRAM_IPV4_OPTI_MATCH   0x02
 394 #define FCRAM_IPV6_OPTI_MATCH   0x03
 395
 396
 397 #define NXGE_HASH_MAX_ENTRY     256
 398
 399
 400 #define MAC_ADDR_LENGTH         6
 401
 402 /* convert values */
 403 #define NXGE_BASE(x, y)         (((y) << (x ## _SHIFT)) & (x ## _MASK))
 404 #define NXGE_VAL(x, y)          (((y) & (x ## _MASK)) >> (x ## _SHIFT))
 405
 406 /*
 407  * Locate the DMA channel start offset (PIO_VADDR)
 408  * (DMA virtual address space of the PIO block)
 409  */
 410 #define TDMC_PIOVADDR_OFFSET(channel)   (2 * DMA_CSR_SIZE * channel)
 411 #define RDMC_PIOVADDR_OFFSET(channel)   (TDMC_OFFSET(channel) + DMA_CSR_SIZE)
 412
 413 /*
 414  * PIO access using the DMC block directly (DMC)
 415  */
 416 #define DMC_OFFSET(channel)     (DMA_CSR_SIZE * channel)
 417 #define TDMC_OFFSET(channel)    (TX_RNG_CFIG + DMA_CSR_SIZE * channel)
 418
 419 /*
 420  * Number of logical pages.
 421  */
 422 #define NXGE_MAX_LOGICAL_PAGES          2
 423
 424 #ifdef  SOLARIS
 425 #ifndef i386
 426 #define _BIT_FIELDS_BIG_ENDIAN          _BIT_FIELDS_HTOL
 427 #else
 428 #define _BIT_FIELDS_LITTLE_ENDIAN       _BIT_FIELDS_LTOH
 429 #endif
 430 #else
 431 #define _BIT_FIELDS_LITTLE_ENDIAN       _LITTLE_ENDIAN_BITFIELD
 432 #endif
 433
 434 #define MAX_PIO_RETRIES         32
 435
 436 #define IS_PORT_NUM_VALID(portn)\
 437         (portn < 4)
 438
 439 /*
 440  * The following macros expect unsigned input values.
 441  */
 442 #define TXDMA_CHANNEL_VALID(cn)         (cn < NXGE_MAX_TDCS)
 443 #define TXDMA_PAGE_VALID(pn)            (pn < NXGE_MAX_LOGICAL_PAGES)
 444 #define TXDMA_FUNC_VALID(fn)            (fn < MAX_PORTS_PER_NXGE)
 445 #define FUNC_VALID(n)                   (n < MAX_PORTS_PER_NXGE)
 446
 447 /*
 448  * DMA channel binding definitions.
 449  */
 450 #define VIR_PAGE_INDEX_MAX              8
 451 #define VIR_SUB_REGIONS                 2
 452 #define VIR_DMA_BIND                    1
 453
 454 #define SUBREGION_VALID(n)              (n < VIR_SUB_REGIONS)
 455 #define VIR_PAGE_INDEX_VALID(n)         (n < VIR_PAGE_INDEX_MAX)
 456 #define VRXDMA_CHANNEL_VALID(n)         (n < NXGE_MAX_RDCS)
 457
 458 /*
 459  * Logical device definitions.
 460  */
 461 #define NXGE_INT_MAX_LD         69
 462 #define NXGE_INT_MAX_LDG        64
 463
 464 #define NXGE_RDMA_LD_START       0
 465 #define NXGE_TDMA_LD_START      32
 466 #define NXGE_MIF_LD             63
 467 #define NXGE_MAC_LD_PORT0       64
 468 #define NXGE_MAC_LD_PORT1       65
 469 #define NXGE_MAC_LD_PORT2       66
 470 #define NXGE_MAC_LD_PORT3       67
 471 #define NXGE_SYS_ERROR_LD       68
 472
 473 #define LDG_VALID(n)                    (n < NXGE_INT_MAX_LDG)
 474 #define LD_VALID(n)                     (n < NXGE_INT_MAX_LD)
 475 #define LD_RXDMA_LD_VALID(n)            (n < NXGE_MAX_RDCS)
 476 #define LD_TXDMA_LD_VALID(n)            (n >= NXGE_MAX_RDCS && \
 477                                         ((n - NXGE_MAX_RDCS) < NXGE_MAX_TDCS)))
 478 #define LD_MAC_VALID(n)                 (IS_PORT_NUM_VALID(n))
 479
 480 #define LD_TIMER_MAX                    0x3f
 481 #define LD_INTTIMER_VALID(n)            (n <= LD_TIMER_MAX)
 482
 483 /* System Interrupt Data */
 484 #define SID_VECTOR_MAX                  0x1f
 485 #define SID_VECTOR_VALID(n)             (n <= SID_VECTOR_MAX)
 486
 487 #define NXGE_COMPILE_32
 488
 489 #ifdef  __cplusplus
 490 }
 491 #endif
 492
 493 #endif  /* _SYS_NXGE_NXGE_DEFS_H */