usr/src/cmd/fm/schemes/mem/mem_spd.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License, Version 1.0 only
   6  * (the "License").  You may not use this file except in compliance
   7  * with the License.
   8  *
   9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
  10  * or http://www.opensolaris.org/os/licensing.
  11  * See the License for the specific language governing permissions
  12  * and limitations under the License.
  13  *
  14  * When distributing Covered Code, include this CDDL HEADER in each
  15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  16  * If applicable, add the following below this CDDL HEADER, with the
  17  * fields enclosed by brackets "[]" replaced with your own identifying
  18  * information: Portions Copyright [yyyy] [name of copyright owner]
  19  *
  20  * CDDL HEADER END
  21  */
  22 /*
  23  * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
  24  * Use is subject to license terms.
  25  */
  26
  27 #ifndef _MEM_SPD_H
  28 #define _MEM_SPD_H
  29
  30 #pragma ident   "%Z%%M% %I%     %E% SMI"
  31
  32 /*
  33  * Layout of SPD-format data, as per PICL.
  34  */
  35
  36 #include <sys/types.h>
  37
  38 #ifdef __cplusplus
  39 extern "C" {
  40 #endif
  41
  42 typedef struct spd_data {
  43         uint8_t         spd_len;        /* bytes written by manufacturer */
  44         uint8_t         spd_max_len;    /* total available prom space */
  45         uint8_t         memory_type;    /* e.g. SDRAM DDR = 0x07 */
  46         uint8_t         n_rows;         /* row address bits */
  47         uint8_t         n_cols;         /* column address bits */
  48         uint8_t         n_mod_rows;     /* number of module rows */
  49         uint8_t         ls_data_width;  /* e.g. 72 bits */
  50         uint8_t         ms_data_width;
  51         uint8_t         vddq_if;        /* e.g. SSTL 2.5V = 0x04 */
  52         uint8_t         cycle_time25;   /* cycle time at CAS latency 2.5 */
  53         uint8_t         access_time25;
  54         uint8_t         config;         /* e.g. ECC = 0x02 */
  55         uint8_t         refresh;        /* e.g. 7.8uS & self refresh = 0x82 */
  56         uint8_t         primary_width;
  57         uint8_t         err_chk_width;
  58         uint8_t         tCCD;
  59         uint8_t         burst_lengths;  /* e.g. 2,4,8 = 0x0e */
  60         uint8_t         n_banks;
  61         uint8_t         cas_lat;
  62         uint8_t         cs_lat;
  63         uint8_t         we_lat;
  64         uint8_t         mod_attrs;
  65         uint8_t         dev_attrs;
  66         uint8_t         cycle_time20;   /* cycle time at CAS latency 2.0 */
  67         uint8_t         access_time20;
  68         uint8_t         cycle_time15;
  69         uint8_t         access_time15;
  70         uint8_t         tRP;
  71         uint8_t         tRRD;
  72         uint8_t         tRCD;
  73         uint8_t         tRAS;
  74         uint8_t         mod_row_density;
  75         uint8_t         addr_ip_setup;
  76         uint8_t         addr_ip_hold;
  77         uint8_t         data_ip_setup;
  78         uint8_t         data_ip_hold;
  79         uint8_t         superset[62 - 36];
  80         uint8_t         spd_rev;
  81         uint8_t         chksum_0_62;
  82         uint8_t         jedec[8];
  83         uint8_t         manu_loc;
  84         uint8_t         manu_part_no[91 - 73];
  85         uint8_t         manu_rev_pcb;
  86         uint8_t         manu_rev_comp;
  87         uint8_t         manu_year;
  88         uint8_t         manu_week;
  89         uint8_t         asmb_serial_no[4];
  90         uint8_t         manu_specific[128 - 99];
  91 } spd_data_t;
  92
  93 #ifdef __cplusplus
  94 }
  95 #endif
  96
  97 #endif /* _MEM_SPD_H */