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dmake: do not set MAKEFLAGS=k
[unleashed/tickless.git] / usr / src / uts / i86pc / io / mp_platform_common.c
blobd988047c3f6a64b4bba40ae431f1e3413bd208f8
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved.
23 * Copyright 2016 Nexenta Systems, Inc.
24 * Copyright (c) 2017 by Delphix. All rights reserved.
25 */
26 /*
27 * Copyright (c) 2010, Intel Corporation.
28 * All rights reserved.
29 */
30
31 /*
32 * PSMI 1.1 extensions are supported only in 2.6 and later versions.
33 * PSMI 1.2 extensions are supported only in 2.7 and later versions.
34 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10.
35 * PSMI 1.5 extensions are supported in Solaris Nevada.
36 * PSMI 1.6 extensions are supported in Solaris Nevada.
37 * PSMI 1.7 extensions are supported in Solaris Nevada.
38 */
39 #define PSMI_1_7
40
41 #include <sys/processor.h>
42 #include <sys/time.h>
43 #include <sys/psm.h>
44 #include <sys/smp_impldefs.h>
45 #include <sys/cram.h>
46 #include <sys/acpi/acpi.h>
47 #include <sys/acpica.h>
48 #include <sys/psm_common.h>
49 #include <sys/apic.h>
50 #include <sys/apic_timer.h>
51 #include <sys/pit.h>
52 #include <sys/ddi.h>
53 #include <sys/sunddi.h>
54 #include <sys/ddi_impldefs.h>
55 #include <sys/pci.h>
56 #include <sys/promif.h>
57 #include <sys/x86_archext.h>
58 #include <sys/cpc_impl.h>
59 #include <sys/uadmin.h>
60 #include <sys/panic.h>
61 #include <sys/debug.h>
62 #include <sys/archsystm.h>
63 #include <sys/trap.h>
64 #include <sys/machsystm.h>
65 #include <sys/cpuvar.h>
66 #include <sys/rm_platter.h>
67 #include <sys/privregs.h>
68 #include <sys/cyclic.h>
69 #include <sys/note.h>
70 #include <sys/pci_intr_lib.h>
71 #include <sys/sunndi.h>
72 #include <sys/hpet.h>
73 #include <sys/clock.h>
74
75 /*
76 * Local Function Prototypes
77 */
78 static int apic_handle_defconf();
79 static int apic_parse_mpct(caddr_t mpct, int bypass);
80 static struct apic_mpfps_hdr *apic_find_fps_sig(caddr_t fptr, int size);
81 static int apic_checksum(caddr_t bptr, int len);
82 static int apic_find_bus_type(char *bus);
83 static int apic_find_bus(int busid);
84 static struct apic_io_intr *apic_find_io_intr(int irqno);
85 static int apic_find_free_irq(int start, int end);
86 struct apic_io_intr *apic_find_io_intr_w_busid(int irqno, int busid);
87 static void apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp);
88 static void apic_free_apic_cpus(void);
89 static boolean_t apic_is_ioapic_AMD_813x(uint32_t physaddr);
90 static int apic_acpi_enter_apicmode(void);
91
92 int apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno,
93 int child_ipin, struct apic_io_intr **intrp);
94 int apic_find_bus_id(int bustype);
95 int apic_find_intin(uchar_t ioapic, uchar_t intin);
96 void apic_record_rdt_entry(apic_irq_t *irqptr, int irq);
97
98 int apic_debug_mps_id = 0; /* 1 - print MPS ID strings */
99
100 /* ACPI SCI interrupt configuration; -1 if SCI not used */
101 int apic_sci_vect = -1;
102 iflag_t apic_sci_flags;
103
104 /* ACPI HPET interrupt configuration; -1 if HPET not used */
105 int apic_hpet_vect = -1;
106 iflag_t apic_hpet_flags;
107
108 /*
109 * psm name pointer
110 */
111 char *psm_name;
112
113 /* ACPI support routines */
114 static int acpi_probe(char *);
115 static int apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
116 int *pci_irqp, iflag_t *intr_flagp);
117
118 int apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
119 int ipin, int *pci_irqp, iflag_t *intr_flagp);
120 uchar_t acpi_find_ioapic(int irq);
121 static int acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2);
122
123 /* Max wait time (in repetitions) for flags to clear in an RDT entry. */
124 int apic_max_reps_clear_pending = 1000;
125
126 int apic_intr_policy = INTR_ROUND_ROBIN;
127
128 int apic_next_bind_cpu = 1; /* For round robin assignment */
129 /* start with cpu 1 */
130
131 /*
132 * If enabled, the distribution works as follows:
133 * On every interrupt entry, the current ipl for the CPU is set in cpu_info
134 * and the irq corresponding to the ipl is also set in the aci_current array.
135 * interrupt exit and setspl (due to soft interrupts) will cause the current
136 * ipl to be be changed. This is cache friendly as these frequently used
137 * paths write into a per cpu structure.
138 *
139 * Sampling is done by checking the structures for all CPUs and incrementing
140 * the busy field of the irq (if any) executing on each CPU and the busy field
141 * of the corresponding CPU.
142 * In periodic mode this is done on every clock interrupt.
143 * In one-shot mode, this is done thru a cyclic with an interval of
144 * apic_redistribute_sample_interval (default 10 milli sec).
145 *
146 * Every apic_sample_factor_redistribution times we sample, we do computations
147 * to decide which interrupt needs to be migrated (see comments
148 * before apic_intr_redistribute().
149 */
150
151 /*
152 * Following 3 variables start as % and can be patched or set using an
153 * API to be defined in future. They will be scaled to
154 * sample_factor_redistribution which is in turn set to hertz+1 (in periodic
155 * mode), or 101 in one-shot mode to stagger it away from one sec processing
156 */
157
158 int apic_int_busy_mark = 60;
159 int apic_int_free_mark = 20;
160 int apic_diff_for_redistribution = 10;
161
162 /* sampling interval for interrupt redistribution for dynamic migration */
163 int apic_redistribute_sample_interval = NANOSEC / 100; /* 10 millisec */
164
165 /*
166 * number of times we sample before deciding to redistribute interrupts
167 * for dynamic migration
168 */
169 int apic_sample_factor_redistribution = 101;
170
171 int apic_redist_cpu_skip = 0;
172 int apic_num_imbalance = 0;
173 int apic_num_rebind = 0;
174
175 /*
176 * Maximum number of APIC CPUs in the system, -1 indicates that dynamic
177 * allocation of CPU ids is disabled.
178 */
179 int apic_max_nproc = -1;
180 int apic_nproc = 0;
181 size_t apic_cpus_size = 0;
182 int apic_defconf = 0;
183 int apic_irq_translate = 0;
184 int apic_spec_rev = 0;
185 int apic_imcrp = 0;
186
187 int apic_use_acpi = 1; /* 1 = use ACPI, 0 = don't use ACPI */
188 int apic_use_acpi_madt_only = 0; /* 1=ONLY use MADT from ACPI */
189
190 /*
191 * For interrupt link devices, if apic_unconditional_srs is set, an irq resource
192 * will be assigned (via _SRS). If it is not set, use the current
193 * irq setting (via _CRS), but only if that irq is in the set of possible
194 * irqs (returned by _PRS) for the device.
195 */
196 int apic_unconditional_srs = 1;
197
198 /*
199 * For interrupt link devices, if apic_prefer_crs is set when we are
200 * assigning an IRQ resource to a device, prefer the current IRQ setting
201 * over other possible irq settings under same conditions.
202 */
203
204 int apic_prefer_crs = 1;
205
206 uchar_t apic_io_id[MAX_IO_APIC];
207 volatile uint32_t *apicioadr[MAX_IO_APIC];
208 uchar_t apic_io_ver[MAX_IO_APIC];
209 uchar_t apic_io_vectbase[MAX_IO_APIC];
210 uchar_t apic_io_vectend[MAX_IO_APIC];
211 uchar_t apic_reserved_irqlist[MAX_ISA_IRQ + 1];
212 uint32_t apic_physaddr[MAX_IO_APIC];
213
214 boolean_t ioapic_mask_workaround[MAX_IO_APIC];
215
216 /*
217 * First available slot to be used as IRQ index into the apic_irq_table
218 * for those interrupts (like MSI/X) that don't have a physical IRQ.
219 */
220 int apic_first_avail_irq = APIC_FIRST_FREE_IRQ;
221
222 /*
223 * apic_ioapic_lock protects the ioapics (reg select), the status, temp_bound
224 * and bound elements of cpus_info and the temp_cpu element of irq_struct
225 */
226 lock_t apic_ioapic_lock;
227
228 int apic_io_max = 0; /* no. of i/o apics enabled */
229
230 struct apic_io_intr *apic_io_intrp = NULL;
231 static struct apic_bus *apic_busp;
232
233 uchar_t apic_resv_vector[MAXIPL+1];
234
235 char apic_level_intr[APIC_MAX_VECTOR+1];
236
237 uint32_t eisa_level_intr_mask = 0;
238 /* At least MSB will be set if EISA bus */
239
240 int apic_pci_bus_total = 0;
241 uchar_t apic_single_pci_busid = 0;
242
243 /*
244 * airq_mutex protects additions to the apic_irq_table - the first
245 * pointer and any airq_nexts off of that one. It also protects
246 * apic_max_device_irq & apic_min_device_irq. It also guarantees
247 * that share_id is unique as new ids are generated only when new
248 * irq_t structs are linked in. Once linked in the structs are never
249 * deleted. temp_cpu & mps_intr_index field indicate if it is programmed
250 * or allocated. Note that there is a slight gap between allocating in
251 * apic_introp_xlate and programming in addspl.
252 */
253 kmutex_t airq_mutex;
254 apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
255 int apic_max_device_irq = 0;
256 int apic_min_device_irq = APIC_MAX_VECTOR;
257
258 typedef struct prs_irq_list_ent {
259 int list_prio;
260 int32_t irq;
261 iflag_t intrflags;
262 acpi_prs_private_t prsprv;
263 struct prs_irq_list_ent *next;
264 } prs_irq_list_t;
265
266
267 /*
268 * ACPI variables
269 */
270 /* 1 = acpi is enabled & working, 0 = acpi is not enabled or not there */
271 int apic_enable_acpi = 0;
272
273 /* ACPI Multiple APIC Description Table ptr */
274 static ACPI_TABLE_MADT *acpi_mapic_dtp = NULL;
275
276 /* ACPI Interrupt Source Override Structure ptr */
277 ACPI_MADT_INTERRUPT_OVERRIDE *acpi_isop = NULL;
278 int acpi_iso_cnt = 0;
279
280 /* ACPI Non-maskable Interrupt Sources ptr */
281 static ACPI_MADT_NMI_SOURCE *acpi_nmi_sp = NULL;
282 static int acpi_nmi_scnt = 0;
283 static ACPI_MADT_LOCAL_APIC_NMI *acpi_nmi_cp = NULL;
284 static int acpi_nmi_ccnt = 0;
285
286 static boolean_t acpi_found_smp_config = B_FALSE;
287
288 /*
289 * The following added to identify a software poweroff method if available.
290 */
291
292 static struct {
293 int poweroff_method;
294 char oem_id[APIC_MPS_OEM_ID_LEN + 1]; /* MAX + 1 for NULL */
295 char prod_id[APIC_MPS_PROD_ID_LEN + 1]; /* MAX + 1 for NULL */
296 } apic_mps_ids[] = {
297 { APIC_POWEROFF_VIA_RTC, "INTEL", "ALDER" }, /* 4300 */
298 { APIC_POWEROFF_VIA_RTC, "NCR", "AMC" }, /* 4300 */
299 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "A450NX" }, /* 4400? */
300 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AD450NX" }, /* 4400 */
301 { APIC_POWEROFF_VIA_ASPEN_BMC, "INTEL", "AC450NX" }, /* 4400R */
302 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "S450NX" }, /* S50 */
303 { APIC_POWEROFF_VIA_SITKA_BMC, "INTEL", "SC450NX" } /* S50? */
304 };
305
306 int apic_poweroff_method = APIC_POWEROFF_NONE;
307
308 /*
309 * Auto-configuration routines
310 */
311
312 /*
313 * Look at MPSpec 1.4 (Intel Order # 242016-005) for details of what we do here
314 * May work with 1.1 - but not guaranteed.
315 * According to the MP Spec, the MP floating pointer structure
316 * will be searched in the order described below:
317 * 1. In the first kilobyte of Extended BIOS Data Area (EBDA)
318 * 2. Within the last kilobyte of system base memory
319 * 3. In the BIOS ROM address space between 0F0000h and 0FFFFh
320 * Once we find the right signature with proper checksum, we call
321 * either handle_defconf or parse_mpct to get all info necessary for
322 * subsequent operations.
323 */
324 int
325 apic_probe_common(char *modname)
326 {
327 uint32_t mpct_addr, ebda_start = 0, base_mem_end;
328 caddr_t biosdatap;
329 caddr_t mpct = 0;
330 caddr_t fptr;
331 int i, mpct_size, mapsize, retval = PSM_FAILURE;
332 ushort_t ebda_seg, base_mem_size;
333 struct apic_mpfps_hdr *fpsp;
334 struct apic_mp_cnf_hdr *hdrp;
335 int bypass_cpu_and_ioapics_in_mptables;
336 int acpi_user_options;
337
338 if (apic_forceload < 0)
339 return (retval);
340
341 /*
342 * Remember who we are
343 */
344 psm_name = modname;
345
346 /* Allow override for MADT-only mode */
347 acpi_user_options = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_root_node(), 0,
348 "acpi-user-options", 0);
349 apic_use_acpi_madt_only = ((acpi_user_options & ACPI_OUSER_MADT) != 0);
350
351 /* Allow apic_use_acpi to override MADT-only mode */
352 if (!apic_use_acpi)
353 apic_use_acpi_madt_only = 0;
354
355 retval = acpi_probe(modname);
356
357 /*
358 * mapin the bios data area 40:0
359 * 40:13h - two-byte location reports the base memory size
360 * 40:0Eh - two-byte location for the exact starting address of
361 * the EBDA segment for EISA
362 */
363 biosdatap = psm_map_phys(0x400, 0x20, PROT_READ);
364 if (!biosdatap)
365 goto apic_ret;
366 fpsp = NULL;
367 mapsize = MPFPS_RAM_WIN_LEN;
368 /*LINTED: pointer cast may result in improper alignment */
369 ebda_seg = *((ushort_t *)(biosdatap+0xe));
370 /* check the 1k of EBDA */
371 if (ebda_seg) {
372 ebda_start = ((uint32_t)ebda_seg) << 4;
373 fptr = psm_map_phys(ebda_start, MPFPS_RAM_WIN_LEN, PROT_READ);
374 if (fptr) {
375 if (!(fpsp =
376 apic_find_fps_sig(fptr, MPFPS_RAM_WIN_LEN)))
377 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
378 }
379 }
380 /* If not in EBDA, check the last k of system base memory */
381 if (!fpsp) {
382 /*LINTED: pointer cast may result in improper alignment */
383 base_mem_size = *((ushort_t *)(biosdatap + 0x13));
384
385 if (base_mem_size > 512)
386 base_mem_end = 639 * 1024;
387 else
388 base_mem_end = 511 * 1024;
389 /* if ebda == last k of base mem, skip to check BIOS ROM */
390 if (base_mem_end != ebda_start) {
391
392 fptr = psm_map_phys(base_mem_end, MPFPS_RAM_WIN_LEN,
393 PROT_READ);
394
395 if (fptr) {
396 if (!(fpsp = apic_find_fps_sig(fptr,
397 MPFPS_RAM_WIN_LEN)))
398 psm_unmap_phys(fptr, MPFPS_RAM_WIN_LEN);
399 }
400 }
401 }
402 psm_unmap_phys(biosdatap, 0x20);
403
404 /* If still cannot find it, check the BIOS ROM space */
405 if (!fpsp) {
406 mapsize = MPFPS_ROM_WIN_LEN;
407 fptr = psm_map_phys(MPFPS_ROM_WIN_START,
408 MPFPS_ROM_WIN_LEN, PROT_READ);
409 if (fptr) {
410 if (!(fpsp =
411 apic_find_fps_sig(fptr, MPFPS_ROM_WIN_LEN))) {
412 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
413 goto apic_ret;
414 }
415 }
416 }
417
418 if (apic_checksum((caddr_t)fpsp, fpsp->mpfps_length * 16) != 0) {
419 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
420 goto apic_ret;
421 }
422
423 apic_spec_rev = fpsp->mpfps_spec_rev;
424 if ((apic_spec_rev != 04) && (apic_spec_rev != 01)) {
425 psm_unmap_phys(fptr, MPFPS_ROM_WIN_LEN);
426 goto apic_ret;
427 }
428
429 /* check IMCR is present or not */
430 apic_imcrp = fpsp->mpfps_featinfo2 & MPFPS_FEATINFO2_IMCRP;
431
432 /* check default configuration (dual CPUs) */
433 if ((apic_defconf = fpsp->mpfps_featinfo1) != 0) {
434 psm_unmap_phys(fptr, mapsize);
435 if ((retval = apic_handle_defconf()) != PSM_SUCCESS)
436 return (retval);
437
438 goto apic_ret;
439 }
440
441 /* MP Configuration Table */
442 mpct_addr = (uint32_t)(fpsp->mpfps_mpct_paddr);
443
444 psm_unmap_phys(fptr, mapsize); /* unmap floating ptr struct */
445
446 /*
447 * Map in enough memory for the MP Configuration Table Header.
448 * Use this table to read the total length of the BIOS data and
449 * map in all the info
450 */
451 /*LINTED: pointer cast may result in improper alignment */
452 hdrp = (struct apic_mp_cnf_hdr *)psm_map_phys(mpct_addr,
453 sizeof (struct apic_mp_cnf_hdr), PROT_READ);
454 if (!hdrp)
455 goto apic_ret;
456
457 /* check mp configuration table signature PCMP */
458 if (hdrp->mpcnf_sig != 0x504d4350) {
459 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
460 goto apic_ret;
461 }
462 mpct_size = (int)hdrp->mpcnf_tbl_length;
463
464 apic_set_pwroff_method_from_mpcnfhdr(hdrp);
465
466 psm_unmap_phys((caddr_t)hdrp, sizeof (struct apic_mp_cnf_hdr));
467
468 if ((retval == PSM_SUCCESS) && !apic_use_acpi_madt_only) {
469 /* This is an ACPI machine No need for further checks */
470 goto apic_ret;
471 }
472
473 /*
474 * Map in the entries for this machine, ie. Processor
475 * Entry Tables, Bus Entry Tables, etc.
476 * They are in fixed order following one another
477 */
478 mpct = psm_map_phys(mpct_addr, mpct_size, PROT_READ);
479 if (!mpct)
480 goto apic_ret;
481
482 if (apic_checksum(mpct, mpct_size) != 0)
483 goto apic_fail1;
484
485 /*LINTED: pointer cast may result in improper alignment */
486 hdrp = (struct apic_mp_cnf_hdr *)mpct;
487 apicadr = (uint32_t *)mapin_apic((uint32_t)hdrp->mpcnf_local_apic,
488 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
489 if (!apicadr)
490 goto apic_fail1;
491
492 /* Parse all information in the tables */
493 bypass_cpu_and_ioapics_in_mptables = (retval == PSM_SUCCESS);
494 if (apic_parse_mpct(mpct, bypass_cpu_and_ioapics_in_mptables) ==
495 PSM_SUCCESS) {
496 retval = PSM_SUCCESS;
497 goto apic_ret;
498 }
499
500 apic_fail1:
501 psm_unmap_phys(mpct, mpct_size);
502 mpct = NULL;
503
504 apic_ret:
505 if (retval == PSM_SUCCESS) {
506 extern int apic_ioapic_method_probe();
507
508 if ((retval = apic_ioapic_method_probe()) == PSM_SUCCESS)
509 return (PSM_SUCCESS);
510 }
511
512 for (i = 0; i < apic_io_max; i++)
513 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
514 if (apic_cpus) {
515 kmem_free(apic_cpus, apic_cpus_size);
516 apic_cpus = NULL;
517 }
518 if (apicadr) {
519 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
520 apicadr = NULL;
521 }
522 if (mpct)
523 psm_unmap_phys(mpct, mpct_size);
524
525 return (retval);
526 }
527
528 static void
529 apic_set_pwroff_method_from_mpcnfhdr(struct apic_mp_cnf_hdr *hdrp)
530 {
531 int i;
532
533 for (i = 0; i < (sizeof (apic_mps_ids) / sizeof (apic_mps_ids[0]));
534 i++) {
535 if ((strncmp(hdrp->mpcnf_oem_str, apic_mps_ids[i].oem_id,
536 strlen(apic_mps_ids[i].oem_id)) == 0) &&
537 (strncmp(hdrp->mpcnf_prod_str, apic_mps_ids[i].prod_id,
538 strlen(apic_mps_ids[i].prod_id)) == 0)) {
539
540 apic_poweroff_method = apic_mps_ids[i].poweroff_method;
541 break;
542 }
543 }
544
545 if (apic_debug_mps_id != 0) {
546 cmn_err(CE_CONT, "%s: MPS OEM ID = '%c%c%c%c%c%c%c%c'"
547 "Product ID = '%c%c%c%c%c%c%c%c%c%c%c%c'\n",
548 psm_name,
549 hdrp->mpcnf_oem_str[0],
550 hdrp->mpcnf_oem_str[1],
551 hdrp->mpcnf_oem_str[2],
552 hdrp->mpcnf_oem_str[3],
553 hdrp->mpcnf_oem_str[4],
554 hdrp->mpcnf_oem_str[5],
555 hdrp->mpcnf_oem_str[6],
556 hdrp->mpcnf_oem_str[7],
557 hdrp->mpcnf_prod_str[0],
558 hdrp->mpcnf_prod_str[1],
559 hdrp->mpcnf_prod_str[2],
560 hdrp->mpcnf_prod_str[3],
561 hdrp->mpcnf_prod_str[4],
562 hdrp->mpcnf_prod_str[5],
563 hdrp->mpcnf_prod_str[6],
564 hdrp->mpcnf_prod_str[7],
565 hdrp->mpcnf_prod_str[8],
566 hdrp->mpcnf_prod_str[9],
567 hdrp->mpcnf_prod_str[10],
568 hdrp->mpcnf_prod_str[11]);
569 }
570 }
571
572 static void
573 apic_free_apic_cpus(void)
574 {
575 if (apic_cpus != NULL) {
576 kmem_free(apic_cpus, apic_cpus_size);
577 apic_cpus = NULL;
578 apic_cpus_size = 0;
579 }
580 }
581
582 static int
583 acpi_probe(char *modname)
584 {
585 int i, intmax, index;
586 uint32_t id, ver;
587 int acpi_verboseflags = 0;
588 int madt_seen, madt_size;
589 ACPI_SUBTABLE_HEADER *ap;
590 ACPI_MADT_LOCAL_APIC *mpa;
591 ACPI_MADT_LOCAL_X2APIC *mpx2a;
592 ACPI_MADT_IO_APIC *mia;
593 ACPI_MADT_IO_SAPIC *misa;
594 ACPI_MADT_INTERRUPT_OVERRIDE *mio;
595 ACPI_MADT_NMI_SOURCE *mns;
596 ACPI_MADT_INTERRUPT_SOURCE *mis;
597 ACPI_MADT_LOCAL_APIC_NMI *mlan;
598 ACPI_MADT_LOCAL_X2APIC_NMI *mx2alan;
599 ACPI_MADT_LOCAL_APIC_OVERRIDE *mao;
600 int sci;
601 iflag_t sci_flags;
602 volatile uint32_t *ioapic;
603 int ioapic_ix;
604 uint32_t *local_ids;
605 uint32_t *proc_ids;
606 uchar_t hid;
607 int warned = 0;
608
609 if (!apic_use_acpi)
610 return (PSM_FAILURE);
611
612 if (AcpiGetTable(ACPI_SIG_MADT, 1,
613 (ACPI_TABLE_HEADER **) &acpi_mapic_dtp) != AE_OK) {
614 cmn_err(CE_WARN, "!acpi_probe: No MADT found!");
615 return (PSM_FAILURE);
616 }
617
618 apicadr = mapin_apic((uint32_t)acpi_mapic_dtp->Address,
619 APIC_LOCAL_MEMLEN, PROT_READ | PROT_WRITE);
620 if (!apicadr)
621 return (PSM_FAILURE);
622
623 if ((local_ids = kmem_zalloc(NCPU * sizeof (uint32_t),
624 KM_NOSLEEP)) == NULL)
625 return (PSM_FAILURE);
626
627 if ((proc_ids = kmem_zalloc(NCPU * sizeof (uint32_t),
628 KM_NOSLEEP)) == NULL) {
629 kmem_free(local_ids, NCPU * sizeof (uint32_t));
630 return (PSM_FAILURE);
631 }
632
633 id = apic_reg_ops->apic_read(APIC_LID_REG);
634 local_ids[0] = (uchar_t)(id >> 24);
635 apic_nproc = index = 1;
636 apic_io_max = 0;
637
638 ap = (ACPI_SUBTABLE_HEADER *) (acpi_mapic_dtp + 1);
639 madt_size = acpi_mapic_dtp->Header.Length;
640 madt_seen = sizeof (*acpi_mapic_dtp);
641
642 while (madt_seen < madt_size) {
643 switch (ap->Type) {
644 case ACPI_MADT_TYPE_LOCAL_APIC:
645 mpa = (ACPI_MADT_LOCAL_APIC *) ap;
646 if (mpa->LapicFlags & ACPI_MADT_ENABLED) {
647 if (mpa->Id == 255) {
648 cmn_err(CE_WARN, "!%s: encountered "
649 "invalid entry in MADT: CPU %d "
650 "has Local APIC Id equal to 255 ",
651 psm_name, mpa->ProcessorId);
652 }
653 if (mpa->Id == local_ids[0]) {
654 ASSERT(index == 1);
655 proc_ids[0] = mpa->ProcessorId;
656 } else if (apic_nproc < NCPU && use_mp &&
657 apic_nproc < boot_ncpus) {
658 local_ids[index] = mpa->Id;
659 proc_ids[index] = mpa->ProcessorId;
660 index++;
661 apic_nproc++;
662 } else if (apic_nproc == NCPU && !warned) {
663 cmn_err(CE_WARN, "%s: CPU limit "
664 "exceeded"
665 #if !defined(__amd64)
666 " for 32-bit mode"
667 #endif
668 "; Solaris will use %d CPUs.",
669 psm_name, NCPU);
670 warned = 1;
671 }
672 }
673 break;
674
675 case ACPI_MADT_TYPE_IO_APIC:
676 mia = (ACPI_MADT_IO_APIC *) ap;
677 if (apic_io_max < MAX_IO_APIC) {
678 ioapic_ix = apic_io_max;
679 apic_io_id[apic_io_max] = mia->Id;
680 apic_io_vectbase[apic_io_max] =
681 mia->GlobalIrqBase;
682 apic_physaddr[apic_io_max] =
683 (uint32_t)mia->Address;
684 ioapic = apicioadr[apic_io_max] =
685 mapin_ioapic((uint32_t)mia->Address,
686 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
687 if (!ioapic)
688 goto cleanup;
689 ioapic_mask_workaround[apic_io_max] =
690 apic_is_ioapic_AMD_813x(mia->Address);
691 apic_io_max++;
692 }
693 break;
694
695 case ACPI_MADT_TYPE_INTERRUPT_OVERRIDE:
696 mio = (ACPI_MADT_INTERRUPT_OVERRIDE *) ap;
697 if (acpi_isop == NULL)
698 acpi_isop = mio;
699 acpi_iso_cnt++;
700 break;
701
702 case ACPI_MADT_TYPE_NMI_SOURCE:
703 /* UNIMPLEMENTED */
704 mns = (ACPI_MADT_NMI_SOURCE *) ap;
705 if (acpi_nmi_sp == NULL)
706 acpi_nmi_sp = mns;
707 acpi_nmi_scnt++;
708
709 cmn_err(CE_NOTE, "!apic: nmi source: %d 0x%x\n",
710 mns->GlobalIrq, mns->IntiFlags);
711 break;
712
713 case ACPI_MADT_TYPE_LOCAL_APIC_NMI:
714 /* UNIMPLEMENTED */
715 mlan = (ACPI_MADT_LOCAL_APIC_NMI *) ap;
716 if (acpi_nmi_cp == NULL)
717 acpi_nmi_cp = mlan;
718 acpi_nmi_ccnt++;
719
720 cmn_err(CE_NOTE, "!apic: local nmi: %d 0x%x %d\n",
721 mlan->ProcessorId, mlan->IntiFlags,
722 mlan->Lint);
723 break;
724
725 case ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE:
726 /* UNIMPLEMENTED */
727 mao = (ACPI_MADT_LOCAL_APIC_OVERRIDE *) ap;
728 cmn_err(CE_NOTE, "!apic: address override: %lx\n",
729 (long)mao->Address);
730 break;
731
732 case ACPI_MADT_TYPE_IO_SAPIC:
733 /* UNIMPLEMENTED */
734 misa = (ACPI_MADT_IO_SAPIC *) ap;
735
736 cmn_err(CE_NOTE, "!apic: io sapic: %d %d %lx\n",
737 misa->Id, misa->GlobalIrqBase,
738 (long)misa->Address);
739 break;
740
741 case ACPI_MADT_TYPE_INTERRUPT_SOURCE:
742 /* UNIMPLEMENTED */
743 mis = (ACPI_MADT_INTERRUPT_SOURCE *) ap;
744
745 cmn_err(CE_NOTE,
746 "!apic: irq source: %d %d %d 0x%x %d %d\n",
747 mis->Id, mis->Eid, mis->GlobalIrq,
748 mis->IntiFlags, mis->Type,
749 mis->IoSapicVector);
750 break;
751
752 case ACPI_MADT_TYPE_LOCAL_X2APIC:
753 mpx2a = (ACPI_MADT_LOCAL_X2APIC *) ap;
754
755 /*
756 * All logical processors with APIC ID values
757 * of 255 and greater will have their APIC
758 * reported through Processor X2APIC structure.
759 * All logical processors with APIC ID less than
760 * 255 will have their APIC reported through
761 * Processor Local APIC.
762 *
763 * Some systems apparently don't care and report all
764 * processors through Processor X2APIC structures. We
765 * warn about that but don't ignore those CPUs.
766 */
767 if (mpx2a->LocalApicId < 255) {
768 cmn_err(CE_WARN, "!%s: ignoring invalid entry "
769 "in MADT: CPU %d has X2APIC Id %d (< 255)",
770 psm_name, mpx2a->Uid, mpx2a->LocalApicId);
771 }
772 if (mpx2a->LapicFlags & ACPI_MADT_ENABLED) {
773 if (mpx2a->LocalApicId == local_ids[0]) {
774 ASSERT(index == 1);
775 proc_ids[0] = mpx2a->Uid;
776 } else if (apic_nproc < NCPU && use_mp &&
777 apic_nproc < boot_ncpus) {
778 local_ids[index] = mpx2a->LocalApicId;
779 proc_ids[index] = mpx2a->Uid;
780 index++;
781 apic_nproc++;
782 } else if (apic_nproc == NCPU && !warned) {
783 cmn_err(CE_WARN, "%s: CPU limit "
784 "exceeded"
785 #if !defined(__amd64)
786 " for 32-bit mode"
787 #endif
788 "; Solaris will use %d CPUs.",
789 psm_name, NCPU);
790 warned = 1;
791 }
792 }
793
794 break;
795
796 case ACPI_MADT_TYPE_LOCAL_X2APIC_NMI:
797 /* UNIMPLEMENTED */
798 mx2alan = (ACPI_MADT_LOCAL_X2APIC_NMI *) ap;
799 if (mx2alan->Uid >> 8)
800 acpi_nmi_ccnt++;
801
802 #ifdef DEBUG
803 cmn_err(CE_NOTE,
804 "!apic: local x2apic nmi: %d 0x%x %d\n",
805 mx2alan->Uid, mx2alan->IntiFlags, mx2alan->Lint);
806 #endif
807
808 break;
809
810 case ACPI_MADT_TYPE_RESERVED:
811 default:
812 break;
813 }
814
815 /* advance to next entry */
816 madt_seen += ap->Length;
817 ap = (ACPI_SUBTABLE_HEADER *)(((char *)ap) + ap->Length);
818 }
819
820 /* We found multiple enabled cpus via MADT */
821 if ((apic_nproc > 1) && (apic_io_max > 0)) {
822 acpi_found_smp_config = B_TRUE;
823 cmn_err(CE_NOTE,
824 "!apic: Using ACPI (MADT) for SMP configuration");
825 }
826
827 /*
828 * allocate enough space for possible hot-adding of CPUs.
829 * max_ncpus may be less than apic_nproc if it's set by user.
830 */
831 if (plat_dr_support_cpu()) {
832 apic_max_nproc = max_ncpus;
833 }
834 apic_cpus_size = max(apic_nproc, max_ncpus) * sizeof (*apic_cpus);
835 if ((apic_cpus = kmem_zalloc(apic_cpus_size, KM_NOSLEEP)) == NULL)
836 goto cleanup;
837
838 /*
839 * ACPI doesn't provide the local apic ver, get it directly from the
840 * local apic
841 */
842 ver = apic_reg_ops->apic_read(APIC_VERS_REG);
843 for (i = 0; i < apic_nproc; i++) {
844 apic_cpus[i].aci_local_id = local_ids[i];
845 apic_cpus[i].aci_local_ver = (uchar_t)(ver & 0xFF);
846 apic_cpus[i].aci_processor_id = proc_ids[i];
847 /* Only build mapping info for CPUs present at boot. */
848 if (i < boot_ncpus)
849 (void) acpica_map_cpu(i, proc_ids[i]);
850 }
851
852 /*
853 * To support CPU dynamic reconfiguration, the apic CPU info structure
854 * for each possible CPU will be pre-allocated at boot time.
855 * The state for each apic CPU info structure will be assigned according
856 * to the following rules:
857 * Rule 1:
858 * Slot index range: [0, min(apic_nproc, boot_ncpus))
859 * State flags: 0
860 * Note: cpu exists and will be configured/enabled at boot time
861 * Rule 2:
862 * Slot index range: [boot_ncpus, apic_nproc)
863 * State flags: APIC_CPU_FREE | APIC_CPU_DIRTY
864 * Note: cpu exists but won't be configured/enabled at boot time
865 * Rule 3:
866 * Slot index range: [apic_nproc, boot_ncpus)
867 * State flags: APIC_CPU_FREE
868 * Note: cpu doesn't exist at boot time
869 * Rule 4:
870 * Slot index range: [max(apic_nproc, boot_ncpus), max_ncpus)
871 * State flags: APIC_CPU_FREE
872 * Note: cpu doesn't exist at boot time
873 */
874 CPUSET_ZERO(apic_cpumask);
875 for (i = 0; i < min(boot_ncpus, apic_nproc); i++) {
876 CPUSET_ADD(apic_cpumask, i);
877 apic_cpus[i].aci_status = 0;
878 }
879 for (i = boot_ncpus; i < apic_nproc; i++) {
880 apic_cpus[i].aci_status = APIC_CPU_FREE | APIC_CPU_DIRTY;
881 }
882 for (i = apic_nproc; i < boot_ncpus; i++) {
883 apic_cpus[i].aci_status = APIC_CPU_FREE;
884 }
885 for (i = max(boot_ncpus, apic_nproc); i < max_ncpus; i++) {
886 apic_cpus[i].aci_status = APIC_CPU_FREE;
887 }
888
889 for (i = 0; i < apic_io_max; i++) {
890 ioapic_ix = i;
891
892 /*
893 * need to check Sitka on the following acpi problem
894 * On the Sitka, the ioapic's apic_id field isn't reporting
895 * the actual io apic id. We have reported this problem
896 * to Intel. Until they fix the problem, we will get the
897 * actual id directly from the ioapic.
898 */
899 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
900 hid = (uchar_t)(id >> 24);
901
902 if (hid != apic_io_id[i]) {
903 if (apic_io_id[i] == 0)
904 apic_io_id[i] = hid;
905 else { /* set ioapic id to whatever reported by ACPI */
906 id = ((uint32_t)apic_io_id[i]) << 24;
907 ioapic_write(ioapic_ix, APIC_ID_CMD, id);
908 }
909 }
910 ver = ioapic_read(ioapic_ix, APIC_VERS_CMD);
911 apic_io_ver[i] = (uchar_t)(ver & 0xff);
912 intmax = (ver >> 16) & 0xff;
913 apic_io_vectend[i] = apic_io_vectbase[i] + intmax;
914 if (apic_first_avail_irq <= apic_io_vectend[i])
915 apic_first_avail_irq = apic_io_vectend[i] + 1;
916 }
917
918
919 /*
920 * Process SCI configuration here
921 * An error may be returned here if
922 * acpi-user-options specifies legacy mode
923 * (no SCI, no ACPI mode)
924 */
925 if (acpica_get_sci(&sci, &sci_flags) != AE_OK)
926 sci = -1;
927
928 /*
929 * Now call acpi_init() to generate namespaces
930 * If this fails, we don't attempt to use ACPI
931 * even if we were able to get a MADT above
932 */
933 if (acpica_init() != AE_OK) {
934 cmn_err(CE_WARN, "!apic: Failed to initialize acpica!");
935 goto cleanup;
936 }
937
938 /*
939 * Call acpica_build_processor_map() now that we have
940 * ACPI namesspace access
941 */
942 (void) acpica_build_processor_map();
943
944 /*
945 * Squirrel away the SCI and flags for later on
946 * in apic_picinit() when we're ready
947 */
948 apic_sci_vect = sci;
949 apic_sci_flags = sci_flags;
950
951 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG)
952 acpi_verboseflags |= PSM_VERBOSE_IRQ_FLAG;
953
954 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG)
955 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_FLAG;
956
957 if (apic_verbose & APIC_VERBOSE_POWEROFF_PAUSE_FLAG)
958 acpi_verboseflags |= PSM_VERBOSE_POWEROFF_PAUSE_FLAG;
959
960 if (acpi_psm_init(modname, acpi_verboseflags) == ACPI_PSM_FAILURE)
961 goto cleanup;
962
963 /* Enable ACPI APIC interrupt routing */
964 if (apic_acpi_enter_apicmode() != PSM_FAILURE) {
965 cmn_err(CE_NOTE, "!apic: Using APIC interrupt routing mode");
966 build_reserved_irqlist((uchar_t *)apic_reserved_irqlist);
967 apic_enable_acpi = 1;
968 if (apic_sci_vect > 0) {
969 acpica_set_core_feature(ACPI_FEATURE_SCI_EVENT);
970 }
971 if (apic_use_acpi_madt_only) {
972 cmn_err(CE_CONT,
973 "?Using ACPI for CPU/IOAPIC information ONLY\n");
974 }
975
976 /*
977 * probe ACPI for hpet information here which is used later
978 * in apic_picinit().
979 */
980 if (hpet_acpi_init(&apic_hpet_vect, &apic_hpet_flags) < 0) {
981 cmn_err(CE_NOTE, "!ACPI HPET table query failed\n");
982 }
983
984 kmem_free(local_ids, NCPU * sizeof (uint32_t));
985 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
986 return (PSM_SUCCESS);
987 }
988 /* if setting APIC mode failed above, we fall through to cleanup */
989
990 cleanup:
991 cmn_err(CE_WARN, "!apic: Failed acpi_probe, SMP config was %s",
992 acpi_found_smp_config ? "found" : "not found");
993 apic_free_apic_cpus();
994 if (apicadr != NULL) {
995 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
996 apicadr = NULL;
997 }
998 apic_max_nproc = -1;
999 apic_nproc = 0;
1000 for (i = 0; i < apic_io_max; i++) {
1001 mapout_ioapic((caddr_t)apicioadr[i], APIC_IO_MEMLEN);
1002 apicioadr[i] = NULL;
1003 }
1004 apic_io_max = 0;
1005 acpi_isop = NULL;
1006 acpi_iso_cnt = 0;
1007 acpi_nmi_sp = NULL;
1008 acpi_nmi_scnt = 0;
1009 acpi_nmi_cp = NULL;
1010 acpi_nmi_ccnt = 0;
1011 acpi_found_smp_config = B_FALSE;
1012 kmem_free(local_ids, NCPU * sizeof (uint32_t));
1013 kmem_free(proc_ids, NCPU * sizeof (uint32_t));
1014 return (PSM_FAILURE);
1015 }
1016
1017 /*
1018 * Handle default configuration. Fill in reqd global variables & tables
1019 * Fill all details as MP table does not give any more info
1020 */
1021 static int
1022 apic_handle_defconf()
1023 {
1024 uint_t lid;
1025
1026 /* Failed to probe ACPI MADT tables, disable CPU DR. */
1027 apic_max_nproc = -1;
1028 apic_free_apic_cpus();
1029 plat_dr_disable_cpu();
1030
1031 apicioadr[0] = (void *)mapin_ioapic(APIC_IO_ADDR,
1032 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1033 apicadr = (void *)psm_map_phys(APIC_LOCAL_ADDR,
1034 APIC_LOCAL_MEMLEN, PROT_READ);
1035 apic_cpus_size = 2 * sizeof (*apic_cpus);
1036 apic_cpus = (apic_cpus_info_t *)
1037 kmem_zalloc(apic_cpus_size, KM_NOSLEEP);
1038 if ((!apicadr) || (!apicioadr[0]) || (!apic_cpus))
1039 goto apic_handle_defconf_fail;
1040 CPUSET_ONLY(apic_cpumask, 0);
1041 CPUSET_ADD(apic_cpumask, 1);
1042 apic_nproc = 2;
1043 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1044 apic_cpus[0].aci_local_id = (uchar_t)(lid >> APIC_ID_BIT_OFFSET);
1045 /*
1046 * According to the PC+MP spec 1.1, the local ids
1047 * for the default configuration has to be 0 or 1
1048 */
1049 if (apic_cpus[0].aci_local_id == 1)
1050 apic_cpus[1].aci_local_id = 0;
1051 else if (apic_cpus[0].aci_local_id == 0)
1052 apic_cpus[1].aci_local_id = 1;
1053 else
1054 goto apic_handle_defconf_fail;
1055
1056 apic_io_id[0] = 2;
1057 apic_io_max = 1;
1058 if (apic_defconf >= 5) {
1059 apic_cpus[0].aci_local_ver = APIC_INTEGRATED_VERS;
1060 apic_cpus[1].aci_local_ver = APIC_INTEGRATED_VERS;
1061 apic_io_ver[0] = APIC_INTEGRATED_VERS;
1062 } else {
1063 apic_cpus[0].aci_local_ver = 0; /* 82489 DX */
1064 apic_cpus[1].aci_local_ver = 0;
1065 apic_io_ver[0] = 0;
1066 }
1067 if (apic_defconf == 2 || apic_defconf == 3 || apic_defconf == 6)
1068 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1069 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1070 return (PSM_SUCCESS);
1071
1072 apic_handle_defconf_fail:
1073 if (apicadr)
1074 mapout_apic((caddr_t)apicadr, APIC_LOCAL_MEMLEN);
1075 if (apicioadr[0])
1076 mapout_ioapic((caddr_t)apicioadr[0], APIC_IO_MEMLEN);
1077 return (PSM_FAILURE);
1078 }
1079
1080 /* Parse the entries in MP configuration table and collect info that we need */
1081 static int
1082 apic_parse_mpct(caddr_t mpct, int bypass_cpus_and_ioapics)
1083 {
1084 struct apic_procent *procp;
1085 struct apic_bus *busp;
1086 struct apic_io_entry *ioapicp;
1087 struct apic_io_intr *intrp;
1088 int ioapic_ix;
1089 uint_t lid;
1090 uint32_t id;
1091 uchar_t hid;
1092 int warned = 0;
1093
1094 /*LINTED: pointer cast may result in improper alignment */
1095 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1096
1097 /* No need to count cpu entries if we won't use them */
1098 if (!bypass_cpus_and_ioapics) {
1099
1100 /* Find max # of CPUS and allocate structure accordingly */
1101 apic_nproc = 0;
1102 CPUSET_ZERO(apic_cpumask);
1103 while (procp->proc_entry == APIC_CPU_ENTRY) {
1104 if (procp->proc_cpuflags & CPUFLAGS_EN) {
1105 if (apic_nproc < NCPU && use_mp &&
1106 apic_nproc < boot_ncpus) {
1107 CPUSET_ADD(apic_cpumask, apic_nproc);
1108 apic_nproc++;
1109 } else if (apic_nproc == NCPU && !warned) {
1110 cmn_err(CE_WARN, "%s: CPU limit "
1111 "exceeded"
1112 #if !defined(__amd64)
1113 " for 32-bit mode"
1114 #endif
1115 "; Solaris will use %d CPUs.",
1116 psm_name, NCPU);
1117 warned = 1;
1118 }
1119
1120 }
1121 procp++;
1122 }
1123 apic_cpus_size = apic_nproc * sizeof (*apic_cpus);
1124 if (!apic_nproc || !(apic_cpus = (apic_cpus_info_t *)
1125 kmem_zalloc(apic_cpus_size, KM_NOSLEEP)))
1126 return (PSM_FAILURE);
1127 }
1128
1129 /*LINTED: pointer cast may result in improper alignment */
1130 procp = (struct apic_procent *)(mpct + sizeof (struct apic_mp_cnf_hdr));
1131
1132 /*
1133 * start with index 1 as 0 needs to be filled in with Boot CPU, but
1134 * if we're bypassing this information, it has already been filled
1135 * in by acpi_probe(), so don't overwrite it.
1136 */
1137 if (!bypass_cpus_and_ioapics)
1138 apic_nproc = 1;
1139
1140 while (procp->proc_entry == APIC_CPU_ENTRY) {
1141 /* check whether the cpu exists or not */
1142 if (!bypass_cpus_and_ioapics &&
1143 procp->proc_cpuflags & CPUFLAGS_EN) {
1144 if (procp->proc_cpuflags & CPUFLAGS_BP) { /* Boot CPU */
1145 lid = apic_reg_ops->apic_read(APIC_LID_REG);
1146 apic_cpus[0].aci_local_id = procp->proc_apicid;
1147 if (apic_cpus[0].aci_local_id !=
1148 (uchar_t)(lid >> APIC_ID_BIT_OFFSET)) {
1149 return (PSM_FAILURE);
1150 }
1151 apic_cpus[0].aci_local_ver =
1152 procp->proc_version;
1153 } else if (apic_nproc < NCPU && use_mp &&
1154 apic_nproc < boot_ncpus) {
1155 apic_cpus[apic_nproc].aci_local_id =
1156 procp->proc_apicid;
1157
1158 apic_cpus[apic_nproc].aci_local_ver =
1159 procp->proc_version;
1160 apic_nproc++;
1161
1162 }
1163 }
1164 procp++;
1165 }
1166
1167 /*
1168 * Save start of bus entries for later use.
1169 * Get EISA level cntrl if EISA bus is present.
1170 * Also get the CPI bus id for single CPI bus case
1171 */
1172 apic_busp = busp = (struct apic_bus *)procp;
1173 while (busp->bus_entry == APIC_BUS_ENTRY) {
1174 lid = apic_find_bus_type((char *)&busp->bus_str1);
1175 if (lid == BUS_EISA) {
1176 eisa_level_intr_mask = (inb(EISA_LEVEL_CNTL + 1) << 8) |
1177 inb(EISA_LEVEL_CNTL) | ((uint_t)INT32_MAX + 1);
1178 } else if (lid == BUS_PCI) {
1179 /*
1180 * apic_single_pci_busid will be used only if
1181 * apic_pic_bus_total is equal to 1
1182 */
1183 apic_pci_bus_total++;
1184 apic_single_pci_busid = busp->bus_id;
1185 }
1186 busp++;
1187 }
1188
1189 ioapicp = (struct apic_io_entry *)busp;
1190
1191 if (!bypass_cpus_and_ioapics)
1192 apic_io_max = 0;
1193 do {
1194 if (!bypass_cpus_and_ioapics && apic_io_max < MAX_IO_APIC) {
1195 if (ioapicp->io_flags & IOAPIC_FLAGS_EN) {
1196 apic_io_id[apic_io_max] = ioapicp->io_apicid;
1197 apic_io_ver[apic_io_max] = ioapicp->io_version;
1198 apicioadr[apic_io_max] =
1199 (void *)mapin_ioapic(
1200 (uint32_t)ioapicp->io_apic_addr,
1201 APIC_IO_MEMLEN, PROT_READ | PROT_WRITE);
1202
1203 if (!apicioadr[apic_io_max])
1204 return (PSM_FAILURE);
1205
1206 ioapic_mask_workaround[apic_io_max] =
1207 apic_is_ioapic_AMD_813x(
1208 ioapicp->io_apic_addr);
1209
1210 ioapic_ix = apic_io_max;
1211 id = ioapic_read(ioapic_ix, APIC_ID_CMD);
1212 hid = (uchar_t)(id >> 24);
1213
1214 if (hid != apic_io_id[apic_io_max]) {
1215 if (apic_io_id[apic_io_max] == 0)
1216 apic_io_id[apic_io_max] = hid;
1217 else {
1218 /*
1219 * set ioapic id to whatever
1220 * reported by MPS
1221 *
1222 * may not need to set index
1223 * again ???
1224 * take it out and try
1225 */
1226
1227 id = ((uint32_t)
1228 apic_io_id[apic_io_max]) <<
1229 24;
1230
1231 ioapic_write(ioapic_ix,
1232 APIC_ID_CMD, id);
1233 }
1234 }
1235 apic_io_max++;
1236 }
1237 }
1238 ioapicp++;
1239 } while (ioapicp->io_entry == APIC_IO_ENTRY);
1240
1241 apic_io_intrp = (struct apic_io_intr *)ioapicp;
1242
1243 intrp = apic_io_intrp;
1244 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1245 if ((intrp->intr_irq > APIC_MAX_ISA_IRQ) ||
1246 (apic_find_bus(intrp->intr_busid) == BUS_PCI)) {
1247 apic_irq_translate = 1;
1248 break;
1249 }
1250 intrp++;
1251 }
1252
1253 return (PSM_SUCCESS);
1254 }
1255
1256 boolean_t
1257 apic_cpu_in_range(int cpu)
1258 {
1259 cpu &= ~IRQ_USER_BOUND;
1260 /* Check whether cpu id is in valid range. */
1261 if (cpu < 0 || cpu >= apic_nproc) {
1262 return (B_FALSE);
1263 } else if (apic_max_nproc != -1 && cpu >= apic_max_nproc) {
1264 /*
1265 * Check whether cpuid is in valid range if CPU DR is enabled.
1266 */
1267 return (B_FALSE);
1268 } else if (!CPU_IN_SET(apic_cpumask, cpu)) {
1269 return (B_FALSE);
1270 }
1271
1272 return (B_TRUE);
1273 }
1274
1275 processorid_t
1276 apic_get_next_bind_cpu(void)
1277 {
1278 int i, count;
1279 processorid_t cpuid = 0;
1280
1281 for (count = 0; count < apic_nproc; count++) {
1282 if (apic_next_bind_cpu >= apic_nproc) {
1283 apic_next_bind_cpu = 0;
1284 }
1285 i = apic_next_bind_cpu++;
1286 if (apic_cpu_in_range(i)) {
1287 cpuid = i;
1288 break;
1289 }
1290 }
1291
1292 return (cpuid);
1293 }
1294
1295 uint16_t
1296 apic_get_apic_version()
1297 {
1298 int i;
1299 uchar_t min_io_apic_ver = 0;
1300 static uint16_t version; /* Cache as value is constant */
1301 static boolean_t found = B_FALSE; /* Accomodate zero version */
1302
1303 if (found == B_FALSE) {
1304 found = B_TRUE;
1305
1306 /*
1307 * Don't assume all IO APICs in the system are the same.
1308 *
1309 * Set to the minimum version.
1310 */
1311 for (i = 0; i < apic_io_max; i++) {
1312 if ((apic_io_ver[i] != 0) &&
1313 ((min_io_apic_ver == 0) ||
1314 (min_io_apic_ver >= apic_io_ver[i])))
1315 min_io_apic_ver = apic_io_ver[i];
1316 }
1317
1318 /* Assume all local APICs are of the same version. */
1319 version = (min_io_apic_ver << 8) | apic_cpus[0].aci_local_ver;
1320 }
1321 return (version);
1322 }
1323
1324 static struct apic_mpfps_hdr *
1325 apic_find_fps_sig(caddr_t cptr, int len)
1326 {
1327 int i;
1328
1329 /* Look for the pattern "_MP_" */
1330 for (i = 0; i < len; i += 16) {
1331 if ((*(cptr+i) == '_') &&
1332 (*(cptr+i+1) == 'M') &&
1333 (*(cptr+i+2) == 'P') &&
1334 (*(cptr+i+3) == '_'))
1335 /*LINTED: pointer cast may result in improper alignment */
1336 return ((struct apic_mpfps_hdr *)(cptr + i));
1337 }
1338 return (NULL);
1339 }
1340
1341 static int
1342 apic_checksum(caddr_t bptr, int len)
1343 {
1344 int i;
1345 uchar_t cksum;
1346
1347 cksum = 0;
1348 for (i = 0; i < len; i++)
1349 cksum += *bptr++;
1350 return ((int)cksum);
1351 }
1352
1353 /*
1354 * On machines with PCI-PCI bridges, a device behind a PCI-PCI bridge
1355 * needs special handling. We may need to chase up the device tree,
1356 * using the PCI-PCI Bridge specification's "rotating IPIN assumptions",
1357 * to find the IPIN at the root bus that relates to the IPIN on the
1358 * subsidiary bus (for ACPI or MP). We may, however, have an entry
1359 * in the MP table or the ACPI namespace for this device itself.
1360 * We handle both cases in the search below.
1361 */
1362 /* this is the non-acpi version */
1363 int
1364 apic_handle_pci_pci_bridge(dev_info_t *idip, int child_devno, int child_ipin,
1365 struct apic_io_intr **intrp)
1366 {
1367 dev_info_t *dipp, *dip;
1368 int pci_irq;
1369 ddi_acc_handle_t cfg_handle;
1370 int bridge_devno, bridge_bus;
1371 int ipin;
1372
1373 dip = idip;
1374
1375 /*CONSTCOND*/
1376 while (1) {
1377 if (((dipp = ddi_get_parent(dip)) == (dev_info_t *)NULL) ||
1378 (pci_config_setup(dipp, &cfg_handle) != DDI_SUCCESS))
1379 return (-1);
1380 if ((pci_config_get8(cfg_handle, PCI_CONF_BASCLASS) ==
1381 PCI_CLASS_BRIDGE) && (pci_config_get8(cfg_handle,
1382 PCI_CONF_SUBCLASS) == PCI_BRIDGE_PCI)) {
1383 pci_config_teardown(&cfg_handle);
1384 if (acpica_get_bdf(dipp, &bridge_bus, &bridge_devno,
1385 NULL) != 0)
1386 return (-1);
1387 /*
1388 * This is the rotating scheme documented in the
1389 * PCI-to-PCI spec. If the PCI-to-PCI bridge is
1390 * behind another PCI-to-PCI bridge, then it needs
1391 * to keep ascending until an interrupt entry is
1392 * found or the root is reached.
1393 */
1394 ipin = (child_devno + child_ipin) % PCI_INTD;
1395 if (bridge_bus == 0 && apic_pci_bus_total == 1)
1396 bridge_bus = (int)apic_single_pci_busid;
1397 pci_irq = ((bridge_devno & 0x1f) << 2) |
1398 (ipin & 0x3);
1399 if ((*intrp = apic_find_io_intr_w_busid(pci_irq,
1400 bridge_bus)) != NULL) {
1401 return (pci_irq);
1402 }
1403 dip = dipp;
1404 child_devno = bridge_devno;
1405 child_ipin = ipin;
1406 } else {
1407 pci_config_teardown(&cfg_handle);
1408 return (-1);
1409 }
1410 }
1411 /*LINTED: function will not fall off the bottom */
1412 }
1413
1414 uchar_t
1415 acpi_find_ioapic(int irq)
1416 {
1417 int i;
1418
1419 for (i = 0; i < apic_io_max; i++) {
1420 if (irq >= apic_io_vectbase[i] && irq <= apic_io_vectend[i])
1421 return ((uchar_t)i);
1422 }
1423 return (0xFF); /* shouldn't happen */
1424 }
1425
1426 /*
1427 * See if two irqs are compatible for sharing a vector.
1428 * Currently we only support sharing of PCI devices.
1429 */
1430 static int
1431 acpi_intr_compatible(iflag_t iflag1, iflag_t iflag2)
1432 {
1433 uint_t level1, po1;
1434 uint_t level2, po2;
1435
1436 /* Assume active high by default */
1437 po1 = 0;
1438 po2 = 0;
1439
1440 if (iflag1.bustype != iflag2.bustype || iflag1.bustype != BUS_PCI)
1441 return (0);
1442
1443 if (iflag1.intr_el == INTR_EL_CONFORM)
1444 level1 = AV_LEVEL;
1445 else
1446 level1 = (iflag1.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1447
1448 if (level1 && ((iflag1.intr_po == INTR_PO_ACTIVE_LOW) ||
1449 (iflag1.intr_po == INTR_PO_CONFORM)))
1450 po1 = AV_ACTIVE_LOW;
1451
1452 if (iflag2.intr_el == INTR_EL_CONFORM)
1453 level2 = AV_LEVEL;
1454 else
1455 level2 = (iflag2.intr_el == INTR_EL_LEVEL) ? AV_LEVEL : 0;
1456
1457 if (level2 && ((iflag2.intr_po == INTR_PO_ACTIVE_LOW) ||
1458 (iflag2.intr_po == INTR_PO_CONFORM)))
1459 po2 = AV_ACTIVE_LOW;
1460
1461 if ((level1 == level2) && (po1 == po2))
1462 return (1);
1463
1464 return (0);
1465 }
1466
1467 struct apic_io_intr *
1468 apic_find_io_intr_w_busid(int irqno, int busid)
1469 {
1470 struct apic_io_intr *intrp;
1471
1472 /*
1473 * It can have more than 1 entry with same source bus IRQ,
1474 * but unique with the source bus id
1475 */
1476 intrp = apic_io_intrp;
1477 if (intrp != NULL) {
1478 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1479 if (intrp->intr_irq == irqno &&
1480 intrp->intr_busid == busid &&
1481 intrp->intr_type == IO_INTR_INT)
1482 return (intrp);
1483 intrp++;
1484 }
1485 }
1486 APIC_VERBOSE_IOAPIC((CE_NOTE, "Did not find io intr for irqno:"
1487 "busid %x:%x\n", irqno, busid));
1488 return (NULL);
1489 }
1490
1491
1492 struct mps_bus_info {
1493 char *bus_name;
1494 int bus_id;
1495 } bus_info_array[] = {
1496 "ISA ", BUS_ISA,
1497 "PCI ", BUS_PCI,
1498 "EISA ", BUS_EISA,
1499 "XPRESS", BUS_XPRESS,
1500 "PCMCIA", BUS_PCMCIA,
1501 "VL ", BUS_VL,
1502 "CBUS ", BUS_CBUS,
1503 "CBUSII", BUS_CBUSII,
1504 "FUTURE", BUS_FUTURE,
1505 "INTERN", BUS_INTERN,
1506 "MBI ", BUS_MBI,
1507 "MBII ", BUS_MBII,
1508 "MPI ", BUS_MPI,
1509 "MPSA ", BUS_MPSA,
1510 "NUBUS ", BUS_NUBUS,
1511 "TC ", BUS_TC,
1512 "VME ", BUS_VME,
1513 "PCI-E ", BUS_PCIE
1514 };
1515
1516 static int
1517 apic_find_bus_type(char *bus)
1518 {
1519 int i = 0;
1520
1521 for (; i < sizeof (bus_info_array)/sizeof (struct mps_bus_info); i++)
1522 if (strncmp(bus, bus_info_array[i].bus_name,
1523 strlen(bus_info_array[i].bus_name)) == 0)
1524 return (bus_info_array[i].bus_id);
1525 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus type for bus %s", bus));
1526 return (0);
1527 }
1528
1529 static int
1530 apic_find_bus(int busid)
1531 {
1532 struct apic_bus *busp;
1533
1534 busp = apic_busp;
1535 while (busp->bus_entry == APIC_BUS_ENTRY) {
1536 if (busp->bus_id == busid)
1537 return (apic_find_bus_type((char *)&busp->bus_str1));
1538 busp++;
1539 }
1540 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus for bus id %x", busid));
1541 return (0);
1542 }
1543
1544 int
1545 apic_find_bus_id(int bustype)
1546 {
1547 struct apic_bus *busp;
1548
1549 busp = apic_busp;
1550 while (busp->bus_entry == APIC_BUS_ENTRY) {
1551 if (apic_find_bus_type((char *)&busp->bus_str1) == bustype)
1552 return (busp->bus_id);
1553 busp++;
1554 }
1555 APIC_VERBOSE_IOAPIC((CE_WARN, "Did not find bus id for bustype %x",
1556 bustype));
1557 return (-1);
1558 }
1559
1560 /*
1561 * Check if a particular irq need to be reserved for any io_intr
1562 */
1563 static struct apic_io_intr *
1564 apic_find_io_intr(int irqno)
1565 {
1566 struct apic_io_intr *intrp;
1567
1568 intrp = apic_io_intrp;
1569 if (intrp != NULL) {
1570 while (intrp->intr_entry == APIC_IO_INTR_ENTRY) {
1571 if (intrp->intr_irq == irqno &&
1572 intrp->intr_type == IO_INTR_INT)
1573 return (intrp);
1574 intrp++;
1575 }
1576 }
1577 return (NULL);
1578 }
1579
1580 /*
1581 * Check if the given ioapicindex intin combination has already been assigned
1582 * an irq. If so return irqno. Else -1
1583 */
1584 int
1585 apic_find_intin(uchar_t ioapic, uchar_t intin)
1586 {
1587 apic_irq_t *irqptr;
1588 int i;
1589
1590 /* find ioapic and intin in the apic_irq_table[] and return the index */
1591 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) {
1592 irqptr = apic_irq_table[i];
1593 while (irqptr) {
1594 if ((irqptr->airq_mps_intr_index >= 0) &&
1595 (irqptr->airq_intin_no == intin) &&
1596 (irqptr->airq_ioapicindex == ioapic)) {
1597 APIC_VERBOSE_IOAPIC((CE_NOTE, "!Found irq "
1598 "entry for ioapic:intin %x:%x "
1599 "shared interrupts ?", ioapic, intin));
1600 return (i);
1601 }
1602 irqptr = irqptr->airq_next;
1603 }
1604 }
1605 return (-1);
1606 }
1607
1608 int
1609 apic_allocate_irq(int irq)
1610 {
1611 int freeirq, i;
1612
1613 if ((freeirq = apic_find_free_irq(irq, (APIC_RESV_IRQ - 1))) == -1)
1614 if ((freeirq = apic_find_free_irq(APIC_FIRST_FREE_IRQ,
1615 (irq - 1))) == -1) {
1616 /*
1617 * if BIOS really defines every single irq in the mps
1618 * table, then don't worry about conflicting with
1619 * them, just use any free slot in apic_irq_table
1620 */
1621 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) {
1622 if ((apic_irq_table[i] == NULL) ||
1623 apic_irq_table[i]->airq_mps_intr_index ==
1624 FREE_INDEX) {
1625 freeirq = i;
1626 break;
1627 }
1628 }
1629 if (freeirq == -1) {
1630 /* This shouldn't happen, but just in case */
1631 cmn_err(CE_WARN, "%s: NO available IRQ", psm_name);
1632 return (-1);
1633 }
1634 }
1635 if (apic_irq_table[freeirq] == NULL) {
1636 apic_irq_table[freeirq] =
1637 kmem_zalloc(sizeof (apic_irq_t), KM_NOSLEEP);
1638 if (apic_irq_table[freeirq] == NULL) {
1639 cmn_err(CE_WARN, "%s: NO memory to allocate IRQ",
1640 psm_name);
1641 return (-1);
1642 }
1643 apic_irq_table[freeirq]->airq_temp_cpu = IRQ_UNINIT;
1644 apic_irq_table[freeirq]->airq_mps_intr_index = FREE_INDEX;
1645 }
1646 return (freeirq);
1647 }
1648
1649 static int
1650 apic_find_free_irq(int start, int end)
1651 {
1652 int i;
1653
1654 for (i = start; i <= end; i++)
1655 /* Check if any I/O entry needs this IRQ */
1656 if (apic_find_io_intr(i) == NULL) {
1657 /* Then see if it is free */
1658 if ((apic_irq_table[i] == NULL) ||
1659 (apic_irq_table[i]->airq_mps_intr_index ==
1660 FREE_INDEX)) {
1661 return (i);
1662 }
1663 }
1664 return (-1);
1665 }
1666
1667 /*
1668 * compute the polarity, trigger mode and vector for programming into
1669 * the I/O apic and record in airq_rdt_entry.
1670 */
1671 void
1672 apic_record_rdt_entry(apic_irq_t *irqptr, int irq)
1673 {
1674 int ioapicindex, bus_type, vector;
1675 short intr_index;
1676 uint_t level, po, io_po;
1677 struct apic_io_intr *iointrp;
1678
1679 intr_index = irqptr->airq_mps_intr_index;
1680 DDI_INTR_IMPLDBG((CE_CONT, "apic_record_rdt_entry: intr_index=%d "
1681 "irq = 0x%x dip = 0x%p vector = 0x%x\n", intr_index, irq,
1682 (void *)irqptr->airq_dip, irqptr->airq_vector));
1683
1684 if (intr_index == RESERVE_INDEX) {
1685 apic_error |= APIC_ERR_INVALID_INDEX;
1686 return;
1687 } else if (APIC_IS_MSI_OR_MSIX_INDEX(intr_index)) {
1688 return;
1689 }
1690
1691 vector = irqptr->airq_vector;
1692 ioapicindex = irqptr->airq_ioapicindex;
1693 /* Assume edge triggered by default */
1694 level = 0;
1695 /* Assume active high by default */
1696 po = 0;
1697
1698 if (intr_index == DEFAULT_INDEX || intr_index == FREE_INDEX) {
1699 ASSERT(irq < 16);
1700 if (eisa_level_intr_mask & (1 << irq))
1701 level = AV_LEVEL;
1702 if (intr_index == FREE_INDEX && apic_defconf == 0)
1703 apic_error |= APIC_ERR_INVALID_INDEX;
1704 } else if (intr_index == ACPI_INDEX) {
1705 bus_type = irqptr->airq_iflag.bustype;
1706 if (irqptr->airq_iflag.intr_el == INTR_EL_CONFORM) {
1707 if (bus_type == BUS_PCI)
1708 level = AV_LEVEL;
1709 } else
1710 level = (irqptr->airq_iflag.intr_el == INTR_EL_LEVEL) ?
1711 AV_LEVEL : 0;
1712 if (level &&
1713 ((irqptr->airq_iflag.intr_po == INTR_PO_ACTIVE_LOW) ||
1714 (irqptr->airq_iflag.intr_po == INTR_PO_CONFORM &&
1715 bus_type == BUS_PCI)))
1716 po = AV_ACTIVE_LOW;
1717 } else {
1718 iointrp = apic_io_intrp + intr_index;
1719 bus_type = apic_find_bus(iointrp->intr_busid);
1720 if (iointrp->intr_el == INTR_EL_CONFORM) {
1721 if ((irq < 16) && (eisa_level_intr_mask & (1 << irq)))
1722 level = AV_LEVEL;
1723 else if (bus_type == BUS_PCI)
1724 level = AV_LEVEL;
1725 } else
1726 level = (iointrp->intr_el == INTR_EL_LEVEL) ?
1727 AV_LEVEL : 0;
1728 if (level && ((iointrp->intr_po == INTR_PO_ACTIVE_LOW) ||
1729 (iointrp->intr_po == INTR_PO_CONFORM &&
1730 bus_type == BUS_PCI)))
1731 po = AV_ACTIVE_LOW;
1732 }
1733 if (level)
1734 apic_level_intr[irq] = 1;
1735 /*
1736 * The 82489DX External APIC cannot do active low polarity interrupts.
1737 */
1738 if (po && (apic_io_ver[ioapicindex] != IOAPIC_VER_82489DX))
1739 io_po = po;
1740 else
1741 io_po = 0;
1742
1743 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG)
1744 prom_printf("setio: ioapic=0x%x intin=0x%x level=0x%x po=0x%x "
1745 "vector=0x%x cpu=0x%x\n\n", ioapicindex,
1746 irqptr->airq_intin_no, level, io_po, vector,
1747 irqptr->airq_cpu);
1748
1749 irqptr->airq_rdt_entry = level|io_po|vector;
1750 }
1751
1752 int
1753 apic_acpi_translate_pci_irq(dev_info_t *dip, int busid, int devid,
1754 int ipin, int *pci_irqp, iflag_t *intr_flagp)
1755 {
1756
1757 int status;
1758 acpi_psm_lnk_t acpipsmlnk;
1759
1760 if ((status = acpi_get_irq_cache_ent(busid, devid, ipin, pci_irqp,
1761 intr_flagp)) == ACPI_PSM_SUCCESS) {
1762 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Found irqno %d "
1763 "from cache for device %s, instance #%d\n", psm_name,
1764 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1765 return (status);
1766 }
1767
1768 bzero(&acpipsmlnk, sizeof (acpi_psm_lnk_t));
1769
1770 if ((status = acpi_translate_pci_irq(dip, ipin, pci_irqp, intr_flagp,
1771 &acpipsmlnk)) == ACPI_PSM_FAILURE) {
1772 APIC_VERBOSE_IRQ((CE_WARN, "%s: "
1773 " acpi_translate_pci_irq failed for device %s, instance"
1774 " #%d", psm_name, ddi_get_name(dip),
1775 ddi_get_instance(dip)));
1776 return (status);
1777 }
1778
1779 if (status == ACPI_PSM_PARTIAL && acpipsmlnk.lnkobj != NULL) {
1780 status = apic_acpi_irq_configure(&acpipsmlnk, dip, pci_irqp,
1781 intr_flagp);
1782 if (status != ACPI_PSM_SUCCESS) {
1783 status = acpi_get_current_irq_resource(&acpipsmlnk,
1784 pci_irqp, intr_flagp);
1785 }
1786 }
1787
1788 if (status == ACPI_PSM_SUCCESS) {
1789 acpi_new_irq_cache_ent(busid, devid, ipin, *pci_irqp,
1790 intr_flagp, &acpipsmlnk);
1791
1792 APIC_VERBOSE_IRQ((CE_CONT, "%s: [ACPI] "
1793 "new irq %d for device %s, instance #%d\n", psm_name,
1794 *pci_irqp, ddi_get_name(dip), ddi_get_instance(dip)));
1795 }
1796
1797 return (status);
1798 }
1799
1800 /*
1801 * Adds an entry to the irq list passed in, and returns the new list.
1802 * Entries are added in priority order (lower numerical priorities are
1803 * placed closer to the head of the list)
1804 */
1805 static prs_irq_list_t *
1806 acpi_insert_prs_irq_ent(prs_irq_list_t *listp, int priority, int irq,
1807 iflag_t *iflagp, acpi_prs_private_t *prsprvp)
1808 {
1809 struct prs_irq_list_ent *newent, *prevp = NULL, *origlistp;
1810
1811 newent = kmem_zalloc(sizeof (struct prs_irq_list_ent), KM_SLEEP);
1812
1813 newent->list_prio = priority;
1814 newent->irq = irq;
1815 newent->intrflags = *iflagp;
1816 newent->prsprv = *prsprvp;
1817 /* ->next is NULL from kmem_zalloc */
1818
1819 /*
1820 * New list -- return the new entry as the list.
1821 */
1822 if (listp == NULL)
1823 return (newent);
1824
1825 /*
1826 * Save original list pointer for return (since we're not modifying
1827 * the head)
1828 */
1829 origlistp = listp;
1830
1831 /*
1832 * Insertion sort, with entries with identical keys stored AFTER
1833 * existing entries (the less-than-or-equal test of priority does
1834 * this for us).
1835 */
1836 while (listp != NULL && listp->list_prio <= priority) {
1837 prevp = listp;
1838 listp = listp->next;
1839 }
1840
1841 newent->next = listp;
1842
1843 if (prevp == NULL) { /* Add at head of list (newent is the new head) */
1844 return (newent);
1845 } else {
1846 prevp->next = newent;
1847 return (origlistp);
1848 }
1849 }
1850
1851 /*
1852 * Frees the list passed in, deallocating all memory and leaving *listpp
1853 * set to NULL.
1854 */
1855 static void
1856 acpi_destroy_prs_irq_list(prs_irq_list_t **listpp)
1857 {
1858 struct prs_irq_list_ent *nextp;
1859
1860 ASSERT(listpp != NULL);
1861
1862 while (*listpp != NULL) {
1863 nextp = (*listpp)->next;
1864 kmem_free(*listpp, sizeof (struct prs_irq_list_ent));
1865 *listpp = nextp;
1866 }
1867 }
1868
1869 /*
1870 * apic_choose_irqs_from_prs returns a list of irqs selected from the list of
1871 * irqs returned by the link device's _PRS method. The irqs are chosen
1872 * to minimize contention in situations where the interrupt link device
1873 * can be programmed to steer interrupts to different interrupt controller
1874 * inputs (some of which may already be in use). The list is sorted in order
1875 * of irqs to use, with the highest priority given to interrupt controller
1876 * inputs that are not shared. When an interrupt controller input
1877 * must be shared, apic_choose_irqs_from_prs adds the possible irqs to the
1878 * returned list in the order that minimizes sharing (thereby ensuring lowest
1879 * possible latency from interrupt trigger time to ISR execution time).
1880 */
1881 static prs_irq_list_t *
1882 apic_choose_irqs_from_prs(acpi_irqlist_t *irqlistent, dev_info_t *dip,
1883 int crs_irq)
1884 {
1885 int32_t irq;
1886 int i;
1887 prs_irq_list_t *prsirqlistp = NULL;
1888 iflag_t iflags;
1889
1890 while (irqlistent != NULL) {
1891 irqlistent->intr_flags.bustype = BUS_PCI;
1892
1893 for (i = 0; i < irqlistent->num_irqs; i++) {
1894
1895 irq = irqlistent->irqs[i];
1896
1897 if (irq <= 0) {
1898 /* invalid irq number */
1899 continue;
1900 }
1901
1902 if ((irq < 16) && (apic_reserved_irqlist[irq]))
1903 continue;
1904
1905 if ((apic_irq_table[irq] == NULL) ||
1906 (apic_irq_table[irq]->airq_dip == dip)) {
1907
1908 prsirqlistp = acpi_insert_prs_irq_ent(
1909 prsirqlistp, 0 /* Highest priority */, irq,
1910 &irqlistent->intr_flags,
1911 &irqlistent->acpi_prs_prv);
1912
1913 /*
1914 * If we do not prefer the current irq from _CRS
1915 * or if we do and this irq is the same as the
1916 * current irq from _CRS, this is the one
1917 * to pick.
1918 */
1919 if (!(apic_prefer_crs) || (irq == crs_irq)) {
1920 return (prsirqlistp);
1921 }
1922 continue;
1923 }
1924
1925 /*
1926 * Edge-triggered interrupts cannot be shared
1927 */
1928 if (irqlistent->intr_flags.intr_el == INTR_EL_EDGE)
1929 continue;
1930
1931 /*
1932 * To work around BIOSes that contain incorrect
1933 * interrupt polarity information in interrupt
1934 * descriptors returned by _PRS, we assume that
1935 * the polarity of the other device sharing this
1936 * interrupt controller input is compatible.
1937 * If it's not, the caller will catch it when
1938 * the caller invokes the link device's _CRS method
1939 * (after invoking its _SRS method).
1940 */
1941 iflags = irqlistent->intr_flags;
1942 iflags.intr_po =
1943 apic_irq_table[irq]->airq_iflag.intr_po;
1944
1945 if (!acpi_intr_compatible(iflags,
1946 apic_irq_table[irq]->airq_iflag)) {
1947 APIC_VERBOSE_IRQ((CE_CONT, "!%s: irq %d "
1948 "not compatible [%x:%x:%x !~ %x:%x:%x]",
1949 psm_name, irq,
1950 iflags.intr_po,
1951 iflags.intr_el,
1952 iflags.bustype,
1953 apic_irq_table[irq]->airq_iflag.intr_po,
1954 apic_irq_table[irq]->airq_iflag.intr_el,
1955 apic_irq_table[irq]->airq_iflag.bustype));
1956 continue;
1957 }
1958
1959 /*
1960 * If we prefer the irq from _CRS, no need
1961 * to search any further (and make sure
1962 * to add this irq with the highest priority
1963 * so it's tried first).
1964 */
1965 if (crs_irq == irq && apic_prefer_crs) {
1966
1967 return (acpi_insert_prs_irq_ent(
1968 prsirqlistp,
1969 0 /* Highest priority */,
1970 irq, &iflags,
1971 &irqlistent->acpi_prs_prv));
1972 }
1973
1974 /*
1975 * Priority is equal to the share count (lower
1976 * share count is higher priority). Note that
1977 * the intr flags passed in here are the ones we
1978 * changed above -- if incorrect, it will be
1979 * caught by the caller's _CRS flags comparison.
1980 */
1981 prsirqlistp = acpi_insert_prs_irq_ent(
1982 prsirqlistp,
1983 apic_irq_table[irq]->airq_share, irq,
1984 &iflags, &irqlistent->acpi_prs_prv);
1985 }
1986
1987 /* Go to the next irqlist entry */
1988 irqlistent = irqlistent->next;
1989 }
1990
1991 return (prsirqlistp);
1992 }
1993
1994 /*
1995 * Configures the irq for the interrupt link device identified by
1996 * acpipsmlnkp.
1997 *
1998 * Gets the current and the list of possible irq settings for the
1999 * device. If apic_unconditional_srs is not set, and the current
2000 * resource setting is in the list of possible irq settings,
2001 * current irq resource setting is passed to the caller.
2002 *
2003 * Otherwise, picks an irq number from the list of possible irq
2004 * settings, and sets the irq of the device to this value.
2005 * If prefer_crs is set, among a set of irq numbers in the list that have
2006 * the least number of devices sharing the interrupt, we pick current irq
2007 * resource setting if it is a member of this set.
2008 *
2009 * Passes the irq number in the value pointed to by pci_irqp, and
2010 * polarity and sensitivity in the structure pointed to by dipintrflagp
2011 * to the caller.
2012 *
2013 * Note that if setting the irq resource failed, but successfuly obtained
2014 * the current irq resource settings, passes the current irq resources
2015 * and considers it a success.
2016 *
2017 * Returns:
2018 * ACPI_PSM_SUCCESS on success.
2019 *
2020 * ACPI_PSM_FAILURE if an error occured during the configuration or
2021 * if a suitable irq was not found for this device, or if setting the
2022 * irq resource and obtaining the current resource fails.
2023 *
2024 */
2025 static int
2026 apic_acpi_irq_configure(acpi_psm_lnk_t *acpipsmlnkp, dev_info_t *dip,
2027 int *pci_irqp, iflag_t *dipintr_flagp)
2028 {
2029 int32_t irq;
2030 int cur_irq = -1;
2031 acpi_irqlist_t *irqlistp;
2032 prs_irq_list_t *prs_irq_listp, *prs_irq_entp;
2033 boolean_t found_irq = B_FALSE;
2034
2035 dipintr_flagp->bustype = BUS_PCI;
2036
2037 if ((acpi_get_possible_irq_resources(acpipsmlnkp, &irqlistp))
2038 == ACPI_PSM_FAILURE) {
2039 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Unable to determine "
2040 "or assign IRQ for device %s, instance #%d: The system was "
2041 "unable to get the list of potential IRQs from ACPI.",
2042 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2043
2044 return (ACPI_PSM_FAILURE);
2045 }
2046
2047 if ((acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2048 dipintr_flagp) == ACPI_PSM_SUCCESS) && (!apic_unconditional_srs) &&
2049 (cur_irq > 0)) {
2050 /*
2051 * If an IRQ is set in CRS and that IRQ exists in the set
2052 * returned from _PRS, return that IRQ, otherwise print
2053 * a warning
2054 */
2055
2056 if (acpi_irqlist_find_irq(irqlistp, cur_irq, NULL)
2057 == ACPI_PSM_SUCCESS) {
2058
2059 ASSERT(pci_irqp != NULL);
2060 *pci_irqp = cur_irq;
2061 acpi_free_irqlist(irqlistp);
2062 return (ACPI_PSM_SUCCESS);
2063 }
2064
2065 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find the "
2066 "current irq %d for device %s, instance #%d in ACPI's "
2067 "list of possible irqs for this device. Picking one from "
2068 " the latter list.", psm_name, cur_irq, ddi_get_name(dip),
2069 ddi_get_instance(dip)));
2070 }
2071
2072 if ((prs_irq_listp = apic_choose_irqs_from_prs(irqlistp, dip,
2073 cur_irq)) == NULL) {
2074
2075 APIC_VERBOSE_IRQ((CE_WARN, "!%s: Could not find a "
2076 "suitable irq from the list of possible irqs for device "
2077 "%s, instance #%d in ACPI's list of possible irqs",
2078 psm_name, ddi_get_name(dip), ddi_get_instance(dip)));
2079
2080 acpi_free_irqlist(irqlistp);
2081 return (ACPI_PSM_FAILURE);
2082 }
2083
2084 acpi_free_irqlist(irqlistp);
2085
2086 for (prs_irq_entp = prs_irq_listp;
2087 prs_irq_entp != NULL && found_irq == B_FALSE;
2088 prs_irq_entp = prs_irq_entp->next) {
2089
2090 acpipsmlnkp->acpi_prs_prv = prs_irq_entp->prsprv;
2091 irq = prs_irq_entp->irq;
2092
2093 APIC_VERBOSE_IRQ((CE_CONT, "!%s: Setting irq %d for "
2094 "device %s instance #%d\n", psm_name, irq,
2095 ddi_get_name(dip), ddi_get_instance(dip)));
2096
2097 if ((acpi_set_irq_resource(acpipsmlnkp, irq))
2098 == ACPI_PSM_SUCCESS) {
2099 /*
2100 * setting irq was successful, check to make sure CRS
2101 * reflects that. If CRS does not agree with what we
2102 * set, return the irq that was set.
2103 */
2104
2105 if (acpi_get_current_irq_resource(acpipsmlnkp, &cur_irq,
2106 dipintr_flagp) == ACPI_PSM_SUCCESS) {
2107
2108 if (cur_irq != irq)
2109 APIC_VERBOSE_IRQ((CE_WARN,
2110 "!%s: IRQ resource set "
2111 "(irqno %d) for device %s "
2112 "instance #%d, differs from "
2113 "current setting irqno %d",
2114 psm_name, irq, ddi_get_name(dip),
2115 ddi_get_instance(dip), cur_irq));
2116 } else {
2117 /*
2118 * On at least one system, there was a bug in
2119 * a DSDT method called by _STA, causing _STA to
2120 * indicate that the link device was disabled
2121 * (when, in fact, it was enabled). Since _SRS
2122 * succeeded, assume that _CRS is lying and use
2123 * the iflags from this _PRS interrupt choice.
2124 * If we're wrong about the flags, the polarity
2125 * will be incorrect and we may get an interrupt
2126 * storm, but there's not much else we can do
2127 * at this point.
2128 */
2129 *dipintr_flagp = prs_irq_entp->intrflags;
2130 }
2131
2132 /*
2133 * Return the irq that was set, and not what _CRS
2134 * reports, since _CRS has been seen to return
2135 * different IRQs than what was passed to _SRS on some
2136 * systems (and just not return successfully on others).
2137 */
2138 cur_irq = irq;
2139 found_irq = B_TRUE;
2140 } else {
2141 APIC_VERBOSE_IRQ((CE_WARN, "!%s: set resource "
2142 "irq %d failed for device %s instance #%d",
2143 psm_name, irq, ddi_get_name(dip),
2144 ddi_get_instance(dip)));
2145
2146 if (cur_irq == -1) {
2147 acpi_destroy_prs_irq_list(&prs_irq_listp);
2148 return (ACPI_PSM_FAILURE);
2149 }
2150 }
2151 }
2152
2153 acpi_destroy_prs_irq_list(&prs_irq_listp);
2154
2155 if (!found_irq)
2156 return (ACPI_PSM_FAILURE);
2157
2158 ASSERT(pci_irqp != NULL);
2159 *pci_irqp = cur_irq;
2160 return (ACPI_PSM_SUCCESS);
2161 }
2162
2163 void
2164 ioapic_disable_redirection()
2165 {
2166 int ioapic_ix;
2167 int intin_max;
2168 int intin_ix;
2169
2170 /* Disable the I/O APIC redirection entries */
2171 for (ioapic_ix = 0; ioapic_ix < apic_io_max; ioapic_ix++) {
2172
2173 /* Bits 23-16 define the maximum redirection entries */
2174 intin_max = (ioapic_read(ioapic_ix, APIC_VERS_CMD) >> 16)
2175 & 0xff;
2176
2177 for (intin_ix = 0; intin_ix <= intin_max; intin_ix++) {
2178 /*
2179 * The assumption here is that this is safe, even for
2180 * systems with IOAPICs that suffer from the hardware
2181 * erratum because all devices have been quiesced before
2182 * this function is called from apic_shutdown()
2183 * (or equivalent). If that assumption turns out to be
2184 * false, this mask operation can induce the same
2185 * erratum result we're trying to avoid.
2186 */
2187 ioapic_write(ioapic_ix, APIC_RDT_CMD + 2 * intin_ix,
2188 AV_MASK);
2189 }
2190 }
2191 }
2192
2193 /*
2194 * Looks for an IOAPIC with the specified physical address in the /ioapics
2195 * node in the device tree (created by the PCI enumerator).
2196 */
2197 static boolean_t
2198 apic_is_ioapic_AMD_813x(uint32_t physaddr)
2199 {
2200 /*
2201 * Look in /ioapics, for the ioapic with
2202 * the physical address given
2203 */
2204 dev_info_t *ioapicsnode = ddi_find_devinfo(IOAPICS_NODE_NAME, -1, 0);
2205 dev_info_t *ioapic_child;
2206 boolean_t rv = B_FALSE;
2207 int vid, did;
2208 uint64_t ioapic_paddr;
2209 boolean_t done = B_FALSE;
2210
2211 if (ioapicsnode == NULL)
2212 return (B_FALSE);
2213
2214 /* Load first child: */
2215 ioapic_child = ddi_get_child(ioapicsnode);
2216 while (!done && ioapic_child != 0) { /* Iterate over children */
2217
2218 if ((ioapic_paddr = (uint64_t)ddi_prop_get_int64(DDI_DEV_T_ANY,
2219 ioapic_child, DDI_PROP_DONTPASS, "reg", 0))
2220 != 0 && physaddr == ioapic_paddr) {
2221
2222 vid = ddi_prop_get_int(DDI_DEV_T_ANY, ioapic_child,
2223 DDI_PROP_DONTPASS, IOAPICS_PROP_VENID, 0);
2224
2225 if (vid == VENID_AMD) {
2226
2227 did = ddi_prop_get_int(DDI_DEV_T_ANY,
2228 ioapic_child, DDI_PROP_DONTPASS,
2229 IOAPICS_PROP_DEVID, 0);
2230
2231 if (did == DEVID_8131_IOAPIC ||
2232 did == DEVID_8132_IOAPIC) {
2233 rv = B_TRUE;
2234 done = B_TRUE;
2235 }
2236 }
2237 }
2238
2239 if (!done)
2240 ioapic_child = ddi_get_next_sibling(ioapic_child);
2241 }
2242
2243 /* The ioapics node was held by ddi_find_devinfo, so release it */
2244 ndi_rele_devi(ioapicsnode);
2245 return (rv);
2246 }
2247
2248 struct apic_state {
2249 int32_t as_task_reg;
2250 int32_t as_dest_reg;
2251 int32_t as_format_reg;
2252 int32_t as_local_timer;
2253 int32_t as_pcint_vect;
2254 int32_t as_int_vect0;
2255 int32_t as_int_vect1;
2256 int32_t as_err_vect;
2257 int32_t as_init_count;
2258 int32_t as_divide_reg;
2259 int32_t as_spur_int_reg;
2260 uint32_t as_ioapic_ids[MAX_IO_APIC];
2261 };
2262
2263
2264 static int
2265 apic_acpi_enter_apicmode(void)
2266 {
2267 ACPI_OBJECT_LIST arglist;
2268 ACPI_OBJECT arg;
2269 ACPI_STATUS status;
2270
2271 /* Setup parameter object */
2272 arglist.Count = 1;
2273 arglist.Pointer = &arg;
2274 arg.Type = ACPI_TYPE_INTEGER;
2275 arg.Integer.Value = ACPI_APIC_MODE;
2276
2277 status = AcpiEvaluateObject(NULL, "\\_PIC", &arglist, NULL);
2278 /*
2279 * Per ACPI spec - section 5.8.1 _PIC Method
2280 * calling the \_PIC control method is optional for the OS
2281 * and might not be found. It's ok to not fail in such cases.
2282 * This is the case on linux KVM and qemu (status AE_NOT_FOUND)
2283 */
2284 if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
2285 cmn_err(CE_NOTE,
2286 "!apic: Reporting APIC mode failed (via _PIC), err: 0x%x",
2287 ACPI_FAILURE(status));
2288 return (PSM_FAILURE);
2289 } else {
2290 return (PSM_SUCCESS);
2291 }
2292 }
2293
2294
2295 static void
2296 apic_save_state(struct apic_state *sp)
2297 {
2298 int i, cpuid;
2299 ulong_t iflag;
2300
2301 PMD(PMD_SX, ("apic_save_state %p\n", (void *)sp))
2302 /*
2303 * First the local APIC.
2304 */
2305 sp->as_task_reg = apic_reg_ops->apic_get_pri();
2306 sp->as_dest_reg = apic_reg_ops->apic_read(APIC_DEST_REG);
2307 if (apic_mode == LOCAL_APIC)
2308 sp->as_format_reg = apic_reg_ops->apic_read(APIC_FORMAT_REG);
2309 sp->as_local_timer = apic_reg_ops->apic_read(APIC_LOCAL_TIMER);
2310 sp->as_pcint_vect = apic_reg_ops->apic_read(APIC_PCINT_VECT);
2311 sp->as_int_vect0 = apic_reg_ops->apic_read(APIC_INT_VECT0);
2312 sp->as_int_vect1 = apic_reg_ops->apic_read(APIC_INT_VECT1);
2313 sp->as_err_vect = apic_reg_ops->apic_read(APIC_ERR_VECT);
2314 sp->as_init_count = apic_reg_ops->apic_read(APIC_INIT_COUNT);
2315 sp->as_divide_reg = apic_reg_ops->apic_read(APIC_DIVIDE_REG);
2316 sp->as_spur_int_reg = apic_reg_ops->apic_read(APIC_SPUR_INT_REG);
2317
2318 /*
2319 * If on the boot processor then save the IOAPICs' IDs
2320 */
2321 if ((cpuid = psm_get_cpu_id()) == 0) {
2322
2323 iflag = intr_clear();
2324 lock_set(&apic_ioapic_lock);
2325
2326 for (i = 0; i < apic_io_max; i++)
2327 sp->as_ioapic_ids[i] = ioapic_read(i, APIC_ID_CMD);
2328
2329 lock_clear(&apic_ioapic_lock);
2330 intr_restore(iflag);
2331 }
2332
2333 /* apic_state() is currently invoked only in Suspend/Resume */
2334 apic_cpus[cpuid].aci_status |= APIC_CPU_SUSPEND;
2335 }
2336
2337 static void
2338 apic_restore_state(struct apic_state *sp)
2339 {
2340 int i;
2341 ulong_t iflag;
2342
2343 /*
2344 * First the local APIC.
2345 */
2346 apic_reg_ops->apic_write_task_reg(sp->as_task_reg);
2347 if (apic_mode == LOCAL_APIC) {
2348 apic_reg_ops->apic_write(APIC_DEST_REG, sp->as_dest_reg);
2349 apic_reg_ops->apic_write(APIC_FORMAT_REG, sp->as_format_reg);
2350 }
2351 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, sp->as_local_timer);
2352 apic_reg_ops->apic_write(APIC_PCINT_VECT, sp->as_pcint_vect);
2353 apic_reg_ops->apic_write(APIC_INT_VECT0, sp->as_int_vect0);
2354 apic_reg_ops->apic_write(APIC_INT_VECT1, sp->as_int_vect1);
2355 apic_reg_ops->apic_write(APIC_ERR_VECT, sp->as_err_vect);
2356 apic_reg_ops->apic_write(APIC_INIT_COUNT, sp->as_init_count);
2357 apic_reg_ops->apic_write(APIC_DIVIDE_REG, sp->as_divide_reg);
2358 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, sp->as_spur_int_reg);
2359
2360 /*
2361 * the following only needs to be done once, so we do it on the
2362 * boot processor, since we know that we only have one of those
2363 */
2364 if (psm_get_cpu_id() == 0) {
2365
2366 iflag = intr_clear();
2367 lock_set(&apic_ioapic_lock);
2368
2369 /* Restore IOAPICs' APIC IDs */
2370 for (i = 0; i < apic_io_max; i++) {
2371 ioapic_write(i, APIC_ID_CMD, sp->as_ioapic_ids[i]);
2372 }
2373
2374 lock_clear(&apic_ioapic_lock);
2375 intr_restore(iflag);
2376
2377 /*
2378 * Reenter APIC mode before restoring LNK devices
2379 */
2380 (void) apic_acpi_enter_apicmode();
2381
2382 /*
2383 * restore acpi link device mappings
2384 */
2385 acpi_restore_link_devices();
2386 }
2387 }
2388
2389 /*
2390 * Returns 0 on success
2391 */
2392 int
2393 apic_state(psm_state_request_t *rp)
2394 {
2395 PMD(PMD_SX, ("apic_state "))
2396 switch (rp->psr_cmd) {
2397 case PSM_STATE_ALLOC:
2398 rp->req.psm_state_req.psr_state =
2399 kmem_zalloc(sizeof (struct apic_state), KM_NOSLEEP);
2400 if (rp->req.psm_state_req.psr_state == NULL)
2401 return (ENOMEM);
2402 rp->req.psm_state_req.psr_state_size =
2403 sizeof (struct apic_state);
2404 PMD(PMD_SX, (":STATE_ALLOC: state %p, size %lx\n",
2405 rp->req.psm_state_req.psr_state,
2406 rp->req.psm_state_req.psr_state_size))
2407 return (0);
2408
2409 case PSM_STATE_FREE:
2410 kmem_free(rp->req.psm_state_req.psr_state,
2411 rp->req.psm_state_req.psr_state_size);
2412 PMD(PMD_SX, (" STATE_FREE: state %p, size %lx\n",
2413 rp->req.psm_state_req.psr_state,
2414 rp->req.psm_state_req.psr_state_size))
2415 return (0);
2416
2417 case PSM_STATE_SAVE:
2418 PMD(PMD_SX, (" STATE_SAVE: state %p, size %lx\n",
2419 rp->req.psm_state_req.psr_state,
2420 rp->req.psm_state_req.psr_state_size))
2421 apic_save_state(rp->req.psm_state_req.psr_state);
2422 return (0);
2423
2424 case PSM_STATE_RESTORE:
2425 apic_restore_state(rp->req.psm_state_req.psr_state);
2426 PMD(PMD_SX, (" STATE_RESTORE: state %p, size %lx\n",
2427 rp->req.psm_state_req.psr_state,
2428 rp->req.psm_state_req.psr_state_size))
2429 return (0);
2430
2431 default:
2432 return (EINVAL);
2433 }
2434 }
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