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dmake: do not set MAKEFLAGS=k
[unleashed/tickless.git] / usr / src / uts / intel / io / drm / i915_dma.c
blob1032bed4d65af708a8aa6e69a17b4150e3d792df
1 /* BEGIN CSTYLED */
2
3 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 */
5 /*
6 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Copyright (c) 2009, Intel Corporation.
8 * All Rights Reserved.
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the
12 * "Software"), to deal in the Software without restriction, including
13 * without limitation the rights to use, copy, modify, merge, publish,
14 * distribute, sub license, and/or sell copies of the Software, and to
15 * permit persons to whom the Software is furnished to do so, subject to
16 * the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
23 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
25 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
26 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 *
30 */
31
32 /*
33 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
34 * Use is subject to license terms.
35 */
36
37 #include "drmP.h"
38 #include "drm.h"
39 #include "i915_drm.h"
40 #include "i915_drv.h"
41
42
43
44 /* Really want an OS-independent resettable timer. Would like to have
45 * this loop run for (eg) 3 sec, but have the timer reset every time
46 * the head pointer changes, so that EBUSY only happens if the ring
47 * actually stalls for (eg) 3 seconds.
48 */
49 /*ARGSUSED*/
50 int i915_wait_ring(drm_device_t * dev, int n, const char *caller)
51 {
52 drm_i915_private_t *dev_priv = dev->dev_private;
53 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
54 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
55 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
56 u32 last_acthd = I915_READ(acthd_reg);
57 u32 acthd;
58 int i;
59
60 for (i = 0; i < 100000; i++) {
61 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
62 acthd = I915_READ(acthd_reg);
63 ring->space = ring->head - (ring->tail + 8);
64 if (ring->space < 0)
65 ring->space += ring->Size;
66 if (ring->space >= n)
67 return 0;
68
69 if (ring->head != last_head)
70 i = 0;
71
72 if (acthd != last_acthd)
73 i = 0;
74
75 last_head = ring->head;
76 last_acthd = acthd;
77 DRM_UDELAY(10);
78 }
79
80 return (EBUSY);
81 }
82
83 int i915_init_hardware_status(drm_device_t *dev)
84 {
85 drm_i915_private_t *dev_priv = dev->dev_private;
86 drm_dma_handle_t *dmah;
87
88 /* Program Hardware Status Page */
89 dmah = drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff,1);
90
91 if (!dmah) {
92 DRM_ERROR("Can not allocate hardware status page\n");
93 return -ENOMEM;
94 }
95
96 dev_priv->status_page_dmah = dmah;
97 dev_priv->hw_status_page = (void *)dmah->vaddr;
98 dev_priv->dma_status_page = dmah->paddr;
99
100 (void) memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
101
102 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
103 (void) I915_READ(HWS_PGA);
104
105 DRM_DEBUG("Enabled hardware status page add 0x%lx read GEM HWS 0x%x\n",dev_priv->hw_status_page, READ_HWSP(dev_priv, 0x20));
106 return 0;
107 }
108
109 void i915_free_hardware_status(drm_device_t *dev)
110 {
111 drm_i915_private_t *dev_priv = dev->dev_private;
112 if (!I915_NEED_GFX_HWS(dev)) {
113 if (dev_priv->status_page_dmah) {
114 DRM_DEBUG("free status_page_dmal %x", dev_priv->status_page_dmah);
115 drm_pci_free(dev, dev_priv->status_page_dmah);
116 dev_priv->status_page_dmah = NULL;
117 /* Need to rewrite hardware status page */
118 I915_WRITE(HWS_PGA, 0x1ffff000);
119 }
120 } else {
121 if (dev_priv->status_gfx_addr) {
122 DRM_DEBUG("free status_gfx_addr %x", dev_priv->status_gfx_addr);
123 dev_priv->status_gfx_addr = 0;
124 drm_core_ioremapfree(&dev_priv->hws_map, dev);
125 I915_WRITE(HWS_PGA, 0x1ffff000);
126 }
127 }
128
129 }
130
131 void i915_kernel_lost_context(drm_device_t * dev)
132 {
133 drm_i915_private_t *dev_priv = dev->dev_private;
134 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
135
136 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
137 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
138 ring->space = ring->head - (ring->tail + 8);
139 if (ring->space < 0)
140 ring->space += ring->Size;
141
142 }
143
144 static int i915_dma_cleanup(drm_device_t * dev)
145 {
146 drm_i915_private_t *dev_priv =
147 (drm_i915_private_t *) dev->dev_private;
148
149 /* Make sure interrupts are disabled here because the uninstall ioctl
150 * may not have been called from userspace and after dev_private
151 * is freed, it's too late.
152 */
153 if (dev->irq_enabled)
154 (void) drm_irq_uninstall(dev);
155
156 if (dev_priv->ring.virtual_start) {
157 drm_core_ioremapfree(&dev_priv->ring.map, dev);
158 dev_priv->ring.virtual_start = 0;
159 dev_priv->ring.map.handle = 0;
160 dev_priv->ring.map.size = 0;
161 }
162
163 #ifdef I915_HAVE_GEM
164 if (I915_NEED_GFX_HWS(dev))
165 #endif
166 i915_free_hardware_status(dev);
167
168 dev_priv->sarea = NULL;
169 dev_priv->sarea_priv = NULL;
170
171 return 0;
172 }
173
174 static int i915_initialize(drm_device_t * dev,
175 drm_i915_init_t * init)
176 {
177 drm_i915_private_t *dev_priv =
178 (drm_i915_private_t *)dev->dev_private;
179
180 DRM_GETSAREA();
181 if (!dev_priv->sarea) {
182 DRM_ERROR("can not find sarea!\n");
183 dev->dev_private = (void *)dev_priv;
184 (void) i915_dma_cleanup(dev);
185 return (EINVAL);
186 }
187
188 dev_priv->sarea_priv = (drm_i915_sarea_t *)(uintptr_t)
189 ((u8 *) dev_priv->sarea->handle +
190 init->sarea_priv_offset);
191
192 if (init->ring_size != 0) {
193 if (dev_priv->ring.ring_obj != NULL) {
194 (void) i915_dma_cleanup(dev);
195 DRM_ERROR("Client tried to initialize ringbuffer in "
196 "GEM mode\n");
197 return -EINVAL;
198 }
199
200 dev_priv->ring.Size = init->ring_size;
201 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
202
203 dev_priv->ring.map.offset = (uoff_t)init->ring_start;
204 dev_priv->ring.map.size = init->ring_size;
205 dev_priv->ring.map.type = 0;
206 dev_priv->ring.map.flags = 0;
207 dev_priv->ring.map.mtrr = 0;
208
209 drm_core_ioremap(&dev_priv->ring.map, dev);
210
211 if (dev_priv->ring.map.handle == NULL) {
212 (void) i915_dma_cleanup(dev);
213 DRM_ERROR("can not ioremap virtual address for"
214 " ring buffer\n");
215 return (ENOMEM);
216 }
217 }
218
219 dev_priv->ring.virtual_start = (u8 *)dev_priv->ring.map.dev_addr;
220 dev_priv->cpp = init->cpp;
221 dev_priv->back_offset = init->back_offset;
222 dev_priv->front_offset = init->front_offset;
223 dev_priv->current_page = 0;
224 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
225
226 /* Allow hardware batchbuffers unless told otherwise.
227 */
228 dev_priv->allow_batchbuffer = 1;
229 return 0;
230 }
231
232 static int i915_dma_resume(drm_device_t * dev)
233 {
234 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
235
236 if (!dev_priv->sarea) {
237 DRM_ERROR("can not find sarea!\n");
238 return (EINVAL);
239 }
240
241 if (dev_priv->ring.map.handle == NULL) {
242 DRM_ERROR("can not ioremap virtual address for"
243 " ring buffer\n");
244 return (ENOMEM);
245 }
246
247 /* Program Hardware Status Page */
248 if (!dev_priv->hw_status_page) {
249 DRM_ERROR("Can not find hardware status page\n");
250 return (EINVAL);
251 }
252 DRM_DEBUG("i915_dma_resume hw status page @ %p\n", dev_priv->hw_status_page);
253
254 if (!I915_NEED_GFX_HWS(dev))
255 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
256 else
257 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
258 DRM_DEBUG("Enabled hardware status page\n");
259
260 return 0;
261 }
262
263 /*ARGSUSED*/
264 static int i915_dma_init(DRM_IOCTL_ARGS)
265 {
266 DRM_DEVICE;
267 drm_i915_init_t init;
268 int retcode = 0;
269
270 DRM_COPYFROM_WITH_RETURN(&init, (drm_i915_init_t *)data, sizeof(init));
271
272 switch (init.func) {
273 case I915_INIT_DMA:
274 retcode = i915_initialize(dev, &init);
275 break;
276 case I915_CLEANUP_DMA:
277 retcode = i915_dma_cleanup(dev);
278 break;
279 case I915_RESUME_DMA:
280 retcode = i915_dma_resume(dev);
281 break;
282 default:
283 retcode = EINVAL;
284 break;
285 }
286
287 return retcode;
288 }
289
290 /* Implement basically the same security restrictions as hardware does
291 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
292 *
293 * Most of the calculations below involve calculating the size of a
294 * particular instruction. It's important to get the size right as
295 * that tells us where the next instruction to check is. Any illegal
296 * instruction detected will be given a size of zero, which is a
297 * signal to abort the rest of the buffer.
298 */
299 static int do_validate_cmd(int cmd)
300 {
301 switch (((cmd >> 29) & 0x7)) {
302 case 0x0:
303 switch ((cmd >> 23) & 0x3f) {
304 case 0x0:
305 return 1; /* MI_NOOP */
306 case 0x4:
307 return 1; /* MI_FLUSH */
308 default:
309 return 0; /* disallow everything else */
310 }
311 break;
312 case 0x1:
313 return 0; /* reserved */
314 case 0x2:
315 return (cmd & 0xff) + 2; /* 2d commands */
316 case 0x3:
317 if (((cmd >> 24) & 0x1f) <= 0x18)
318 return 1;
319
320 switch ((cmd >> 24) & 0x1f) {
321 case 0x1c:
322 return 1;
323 case 0x1d:
324 switch ((cmd >> 16) & 0xff) {
325 case 0x3:
326 return (cmd & 0x1f) + 2;
327 case 0x4:
328 return (cmd & 0xf) + 2;
329 default:
330 return (cmd & 0xffff) + 2;
331 }
332 case 0x1e:
333 if (cmd & (1 << 23))
334 return (cmd & 0xffff) + 1;
335 else
336 return 1;
337 case 0x1f:
338 if ((cmd & (1 << 23)) == 0) /* inline vertices */
339 return (cmd & 0x1ffff) + 2;
340 else if (cmd & (1 << 17)) /* indirect random */
341 if ((cmd & 0xffff) == 0)
342 return 0; /* unknown length, too hard */
343 else
344 return (((cmd & 0xffff) + 1) / 2) + 1;
345 else
346 return 2; /* indirect sequential */
347 default:
348 return 0;
349 }
350 default:
351 return 0;
352 }
353
354 return 0;
355 }
356
357 static int validate_cmd(int cmd)
358 {
359 int ret = do_validate_cmd(cmd);
360
361 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
362
363 return ret;
364 }
365
366 static int i915_emit_cmds(drm_device_t * dev, int __user * buffer, int dwords)
367 {
368 drm_i915_private_t *dev_priv = dev->dev_private;
369 int i;
370 RING_LOCALS;
371
372 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8) {
373 DRM_ERROR(" emit cmds invalid arg");
374 return (EINVAL);
375 }
376 BEGIN_LP_RING((dwords+1)&~1);
377
378 for (i = 0; i < dwords;) {
379 int cmd, sz;
380
381 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd))) {
382 DRM_ERROR("emit cmds failed to get cmd from user");
383 return (EINVAL);
384 }
385
386 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords) {
387 DRM_ERROR("emit cmds invalid");
388 return (EINVAL);
389 }
390 OUT_RING(cmd);
391
392 while (++i, --sz) {
393 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
394 sizeof(cmd))) {
395 DRM_ERROR("emit cmds failed get cmds");
396 return (EINVAL);
397 }
398 OUT_RING(cmd);
399 }
400 }
401
402 if (dwords & 1)
403 OUT_RING(0);
404
405 ADVANCE_LP_RING();
406
407 return 0;
408 }
409
410 int i915_emit_box(drm_device_t * dev,
411 drm_clip_rect_t __user * boxes,
412 int i, int DR1, int DR4)
413 {
414 drm_i915_private_t *dev_priv = dev->dev_private;
415 drm_clip_rect_t box;
416 RING_LOCALS;
417
418 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
419 DRM_ERROR("emit box failed to copy from user");
420 return (EFAULT);
421 }
422
423 if (box.y2 <= box.y1 || box.x2 <= box.x1) {
424 DRM_ERROR("Bad box %d,%d..%d,%d\n",
425 box.x1, box.y1, box.x2, box.y2);
426 return (EINVAL);
427 }
428
429 if (IS_I965G(dev)) {
430 BEGIN_LP_RING(4);
431 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
432 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
433 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
434 OUT_RING(DR4);
435 ADVANCE_LP_RING();
436 } else {
437 BEGIN_LP_RING(6);
438 OUT_RING(GFX_OP_DRAWRECT_INFO);
439 OUT_RING(DR1);
440 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
441 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
442 OUT_RING(DR4);
443 OUT_RING(0);
444 ADVANCE_LP_RING();
445 }
446
447 return 0;
448 }
449
450 /* XXX: Emitting the counter should really be moved to part of the IRQ
451 * emit. For now, do it in both places:
452 */
453
454 void i915_emit_breadcrumb(drm_device_t *dev)
455 {
456 drm_i915_private_t *dev_priv = dev->dev_private;
457 RING_LOCALS;
458
459 dev_priv->counter++;
460 if (dev_priv->counter > 0x7FFFFFFFUL)
461 dev_priv->counter = 0;
462 if (dev_priv->sarea_priv)
463 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
464
465
466 BEGIN_LP_RING(4);
467 OUT_RING(MI_STORE_DWORD_INDEX);
468 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
469 OUT_RING(dev_priv->counter);
470 OUT_RING(0);
471 ADVANCE_LP_RING();
472
473 }
474
475 static int i915_dispatch_cmdbuffer(drm_device_t * dev,
476 drm_i915_cmdbuffer_t * cmd)
477 {
478 int nbox = cmd->num_cliprects;
479 int i = 0, count, ret;
480
481 if (cmd->sz & 0x3) {
482 DRM_ERROR("alignment");
483 return (EINVAL);
484 }
485
486 i915_kernel_lost_context(dev);
487
488 count = nbox ? nbox : 1;
489
490 for (i = 0; i < count; i++) {
491 if (i < nbox) {
492 ret = i915_emit_box(dev, cmd->cliprects, i,
493 cmd->DR1, cmd->DR4);
494 if (ret)
495 return ret;
496 }
497
498 ret = i915_emit_cmds(dev, (int __user *)(void *)cmd->buf, cmd->sz / 4);
499 if (ret)
500 return ret;
501 }
502
503 i915_emit_breadcrumb( dev );
504 return 0;
505 }
506
507 static int i915_dispatch_batchbuffer(drm_device_t * dev,
508 drm_i915_batchbuffer_t * batch)
509 {
510 drm_i915_private_t *dev_priv = dev->dev_private;
511 drm_clip_rect_t __user *boxes = batch->cliprects;
512 int nbox = batch->num_cliprects;
513 int i = 0, count;
514 RING_LOCALS;
515
516 if ((batch->start | batch->used) & 0x7) {
517 DRM_ERROR("alignment");
518 return (EINVAL);
519 }
520
521 i915_kernel_lost_context(dev);
522
523 count = nbox ? nbox : 1;
524
525 for (i = 0; i < count; i++) {
526 if (i < nbox) {
527 int ret = i915_emit_box(dev, boxes, i,
528 batch->DR1, batch->DR4);
529 if (ret)
530 return ret;
531 }
532
533 if (IS_I830(dev) || IS_845G(dev)) {
534 BEGIN_LP_RING(4);
535 OUT_RING(MI_BATCH_BUFFER);
536 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
537 OUT_RING(batch->start + batch->used - 4);
538 OUT_RING(0);
539 ADVANCE_LP_RING();
540 } else {
541 BEGIN_LP_RING(2);
542 if (IS_I965G(dev)) {
543 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
544 OUT_RING(batch->start);
545 } else {
546 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
547 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
548 }
549 ADVANCE_LP_RING();
550 }
551 }
552
553 i915_emit_breadcrumb( dev );
554
555 return 0;
556 }
557
558 static int i915_dispatch_flip(struct drm_device * dev, int planes)
559 {
560 drm_i915_private_t *dev_priv = dev->dev_private;
561 RING_LOCALS;
562
563 if (!dev_priv->sarea_priv)
564 return -EINVAL;
565
566 DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
567 planes, dev_priv->sarea_priv->pf_current_page);
568
569 i915_kernel_lost_context(dev);
570
571 BEGIN_LP_RING(2);
572 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
573 OUT_RING(0);
574 ADVANCE_LP_RING();
575
576 BEGIN_LP_RING(6);
577 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
578 OUT_RING(0);
579 if (dev_priv->current_page == 0) {
580 OUT_RING(dev_priv->back_offset);
581 dev_priv->current_page = 1;
582 } else {
583 OUT_RING(dev_priv->front_offset);
584 dev_priv->current_page = 0;
585 }
586 OUT_RING(0);
587 ADVANCE_LP_RING();
588
589 BEGIN_LP_RING(2);
590 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
591 OUT_RING(0);
592 ADVANCE_LP_RING();
593
594 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
595
596 BEGIN_LP_RING(4);
597 OUT_RING(MI_STORE_DWORD_INDEX);
598 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
599 OUT_RING(dev_priv->counter);
600 OUT_RING(0);
601 ADVANCE_LP_RING();
602
603 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
604 return 0;
605 }
606
607 static int i915_quiescent(drm_device_t * dev)
608 {
609 drm_i915_private_t *dev_priv = dev->dev_private;
610 int ret;
611 i915_kernel_lost_context(dev);
612 ret = i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
613
614 if (ret)
615 {
616 i915_kernel_lost_context (dev);
617 DRM_ERROR ("not quiescent head %08x tail %08x space %08x\n",
618 dev_priv->ring.head,
619 dev_priv->ring.tail,
620 dev_priv->ring.space);
621 }
622 return ret;
623 }
624
625 /*ARGSUSED*/
626 static int i915_flush_ioctl(DRM_IOCTL_ARGS)
627 {
628 int ret;
629 DRM_DEVICE;
630
631 LOCK_TEST_WITH_RETURN(dev, fpriv);
632
633 spin_lock(&dev->struct_mutex);
634 ret = i915_quiescent(dev);
635 spin_unlock(&dev->struct_mutex);
636
637 return ret;
638 }
639
640 /*ARGSUSED*/
641 static int i915_batchbuffer(DRM_IOCTL_ARGS)
642 {
643 DRM_DEVICE;
644 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
645 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
646 dev_priv->sarea_priv;
647 drm_i915_batchbuffer_t batch;
648 int ret;
649
650 if (!dev_priv->allow_batchbuffer) {
651 DRM_ERROR("Batchbuffer ioctl disabled\n");
652 return (EINVAL);
653 }
654
655 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
656 drm_i915_batchbuffer32_t batchbuffer32_t;
657
658 DRM_COPYFROM_WITH_RETURN(&batchbuffer32_t,
659 (void *) data, sizeof (batchbuffer32_t));
660
661 batch.start = batchbuffer32_t.start;
662 batch.used = batchbuffer32_t.used;
663 batch.DR1 = batchbuffer32_t.DR1;
664 batch.DR4 = batchbuffer32_t.DR4;
665 batch.num_cliprects = batchbuffer32_t.num_cliprects;
666 batch.cliprects = (drm_clip_rect_t __user *)
667 (uintptr_t)batchbuffer32_t.cliprects;
668 } else
669 DRM_COPYFROM_WITH_RETURN(&batch, (void *) data,
670 sizeof(batch));
671
672 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d, counter %d\n",
673 batch.start, batch.used, batch.num_cliprects, dev_priv->counter);
674
675 LOCK_TEST_WITH_RETURN(dev, fpriv);
676
677 /*
678 if (batch.num_cliprects && DRM_VERIFYAREA_READ(batch.cliprects,
679 batch.num_cliprects *
680 sizeof(drm_clip_rect_t)))
681 return (EFAULT);
682
683 */
684
685 spin_lock(&dev->struct_mutex);
686 ret = i915_dispatch_batchbuffer(dev, &batch);
687 spin_unlock(&dev->struct_mutex);
688 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
689
690 return ret;
691 }
692
693 /*ARGSUSED*/
694 static int i915_cmdbuffer(DRM_IOCTL_ARGS)
695 {
696 DRM_DEVICE;
697 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
698 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
699 dev_priv->sarea_priv;
700 drm_i915_cmdbuffer_t cmdbuf;
701 int ret;
702
703 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
704 drm_i915_cmdbuffer32_t cmdbuffer32_t;
705
706 DRM_COPYFROM_WITH_RETURN(&cmdbuffer32_t,
707 (drm_i915_cmdbuffer32_t __user *) data,
708 sizeof (drm_i915_cmdbuffer32_t));
709
710 cmdbuf.buf = (char __user *)(uintptr_t)cmdbuffer32_t.buf;
711 cmdbuf.sz = cmdbuffer32_t.sz;
712 cmdbuf.DR1 = cmdbuffer32_t.DR1;
713 cmdbuf.DR4 = cmdbuffer32_t.DR4;
714 cmdbuf.num_cliprects = cmdbuffer32_t.num_cliprects;
715 cmdbuf.cliprects = (drm_clip_rect_t __user *)
716 (uintptr_t)cmdbuffer32_t.cliprects;
717 } else
718 DRM_COPYFROM_WITH_RETURN(&cmdbuf, (void *) data,
719 sizeof(cmdbuf));
720
721 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
722 cmdbuf.buf, cmdbuf.sz, cmdbuf.num_cliprects);
723
724 LOCK_TEST_WITH_RETURN(dev, fpriv);
725
726 /*
727 if (cmdbuf.num_cliprects &&
728 DRM_VERIFYAREA_READ(cmdbuf.cliprects,
729 cmdbuf.num_cliprects *
730 sizeof(drm_clip_rect_t))) {
731 DRM_ERROR("Fault accessing cliprects\n");
732 return (EFAULT);
733 }
734 */
735
736 spin_lock(&dev->struct_mutex);
737 ret = i915_dispatch_cmdbuffer(dev, &cmdbuf);
738 spin_unlock(&dev->struct_mutex);
739 if (ret) {
740 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
741 return ret;
742 }
743
744 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
745 return 0;
746 }
747
748 /*ARGSUSED*/
749 static int i915_flip_bufs(DRM_IOCTL_ARGS)
750 {
751 DRM_DEVICE;
752 drm_i915_flip_t param;
753 int ret;
754 DRM_COPYFROM_WITH_RETURN(&param, (drm_i915_flip_t *) data,
755 sizeof(param));
756
757 DRM_DEBUG("i915_flip_bufs\n");
758
759 LOCK_TEST_WITH_RETURN(dev, fpriv);
760
761 spin_lock(&dev->struct_mutex);
762 ret = i915_dispatch_flip(dev, param.pipes);
763 spin_unlock(&dev->struct_mutex);
764 return ret;
765 }
766
767 /*ARGSUSED*/
768 static int i915_getparam(DRM_IOCTL_ARGS)
769 {
770 DRM_DEVICE;
771 drm_i915_private_t *dev_priv = dev->dev_private;
772 drm_i915_getparam_t param;
773 int value;
774
775 if (!dev_priv) {
776 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
777 return (EINVAL);
778 }
779
780 if (ddi_model_convert_from(mode & FMODELS) == DDI_MODEL_ILP32) {
781 drm_i915_getparam32_t getparam32_t;
782
783 DRM_COPYFROM_WITH_RETURN(&getparam32_t,
784 (drm_i915_getparam32_t __user *) data,
785 sizeof (drm_i915_getparam32_t));
786
787 param.param = getparam32_t.param;
788 param.value = (int __user *)(uintptr_t)getparam32_t.value;
789 } else
790 DRM_COPYFROM_WITH_RETURN(&param,
791 (drm_i915_getparam_t *) data, sizeof(param));
792
793 switch (param.param) {
794 case I915_PARAM_IRQ_ACTIVE:
795 value = dev->irq_enabled ? 1 : 0;
796 break;
797 case I915_PARAM_ALLOW_BATCHBUFFER:
798 value = dev_priv->allow_batchbuffer ? 1 : 0;
799 break;
800 case I915_PARAM_LAST_DISPATCH:
801 value = READ_BREADCRUMB(dev_priv);
802 break;
803 case I915_PARAM_CHIPSET_ID:
804 value = dev->pci_device;
805 break;
806 case I915_PARAM_HAS_GEM:
807 value = dev->driver->use_gem;
808 break;
809 default:
810 DRM_ERROR("Unknown get parameter %d\n", param.param);
811 return (EINVAL);
812 }
813
814 if (DRM_COPY_TO_USER(param.value, &value, sizeof(int))) {
815 DRM_ERROR("i915_getparam failed\n");
816 return (EFAULT);
817 }
818 return 0;
819 }
820
821 /*ARGSUSED*/
822 static int i915_setparam(DRM_IOCTL_ARGS)
823 {
824 DRM_DEVICE;
825 drm_i915_private_t *dev_priv = dev->dev_private;
826 drm_i915_setparam_t param;
827
828 if (!dev_priv) {
829 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
830 return (EINVAL);
831 }
832
833 DRM_COPYFROM_WITH_RETURN(&param, (drm_i915_setparam_t *) data,
834 sizeof(param));
835
836 switch (param.param) {
837 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
838 break;
839 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
840 dev_priv->tex_lru_log_granularity = param.value;
841 break;
842 case I915_SETPARAM_ALLOW_BATCHBUFFER:
843 dev_priv->allow_batchbuffer = param.value;
844 break;
845 default:
846 DRM_ERROR("unknown set parameter %d\n", param.param);
847 return (EINVAL);
848 }
849
850 return 0;
851 }
852
853 /*ARGSUSED*/
854 static int i915_set_status_page(DRM_IOCTL_ARGS)
855 {
856 DRM_DEVICE;
857 drm_i915_private_t *dev_priv = dev->dev_private;
858 drm_i915_hws_addr_t hws;
859
860 if (!I915_NEED_GFX_HWS(dev))
861 return (EINVAL);
862
863 if (!dev_priv) {
864 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
865 return (EINVAL);
866 }
867 DRM_COPYFROM_WITH_RETURN(&hws, (drm_i915_hws_addr_t __user *) data,
868 sizeof(hws));
869 DRM_ERROR("i915_set_status_page set status page addr 0x%08x\n", (u32)hws.addr);
870
871 dev_priv->status_gfx_addr = hws.addr & (0x1ffff<<12);
872 DRM_DEBUG("set gfx_addr 0x%08x\n", dev_priv->status_gfx_addr);
873
874 dev_priv->hws_map.offset =
875 (uoff_t)dev->agp->agp_info.agpi_aperbase + hws.addr;
876 dev_priv->hws_map.size = 4 * 1024; /* 4K pages */
877 dev_priv->hws_map.type = 0;
878 dev_priv->hws_map.flags = 0;
879 dev_priv->hws_map.mtrr = 0;
880
881 DRM_DEBUG("set status page: i915_set_status_page: mapoffset 0x%llx\n",
882 dev_priv->hws_map.offset);
883 drm_core_ioremap(&dev_priv->hws_map, dev);
884 if (dev_priv->hws_map.handle == NULL) {
885 dev->dev_private = (void *)dev_priv;
886 (void) i915_dma_cleanup(dev);
887 dev_priv->status_gfx_addr = 0;
888 DRM_ERROR("can not ioremap virtual address for"
889 " G33 hw status page\n");
890 return (ENOMEM);
891 }
892 dev_priv->hw_status_page = dev_priv->hws_map.dev_addr;
893
894 (void) memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
895 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
896 DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
897 dev_priv->status_gfx_addr);
898 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
899 return 0;
900 }
901
902 /*ARGSUSED*/
903 int i915_driver_load(drm_device_t *dev, unsigned long flags)
904 {
905 struct drm_i915_private *dev_priv;
906 unsigned long base, size;
907 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
908
909 /* i915 has 4 more counters */
910 dev->counters += 4;
911 dev->types[6] = _DRM_STAT_IRQ;
912 dev->types[7] = _DRM_STAT_PRIMARY;
913 dev->types[8] = _DRM_STAT_SECONDARY;
914 dev->types[9] = _DRM_STAT_DMA;
915
916 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
917 if (dev_priv == NULL)
918 return ENOMEM;
919
920 (void) memset(dev_priv, 0, sizeof(drm_i915_private_t));
921 dev->dev_private = (void *)dev_priv;
922 dev_priv->dev = dev;
923
924 /* Add register map (needed for suspend/resume) */
925
926 base = drm_get_resource_start(dev, mmio_bar);
927 size = drm_get_resource_len(dev, mmio_bar);
928 dev_priv->mmio_map = drm_alloc(sizeof (drm_local_map_t), DRM_MEM_MAPS);
929 dev_priv->mmio_map->offset = base;
930 dev_priv->mmio_map->size = size;
931 dev_priv->mmio_map->type = _DRM_REGISTERS;
932 dev_priv->mmio_map->flags = _DRM_REMOVABLE;
933 (void) drm_ioremap(dev, dev_priv->mmio_map);
934
935 DRM_DEBUG("i915_driverload mmio %p mmio_map->dev_addr %x", dev_priv->mmio_map, dev_priv->mmio_map->dev_addr);
936
937 #if defined(__i386)
938 dev->driver->use_gem = 0;
939 #else
940 if (IS_I965G(dev)) {
941 dev->driver->use_gem = 1;
942 } else {
943 dev->driver->use_gem = 0;
944 }
945 #endif /* __i386 */
946
947 dev->driver->get_vblank_counter = i915_get_vblank_counter;
948 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
949 #if defined(__i386)
950 if (IS_G4X(dev) || IS_IGDNG(dev) || IS_GM45(dev))
951 #else
952 if (IS_G4X(dev) || IS_IGDNG(dev))
953 #endif
954 {
955 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
956 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
957 }
958
959
960 #ifdef I915_HAVE_GEM
961 i915_gem_load(dev);
962 #endif
963
964 if (!I915_NEED_GFX_HWS(dev)) {
965 ret = i915_init_hardware_status(dev);
966 if(ret)
967 return ret;
968 }
969
970 mutex_init(&dev_priv->user_irq_lock, "userirq", MUTEX_DRIVER, NULL);
971 mutex_init(&dev_priv->error_lock, "error_lock", MUTEX_DRIVER, NULL);
972
973 ret = drm_vblank_init(dev, I915_NUM_PIPE);
974 if (ret) {
975 (void) i915_driver_unload(dev);
976 return ret;
977 }
978
979 return ret;
980 }
981
982 int i915_driver_unload(struct drm_device *dev)
983 {
984 drm_i915_private_t *dev_priv = dev->dev_private;
985
986 i915_free_hardware_status(dev);
987
988 drm_rmmap(dev, dev_priv->mmio_map);
989
990 mutex_destroy(&dev_priv->user_irq_lock);
991
992 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
993 DRM_MEM_DRIVER);
994 dev->dev_private = NULL;
995
996 return 0;
997 }
998
999 /*ARGSUSED*/
1000 int i915_driver_open(drm_device_t * dev, struct drm_file *file_priv)
1001 {
1002 struct drm_i915_file_private *i915_file_priv;
1003
1004 DRM_DEBUG("\n");
1005 i915_file_priv = (struct drm_i915_file_private *)
1006 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
1007
1008 if (!i915_file_priv)
1009 return -ENOMEM;
1010
1011 file_priv->driver_priv = i915_file_priv;
1012
1013 i915_file_priv->mm.last_gem_seqno = 0;
1014 i915_file_priv->mm.last_gem_throttle_seqno = 0;
1015
1016 return 0;
1017 }
1018
1019 void i915_driver_lastclose(drm_device_t * dev)
1020 {
1021 drm_i915_private_t *dev_priv = dev->dev_private;
1022
1023 /* agp off can use this to get called before dev_priv */
1024 if (!dev_priv)
1025 return;
1026
1027 #ifdef I915_HAVE_GEM
1028 i915_gem_lastclose(dev);
1029 #endif
1030
1031 DRM_GETSAREA();
1032 if (dev_priv->agp_heap)
1033 i915_mem_takedown(&(dev_priv->agp_heap));
1034 (void) i915_dma_cleanup(dev);
1035 }
1036
1037 void i915_driver_preclose(drm_device_t * dev, drm_file_t *fpriv)
1038 {
1039 drm_i915_private_t *dev_priv = dev->dev_private;
1040 i915_mem_release(dev, fpriv, dev_priv->agp_heap);
1041 }
1042
1043 /*ARGSUSED*/
1044 void i915_driver_postclose(drm_device_t * dev, struct drm_file *file_priv)
1045 {
1046 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1047
1048 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
1049 }
1050
1051 drm_ioctl_desc_t i915_ioctls[] = {
1052 [DRM_IOCTL_NR(DRM_I915_INIT)] =
1053 {i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1054 [DRM_IOCTL_NR(DRM_I915_FLUSH)] =
1055 {i915_flush_ioctl, DRM_AUTH},
1056 [DRM_IOCTL_NR(DRM_I915_FLIP)] =
1057 {i915_flip_bufs, DRM_AUTH},
1058 [DRM_IOCTL_NR(DRM_I915_BATCHBUFFER)] =
1059 {i915_batchbuffer, DRM_AUTH},
1060 [DRM_IOCTL_NR(DRM_I915_IRQ_EMIT)] =
1061 {i915_irq_emit, DRM_AUTH},
1062 [DRM_IOCTL_NR(DRM_I915_IRQ_WAIT)] =
1063 {i915_irq_wait, DRM_AUTH},
1064 [DRM_IOCTL_NR(DRM_I915_GETPARAM)] =
1065 {i915_getparam, DRM_AUTH},
1066 [DRM_IOCTL_NR(DRM_I915_SETPARAM)] =
1067 {i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1068 [DRM_IOCTL_NR(DRM_I915_ALLOC)] =
1069 {i915_mem_alloc, DRM_AUTH},
1070 [DRM_IOCTL_NR(DRM_I915_FREE)] =
1071 {i915_mem_free, DRM_AUTH},
1072 [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] =
1073 {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1074 [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] =
1075 {i915_cmdbuffer, DRM_AUTH},
1076 [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] =
1077 {i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1078 [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] =
1079 {i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1080 [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] =
1081 {i915_vblank_pipe_get, DRM_AUTH},
1082 [DRM_IOCTL_NR(DRM_I915_VBLANK_SWAP)] =
1083 {i915_vblank_swap, DRM_AUTH},
1084 [DRM_IOCTL_NR(DRM_I915_HWS_ADDR)] =
1085 {i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1086 #ifdef I915_HAVE_GEM
1087 [DRM_IOCTL_NR(DRM_I915_GEM_INIT)] =
1088 {i915_gem_init_ioctl, DRM_AUTH},
1089 [DRM_IOCTL_NR(DRM_I915_GEM_EXECBUFFER)] =
1090 {i915_gem_execbuffer, DRM_AUTH},
1091 [DRM_IOCTL_NR(DRM_I915_GEM_PIN)] =
1092 {i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY},
1093 [DRM_IOCTL_NR(DRM_I915_GEM_UNPIN)] =
1094 {i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY},
1095 [DRM_IOCTL_NR(DRM_I915_GEM_BUSY)] =
1096 {i915_gem_busy_ioctl, DRM_AUTH},
1097 [DRM_IOCTL_NR(DRM_I915_GEM_THROTTLE)] =
1098 {i915_gem_throttle_ioctl, DRM_AUTH},
1099 [DRM_IOCTL_NR(DRM_I915_GEM_ENTERVT)] =
1100 {i915_gem_entervt_ioctl, DRM_AUTH},
1101 [DRM_IOCTL_NR(DRM_I915_GEM_LEAVEVT)] =
1102 {i915_gem_leavevt_ioctl, DRM_AUTH},
1103 [DRM_IOCTL_NR(DRM_I915_GEM_CREATE)] =
1104 {i915_gem_create_ioctl, 0},
1105 [DRM_IOCTL_NR(DRM_I915_GEM_PREAD)] =
1106 {i915_gem_pread_ioctl, 0},
1107 [DRM_IOCTL_NR(DRM_I915_GEM_PWRITE)] =
1108 {i915_gem_pwrite_ioctl, 0},
1109 [DRM_IOCTL_NR(DRM_I915_GEM_MMAP)] =
1110 {i915_gem_mmap_ioctl, 0},
1111 [DRM_IOCTL_NR(DRM_I915_GEM_SET_DOMAIN)] =
1112 {i915_gem_set_domain_ioctl, 0},
1113 [DRM_IOCTL_NR(DRM_I915_GEM_SW_FINISH)] =
1114 {i915_gem_sw_finish_ioctl, 0},
1115 [DRM_IOCTL_NR(DRM_I915_GEM_SET_TILING)] =
1116 {i915_gem_set_tiling, 0},
1117 [DRM_IOCTL_NR(DRM_I915_GEM_GET_TILING)] =
1118 {i915_gem_get_tiling, 0},
1119 [DRM_IOCTL_NR(DRM_I915_GEM_GET_APERTURE)] =
1120 {i915_gem_get_aperture_ioctl, 0},
1121 #endif
1122 };
1123
1124 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1125
1126 /**
1127 * Determine if the device really is AGP or not.
1128 *
1129 * All Intel graphics chipsets are treated as AGP, even if they are really
1130 * PCI-e.
1131 *
1132 * \param dev The device to be tested.
1133 *
1134 * \returns
1135 * A value of 1 is always retured to indictate every i9x5 is AGP.
1136 */
1137 /*ARGSUSED*/
1138 int i915_driver_device_is_agp(drm_device_t * dev)
1139 {
1140 return 1;
1141 }
1142
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