arch/powerpc/mm/44x_mmu.c

   1 /*
   2  * Modifications by Matt Porter (mporter@mvista.com) to support
   3  * PPC44x Book E processors.
   4  *
   5  * This file contains the routines for initializing the MMU
   6  * on the 4xx series of chips.
   7  *  -- paulus
   8  *
   9  *  Derived from arch/ppc/mm/init.c:
  10  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  11  *
  12  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  13  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
  14  *    Copyright (C) 1996 Paul Mackerras
  15  *
  16  *  Derived from "arch/i386/mm/init.c"
  17  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
  18  *
  19  *  This program is free software; you can redistribute it and/or
  20  *  modify it under the terms of the GNU General Public License
  21  *  as published by the Free Software Foundation; either version
  22  *  2 of the License, or (at your option) any later version.
  23  *
  24  */
  25
  26 #include <linux/init.h>
  27 #include <asm/mmu.h>
  28 #include <asm/system.h>
  29 #include <asm/page.h>
  30
  31 #include "mmu_decl.h"
  32
  33 /* Used by the 44x TLB replacement exception handler.
  34  * Just needed it declared someplace.
  35  */
  36 unsigned int tlb_44x_index; /* = 0 */
  37 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
  38
  39 /*
  40  * "Pins" a 256MB TLB entry in AS0 for kernel lowmem
  41  */
  42 static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
  43 {
  44         __asm__ __volatile__(
  45                 "tlbwe  %2,%3,%4\n"
  46                 "tlbwe  %1,%3,%5\n"
  47                 "tlbwe  %0,%3,%6\n"
  48         :
  49         : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
  50           "r" (phys),
  51           "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
  52           "r" (tlb_44x_hwater--), /* slot for this TLB entry */
  53           "i" (PPC44x_TLB_PAGEID),
  54           "i" (PPC44x_TLB_XLAT),
  55           "i" (PPC44x_TLB_ATTRIB));
  56 }
  57
  58 void __init MMU_init_hw(void)
  59 {
  60         flush_instruction_cache();
  61 }
  62
  63 unsigned long __init mmu_mapin_ram(void)
  64 {
  65         unsigned long addr;
  66
  67         /* Pin in enough TLBs to cover any lowmem not covered by the
  68          * initial 256M mapping established in head_44x.S */
  69         for (addr = PPC_PIN_SIZE; addr < total_lowmem;
  70              addr += PPC_PIN_SIZE)
  71                 ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
  72
  73         return total_lowmem;
  74 }