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2 /*---------------------------------------------------------------*/
3 /*--- begin libvex_ir.h ---*/
4 /*---------------------------------------------------------------*/
6 /*
7 This file is part of Valgrind, a dynamic binary instrumentation
8 framework.
10 Copyright (C) 2004-2017 OpenWorks LLP
11 info@open-works.net
13 This program is free software; you can redistribute it and/or
14 modify it under the terms of the GNU General Public License as
15 published by the Free Software Foundation; either version 2 of the
16 License, or (at your option) any later version.
18 This program is distributed in the hope that it will be useful, but
19 WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, see <http://www.gnu.org/licenses/>.
26 The GNU General Public License is contained in the file COPYING.
28 Neither the names of the U.S. Department of Energy nor the
29 University of California nor the names of its contributors may be
30 used to endorse or promote products derived from this software
31 without prior written permission.
32 */
34 #ifndef __LIBVEX_IR_H
35 #define __LIBVEX_IR_H
40 /*---------------------------------------------------------------*/
41 /*--- High-level IR description ---*/
42 /*---------------------------------------------------------------*/
44 /* Vex IR is an architecture-neutral intermediate representation.
45 Unlike some IRs in systems similar to Vex, it is not like assembly
46 language (ie. a list of instructions). Rather, it is more like the
47 IR that might be used in a compiler.
49 Code blocks
50 ~~~~~~~~~~~
51 The code is broken into small code blocks ("superblocks", type:
52 'IRSB'). Each code block typically represents from 1 to perhaps 50
53 instructions. IRSBs are single-entry, multiple-exit code blocks.
54 Each IRSB contains three things:
55 - a type environment, which indicates the type of each temporary
56 value present in the IRSB
57 - a list of statements, which represent code
58 - a jump that exits from the end the IRSB
59 Because the blocks are multiple-exit, there can be additional
60 conditional exit statements that cause control to leave the IRSB
61 before the final exit. Also because of this, IRSBs can cover
62 multiple non-consecutive sequences of code (up to 3). These are
63 recorded in the type VexGuestExtents (see libvex.h).
65 Statements and expressions
66 ~~~~~~~~~~~~~~~~~~~~~~~~~~
67 Statements (type 'IRStmt') represent operations with side-effects,
68 eg. guest register writes, stores, and assignments to temporaries.
69 Expressions (type 'IRExpr') represent operations without
70 side-effects, eg. arithmetic operations, loads, constants.
71 Expressions can contain sub-expressions, forming expression trees,
72 eg. (3 + (4 * load(addr1)).
74 Storage of guest state
75 ~~~~~~~~~~~~~~~~~~~~~~
76 The "guest state" contains the guest registers of the guest machine
77 (ie. the machine that we are simulating). It is stored by default
78 in a block of memory supplied by the user of the VEX library,
79 generally referred to as the guest state (area). To operate on
80 these registers, one must first read ("Get") them from the guest
81 state into a temporary value. Afterwards, one can write ("Put")
82 them back into the guest state.
84 Get and Put are characterised by a byte offset into the guest
85 state, a small integer which effectively gives the identity of the
86 referenced guest register, and a type, which indicates the size of
87 the value to be transferred.
89 The basic "Get" and "Put" operations are sufficient to model normal
90 fixed registers on the guest. Selected areas of the guest state
91 can be treated as a circular array of registers (type:
92 'IRRegArray'), which can be indexed at run-time. This is done with
93 the "GetI" and "PutI" primitives. This is necessary to describe
94 rotating register files, for example the x87 FPU stack, SPARC
95 register windows, and the Itanium register files.
97 Examples, and flattened vs. unflattened code
98 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
99 For example, consider this x86 instruction:
101 addl %eax, %ebx
103 One Vex IR translation for this code would be this:
105 ------ IMark(0x24F275, 7, 0) ------
106 t3 = GET:I32(0) # get %eax, a 32-bit integer
107 t2 = GET:I32(12) # get %ebx, a 32-bit integer
108 t1 = Add32(t3,t2) # addl
109 PUT(0) = t1 # put %eax
111 (For simplicity, this ignores the effects on the condition codes, and
112 the update of the instruction pointer.)
114 The "IMark" is an IR statement that doesn't represent actual code.
115 Instead it indicates the address and length of the original
116 instruction. The numbers 0 and 12 are offsets into the guest state
117 for %eax and %ebx. The full list of offsets for an architecture
118 <ARCH> can be found in the type VexGuest<ARCH>State in the file
119 VEX/pub/libvex_guest_<ARCH>.h.
121 The five statements in this example are:
122 - the IMark
123 - three assignments to temporaries
124 - one register write (put)
126 The six expressions in this example are:
127 - two register reads (gets)
128 - one arithmetic (add) operation
129 - three temporaries (two nested within the Add32, one in the PUT)
131 The above IR is "flattened", ie. all sub-expressions are "atoms",
132 either constants or temporaries. An equivalent, unflattened version
133 would be:
135 PUT(0) = Add32(GET:I32(0), GET:I32(12))
137 IR is guaranteed to be flattened at instrumentation-time. This makes
138 instrumentation easier. Equivalent flattened and unflattened IR
139 typically results in the same generated code.
141 Another example, this one showing loads and stores:
143 addl %edx,4(%eax)
145 This becomes (again ignoring condition code and instruction pointer
146 updates):
148 ------ IMark(0x4000ABA, 3, 0) ------
149 t3 = Add32(GET:I32(0),0x4:I32)
150 t2 = LDle:I32(t3)
151 t1 = GET:I32(8)
152 t0 = Add32(t2,t1)
153 STle(t3) = t0
155 The "le" in "LDle" and "STle" is short for "little-endian".
157 No need for deallocations
158 ~~~~~~~~~~~~~~~~~~~~~~~~~
159 Although there are allocation functions for various data structures
160 in this file, there are no deallocation functions. This is because
161 Vex uses a memory allocation scheme that automatically reclaims the
162 memory used by allocated structures once translation is completed.
163 This makes things easier for tools that instruments/transforms code
164 blocks.
166 SSAness and typing
167 ~~~~~~~~~~~~~~~~~~
168 The IR is fully typed. For every IRSB (IR block) it is possible to
169 say unambiguously whether or not it is correctly typed.
170 Incorrectly typed IR has no meaning and the VEX will refuse to
171 process it. At various points during processing VEX typechecks the
172 IR and aborts if any violations are found. This seems overkill but
173 makes it a great deal easier to build a reliable JIT.
175 IR also has the SSA property. SSA stands for Static Single
176 Assignment, and what it means is that each IR temporary may be
177 assigned to only once. This idea became widely used in compiler
178 construction in the mid to late 90s. It makes many IR-level
179 transformations/code improvements easier, simpler and faster.
180 Whenever it typechecks an IR block, VEX also checks the SSA
181 property holds, and will abort if not so. So SSAness is
182 mechanically and rigidly enforced.
183 */
185 /*---------------------------------------------------------------*/
186 /*--- Type definitions for the IR ---*/
187 /*---------------------------------------------------------------*/
189 /* General comments about naming schemes:
191 All publically visible functions contain the name of the primary
192 type on which they operate (IRFoo, IRBar, etc). Hence you should
193 be able to identify these functions by grepping for "IR[A-Z]".
195 For some type 'IRFoo':
197 - ppIRFoo is the printing method for IRFoo, printing it to the
198 output channel specified in the LibVEX_Initialise call.
200 - eqIRFoo is a structural equality predicate for IRFoos.
202 - deepCopyIRFoo is a deep copy constructor for IRFoos.
203 It recursively traverses the entire argument tree and
204 produces a complete new tree. All types have a deep copy
205 constructor.
207 - shallowCopyIRFoo is the shallow copy constructor for IRFoos.
208 It creates a new top-level copy of the supplied object,
209 but does not copy any sub-objects. Only some types have a
210 shallow copy constructor.
211 */
213 /* ------------------ Types ------------------ */
215 /* A type indicates the size of a value, and whether it's an integer, a
216 float, or a vector (SIMD) value. */
217 typedef
220 Ity_I1,
221 Ity_I8,
222 Ity_I16,
223 Ity_I32,
224 Ity_I64,
234 Ity_V256 /* 256-bit SIMD */
235 }
236 IRType;
238 /* Pretty-print an IRType */
241 /* Get the size (in bytes) of an IRType */
244 /* Translate 1/2/4/8 into Ity_I{8,16,32,64} respectively. Asserts on
245 any other input. */
249 /* ------------------ Endianness ------------------ */
251 /* IREndness is used in load IRExprs and store IRStmts. */
252 typedef
255 Iend_BE /* big endian */
256 }
257 IREndness;
260 /* ------------------ Constants ------------------ */
262 /* IRConsts are used within 'Const' and 'Exit' IRExprs. */
264 /* The various kinds of constant. */
265 typedef
268 Ico_U8,
269 Ico_U16,
270 Ico_U32,
271 Ico_U64,
274 as a IEEE754 single value. */
277 as a IEEE754 double value. */
279 (repeated 8 times) for each of the 16 x 1-byte lanes */
280 Ico_V256 /* 256-bit restricted vector constant, with 1 bit
281 (repeated 8 times) for each of the 32 x 1-byte lanes */
282 }
283 IRConstTag;
285 /* A constant. Stored as a tagged union. 'tag' indicates what kind of
286 constant this is. 'Ico' is the union that holds the fields. If an
287 IRConst 'c' has c.tag equal to Ico_U32, then it's a 32-bit constant,
288 and its value can be accessed with 'c.Ico.U32'. */
289 typedef
291 IRConstTag tag;
293 Bool U1;
294 UChar U8;
295 UShort U16;
296 UInt U32;
297 ULong U64;
298 Float F32;
299 UInt F32i;
300 Double F64;
301 ULong F64i;
305 }
306 IRConst;
308 /* IRConst constructors */
321 /* Deep-copy an IRConst */
324 /* Pretty-print an IRConst */
327 /* Compare two IRConsts for equality */
331 /* ------------------ Call targets ------------------ */
333 /* Describes a helper function to call. The name part is purely for
334 pretty printing and not actually used. regparms=n tells the back
335 end that the callee has been declared
336 "__attribute__((regparm(n)))", although indirectly using the
337 VEX_REGPARM(n) macro. On some targets (x86) the back end will need
338 to construct a non-standard sequence to call a function declared
339 like this.
341 mcx_mask is a sop to Memcheck. It indicates which args should be
342 considered 'always defined' when lazily computing definedness of
343 the result. Bit 0 of mcx_mask corresponds to args[0], bit 1 to
344 args[1], etc. If a bit is set, the corresponding arg is excluded
345 (hence "x" in "mcx") from definedness checking.
346 */
348 typedef
350 Int regparms;
353 UInt mcx_mask;
354 }
355 IRCallee;
357 /* Create an IRCallee. */
360 /* Deep-copy an IRCallee. */
363 /* Pretty-print an IRCallee. */
367 /* ------------------ Guest state arrays ------------------ */
369 /* This describes a section of the guest state that we want to
370 be able to index at run time, so as to be able to describe
371 indexed or rotating register files on the guest. */
372 typedef
377 }
378 IRRegArray;
388 /* ------------------ Temporaries ------------------ */
390 /* This represents a temporary, eg. t1. The IR optimiser relies on the
391 fact that IRTemps are 32-bit ints. Do not change them to be ints of
392 any other size. */
395 /* Pretty-print an IRTemp. */
398 #define IRTemp_INVALID ((IRTemp)0xFFFFFFFF)
401 /* --------------- Primops (arity 1,2,3 and 4) --------------- */
403 /* Primitive operations that are used in Unop, Binop, Triop and Qop
404 IRExprs. Once we take into account integer, floating point and SIMD
405 operations of all the different sizes, there are quite a lot of them.
406 Most instructions supported by the architectures that Vex supports
407 (x86, PPC, etc) are represented. Some more obscure ones (eg. cpuid)
408 are not; they are instead handled with dirty helpers that emulate
409 their functionality. Such obscure ones are thus not directly visible
410 in the IR, but their effects on guest state (memory and registers)
411 are made visible via the annotations in IRDirty structures.
413 2018-Dec-27: some of int<->fp conversion operations have been renamed so as
414 to have a trailing _DEP, meaning "deprecated". This is because they don't
415 specify a rounding mode to be used for the conversion and so are
416 underspecified. Their use should be replaced with equivalents that do
417 specify a rounding mode, either as a first argument or using a suffix on the
418 name, that indicates the rounding mode to use.
419 */
420 typedef
422 /* -- Do not change this ordering. The IR generators rely on
423 (eg) Iop_Add64 == IopAdd8 + 3. -- */
428 /* Signless mul. MullS/MullU is elsewhere. */
436 /* Integer comparisons. */
439 /* Tags for unary ops */
442 /* Exactly like CmpEQ8/16/32/64, but carrying the additional
443 hint that these compute the success/failure of a CAS
444 operation, and hence are almost certainly applied to two
445 copies of the same value, which in turn has implications for
446 Memcheck's instrumentation. */
450 /* Exactly like CmpNE8/16/32/64, but carrying the additional
451 hint that these needs expensive definedness tracking. */
454 /* -- Ordering not important after here. -- */
456 /* Widening multiplies */
460 /* Counting bits */
461 /* Ctz64/Ctz32/Clz64/Clz32 are UNDEFINED when given arguments of zero.
462 You must ensure they are never given a zero argument. As of
463 2018-Nov-14 they are deprecated. Try to use the Nat variants
464 immediately below, if you can.
465 */
468 /* Count leading/trailing zeroes, with "natural" semantics for the
469 case where the input is zero: then the result is the number of bits
470 in the word. */
473 /* Population count -- compute the number of 1 bits in the argument. */
476 /* Standard integer comparisons */
482 /* As a sop to Valgrind-Memcheck, the following are useful. */
488 /* PowerPC-style 3-way integer comparisons. Without them it is
489 difficult to simulate PPC efficiently.
490 op(x,y) | x < y = 0x8 else
491 | x > y = 0x4 else
492 | x == y = 0x2
493 */
497 /* Division */
498 /* TODO: clarify semantics wrt rounding, negative values, whatever */
504 // concat with 64 0's (low))
507 // concat with 32 0's (low))
511 // of which lo half is div and hi half is mod
515 // of which lo half is div and hi half is mod
519 // of which lo half is div and hi half is mod
521 // of which lo half is div and hi half is mod
523 // of which lo half is div and hi half is mod
525 // of which lo half is div and hi half is mod
527 /* Integer conversions. Some of these are redundant (eg
528 Iop_64to8 is the same as Iop_64to32 and then Iop_32to8), but
529 having a complete set reduces the typical dynamic size of IR
530 and makes the instruction selectors easier to write. */
532 /* Widening conversions */
535 Iop_32Uto64,
538 Iop_32Sto64,
540 /* Narrowing conversions */
542 /* 8 <-> 16 bit conversions */
546 /* 16 <-> 32 bit conversions */
550 /* 32 <-> 64 bit conversions */
554 /* 64 <-> 128 bit conversions */
558 /* 1-bit stuff */
572 /* ------ Floating point. We try to be IEEE754 compliant. ------ */
574 /* --- Simple stuff as mandated by 754. --- */
576 /* Binary operations, with rounding. */
577 /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
580 /* :: IRRoundingMode(I32) x F32 x F32 -> F32 */
583 /* Variants of the above which produce a 64-bit result but which
584 round their result to a IEEE float range first. */
585 /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
588 /* Unary operations, without rounding. */
589 /* :: F64 -> F64 */
592 /* :: F32 -> F32 */
595 /* Unary operations, with rounding. */
596 /* :: IRRoundingMode(I32) x F64 -> F64 */
597 Iop_SqrtF64,
599 /* :: IRRoundingMode(I32) x F32 -> F32 */
600 Iop_SqrtF32,
602 /* Comparison, yielding GT/LT/EQ/UN(ordered), as per the following:
603 0x45 Unordered
604 0x01 LT
605 0x00 GT
606 0x40 EQ
607 This just happens to be the Intel encoding. The values
608 are recorded in the type IRCmpF64Result.
609 */
610 /* :: F64 x F64 -> IRCmpF64Result(I32) */
611 Iop_CmpF64,
612 Iop_CmpF32,
613 Iop_CmpF128,
615 /* --- Int to/from FP conversions. --- */
617 /* For the most part, these take a first argument :: Ity_I32 (as
618 IRRoundingMode) which is an indication of the rounding mode
619 to use, as per the following encoding ("the standard
620 encoding"):
621 00b to nearest (the default)
622 01b to -infinity
623 10b to +infinity
624 11b to zero
625 This just happens to be the Intel encoding. For reference only,
626 the PPC encoding is:
627 00b to nearest (the default)
628 01b to zero
629 10b to +infinity
630 11b to -infinity
631 Any PPC -> IR front end will have to translate these PPC
632 encodings, as encoded in the guest state, to the standard
633 encodings, to pass to the primops.
634 For reference only, the ARM VFP encoding is:
635 00b to nearest
636 01b to +infinity
637 10b to -infinity
638 11b to zero
639 Again, this will have to be converted to the standard encoding
640 to pass to primops.
642 If one of these conversions gets an out-of-range condition,
643 or a NaN, as an argument, the result is host-defined. On x86
644 the "integer indefinite" value 0x80..00 is produced. On PPC
645 it is either 0x80..00 or 0x7F..FF depending on the sign of
646 the argument.
648 On ARMvfp, when converting to a signed integer result, the
649 overflow result is 0x80..00 for negative args and 0x7F..FF
650 for positive args. For unsigned integer results it is
651 0x00..00 and 0xFF..FF respectively.
653 Rounding is required whenever the destination type cannot
654 represent exactly all values of the source type.
655 */
679 /* Conversion between floating point formats */
683 /* Reinterpretation. Take an F64 and produce an I64 with
684 the same bit pattern, or vice versa. */
688 /* Support for 128-bit floating point */
693 /* :: IRRoundingMode(I32) x F128 x F128 -> F128 */
700 /* :: F128 -> F128 */
703 /* :: IRRoundingMode(I32) x F128 -> F128 */
704 Iop_SqrtF128,
722 /* Truncate to the specified value, source and result
723 * are stroed in a F128 register.
724 */
730 /* --- guest x86/amd64 specifics, not mandated by 754. --- */
732 /* Binary ops, with rounding. */
733 /* :: IRRoundingMode(I32) x F64 x F64 -> F64 */
742 /* Note that on x86 guest, PRem1{C3210} has the same behaviour
743 as the IEEE mandated RemF64, except it is limited in the
744 range of its operand. Hence the partialness. */
746 /* Unary ops, with rounding. */
747 /* :: IRRoundingMode(I32) x F64 -> F64 */
753 as F128) */
755 as F64) */
757 as F32) */
759 /* --- guest s390 specifics, not mandated by 754. --- */
761 /* Fused multiply-add/sub */
762 /* :: IRRoundingMode(I32) x F32 x F32 x F32 -> F32
763 (computes arg2 * arg3 +/- arg4) */
766 /* --- guest ppc32/64 specifics, not mandated by 754. --- */
768 /* Ternary operations, with rounding. */
769 /* Fused multiply-add/sub, with 112-bit intermediate
770 precision for ppc.
771 Also used to implement fused multiply-add/sub for s390. */
772 /* :: IRRoundingMode(I32) x F64 x F64 x F64 -> F64
773 (computes arg2 * arg3 +/- arg4) */
776 /* Variants of the above which produce a 64-bit result but which
777 round their result to a IEEE float range first. */
778 /* :: IRRoundingMode(I32) x F64 x F64 x F64 -> F64 */
781 /* :: F64 -> F64 */
788 /* :: F64 -> F32 */
791 /* :: IRRoundingMode(I32) x F64 -> F64 */
793 /* NB: pretty much the same as Iop_F64toF32, except no change
794 of type. */
796 /* --- guest arm64 specifics, not mandated by 754. --- */
801 /* --------- Possibly required by IEEE 754-2008. --------- */
808 /* ------------------ 16-bit scalar FP ------------------ */
816 /* ------------------ 32-bit SIMD Integer ------------------ */
818 /* 32x1 saturating add/sub (ok, well, not really SIMD :) */
819 Iop_QAdd32S,
820 Iop_QSub32S,
822 /* 16x2 add/sub, also signed/unsigned saturating variants */
827 /* 16x2 signed/unsigned halving add/sub. For each lane, these
828 compute bits 16:1 of (eg) sx(argL) + sx(argR),
829 or zx(argL) - zx(argR) etc. */
833 /* 8x4 add/sub, also signed/unsigned saturating variants */
838 /* 8x4 signed/unsigned halving add/sub. For each lane, these
839 compute bits 8:1 of (eg) sx(argL) + sx(argR),
840 or zx(argL) - zx(argR) etc. */
844 /* 8x4 sum of absolute unsigned differences. */
845 Iop_Sad8Ux4,
847 /* MISC (vector integer cmp != 0) */
850 /* Byte swap in a 32-bit word */
851 Iop_Reverse8sIn32_x1,
853 /* ------------------ 64-bit SIMD FP ------------------------ */
855 /* Conversion to/from int */
856 // Deprecated: these don't specify a rounding mode
861 /* Fixed32 format is floating-point number with fixed number of fraction
862 bits. The number of fraction bits is passed as a second argument of
863 type I8. */
867 /* Binary operations */
869 /* Pairwise Min and Max. See integer pairwise operations for more
870 details. */
872 /* Note: For the following compares, the arm front-end assumes a
873 nan in a lane of either argument returns zero for that lane. */
876 /* Vector Reciprocal Estimate finds an approximate reciprocal of each
877 element in the operand vector, and places the results in the destination
878 vector. */
879 Iop_RecipEst32Fx2,
881 /* Vector Reciprocal Step computes (2.0 - arg1 * arg2).
882 Note, that if one of the arguments is zero and another one is infinity
883 of arbitrary sign the result of the operation is 2.0. */
884 Iop_RecipStep32Fx2,
886 /* Vector Reciprocal Square Root Estimate finds an approximate reciprocal
887 square root of each element in the operand vector. */
888 Iop_RSqrtEst32Fx2,
890 /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0.
891 Note, that of one of the arguments is zero and another one is infiinty
892 of arbitrary sign the result of the operation is 1.5. */
893 Iop_RSqrtStep32Fx2,
895 /* Unary */
898 /* ------------------ 64-bit SIMD Integer. ------------------ */
900 /* MISC (vector integer cmp != 0) */
903 /* ADDITION (normal / unsigned sat / signed sat) */
908 /* PAIRWISE operations */
909 /* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) =
910 [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */
916 /* Longening variant is unary. The resulting vector contains two times
917 less elements than operand, but they are two times wider.
918 Example:
919 Iop_PAddL16Ux4( [a,b,c,d] ) = [a+b,c+d]
920 where a+b and c+d are unsigned 32-bit values. */
924 /* SUBTRACTION (normal / unsigned sat / signed sat) */
929 /* ABSOLUTE VALUE */
932 /* MULTIPLICATION (normal / high half of signed/unsigned / plynomial ) */
934 Iop_Mul32Fx2,
935 Iop_MulHi16Ux4,
936 Iop_MulHi16Sx4,
937 /* Plynomial multiplication treats it's arguments as coefficients of
938 polynoms over {0, 1}. */
939 Iop_PolynomialMul8x8,
941 /* Vector Saturating Doubling Multiply Returning High Half and
942 Vector Saturating Rounding Doubling Multiply Returning High Half */
943 /* These IROp's multiply corresponding elements in two vectors, double
944 the results, and place the most significant half of the final results
945 in the destination vector. The results are truncated or rounded. If
946 any of the results overflow, they are saturated. */
950 /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
951 Iop_Avg8Ux8,
952 Iop_Avg16Ux4,
954 /* MIN/MAX */
960 /* COMPARISON */
965 /* COUNT ones / leading zeroes / leading sign bits (not including topmost
966 bit) */
967 Iop_Cnt8x8,
970 Iop_Clz64x2,
972 /*Vector COUNT trailing zeros */
975 /* VECTOR x VECTOR SHIFT / ROTATE */
981 /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
986 /* VECTOR x VECTOR SATURATING SHIFT */
989 /* VECTOR x INTEGER SATURATING SHIFT */
997 /* NARROWING (binary)
998 -- narrow 2xI64 into 1xI64, hi half from left arg */
999 /* For saturated narrowing, I believe there are 4 variants of
1000 the basic arithmetic operation, depending on the signedness
1001 of argument and result. Here are examples that exemplify
1002 what I mean:
1004 QNarrow16Uto8U ( UShort x ) if (x >u 255) x = 255;
1005 return x[7:0];
1007 QNarrow16Sto8S ( Short x ) if (x <s -128) x = -128;
1008 if (x >s 127) x = 127;
1009 return x[7:0];
1011 QNarrow16Uto8S ( UShort x ) if (x >u 127) x = 127;
1012 return x[7:0];
1014 QNarrow16Sto8U ( Short x ) if (x <s 0) x = 0;
1015 if (x >s 255) x = 255;
1016 return x[7:0];
1017 */
1018 Iop_QNarrowBin16Sto8Ux8,
1022 /* INTERLEAVING */
1023 /* Interleave lanes from low or high halves of
1024 operands. Most-significant result lane is from the left
1025 arg. */
1028 /* Interleave odd/even lanes of operands. Most-significant result lane
1029 is from the left arg. Note that Interleave{Odd,Even}Lanes32x2 are
1030 identical to Interleave{HI,LO}32x2 and so are omitted.*/
1034 /* CONCATENATION -- build a new value by concatenating either
1035 the even or odd lanes of both operands. Note that
1036 Cat{Odd,Even}Lanes32x2 are identical to Interleave{HI,LO}32x2
1037 and so are omitted. */
1041 /* GET / SET elements of VECTOR
1042 GET is binop (I64, I8) -> I<elem_size>
1043 SET is triop (I64, I8, I<elem_size>) -> I64 */
1044 /* Note: the arm back-end handles only constant second argument */
1048 /* DUPLICATING -- copy value to all lanes */
1051 /* SLICE -- produces the lowest 64 bits of (arg1:arg2) >> (8 * arg3).
1052 arg3 is a shift amount in bytes and may be between 0 and 8
1053 inclusive. When 0, the result is arg2; when 8, the result is arg1.
1054 Not all back ends handle all values. The arm32 and arm64 back
1055 ends handle only immediate arg3 values. */
1058 /* REVERSE the order of chunks in vector lanes. Chunks must be
1059 smaller than the vector lanes (obviously) and so may be 8-, 16- and
1060 32-bit in size. Note that the degenerate case,
1061 Iop_Reverse8sIn64_x1, is a simply a vanilla byte-swap. */
1062 /* Examples:
1063 Reverse8sIn16_x4([a,b,c,d,e,f,g,h]) = [b,a,d,c,f,e,h,g]
1064 Reverse8sIn32_x2([a,b,c,d,e,f,g,h]) = [d,c,b,a,h,g,f,e]
1065 Reverse8sIn64_x1([a,b,c,d,e,f,g,h]) = [h,g,f,e,d,c,b,a] */
1066 Iop_Reverse8sIn16_x4,
1070 /* PERMUTING -- copy src bytes to dst,
1071 as indexed by control vector bytes:
1072 for i in 0 .. 7 . result[i] = argL[ argR[i] ]
1073 argR[i] values may only be in the range 0 .. 7, else behaviour
1074 is undefined. That is, argR[i][7:3] must be zero. */
1075 Iop_Perm8x8,
1077 /* PERMUTING with optional zeroing:
1078 for i in 0 .. 7 . result[i] = if argR[i] bit 7 is set
1079 then zero else argL[ argR[i] ]
1080 argR[i][6:3] must be zero, else behaviour is undefined.
1081 */
1082 Iop_PermOrZero8x8,
1084 /* MISC CONVERSION -- get high bits of each byte lane, a la
1085 x86/amd64 pmovmskb */
1088 /* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate
1089 See floating-point equivalents for details. */
1092 /* ------------------ Decimal Floating Point ------------------ */
1094 /* ARITHMETIC INSTRUCTIONS 64-bit
1095 ----------------------------------
1096 IRRoundingMode(I32) X D64 X D64 -> D64
1097 */
1100 /* ARITHMETIC INSTRUCTIONS 128-bit
1101 ----------------------------------
1102 IRRoundingMode(I32) X D128 X D128 -> D128
1103 */
1106 /* SHIFT SIGNIFICAND INSTRUCTIONS
1107 * The DFP significand is shifted by the number of digits specified
1108 * by the U8 operand. Digits shifted out of the leftmost digit are
1109 * lost. Zeros are supplied to the vacated positions on the right.
1110 * The sign of the result is the same as the sign of the original
1111 * operand.
1112 *
1113 * D64 x U8 -> D64 left shift and right shift respectively */
1116 /* D128 x U8 -> D128 left shift and right shift respectively */
1120 /* FORMAT CONVERSION INSTRUCTIONS
1121 * D32 -> D64
1122 */
1123 Iop_D32toD64,
1125 /* D64 -> D128 */
1126 Iop_D64toD128,
1128 /* I32S -> D128 */
1129 Iop_I32StoD128,
1131 /* I32U -> D128 */
1132 Iop_I32UtoD128,
1134 /* I64S -> D128 */
1135 Iop_I64StoD128,
1137 /* I64U -> D128 */
1138 Iop_I64UtoD128,
1140 /* IRRoundingMode(I32) x D64 -> D32 */
1141 Iop_D64toD32,
1143 /* IRRoundingMode(I32) x D128 -> D64 */
1144 Iop_D128toD64,
1146 /* I32S -> D64 */
1147 Iop_I32StoD64,
1149 /* I32U -> D64 */
1150 Iop_I32UtoD64,
1152 /* IRRoundingMode(I32) x I64 -> D64 */
1153 Iop_I64StoD64,
1155 /* IRRoundingMode(I32) x I64 -> D64 */
1156 Iop_I64UtoD64,
1158 /* IRRoundingMode(I32) x D64 -> I32 */
1159 Iop_D64toI32S,
1161 /* IRRoundingMode(I32) x D64 -> I32 */
1162 Iop_D64toI32U,
1164 /* IRRoundingMode(I32) x D64 -> I64 */
1165 Iop_D64toI64S,
1167 /* IRRoundingMode(I32) x D64 -> I64 */
1168 Iop_D64toI64U,
1170 /* IRRoundingMode(I32) x D128 -> I32 */
1171 Iop_D128toI32S,
1173 /* IRRoundingMode(I32) x D128 -> I32 */
1174 Iop_D128toI32U,
1176 /* IRRoundingMode(I32) x D128 -> I64 */
1177 Iop_D128toI64S,
1179 /* IRRoundingMode(I32) x D128 -> I64 */
1180 Iop_D128toI64U,
1182 /* IRRoundingMode(I32) x F32 -> D32 */
1183 Iop_F32toD32,
1185 /* IRRoundingMode(I32) x F32 -> D64 */
1186 Iop_F32toD64,
1188 /* IRRoundingMode(I32) x F32 -> D128 */
1189 Iop_F32toD128,
1191 /* IRRoundingMode(I32) x F64 -> D32 */
1192 Iop_F64toD32,
1194 /* IRRoundingMode(I32) x F64 -> D64 */
1195 Iop_F64toD64,
1197 /* IRRoundingMode(I32) x F64 -> D128 */
1198 Iop_F64toD128,
1200 /* IRRoundingMode(I32) x F128 -> D32 */
1201 Iop_F128toD32,
1203 /* IRRoundingMode(I32) x F128 -> D64 */
1204 Iop_F128toD64,
1206 /* IRRoundingMode(I32) x F128 -> D128 */
1207 Iop_F128toD128,
1209 /* IRRoundingMode(I32) x D32 -> F32 */
1210 Iop_D32toF32,
1212 /* IRRoundingMode(I32) x D32 -> F64 */
1213 Iop_D32toF64,
1215 /* IRRoundingMode(I32) x D32 -> F128 */
1216 Iop_D32toF128,
1218 /* IRRoundingMode(I32) x D64 -> F32 */
1219 Iop_D64toF32,
1221 /* IRRoundingMode(I32) x D64 -> F64 */
1222 Iop_D64toF64,
1224 /* IRRoundingMode(I32) x D64 -> F128 */
1225 Iop_D64toF128,
1227 /* IRRoundingMode(I32) x D128 -> F32 */
1228 Iop_D128toF32,
1230 /* IRRoundingMode(I32) x D128 -> F64 */
1231 Iop_D128toF64,
1233 /* IRRoundingMode(I32) x D128 -> F128 */
1234 Iop_D128toF128,
1236 /* ROUNDING INSTRUCTIONS
1237 * IRRoundingMode(I32) x D64 -> D64
1238 * The D64 operand, if a finite number, it is rounded to a
1239 * floating point integer value, i.e. no fractional part.
1240 */
1241 Iop_RoundD64toInt,
1243 /* IRRoundingMode(I32) x D128 -> D128 */
1244 Iop_RoundD128toInt,
1246 /* COMPARE INSTRUCTIONS
1247 * D64 x D64 -> IRCmpD64Result(I32) */
1248 Iop_CmpD64,
1250 /* D128 x D128 -> IRCmpD128Result(I32) */
1251 Iop_CmpD128,
1253 /* COMPARE BIASED EXPONENET INSTRUCTIONS
1254 * D64 x D64 -> IRCmpD64Result(I32) */
1255 Iop_CmpExpD64,
1257 /* D128 x D128 -> IRCmpD128Result(I32) */
1258 Iop_CmpExpD128,
1260 /* QUANTIZE AND ROUND INSTRUCTIONS
1261 * The source operand is converted and rounded to the form with the
1262 * immediate exponent specified by the rounding and exponent parameter.
1263 *
1264 * The second operand is converted and rounded to the form
1265 * of the first operand's exponent and the rounded based on the specified
1266 * rounding mode parameter.
1267 *
1268 * IRRoundingMode(I32) x D64 x D64-> D64 */
1269 Iop_QuantizeD64,
1271 /* IRRoundingMode(I32) x D128 x D128 -> D128 */
1272 Iop_QuantizeD128,
1274 /* IRRoundingMode(I32) x I8 x D64 -> D64
1275 * The Decimal Floating point operand is rounded to the requested
1276 * significance given by the I8 operand as specified by the rounding
1277 * mode.
1278 */
1279 Iop_SignificanceRoundD64,
1281 /* IRRoundingMode(I32) x I8 x D128 -> D128 */
1282 Iop_SignificanceRoundD128,
1284 /* EXTRACT AND INSERT INSTRUCTIONS
1285 * D64 -> I64
1286 * The exponent of the D32 or D64 operand is extracted. The
1287 * extracted exponent is converted to a 64-bit signed binary integer.
1288 */
1289 Iop_ExtractExpD64,
1291 /* D128 -> I64 */
1292 Iop_ExtractExpD128,
1294 /* D64 -> I64
1295 * The number of significand digits of the D64 operand is extracted.
1296 * The number is stored as a 64-bit signed binary integer.
1297 */
1298 Iop_ExtractSigD64,
1300 /* D128 -> I64 */
1301 Iop_ExtractSigD128,
1303 /* I64 x D64 -> D64
1304 * The exponent is specified by the first I64 operand the signed
1305 * significand is given by the second I64 value. The result is a D64
1306 * value consisting of the specified significand and exponent whose
1307 * sign is that of the specified significand.
1308 */
1309 Iop_InsertExpD64,
1311 /* I64 x D128 -> D128 */
1312 Iop_InsertExpD128,
1314 /* Support for 128-bit DFP type */
1317 /* I64 -> I64
1318 * Convert 50-bit densely packed BCD string to 60 bit BCD string
1319 */
1320 Iop_DPBtoBCD,
1322 /* I64 -> I64
1323 * Convert 60 bit BCD string to 50-bit densely packed BCD string
1324 */
1325 Iop_BCDtoDPB,
1327 /* BCD arithmetic instructions, (V128, V128) -> V128
1328 * The BCD format is the same as that used in the BCD<->DPB conversion
1329 * routines, except using 124 digits (vs 60) plus the trailing 4-bit
1330 * signed code. */
1333 /* Conversion signed 128-bit integer to signed BCD 128-bit */
1334 Iop_I128StoBCD128,
1336 /* Conversion signed BCD 128-bit to 128-bit integer */
1337 Iop_BCD128toI128S,
1339 /* Conversion I64 -> D64 */
1340 Iop_ReinterpI64asD64,
1342 /* Conversion D64 -> I64 */
1343 Iop_ReinterpD64asI64,
1345 /* ------------------ 128-bit SIMD FP. ------------------ */
1347 /* --- 32x4 vector FP --- */
1349 /* ternary :: IRRoundingMode(I32) x V128 x V128 -> V128 */
1352 /* binary */
1355 /* Note: For the following compares, the ppc and arm front-ends assume a
1356 nan in a lane of either argument returns zero for that lane. */
1360 /* Pairwise Max and Min. See integer pairwise operations for details. */
1363 /* unary */
1364 Iop_Abs32Fx4,
1365 Iop_Neg32Fx4,
1367 /* binary :: IRRoundingMode(I32) x V128 -> V128 */
1368 Iop_Sqrt32Fx4,
1370 /* Vector Reciprocal Estimate finds an approximate reciprocal of each
1371 element in the operand vector, and places the results in the
1372 destination vector. */
1373 Iop_RecipEst32Fx4,
1375 /* Vector Reciprocal Step computes (2.0 - arg1 * arg2).
1376 Note, that if one of the arguments is zero and another one is infinity
1377 of arbitrary sign the result of the operation is 2.0. */
1378 Iop_RecipStep32Fx4,
1380 /* Vector Reciprocal Square Root Estimate finds an approximate reciprocal
1381 square root of each element in the operand vector. */
1382 Iop_RSqrtEst32Fx4,
1384 /* Scaling of vector with a power of 2 (wd[i] <- ws[i] * 2^wt[i]) */
1385 Iop_Scale2_32Fx4,
1387 /* Vector floating-point base 2 logarithm */
1388 Iop_Log2_32Fx4,
1390 /* Vector floating-point exponential 2^x */
1391 Iop_Exp2_32Fx4,
1393 /* Vector Reciprocal Square Root Step computes (3.0 - arg1 * arg2) / 2.0.
1394 Note, that of one of the arguments is zero and another one is infiinty
1395 of arbitrary sign the result of the operation is 1.5. */
1396 Iop_RSqrtStep32Fx4,
1398 /* --- Int to/from FP conversion --- */
1399 /* Unlike the standard fp conversions, these irops take no
1400 rounding mode argument. Instead the irop trailers _R{M,P,N,Z}
1401 indicate the mode: {-inf, +inf, nearest, zero} respectively. */
1403 // These carry no rounding mode and are therefore deprecated
1413 /* Fixed32 format is floating-point number with fixed number of fraction
1414 bits. The number of fraction bits is passed as a second argument of
1415 type I8. */
1419 /* --- Single to/from half conversion --- */
1420 /* FIXME: what kind of rounding in F32x4 -> F16x4 case? */
1421 // FIXME these carry no rounding mode
1426 /* -- Double to/from half conversion -- */
1428 Iop_F16toF64x2,
1430 /* Values from two registers converted in smaller type and put in one
1431 IRRoundingMode(I32) x (F32x4 | F32x4) -> Q16x8 */
1432 Iop_F32x4_2toQ16x8,
1435 /* --- 32x4 lowest-lane-only scalar FP --- */
1437 /* In binary cases, upper 3/4 is copied from first operand. In
1438 unary cases, upper 3/4 is copied from the operand. */
1440 /* binary */
1445 /* unary */
1448 /* --- 64x2 vector FP --- */
1450 /* ternary :: IRRoundingMode(I32) x V128 x V128 -> V128 */
1453 /* binary */
1457 /* unary */
1458 Iop_Abs64Fx2,
1459 Iop_Neg64Fx2,
1461 /* binary :: IRRoundingMode(I32) x V128 -> V128 */
1462 Iop_Sqrt64Fx2,
1464 /* Scaling of vector with a power of 2 (wd[i] <- ws[i] * 2^wt[i]) */
1465 Iop_Scale2_64Fx2,
1467 /* Vector floating-point base 2 logarithm */
1468 Iop_Log2_64Fx2,
1470 /* see 32Fx4 variants for description */
1477 /* Values from two registers converted in smaller type and put in one
1478 IRRoundingMode(I32) x (F64x2 | F64x2) -> Q32x4 */
1479 Iop_F64x2_2toQ32x4,
1481 /* --- 64x2 lowest-lane-only scalar FP --- */
1483 /* In binary cases, upper half is copied from first operand. In
1484 unary cases, upper half is copied from the operand. */
1486 /* binary */
1491 /* unary */
1492 Iop_Sqrt64F0x2,
1494 /* --- pack / unpack --- */
1496 /* 64 <-> 128 bit vector */
1501 Iop_64UtoV128,
1502 Iop_SetV128lo64,
1504 /* Copies lower 64/32/16/8 bits, zeroes out the rest. */
1510 /* 32 <-> 128 bit vector */
1511 Iop_32UtoV128,
1515 /* ------------------ 128-bit SIMD Integer. ------------------ */
1517 /* BITWISE OPS */
1518 Iop_NotV128,
1521 /* VECTOR SHIFT (shift amt :: Ity_I8) */
1524 /* MISC (vector integer cmp != 0) */
1526 Iop_CmpNEZ128x1,
1528 /* ADDITION (normal / U->U sat / S->S sat) */
1533 /* ADDITION, ARM64 specific saturating variants. */
1534 /* Unsigned widen left arg, signed widen right arg, add, saturate S->S.
1535 This corresponds to SUQADD. */
1538 /* Signed widen left arg, unsigned widen right arg, add, saturate U->U.
1539 This corresponds to USQADD. */
1543 /* SUBTRACTION (normal / unsigned sat / signed sat) */
1548 /* MULTIPLICATION (normal / high half of signed/unsigned) */
1552 /* (widening signed/unsigned of even lanes, with lowest lane=zero) */
1556 /* Widening multiplies, all of the form (I64, I64) -> V128 */
1561 /* Signed doubling saturating widening multiplies, (I64, I64) -> V128 */
1564 /* Vector Saturating Doubling Multiply Returning High Half and
1565 Vector Saturating Rounding Doubling Multiply Returning High Half.
1566 These IROps multiply corresponding elements in two vectors, double
1567 the results, and place the most significant half of the final results
1568 in the destination vector. The results are truncated or rounded. If
1569 any of the results overflow, they are saturated. To be more precise,
1570 for each lane, the computed result is:
1571 QDMulHi:
1572 hi-half( sign-extend(laneL) *q sign-extend(laneR) *q 2 )
1573 QRDMulHi:
1574 hi-half( sign-extend(laneL) *q sign-extend(laneR) *q 2
1575 +q (1 << (lane-width-in-bits - 1)) )
1576 */
1580 /* Polynomial multiplication treats its arguments as
1581 coefficients of polynomials over {0, 1}. */
1585 /* Vector Polynomial multiplication add. (V128, V128) -> V128
1587 *** Below is the algorithm for the instructions. These Iops could
1588 be emulated to get this functionality, but the emulation would
1589 be long and messy.
1591 Example for polynomial multiply add for vector of bytes
1592 do i = 0 to 15
1593 prod[i].bit[0:14] <- 0
1594 srcA <- VR[argL].byte[i]
1595 srcB <- VR[argR].byte[i]
1596 do j = 0 to 7
1597 do k = 0 to j
1598 gbit <- srcA.bit[k] & srcB.bit[j-k]
1599 prod[i].bit[j] <- prod[i].bit[j] ^ gbit
1600 end
1601 end
1603 do j = 8 to 14
1604 do k = j-7 to 7
1605 gbit <- (srcA.bit[k] & srcB.bit[j-k])
1606 prod[i].bit[j] <- prod[i].bit[j] ^ gbit
1607 end
1608 end
1609 end
1611 do i = 0 to 7
1612 VR[dst].hword[i] <- 0b0 || (prod[2×i] ^ prod[2×i+1])
1613 end
1614 */
1618 /* PAIRWISE operations */
1619 /* Iop_PwFoo16x4( [a,b,c,d], [e,f,g,h] ) =
1620 [Foo16(a,b), Foo16(c,d), Foo16(e,f), Foo16(g,h)] */
1622 Iop_PwAdd32Fx2,
1624 /* Longening variant is unary. The resulting vector contains two times
1625 less elements than operand, but they are two times wider.
1626 Example:
1627 Iop_PwAddL16Ux4( [a,b,c,d] ) = [a+b,c+d]
1628 where a+b and c+d are unsigned 32-bit values. */
1632 /* This is amd64 PMADDUBSW, (V128, V128) -> V128. For each adjacent pair
1633 of bytes [a,b] in the first arg and [c,d] in the second, computes:
1634 signed/signed sat to 16 bits ( zxTo16(a) * sxTo16(b)
1635 + zxTo16(c) * sxTo16(d) )
1636 This exists because it's frequently used and there's no reasonably
1637 concise way to express it using other IROps.
1638 */
1639 Iop_PwExtUSMulQAdd8x16,
1641 /* Other unary pairwise ops */
1643 /* Vector bit matrix transpose. (V128) -> V128 */
1644 /* For each doubleword element of the source vector, an 8-bit x 8-bit
1645 * matrix transpose is performed. */
1646 Iop_PwBitMtxXpose64x2,
1648 /* ABSOLUTE VALUE */
1651 /* AVERAGING: note: (arg1 + arg2 + 1) >>u 1 */
1655 /* MIN/MAX */
1661 /* COMPARISON */
1666 /* COUNT ones / leading zeroes / leading sign bits (not including topmost
1667 bit) */
1668 Iop_Cnt8x16,
1672 /* VECTOR x SCALAR SHIFT (shift amt :: Ity_I8) */
1677 /* VECTOR x VECTOR SHIFT / ROTATE */
1678 /* FIXME: I'm pretty sure the ARM32 front/back ends interpret these
1679 differently from all other targets. The intention is that
1680 the shift amount (2nd arg) is interpreted as unsigned and
1681 only the lowest log2(lane-bits) bits are relevant. But the
1682 ARM32 versions treat the shift amount as an 8 bit signed
1683 number. The ARM32 uses should be replaced by the relevant
1684 vector x vector bidirectional shifts instead. */
1691 /* VECTOR x VECTOR SATURATING SHIFT */
1694 /* VECTOR x INTEGER SATURATING SHIFT */
1702 /* VECTOR x VECTOR BIDIRECTIONAL SATURATING (& MAYBE ROUNDING) SHIFT */
1703 /* All of type (V128, V128) -> V256. */
1704 /* The least significant 8 bits of each lane of the second
1705 operand are used as the shift amount, and interpreted signedly.
1706 Positive values mean a shift left, negative a shift right. The
1707 result is signedly or unsignedly saturated. There are also
1708 rounding variants, which add 2^(shift_amount-1) to the value before
1709 shifting, but only in the shift-right case. Vacated positions
1710 are filled with zeroes. IOW, it's either SHR or SHL, but not SAR.
1712 These operations return 129 bits: one bit ("Q") indicating whether
1713 saturation occurred, and the shift result. The result type is V256,
1714 of which the lower V128 is the shift result, and Q occupies the
1715 least significant bit of the upper V128. All other bits of the
1716 upper V128 are zero. */
1717 // Unsigned saturation, no rounding
1720 // Signed saturation, no rounding
1724 // Unsigned saturation, rounding
1727 // Signed saturation, rounding
1731 /* VECTOR x VECTOR BIDIRECTIONAL (& MAYBE ROUNDING) SHIFT */
1732 /* All of type (V128, V128) -> V128 */
1733 /* The least significant 8 bits of each lane of the second
1734 operand are used as the shift amount, and interpreted signedly.
1735 Positive values mean a shift left, negative a shift right.
1736 There are also rounding variants, which add 2^(shift_amount-1)
1737 to the value before shifting, but only in the shift-right case.
1739 For left shifts, the vacated places are filled with zeroes.
1740 For right shifts, the vacated places are filled with zeroes
1741 for the U variants and sign bits for the S variants. */
1742 // Signed and unsigned, non-rounding
1746 // Signed and unsigned, rounding
1750 /* The least significant 8 bits of each lane of the second
1751 operand are used as the shift amount, and interpreted signedly.
1752 Positive values mean a shift left, negative a shift right. The
1753 result is signedly or unsignedly saturated. There are also
1754 rounding variants, which add 2^(shift_amount-1) to the value before
1755 shifting, but only in the shift-right case. Vacated positions
1756 are filled with zeroes. IOW, it's either SHR or SHL, but not SAR.
1757 */
1759 /* VECTOR x SCALAR SATURATING (& MAYBE ROUNDING) NARROWING SHIFT RIGHT */
1760 /* All of type (V128, I8) -> V128 */
1761 /* The first argument is shifted right, then narrowed to half the width
1762 by saturating it. The second argument is a scalar shift amount that
1763 applies to all lanes, and must be a value in the range 1 to lane_width.
1764 The shift may be done signedly (Sar variants) or unsignedly (Shr
1765 variants). The saturation is done according to the two signedness
1766 indicators at the end of the name. For example 64Sto32U means a
1767 signed 64 bit value is saturated into an unsigned 32 bit value.
1768 Additionally, the QRS variants do rounding, that is, they add the
1769 value (1 << (shift_amount-1)) to each source lane before shifting.
1771 These operations return 65 bits: one bit ("Q") indicating whether
1772 saturation occurred, and the shift result. The result type is V128,
1773 of which the lower half is the shift result, and Q occupies the
1774 least significant bit of the upper half. All other bits of the
1775 upper half are zero. */
1776 // No rounding, sat U->U
1777 Iop_QandQShrNnarrow16Uto8Ux8,
1779 // No rounding, sat S->S
1780 Iop_QandQSarNnarrow16Sto8Sx8,
1782 // No rounding, sat S->U
1783 Iop_QandQSarNnarrow16Sto8Ux8,
1786 // Rounding, sat U->U
1787 Iop_QandQRShrNnarrow16Uto8Ux8,
1789 // Rounding, sat S->S
1790 Iop_QandQRSarNnarrow16Sto8Sx8,
1792 // Rounding, sat S->U
1793 Iop_QandQRSarNnarrow16Sto8Ux8,
1796 /* NARROWING (binary)
1797 -- narrow 2xV128 into 1xV128, hi half from left arg */
1798 /* See comments above w.r.t. U vs S issues in saturated narrowing. */
1804 Iop_NarrowBin64to32x4,
1806 /* NARROWING (unary) -- narrow V128 into I64 */
1808 /* Saturating narrowing from signed source to signed/unsigned
1809 destination */
1812 /* Saturating narrowing from unsigned source to unsigned destination */
1815 /* WIDENING -- sign or zero extend each element of the argument
1816 vector to the twice original size. The resulting vector consists of
1817 the same number of elements but each element and the vector itself
1818 are twice as wide.
1819 All operations are I64->V128.
1820 Example
1821 Iop_Widen32Sto64x2( [a, b] ) = [c, d]
1822 where c = Iop_32Sto64(a) and d = Iop_32Sto64(b) */
1826 /* INTERLEAVING */
1827 /* Interleave lanes from low or high halves of
1828 operands. Most-significant result lane is from the left
1829 arg. */
1834 /* Interleave odd/even lanes of operands. Most-significant result lane
1835 is from the left arg. */
1840 /* Pack even/odd lanes. */
1845 /* CONCATENATION -- build a new value by concatenating either
1846 the even or odd lanes of both operands. Note that
1847 Cat{Odd,Even}Lanes64x2 are identical to Interleave{HI,LO}64x2
1848 and so are omitted. */
1852 /* GET elements of VECTOR
1853 GET is binop (V128, I8) -> I<elem_size>
1854 SET is triop (V128, I8, I<elem_size>) -> V128 */
1855 /* Note: the arm back-end handles only constant second argument. */
1859 /* DUPLICATING -- copy value to all lanes */
1862 /* SLICE -- produces the lowest 128 bits of (arg1:arg2) >> (8 * arg3).
1863 arg3 is a shift amount in bytes and may be between 0 and 16
1864 inclusive. When 0, the result is arg2; when 16, the result is arg1.
1865 Not all back ends handle all values. The arm64 back
1866 end handles only immediate arg3 values. */
1869 /* REVERSE the order of chunks in vector lanes. Chunks must be
1870 smaller than the vector lanes (obviously) and so may be 8-,
1871 16- and 32-bit in size. See definitions of 64-bit SIMD
1872 versions above for examples. */
1873 Iop_Reverse8sIn16_x8,
1878 /* PERMUTING -- copy src bytes to dst,
1879 as indexed by control vector bytes:
1880 for i in 0 .. 15 . result[i] = argL[ argR[i] ]
1881 argR[i] values may only be in the range 0 .. 15, else behaviour
1882 is undefined. That is, argR[i][7:4] must be zero. */
1883 Iop_Perm8x16,
1886 /* PERMUTING with optional zeroing:
1887 for i in 0 .. 15 . result[i] = if argR[i] bit 7 is set
1888 then zero else argL[ argR[i] ]
1889 argR[i][6:4] must be zero, else behaviour is undefined.
1890 */
1891 Iop_PermOrZero8x16,
1893 /* same, but Triop (argL consists of two 128-bit parts) */
1894 /* correct range for argR values is 0..31 */
1895 /* (V128, V128, V128) -> V128 */
1896 /* (ArgL_first, ArgL_second, ArgR) -> result */
1897 Iop_Perm8x16x2,
1899 /* MISC CONVERSION -- get high bits of each byte lane, a la
1900 x86/amd64 pmovmskb */
1903 /* Vector Reciprocal Estimate and Vector Reciprocal Square Root Estimate
1904 See floating-point equivalents for details. */
1907 /* 128-bit multipy by 10 instruction, result is lower 128-bits */
1908 Iop_MulI128by10,
1910 /* 128-bit multipy by 10 instruction, result is carry out from the MSB */
1911 Iop_MulI128by10Carry,
1913 /* 128-bit multipy by 10 instruction, result is lower 128-bits of the
1914 * source times 10 plus the carry in
1915 */
1916 Iop_MulI128by10E,
1918 /* 128-bit multipy by 10 instruction, result is carry out from the MSB
1919 * of the source times 10 plus the carry in
1920 */
1921 Iop_MulI128by10ECarry,
1923 /* ------------------ 256-bit SIMD Integer. ------------------ */
1925 /* Pack/unpack */
1927 Iop_V256to64_1,
1928 Iop_V256to64_2,
1932 // first arg is most significant lane
1938 Iop_AndV256,
1939 Iop_OrV256,
1940 Iop_XorV256,
1941 Iop_NotV256,
1943 /* MISC (vector integer cmp != 0) */
1971 Iop_Perm32x8,
1973 /* (V128, V128) -> V128 */
1977 /* Hash instructions, Federal Information Processing Standards
1978 * Publication 180-3 Secure Hash Standard. */
1979 /* (V128, I8) -> V128; The I8 input arg is (ST | SIX), where ST and
1980 * SIX are fields from the insn. See ISA 2.07 description of
1981 * vshasigmad and vshasigmaw insns.*/
1984 /* ------------------ 256-bit SIMD FP. ------------------ */
1986 /* ternary :: IRRoundingMode(I32) x V256 x V256 -> V256 */
1996 Iop_Sqrt32Fx8,
1997 Iop_Sqrt64Fx4,
1998 Iop_RSqrtEst32Fx8,
1999 Iop_RecipEst32Fx8,
2004 Iop_LAST /* must be the last enumerator */
2005 }
2006 IROp;
2008 /* Pretty-print an op. */
2011 /* For a given operand return the types of its arguments and its result. */
2016 /* Might the given primop trap (eg, attempt integer division by zero)? If in
2017 doubt returns True. However, the vast majority of primops will never
2018 trap. */
2021 /* Encoding of IEEE754-specified rounding modes.
2022 Note, various front and back ends rely on the actual numerical
2023 values of these, so do not change them. */
2024 typedef
2032 // precision
2035 }
2036 IRRoundingMode;
2038 /* Binary floating point comparison result values.
2039 This is also derived from what IA32 does. */
2040 typedef
2046 }
2047 IRCmpFResult;
2053 /* Decimal floating point result values. */
2058 /* ------------------ Expressions ------------------ */
2064 /* The different kinds of expressions. Their meaning is explained below
2065 in the comments for IRExpr. */
2066 typedef
2069 Iex_Get,
2070 Iex_GetI,
2071 Iex_RdTmp,
2072 Iex_Qop,
2073 Iex_Triop,
2074 Iex_Binop,
2075 Iex_Unop,
2076 Iex_Load,
2077 Iex_Const,
2078 Iex_ITE,
2079 Iex_CCall,
2080 Iex_VECRET,
2081 Iex_GSPTR
2082 }
2083 IRExprTag;
2085 /* An expression. Stored as a tagged union. 'tag' indicates what kind
2086 of expression this is. 'Iex' is the union that holds the fields. If
2087 an IRExpr 'e' has e.tag equal to Iex_Load, then it's a load
2088 expression, and the fields can be accessed with
2089 'e.Iex.Load.<fieldname>'.
2091 For each kind of expression, we show what it looks like when
2092 pretty-printed with ppIRExpr().
2093 */
2094 typedef
2095 struct _IRExpr
2096 IRExpr;
2099 IRExprTag tag;
2101 /* Used only in pattern matching within Vex. Should not be seen
2102 outside of Vex. */
2104 Int binder;
2107 /* Read a guest register, at a fixed offset in the guest state.
2108 ppIRExpr output: GET:<ty>(<offset>), eg. GET:I32(0)
2109 */
2115 /* Read a guest register at a non-fixed offset in the guest
2116 state. This allows circular indexing into parts of the guest
2117 state, which is essential for modelling situations where the
2118 identity of guest registers is not known until run time. One
2119 example is the x87 FP register stack.
2121 The part of the guest state to be treated as a circular array
2122 is described in the IRRegArray 'descr' field. It holds the
2123 offset of the first element in the array, the type of each
2124 element, and the number of elements.
2126 The array index is indicated rather indirectly, in a way
2127 which makes optimisation easy: as the sum of variable part
2128 (the 'ix' field) and a constant offset (the 'bias' field).
2130 Since the indexing is circular, the actual array index to use
2131 is computed as (ix + bias) % num-of-elems-in-the-array.
2133 Here's an example. The description
2135 (96:8xF64)[t39,-7]
2137 describes an array of 8 F64-typed values, the
2138 guest-state-offset of the first being 96. This array is
2139 being indexed at (t39 - 7) % 8.
2141 It is important to get the array size/type exactly correct
2142 since IR optimisation looks closely at such info in order to
2143 establish aliasing/non-aliasing between seperate GetI and
2144 PutI events, which is used to establish when they can be
2145 reordered, etc. Putting incorrect info in will lead to
2146 obscure IR optimisation bugs.
2148 ppIRExpr output: GETI<descr>[<ix>,<bias]
2149 eg. GETI(128:8xI8)[t1,0]
2150 */
2157 /* The value held by a temporary.
2158 ppIRExpr output: t<tmp>, eg. t1
2159 */
2164 /* A quaternary operation.
2165 ppIRExpr output: <op>(<arg1>, <arg2>, <arg3>, <arg4>),
2166 eg. MAddF64r32(t1, t2, t3, t4)
2167 */
2172 /* A ternary operation.
2173 ppIRExpr output: <op>(<arg1>, <arg2>, <arg3>),
2174 eg. MulF64(1, 2.0, 3.0)
2175 */
2180 /* A binary operation.
2181 ppIRExpr output: <op>(<arg1>, <arg2>), eg. Add32(t1,t2)
2182 */
2189 /* A unary operation.
2190 ppIRExpr output: <op>(<arg>), eg. Neg8(t1)
2191 */
2197 /* A load from memory -- a normal load, not a load-linked.
2198 Load-Linkeds (and Store-Conditionals) are instead represented
2199 by IRStmt.LLSC since Load-Linkeds have side effects and so
2200 are not semantically valid IRExpr's.
2201 ppIRExpr output: LD<end>:<ty>(<addr>), eg. LDle:I32(t1)
2202 */
2209 /* A constant-valued expression.
2210 ppIRExpr output: <con>, eg. 0x4:I32
2211 */
2216 /* A call to a pure (no side-effects) helper C function.
2218 With the 'cee' field, 'name' is the function's name. It is
2219 only used for pretty-printing purposes. The address to call
2220 (host address, of course) is stored in the 'addr' field
2221 inside 'cee'.
2223 The 'args' field is a NULL-terminated array of arguments.
2224 The stated return IRType, and the implied argument types,
2225 must match that of the function being called well enough so
2226 that the back end can actually generate correct code for the
2227 call.
2229 The called function **must** satisfy the following:
2231 * no side effects -- must be a pure function, the result of
2232 which depends only on the passed parameters.
2234 * it may not look at, nor modify, any of the guest state
2235 since that would hide guest state transitions from
2236 instrumenters
2238 * it may not access guest memory, since that would hide
2239 guest memory transactions from the instrumenters
2241 * it must not assume that arguments are being evaluated in a
2242 particular order. The oder of evaluation is unspecified.
2244 This is restrictive, but makes the semantics clean, and does
2245 not interfere with IR optimisation.
2247 If you want to call a helper which can mess with guest state
2248 and/or memory, instead use Ist_Dirty. This is a lot more
2249 flexible, but you have to give a bunch of details about what
2250 the helper does (and you better be telling the truth,
2251 otherwise any derived instrumentation will be wrong). Also
2252 Ist_Dirty inhibits various IR optimisations and so can cause
2253 quite poor code to be generated. Try to avoid it.
2255 In principle it would be allowable to have the arg vector
2256 contain an IRExpr_VECRET(), although not IRExpr_GSPTR(). However,
2257 at the moment there is no requirement for clean helper calls to
2258 be able to return V128 or V256 values. Hence this is not allowed.
2260 ppIRExpr output: <cee>(<args>):<retty>
2261 eg. foo{0x80489304}(t1, t2):I32
2262 */
2269 /* A ternary if-then-else operator. It returns iftrue if cond is
2270 nonzero, iffalse otherwise. Note that it is STRICT, ie. both
2271 iftrue and iffalse are evaluated in all cases.
2273 ppIRExpr output: ITE(<cond>,<iftrue>,<iffalse>),
2274 eg. ITE(t6,t7,t8)
2275 */
2282 };
2284 /* Expression auxiliaries: a ternary expression. */
2290 };
2292 /* Expression auxiliaries: a quarternary expression. */
2299 };
2302 /* Two special kinds of IRExpr, which can ONLY be used in
2303 argument lists for dirty helper calls (IRDirty.args) and in NO
2304 OTHER PLACES. And then only in very limited ways. */
2306 /* Denotes an argument which (in the helper) takes a pointer to a
2307 (naturally aligned) V128 or V256, into which the helper is expected
2308 to write its result. Use of IRExpr_VECRET() is strictly
2309 controlled. If the helper returns a V128 or V256 value then
2310 IRExpr_VECRET() must appear exactly once in the arg list, although
2311 it can appear anywhere, and the helper must have a C 'void' return
2312 type. If the helper returns any other type, IRExpr_VECRET() may
2313 not appear in the argument list. */
2315 /* Denotes an void* argument which is passed to the helper, which at
2316 run time will point to the thread's guest state area. This can
2317 only appear at most once in an argument list, and it may not appear
2318 at all in argument lists for clean helper calls. */
2322 }
2325 /* Expression constructors. */
2343 /* Deep-copy an IRExpr. */
2346 /* Pretty-print an IRExpr. */
2349 /* NULL-terminated IRExpr vector constructors, suitable for
2350 use as arg lists in clean/dirty helper calls. */
2357 IRExpr* );
2370 /* IRExpr copiers:
2371 - shallowCopy: shallow-copy (ie. create a new vector that shares the
2372 elements with the original).
2373 - deepCopy: deep-copy (ie. create a completely new vector). */
2377 /* Make a constant expression from the given host word taking into
2378 account (of course) the host word size. */
2381 /* Convenience function for constructing clean helper calls. */
2382 extern
2388 /* Convenience functions for atoms (IRExprs which are either Iex_Tmp or
2389 * Iex_Const). */
2392 }
2394 /* Are these two IR atoms identical? Causes an assertion
2395 failure if they are passed non-atoms. */
2399 /* ------------------ Jump kinds ------------------ */
2401 /* This describes hints which can be passed to the dispatcher at guest
2402 control-flow transfer points.
2404 Re Ijk_InvalICache and Ijk_FlushDCache: the guest state _must_ have
2405 two pseudo-registers, guest_CMSTART and guest_CMLEN, which specify
2406 the start and length of the region to be invalidated. CM stands
2407 for "Cache Management". These are both the size of a guest word.
2408 It is the responsibility of the relevant toIR.c to ensure that
2409 these are filled in with suitable values before issuing a jump of
2410 kind Ijk_InvalICache or Ijk_FlushDCache.
2412 Ijk_InvalICache requests invalidation of translations taken from
2413 the requested range. Ijk_FlushDCache requests flushing of the D
2414 cache for the specified range.
2416 Re Ijk_EmWarn and Ijk_EmFail: the guest state must have a
2417 pseudo-register guest_EMNOTE, which is 32-bits regardless of the
2418 host or guest word size. That register should be made to hold a
2419 VexEmNote value to indicate the reason for the exit.
2421 In the case of Ijk_EmFail, the exit is fatal (Vex-generated code
2422 cannot continue) and so the jump destination can be anything.
2424 Re Ijk_Sys_ (syscall jumps): the guest state must have a
2425 pseudo-register guest_IP_AT_SYSCALL, which is the size of a guest
2426 word. Front ends should set this to be the IP at the most recently
2427 executed kernel-entering (system call) instruction. This makes it
2428 very much easier (viz, actually possible at all) to back up the
2429 guest to restart a syscall that has been interrupted by a signal.
2430 */
2431 typedef
2453 /* Unfortunately, various guest-dependent syscall kinds. They
2454 all mean: do a syscall before continuing. */
2462 Ijk_Sys_sysenter /* x86 'sysenter'. guest_EIP becomes
2463 invalid at the point this happens. */
2464 }
2465 IRJumpKind;
2470 /* ------------------ Dirty helper calls ------------------ */
2472 /* A dirty call is a flexible mechanism for calling (possibly
2473 conditionally) a helper function or procedure. The helper function
2474 may read, write or modify client memory, and may read, write or
2475 modify client state. It can take arguments and optionally return a
2476 value. It may return different results and/or do different things
2477 when called repeatedly with the same arguments, by means of storing
2478 private state.
2480 If a value is returned, it is assigned to the nominated return
2481 temporary.
2483 Dirty calls are statements rather than expressions for obvious
2484 reasons. If a dirty call is marked as writing guest state, any
2485 pre-existing values derived from the written parts of the guest
2486 state are invalid. Similarly, if the dirty call is stated as
2487 writing memory, any pre-existing loaded values are invalidated by
2488 it.
2490 In order that instrumentation is possible, the call must state, and
2491 state correctly:
2493 * Whether it reads, writes or modifies memory, and if so where.
2495 * Whether it reads, writes or modifies guest state, and if so which
2496 pieces. Several pieces may be stated, and their extents must be
2497 known at translation-time. Each piece is allowed to repeat some
2498 number of times at a fixed interval, if required.
2500 Normally, code is generated to pass just the args to the helper.
2501 However, if IRExpr_GSPTR() is present in the argument list (at most
2502 one instance is allowed), then the guest state pointer is passed for
2503 that arg, so that the callee can access the guest state. It is
2504 invalid for .nFxState to be zero but IRExpr_GSPTR() to be present,
2505 since .nFxState==0 is a claim that the call does not access guest
2506 state.
2508 IMPORTANT NOTE re GUARDS: Dirty calls are strict, very strict. The
2509 arguments and 'mFx' are evaluated REGARDLESS of the guard value.
2510 The order of argument evaluation is unspecified. The guard
2511 expression is evaluated AFTER the arguments and 'mFx' have been
2512 evaluated. 'mFx' is expected (by Memcheck) to be a defined value
2513 even if the guard evaluates to false.
2514 */
2518 /* Effects on resources (eg. registers, memory locations) */
2519 typedef
2525 }
2526 IREffect;
2528 /* Pretty-print an IREffect */
2531 typedef
2533 /* What to call, and details of args/results. .guard must be
2534 non-NULL. If .tmp is not IRTemp_INVALID, then the call
2535 returns a result which is placed in .tmp. If at runtime the
2536 guard evaluates to false, .tmp has an 0x555..555 bit pattern
2537 written to it. Hence conditional calls that assign .tmp are
2538 allowed. */
2541 /* The args vector may contain IRExpr_GSPTR() and/or
2542 IRExpr_VECRET(), in both cases, at most once. */
2546 /* Mem effects; we allow only one R/W/M region to be stated */
2551 /* Guest state effects; up to N allowed */
2555 UShort offset;
2556 UShort size;
2557 UChar nRepeats;
2558 UChar repeatLen;
2560 /* The access can be repeated, as specified by nRepeats and
2561 repeatLen. To describe only a single access, nRepeats and
2562 repeatLen should be zero. Otherwise, repeatLen must be a
2563 multiple of size and greater than size. */
2564 /* Overall, the parts of the guest state denoted by (offset,
2565 size, nRepeats, repeatLen) is
2566 [offset, +size)
2567 and, if nRepeats > 0,
2568 for (i = 1; i <= nRepeats; i++)
2569 [offset + i * repeatLen, +size)
2570 A convenient way to enumerate all segments is therefore
2571 for (i = 0; i < 1 + nRepeats; i++)
2572 [offset + i * repeatLen, +size)
2573 */
2574 }
2575 IRDirty;
2577 /* Pretty-print a dirty call */
2580 /* Allocate an uninitialised dirty call */
2583 /* Deep-copy a dirty call */
2586 /* A handy function which takes some of the tedium out of constructing
2587 dirty helper calls. The called function impliedly does not return
2588 any value and has a constant-True guard. The call is marked as
2589 accessing neither guest state nor memory (hence the "unsafe"
2590 designation) -- you can change this marking later if need be. A
2591 suitable IRCallee is constructed from the supplied bits. */
2592 extern
2596 /* Similarly, make a zero-annotation dirty call which returns a value,
2597 and assign that to the given temp. */
2598 extern
2604 /* --------------- Memory Bus Events --------------- */
2606 typedef
2609 /* Needed only on ARM. It cancels a reservation made by a
2610 preceding Linked-Load, and needs to be handed through to the
2611 back end, just as LL and SC themselves are. */
2612 Imbe_CancelReservation
2613 }
2614 IRMBusEvent;
2619 /* --------------- Compare and Swap --------------- */
2621 /* This denotes an atomic compare and swap operation, either
2622 a single-element one or a double-element one.
2624 In the single-element case:
2626 .addr is the memory address.
2627 .end is the endianness with which memory is accessed
2629 If .addr contains the same value as .expdLo, then .dataLo is
2630 written there, else there is no write. In both cases, the
2631 original value at .addr is copied into .oldLo.
2633 Types: .expdLo, .dataLo and .oldLo must all have the same type.
2634 It may be any integral type, viz: I8, I16, I32 or, for 64-bit
2635 guests, I64.
2637 .oldHi must be IRTemp_INVALID, and .expdHi and .dataHi must
2638 be NULL.
2640 In the double-element case:
2642 .addr is the memory address.
2643 .end is the endianness with which memory is accessed
2645 The operation is the same:
2647 If .addr contains the same value as .expdHi:.expdLo, then
2648 .dataHi:.dataLo is written there, else there is no write. In
2649 both cases the original value at .addr is copied into
2650 .oldHi:.oldLo.
2652 Types: .expdHi, .expdLo, .dataHi, .dataLo, .oldHi, .oldLo must
2653 all have the same type, which may be any integral type, viz: I8,
2654 I16, I32 or, for 64-bit guests, I64.
2656 The double-element case is complicated by the issue of
2657 endianness. In all cases, the two elements are understood to be
2658 located adjacently in memory, starting at the address .addr.
2660 If .end is Iend_LE, then the .xxxLo component is at the lower
2661 address and the .xxxHi component is at the higher address, and
2662 each component is itself stored little-endianly.
2664 If .end is Iend_BE, then the .xxxHi component is at the lower
2665 address and the .xxxLo component is at the higher address, and
2666 each component is itself stored big-endianly.
2668 This allows representing more cases than most architectures can
2669 handle. For example, x86 cannot do DCAS on 8- or 16-bit elements.
2671 How to know if the CAS succeeded?
2673 * if .oldLo == .expdLo (resp. .oldHi:.oldLo == .expdHi:.expdLo),
2674 then the CAS succeeded, .dataLo (resp. .dataHi:.dataLo) is now
2675 stored at .addr, and the original value there was .oldLo (resp
2676 .oldHi:.oldLo).
2678 * if .oldLo != .expdLo (resp. .oldHi:.oldLo != .expdHi:.expdLo),
2679 then the CAS failed, and the original value at .addr was .oldLo
2680 (resp. .oldHi:.oldLo).
2682 Hence it is easy to know whether or not the CAS succeeded.
2683 */
2684 typedef
2687 IRTemp oldLo;
2694 }
2695 IRCAS;
2707 /* ------------------ Circular Array Put ------------------ */
2709 typedef
2725 /* --------------- Guarded loads and stores --------------- */
2727 /* Conditional stores are straightforward. They are the same as
2728 normal stores, with an extra 'guard' field :: Ity_I1 that
2729 determines whether or not the store actually happens. If not,
2730 memory is unmodified.
2732 The semantics of this is that 'addr' and 'data' are fully evaluated
2733 even in the case where 'guard' evaluates to zero (false).
2734 */
2735 typedef
2741 }
2742 IRStoreG;
2744 /* Conditional loads are a little more complex. 'addr' is the
2745 address, 'guard' is the guarding condition. If the load takes
2746 place, the loaded value is placed in 'dst'. If it does not take
2747 place, 'alt' is copied to 'dst'. However, the loaded value is not
2748 placed directly in 'dst' -- it is first subjected to the conversion
2749 specified by 'cvt'.
2751 For example, imagine doing a conditional 8-bit load, in which the
2752 loaded value is zero extended to 32 bits. Hence:
2753 * 'dst' and 'alt' must have type I32
2754 * 'cvt' must be a unary op which converts I8 to I32. In this
2755 example, it would be ILGop_8Uto32.
2757 There is no explicit indication of the type at which the load is
2758 done, since that is inferrable from the arg type of 'cvt'. Note
2759 that the types of 'alt' and 'dst' and the result type of 'cvt' must
2760 all be the same.
2762 Semantically, 'addr' is evaluated even in the case where 'guard'
2763 evaluates to zero (false), and 'alt' is evaluated even when 'guard'
2764 evaluates to one (true). That is, 'addr' and 'alt' are always
2765 evaluated.
2766 */
2767 typedef
2776 ILGop_8Sto32 /* 8 bit load, S-widen to 32 */
2777 }
2778 IRLoadGOp;
2780 typedef
2788 }
2789 IRLoadG;
2806 /* ------------------ Statements ------------------ */
2808 /* The different kinds of statements. Their meaning is explained
2809 below in the comments for IRStmt.
2811 Those marked META do not represent code, but rather extra
2812 information about the code. These statements can be removed
2813 without affecting the functional behaviour of the code, however
2814 they are required by some IR consumers such as tools that
2815 instrument the code.
2816 */
2818 typedef
2823 Ist_Put,
2824 Ist_PutI,
2825 Ist_WrTmp,
2826 Ist_Store,
2827 Ist_LoadG,
2828 Ist_StoreG,
2829 Ist_CAS,
2830 Ist_LLSC,
2831 Ist_Dirty,
2832 Ist_MBE,
2833 Ist_Exit
2834 }
2835 IRStmtTag;
2837 /* A statement. Stored as a tagged union. 'tag' indicates what kind
2838 of expression this is. 'Ist' is the union that holds the fields.
2839 If an IRStmt 'st' has st.tag equal to Iex_Store, then it's a store
2840 statement, and the fields can be accessed with
2841 'st.Ist.Store.<fieldname>'.
2843 For each kind of statement, we show what it looks like when
2844 pretty-printed with ppIRStmt().
2845 */
2846 typedef
2848 IRStmtTag tag;
2850 /* A no-op (usually resulting from IR optimisation). Can be
2851 omitted without any effect.
2853 ppIRStmt output: IR-NoOp
2854 */
2858 /* META: instruction mark. Marks the start of the statements
2859 that represent a single machine instruction (the end of
2860 those statements is marked by the next IMark or the end of
2861 the IRSB). Contains the address and length of the
2862 instruction.
2864 It also contains a delta value. The delta must be
2865 subtracted from a guest program counter value before
2866 attempting to establish, by comparison with the address
2867 and length values, whether or not that program counter
2868 value refers to this instruction. For x86, amd64, ppc32,
2869 ppc64 and arm, the delta value is zero. For Thumb
2870 instructions, the delta value is one. This is because, on
2871 Thumb, guest PC values (guest_R15T) are encoded using the
2872 top 31 bits of the instruction address and a 1 in the lsb;
2873 hence they appear to be (numerically) 1 past the start of
2874 the instruction they refer to. IOW, guest_R15T on ARM
2875 holds a standard ARM interworking address.
2877 ppIRStmt output: ------ IMark(<addr>, <len>, <delta>) ------,
2878 eg. ------ IMark(0x4000792, 5, 0) ------,
2879 */
2884 - delta */
2887 /* META: An ABI hint, which says something about this
2888 platform's ABI.
2890 At the moment, the only AbiHint is one which indicates
2891 that a given chunk of address space, [base .. base+len-1],
2892 has become undefined. This is used on amd64-linux and
2893 some ppc variants to pass stack-redzoning hints to whoever
2894 wants to see them. It also indicates the address of the
2895 next (dynamic) instruction that will be executed. This is
2896 to help Memcheck to origin tracking.
2898 ppIRStmt output: ====== AbiHint(<base>, <len>, <nia>) ======
2899 eg. ====== AbiHint(t1, 16, t2) ======
2900 */
2907 /* Write a guest register, at a fixed offset in the guest state.
2908 ppIRStmt output: PUT(<offset>) = <data>, eg. PUT(60) = t1
2909 */
2915 /* Write a guest register, at a non-fixed offset in the guest
2916 state. See the comment for GetI expressions for more
2917 information.
2919 ppIRStmt output: PUTI<descr>[<ix>,<bias>] = <data>,
2920 eg. PUTI(64:8xF64)[t5,0] = t1
2921 */
2926 /* Assign a value to a temporary. Note that SSA rules require
2927 each tmp is only assigned to once. IR sanity checking will
2928 reject any block containing a temporary which is not assigned
2929 to exactly once.
2931 ppIRStmt output: t<tmp> = <data>, eg. t1 = 3
2932 */
2938 /* Write a value to memory. This is a normal store, not a
2939 Store-Conditional. To represent a Store-Conditional,
2940 instead use IRStmt.LLSC.
2941 ppIRStmt output: ST<end>(<addr>) = <data>, eg. STle(t1) = t2
2942 */
2949 /* Guarded store. Note that this is defined to evaluate all
2950 expression fields (addr, data) even if the guard evaluates
2951 to false.
2952 ppIRStmt output:
2953 if (<guard>) ST<end>(<addr>) = <data> */
2958 /* Guarded load. Note that this is defined to evaluate all
2959 expression fields (addr, alt) even if the guard evaluates
2960 to false.
2961 ppIRStmt output:
2962 t<tmp> = if (<guard>) <cvt>(LD<end>(<addr>)) else <alt> */
2967 /* Do an atomic compare-and-swap operation. Semantics are
2968 described above on a comment at the definition of IRCAS.
2970 ppIRStmt output:
2971 t<tmp> = CAS<end>(<addr> :: <expected> -> <new>)
2972 eg
2973 t1 = CASle(t2 :: t3->Add32(t3,1))
2974 which denotes a 32-bit atomic increment
2975 of a value at address t2
2977 A double-element CAS may also be denoted, in which case <tmp>,
2978 <expected> and <new> are all pairs of items, separated by
2979 commas.
2980 */
2985 /* Either Load-Linked or Store-Conditional, depending on
2986 STOREDATA.
2988 If STOREDATA is NULL then this is a Load-Linked, meaning
2989 that data is loaded from memory as normal, but a
2990 'reservation' for the address is also lodged in the
2991 hardware.
2993 result = Load-Linked(addr, end)
2995 The data transfer type is the type of RESULT (I32, I64,
2996 etc). ppIRStmt output:
2998 result = LD<end>-Linked(<addr>), eg. LDbe-Linked(t1)
3000 If STOREDATA is not NULL then this is a Store-Conditional,
3001 hence:
3003 result = Store-Conditional(addr, storedata, end)
3005 The data transfer type is the type of STOREDATA and RESULT
3006 has type Ity_I1. The store may fail or succeed depending
3007 on the state of a previously lodged reservation on this
3008 address. RESULT is written 1 if the store succeeds and 0
3009 if it fails. eg ppIRStmt output:
3011 result = ( ST<end>-Cond(<addr>) = <storedata> )
3012 eg t3 = ( STbe-Cond(t1, t2) )
3014 In all cases, the address must be naturally aligned for
3015 the transfer type -- any misaligned addresses should be
3016 caught by a dominating IR check and side exit. This
3017 alignment restriction exists because on at least some
3018 LL/SC platforms (ppc), stwcx. etc will trap w/ SIGBUS on
3019 misaligned addresses, and we have to actually generate
3020 stwcx. on the host, and we don't want it trapping on the
3021 host.
3023 Summary of rules for transfer type:
3024 STOREDATA == NULL (LL):
3025 transfer type = type of RESULT
3026 STOREDATA != NULL (SC):
3027 transfer type = type of STOREDATA, and RESULT :: Ity_I1
3028 */
3030 IREndness end;
3031 IRTemp result;
3036 /* Call (possibly conditionally) a C function that has side
3037 effects (ie. is "dirty"). See the comments above the
3038 IRDirty type declaration for more information.
3040 ppIRStmt output:
3041 t<tmp> = DIRTY <guard> <effects>
3042 ::: <callee>(<args>)
3043 eg.
3044 t1 = DIRTY t27 RdFX-gst(16,4) RdFX-gst(60,4)
3045 ::: foo{0x380035f4}(t2)
3046 */
3051 /* A memory bus event - a fence, or acquisition/release of the
3052 hardware bus lock. IR optimisation treats all these as fences
3053 across which no memory references may be moved.
3054 ppIRStmt output: MBusEvent-Fence,
3055 MBusEvent-BusLock, MBusEvent-BusUnlock.
3056 */
3058 IRMBusEvent event;
3061 /* Conditional exit from the middle of an IRSB.
3062 ppIRStmt output: if (<guard>) goto {<jk>} <dst>
3063 eg. if (t69) goto {Boring} 0x4000AAA:I32
3064 If <guard> is true, the guest state is also updated by
3065 PUT-ing <dst> at <offsIP>. This is done because a
3066 taken exit must update the guest program counter.
3067 */
3075 }
3076 IRStmt;
3078 /* Statement constructors. */
3096 Int offsIP );
3098 /* Deep-copy an IRStmt. */
3101 /* Pretty-print an IRStmt. */
3105 /* ------------------ Basic Blocks ------------------ */
3107 /* Type environments: a bunch of statements, expressions, etc, are
3108 incomplete without an environment indicating the type of each
3109 IRTemp. So this provides one. IR temporaries are really just
3110 unsigned ints and so this provides an array, 0 .. n_types_used-1 of
3111 them.
3112 */
3113 typedef
3116 Int types_size;
3117 Int types_used;
3118 }
3119 IRTypeEnv;
3121 /* Obtain a new IRTemp */
3124 /* Deep-copy a type environment */
3127 /* Pretty-print a type environment */
3131 /* Code blocks, which in proper compiler terminology are superblocks
3132 (single entry, multiple exit code sequences) contain:
3134 - A table giving a type for each temp (the "type environment")
3135 - An expandable array of statements
3136 - An expression of type 32 or 64 bits, depending on the
3137 guest's word size, indicating the next destination if the block
3138 executes all the way to the end, without a side exit
3139 - An indication of any special actions (JumpKind) needed
3140 for this final jump.
3141 - Offset of the IP field in the guest state. This will be
3142 updated before the final jump is done.
3144 "IRSB" stands for "IR Super Block".
3145 */
3146 typedef
3150 Int stmts_size;
3151 Int stmts_used;
3153 IRJumpKind jumpkind;
3154 Int offsIP;
3155 }
3156 IRSB;
3158 /* Allocate a new, uninitialised IRSB */
3161 /* Deep-copy an IRSB */
3164 /* Deep-copy an IRSB, except for the statements list, which set to be
3165 a new, empty, list of statements. */
3168 /* Pretty-print an IRSB */
3171 /* Append an IRStmt to an IRSB */
3175 /*---------------------------------------------------------------*/
3176 /*--- Helper functions for the IR ---*/
3177 /*---------------------------------------------------------------*/
3179 /* For messing with IR type environments */
3182 /* What is the type of this expression? */
3187 /* What are the arg and result type for this IRLoadGOp? */
3192 /* Sanity check a BB of IR */
3195 Bool require_flatness,
3196 IRType guest_word_size );
3200 /* Is this any value actually in the enumeration 'IRType' ? */
3204 /*---------------------------------------------------------------*/
3205 /*--- IR injection ---*/
3206 /*---------------------------------------------------------------*/
3213 /*---------------------------------------------------------------*/
3214 /*--- libvex_ir.h ---*/
3215 /*---------------------------------------------------------------*/