VEX/priv/common_nanomips_defs.h

   1
   2 /*---------------------------------------------------------------*/
   3 /*--- begin                            common_nanomips_defs.h ---*/
   4 /*---------------------------------------------------------------*/
   5
   6 /*
   7    This file is part of Valgrind, a dynamic binary instrumentation
   8    framework.
   9
  10    Copyright (C) 2017-2018 RT-RK
  11
  12    This program is free software; you can redistribute it and/or
  13    modify it under the terms of the GNU General Public License as
  14    published by the Free Software Foundation; either version 2 of the
  15    License, or (at your option) any later version.
  16
  17    This program is distributed in the hope that it will be useful, but
  18    WITHOUT ANY WARRANTY; without even the implied warranty of
  19    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  20    General Public License for more details.
  21
  22    You should have received a copy of the GNU General Public License
  23    along with this program; if not, write to the Free Software
  24    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  25    02111-1307, USA.
  26
  27    The GNU General Public License is contained in the file COPYING.
  28 */
  29 #ifndef __VEX_COMMON_NANOMIPS_DEFS_H
  30 #define __VEX_COMMON_NANOMIPS_DEFS_H
  31
  32 typedef enum {
  33    P_ADDIURI = 0x00,
  34    ADDIUPC32 = 0x01,
  35    MOVE_BALC = 0x02,
  36    P16MV     = 0x04,
  37    LW16      = 0x05,
  38    BC16      = 0x06,
  39    P16SR     = 0x07,
  40    P32A      = 0x08,
  41    PBAL      = 0x0A,
  42    P16SHIFT  = 0x0C,
  43    LWSP      = 0x0D,
  44    BALC16    = 0x0E,
  45    P164X4    = 0x0F,
  46    PGPW      = 0x10,
  47    PGPBH     = 0x11,
  48    PJ        = 0x12,
  49    P16C      = 0x14,
  50    LWGP16    = 0x15,
  51    P16LB     = 0x17,
  52    P48I      = 0x18,
  53    P16A1     = 0x1C,
  54    LW4X4     = 0x1D,
  55    P16LH     = 0x1F,
  56    PU12      = 0x20,
  57    PLSU12    = 0x21,
  58    PBR1      = 0x22,
  59    P16A2     = 0x24,
  60    SW16      = 0x25,
  61    BEQZC16   = 0x26,
  62    PLSS9     = 0x29,
  63    PBR2      = 0x2A,
  64    P16ADDU   = 0x2C,
  65    SWSP      = 0x2D,
  66    BNEZC16   = 0x2E,
  67    MOVEP     = 0x2F,
  68    PBRI      = 0x32,
  69    LI16      = 0x34,
  70    SWGP16    = 0x35,
  71    P16BR     = 0x36,
  72    P_LUI     = 0x38,
  73    ANDI16    = 0x3C,
  74    SW4X4     = 0x3D,
  75    MOVEPREV  = 0x3F,
  76 } nanoMIPSopcodes;
  77
  78 typedef enum {
  79    P48I_LI       = 0x00,
  80    P48I_ADDIU    = 0x01,
  81    P48I_ADDIU_GP = 0x02,
  82    P48I_ADDIUPC  = 0x03,
  83    P48I_LWPC     = 0x0B,
  84    P48I_SWPC     = 0x0F,
  85 } nanoP48I;
  86
  87 typedef enum {
  88    JALRC32 = 0x00,
  89    JALRCHB = 0x01,
  90    PBALRSC = 0x08
  91 } nano_PJ;
  92
  93 typedef enum {
  94    PLSS0   = 0x00,
  95    PLSS1   = 0x01,
  96    PLSE0   = 0x02,
  97    PLSWM   = 0x04,
  98    PLSUAWM = 0x05,
  99    PLSDM   = 0x06,
 100    PLSUADM = 0x07,
 101 } nanoPLSS9;
 102
 103 typedef enum {
 104    PU12_ORI       = 0x00,
 105    PU12_XORI      = 0x01,
 106    PU12_ANDI      = 0x02,
 107    PU12_PSR       = 0x03,
 108    PU12_SLTI      = 0x04,
 109    PU12_SLTIU     = 0x05,
 110    PU12_SEQI      = 0x06,
 111    PU12_ADDIU_NEG = 0x08,
 112    PU12_PSHIFT    = 0x0C,
 113    PU12_PROTX     = 0x0D,
 114    PU12_PINS      = 0x0E,
 115    PU12_PEXT      = 0x0F
 116 } nanoPU12;
 117
 118 typedef enum {
 119    RI_PSYSCALL  = 0x1,
 120    RI_BREAK     = 0x2,
 121    RI_SDBBP     = 0x3
 122 } nanoP16RI;
 123
 124 typedef enum {
 125    PRI_SIGRIE    = 0x0,
 126    PRI_PSYSCALL  = 0x1,
 127    PRI_BREAK     = 0x2,
 128    PRI_SDBBP     = 0x3
 129 } nanoPRI;
 130
 131 typedef enum {
 132    P32A_POOL32A0 = 0x00,
 133    P32A_POOL32A7 = 0x07
 134 } nano_P32A;
 135
 136 typedef enum {
 137    _POOL32A0_PTRAP  = 0x00,
 138    _POOL32A0_SEB    = 0x01,
 139    _POOL32A0_SLLV   = 0x02,
 140    _POOL32A0_MUL32  = 0x03,
 141    _POOL32A0_MFC0   = 0x06,
 142    _POOL32A0_MFHC0  = 0x07,
 143    _POOL32A0_SEH    = 0x09,
 144    _POOL32A0_SRLV   = 0x0A,
 145    _POOL32A0_MUH    = 0x0B,
 146    _POOL32A0_MTC0   = 0x0E,
 147    _POOL32A0_MTHC0  = 0x0F,
 148    _POOL32A0_SRAV   = 0x12,
 149    _POOL32A0_MULU   = 0x13,
 150    _POOL32A0_MFGC0  = 0x16,
 151    _POOL32A0_MFHGC0 = 0x17,
 152    _POOL32A0_ROTRV  = 0x1A,
 153    _POOL32A0_MUHU   = 0x1B,
 154    _POOL32A0_MTGC0  = 0x1E,
 155    _POOL32A0_MTHGC0 = 0x1F,
 156    _POOL32A0_ADD    = 0x22,
 157    _POOL32A0_DIV    = 0x23,
 158    _POOL32A0_DMFC0  = 0x26,
 159    _POOL32A0_ADDU32 = 0x2A,
 160    _POOL32A0_MOD    = 0x2B,
 161    _POOL32A0_DMTC0  = 0x2E,
 162    _POOL32A0_SUB    = 0x32,
 163    _POOL32A0_DIVU   = 0x33,
 164    _POOL32A0_DMFGC0 = 0x36,
 165    _POOL32A0_RDHWR  = 0x38,
 166    _POOL32A0_SUBU32 = 0x3A,
 167    _POOL32A0_MODU   = 0x3B,
 168    _POOL32A0_DMTGC0 = 0x3E,
 169    _POOL32A0_PCMOVE = 0x42,
 170    _POOL32A0_FORK   = 0x45,
 171    _POOL32A0_MFTR   = 0x46,
 172    _POOL32A0_MFHTR  = 0x47,
 173    _POOL32A0_AND32  = 0x4A,
 174    _POOL32A0_YIELD  = 0x4D,
 175    _POOL32A0_MTTR   = 0x4E,
 176    _POOL32A0_MTHTR  = 0x4F,
 177    _POOL32A0_OR32   = 0x52,
 178    _POOL32A0_PMTVPE = 0x56,
 179    _POOL32A0_NOR    = 0x5A,
 180    _POOL32A0_XOR32  = 0x62,
 181    _POOL32A0_SLT    = 0x6A,
 182    _POOL32A0_PSLTU  = 0x72,
 183    _POOL32A0_SOV    = 0x7A,
 184 } nano_POOL32A0;
 185
 186 typedef enum {
 187    _POOL32A7_PLSX    = 0x00,
 188    _POOL32A7_LSA     = 0x01,
 189    _POOL32A7_EXTW    = 0x03,
 190    _POOL32A7_P32Axf  = 0x07,
 191 } nano_POOL32A7;
 192
 193 typedef enum {
 194    nano_POOL32Axf4_CLO = 0x25,
 195    nano_POOL32Axf4_CLZ = 0x2D,
 196 } nano_POOL32Axf4;
 197
 198 typedef enum {
 199    PLSX_PPLSX  = 0x00,
 200    PLSX_PPLSXS = 0x01,
 201 } nano_PLSX;
 202
 203 typedef enum {
 204    LBX   = 0x00,
 205    SBX   = 0x01,
 206    LBUX  = 0x02,
 207    LHX   = 0x04,
 208    SHX   = 0x05,
 209    LHUX  = 0x06,
 210    LWUX  = 0x07,
 211    LWX   = 0x08,
 212    SWX   = 0x09,
 213    LWC1X = 0x0A,
 214    SWC1X = 0x0B,
 215    LDX   = 0x0C,
 216    SDX   = 0x0D,
 217    LDC1X = 0x0E,
 218    SDC1X = 0x0F
 219 } nano_PPLSX;
 220
 221 typedef enum {
 222    LHXS   = 0x04,
 223    SHXS   = 0x05,
 224    LHUXS  = 0x06,
 225    LWUXS  = 0x07,
 226    LWXS32 = 0x08,
 227    SWXS   = 0x09,
 228    LWC1XS = 0x0A,
 229    SWC1XS = 0x0B,
 230    LDXS   = 0x0C,
 231    SDXS   = 0x0D,
 232    LDC1XS = 0x0E,
 233    SDC1XS = 0x0F
 234 } nano_PPLSXS;
 235
 236 typedef enum {
 237    PLSU12_LB    = 0x00,
 238    PLSU12_SB    = 0x01,
 239    PLSU12_LBU   = 0x02,
 240    PLSU12_PREF  = 0x03,
 241    PLSU12_LH    = 0x04,
 242    PLSU12_SH    = 0x05,
 243    PLSU12_LHU   = 0x06,
 244    PLSU12_LWU   = 0x07,
 245    PLSU12_LW    = 0x08,
 246    PLSU12_SW    = 0x09,
 247    PLSU12_LWC1  = 0x0A,
 248    PLSU12_SWC1  = 0x0B,
 249    PLSU12_LD    = 0x0C,
 250    PLSU12_SD    = 0x0D,
 251    PLSU12_LDC1  = 0x0E,
 252    PLSU12_SDC1  = 0x0F,
 253
 254 } nano_PLSU12;
 255
 256 typedef enum {
 257    PSLL      = 0x00,
 258    SRL32     = 0x02,
 259    SRA       = 0x04,
 260    ROTR      = 0x06,
 261    DSLL      = 0x08,
 262    DSLL32    = 0x09,
 263    DSRL      = 0x0A,
 264    DSRL32    = 0x0B,
 265    DSRA      = 0x0C,
 266    DSRA32    = 0x0D,
 267    DROTR     = 0x0E,
 268    DROTR32   = 0x0F,
 269 } nano_PSHIFT;
 270
 271 typedef enum {
 272    LBS9     = 0x00,
 273    SBS9     = 0x01,
 274    LBUS9    = 0x02,
 275    PPREFS9  = 0x03,
 276    LHS9     = 0x04,
 277    SHS9     = 0x05,
 278    LHUS9    = 0x06,
 279    LWUS9    = 0x07,
 280    LWS9     = 0x08,
 281    SWS9     = 0x09,
 282    LWC1S9   = 0x0A,
 283    SWC1S9   = 0x0B,
 284    LDS9     = 0x0C,
 285    SDS9     = 0x0D,
 286    LDC1S9   = 0x0E,
 287    SDC1S9   = 0x0F,
 288 } nano_PLSS0;
 289
 290 typedef enum {
 291    LBGP     = 0x00,
 292    SBGP     = 0x01,
 293    LBUGP    = 0x02,
 294    ADDIUGPB = 0x03,
 295    PGPLH    = 0x04,
 296    PGPSH    = 0x05,
 297    PGPCP1   = 0x06,
 298    PGPM64   = 0x07
 299 } nano_PGPBH;
 300
 301 typedef enum {
 302    ASET_ACLER = 0x02,
 303    UALH       = 0x04,
 304    UASH       = 0x05,
 305    CACHE      = 0x07,
 306    LWC2       = 0x08,
 307    SWC2       = 0x09,
 308    PLL        = 0x0A,
 309    PSC        = 0x0B,
 310    LDC2       = 0x0C,
 311    SDC2       = 0x0D,
 312    PLLD       = 0x0E,
 313    PSCD       = 0x0F
 314 } nano_PLSS1;
 315
 316 typedef enum {
 317    LL   = 0x00,
 318    LLWP = 0x01
 319 } nano_LL;
 320
 321 typedef enum {
 322    SC   = 0x00,
 323    SCWP = 0x01
 324 } nano_SC;
 325
 326 typedef enum {
 327    PBR1_BEQC32 = 0x00,
 328    PBR1_PBR3A  = 0x01,
 329    PBR1_BGEC   = 0x02,
 330    PBR1_BGEUC  = 0x03,
 331 } nano_PBR1;
 332
 333 typedef enum {
 334    PBR2_BNEC32 = 0x00,
 335    PBR2_BLTC   = 0x02,
 336    PBR2_BLTUC  = 0x03,
 337 } nano_PBR2;
 338
 339 typedef enum {
 340    PBRI_BEQIC  = 0x00,
 341    PBRI_BBEQZC = 0x01,
 342    PBRI_BGEIC  = 0x02,
 343    PBRI_BGEIUC = 0x03,
 344    PBRI_BNEIC  = 0x04,
 345    PBRI_BBNEZC = 0x05,
 346    PBRI_BLTIC  = 0x06,
 347    PBRI_BLTIUC = 0x07
 348 } nano_PBRI;
 349
 350 typedef enum {
 351    PGPW_ADDIU = 0x00,
 352    PGPW_PGPD  = 0X01,
 353    PGPW_LW  = 0X02,
 354    PGPW_SW  = 0X03
 355 } nano_PGPW;
 356
 357 typedef enum {
 358    POOL32aXF_4 = 0x04,
 359    POOL32aXF_5 = 0x05,
 360 } nano_POOL32Axf;
 361
 362 typedef enum {
 363    POOL16C00_NOT = 0x00,
 364    POOL16C00_XOR = 0x04,
 365    POOL16C00_AND = 0x08,
 366    POOL16C00_OR  = 0x0C,
 367 } nano_POOL16C_00;
 368
 369 #endif
 370
 371 /*---------------------------------------------------------------*/
 372 /*--- end                              common_nanomips_defs.h ---*/
 373 /*---------------------------------------------------------------*/