| blob | 1b9821a7cf02e0718676307bf20ca88992f9d7b1 |
2 /*--------------------------------------------------------------------*/
3 /*--- begin guest_generic_bb_to_IR.c ---*/
4 /*--------------------------------------------------------------------*/
6 /*
7 This file is part of Valgrind, a dynamic binary instrumentation
8 framework.
10 Copyright (C) 2004-2017 OpenWorks LLP
11 info@open-works.net
13 This program is free software; you can redistribute it and/or
14 modify it under the terms of the GNU General Public License as
15 published by the Free Software Foundation; either version 2 of the
16 License, or (at your option) any later version.
18 This program is distributed in the hope that it will be useful, but
19 WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21 General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, see <http://www.gnu.org/licenses/>.
26 The GNU General Public License is contained in the file COPYING.
28 Neither the names of the U.S. Department of Energy nor the
29 University of California nor the names of its contributors may be
30 used to endorse or promote products derived from this software
31 without prior written permission.
32 */
43 /*--------------------------------------------------------------*/
44 /*--- Forwards for fns called by self-checking translations ---*/
45 /*--------------------------------------------------------------*/
47 /* Forwards .. */
49 HWord n_w32s );
64 HWord n_w64s );
79 /*--------------------------------------------------------------*/
80 /*--- Creation of self-check IR ---*/
81 /*--------------------------------------------------------------*/
98 const Addr guest_IP_sbstart
99 )
100 {
101 /* The scheme is to compute a rather crude checksum of the code
102 we're making a translation of, and add to the IR a call to a
103 helper routine which recomputes the checksum every time the
104 translation is run, and requests a retranslation if it doesn't
105 match. This is obviously very expensive and considerable
106 efforts are made to speed it up:
108 * the checksum is computed from all the naturally aligned
109 host-sized words that overlap the translated code. That means
110 it could depend on up to 7 bytes before and 7 bytes after
111 which aren't part of the translated area, and so if those
112 change then we'll unnecessarily have to discard and
113 retranslate. This seems like a pretty remote possibility and
114 it seems as if the benefit of not having to deal with the ends
115 of the range at byte precision far outweigh any possible extra
116 translations needed.
118 * there's a generic routine and 12 specialised cases, which
119 handle the cases of 1 through 12-word lengths respectively.
120 They seem to cover about 90% of the cases that occur in
121 practice.
123 We ask the caller, via needs_self_check, which of the 3 vge
124 extents needs a check, and only generate check code for those
125 that do.
126 */
127 {
128 Addr base2check;
129 UInt len2check;
130 HWord expectedhW;
141 UInt extents_needing_check
150 /* Caller shouldn't claim that nonexistent extents need a
151 check. */
154 /* Guest addresses as IRConsts. Used in self-checks to specify the
155 restart-after-discard point. */
156 IRConst* guest_IP_sbstart_IRConst
167 /* Do we need to generate a check for this extent? */
171 /* Tell the caller */
174 /* the extent we're generating a check for */
178 /* stay sane */
181 /* Skip the check if the translation involved zero bytes */
196 /* vex_printf("%lx %lx %ld\n", first_hW, last_hW, hWs_to_check); */
200 genericg_compute_checksum_8al;
204 genericg_compute_checksum_4al;
206 }
240 }
272 }
275 }
278 /* If we got a specialised version, check it produces the same
279 result as the generic version! */
285 }
287 /* Set CMSTART and CMLEN. These will describe to the despatcher
288 the area of guest code to invalidate should we exit with a
289 self-check failure. */
293 IRConst* base2check_IRConst
296 IRConst* len2check_IRConst
320 /* Generate the entry point descriptors */
329 }
336 }
337 }
339 /* Generate the call to the relevant function, and the comparison of
340 the result against the expected value. */
348 )
349 );
357 )
358 );
359 }
366 exitguard_tmp,
370 host_word_type==Ity_I64
376 Ijk_InvalICache,
377 /* Where we must restart if there's a failure: at the
378 first extent, regardless of which extent the failure
379 actually happened in. */
380 guest_IP_sbstart_IRConst,
381 offB_GUEST_IP
382 );
401 }
402 }
403 }
406 /*--------------------------------------------------------------*/
407 /*--- To do with guarding (conditionalisation) of IRStmts ---*/
408 /*--------------------------------------------------------------*/
410 // Is it possible to guard |e|? Meaning, is it safe (exception-free) to compute
411 // |e| and ignore the result? Since |e| is by definition otherwise
412 // side-effect-free, we don't have to ask about any other effects caused by
413 // first computing |e| and then ignoring the result.
415 {
437 }
438 }
440 // Is it possible to guard |st|? Meaning, is it possible to replace |st| by
441 // some other sequence of IRStmts which have the same effect on the architected
442 // state when the guard is true, but when it is false, have no effect on the
443 // architected state and are guaranteed not to cause any exceptions?
444 //
445 // Note that this isn't as aggressive as it could be: it sometimes returns False
446 // in cases where |st| is actually guardable. This routine must coordinate
447 // closely with add_guarded_stmt_to_end_of below, in the sense that that routine
448 // must be able to handle any |st| for which this routine returns True.
450 {
452 // These are easily guarded.
458 // These are definitely not guardable, or at least it's way too much
459 // hassle to do so.
464 // These could be guarded, with some effort, if really needed, but
465 // currently aren't guardable.
472 // This is probably guardable, but it depends on the RHS of the
473 // assignment.
479 }
480 }
482 // Are all stmts (but not the end dst value) in |bb| guardable, per
483 // stmt_is_guardable?
485 {
488 i--;
490 i--;
494 }
496 }
498 // Guard |st| with |guard| and add it to |bb|. This must be able to handle any
499 // |st| for which stmt_is_guardable returns True.
502 {
510 // Put(offs, e) ==> Put(offs, ITE(guard, e, Get(offs, sizeof(e))))
511 // Which when flattened out is:
512 // t1 = Get(offs, sizeof(e))
513 // t2 = ITE(guard, e, t1)
514 // Put(offs, t2)
525 }
527 // PutI(descr,ix,bias, e) ==> Put(descr,ix,bias, ITE(guard, e, GetI(descr,ix,bias)))
528 // Which when flattened out is:
529 // t1 = GetI(descr,ix,bias)
530 // t2 = ITE(guard, e, t1)
531 // PutI(descr,ix,bias, t2)
545 }
547 // Exit(xguard, dst, jk, offsIP)
548 // ==> t1 = And1(xguard, guard)
549 // Exit(t1, dst, jk, offsIP)
557 }
561 }
562 }
565 /*--------------------------------------------------------------*/
566 /*--- Analysis of block ends ---*/
567 /*--------------------------------------------------------------*/
569 typedef
573 Be_Cond // Conditional branch to known destinations, unassisted
574 }
575 BlockEndTag;
577 typedef
579 BlockEndTag tag;
584 Long delta;
587 IRTemp condSX;
588 Long deltaSX;
589 Long deltaFT;
592 }
593 BlockEnd;
596 {
612 }
613 }
615 // Return True if |be| definitely does not jump to |delta|. In case of
616 // doubt, returns False.
618 {
628 }
629 }
632 {
642 }
643 }
651 {
656 // Extract the destination guest address.
659 // Check we're allowed to chase into it.
664 // Either |delta_as_Addr| is a 64-bit value, in which case copy it directly
665 // to |delta|, or it's a 32 bit value, in which case sign extend it.
668 }
671 {
677 }
679 /* Scan |stmts|, starting at |scan_start| and working backwards, to detect the
680 case where there are no IRStmt_Exits before we find the IMark. In other
681 words, it scans backwards through some prefix of an instruction's IR to see
682 if there is an exit there.
684 It also checks for explicit PUTs to the PC, via Ist_Put, Ist_PutI or
685 Ist_Dirty. I suspect this is ridiculous overkill, but is here for safety. */
690 )
691 {
700 // We're back at the start of the insn. Stop searching.
702 }
706 }
713 }
714 }
723 }
724 }
740 }
741 }
742 }
743 }
746 }
747 }
748 i--;
749 }
750 // We expect IR for all instructions to start with an IMark.
753 }
760 Int offB_GUEST_IP,
761 Int szB_GUEST_IP,
762 Bool debug_print )
763 {
766 // -- Conditional branch to known destination
767 /* In short, detect the following end form:
768 ------ IMark(0x4002009, 2, 0) ------
769 // Zero or more non-exit statements
770 if (t14) { PUT(184) = 0x4002040:I64; exit-Boring }
771 PUT(184) = 0x400200B:I64; exit-Boring
772 Checks:
773 - Both transfers are 'boring'
774 - Both dsts are constants
775 - The cond is non-constant (an IRExpr_Tmp)
776 - There are no other exits in this instruction
777 - The client allows chasing into both destinations
778 */
794 Bool ok_SX
798 Bool ok_FT
808 }
809 }
810 }
812 // -- Unconditional branch/call to known destination
813 /* Four checks:
814 - The transfer is 'boring' or 'call', so that no assistance is needed
815 - The dst is a constant (known at jit time)
816 - There are no other exits in this instruction. In other words, the
817 transfer is unconditional.
818 - The client allows chasing into the destination.
819 */
825 // We've got the right pattern. Check whether we can chase into the
826 // destination, and if so convert that to a delta value.
829 // This call also checks the type of the dst addr, and that the client
830 // allows chasing into it.
838 }
839 }
840 }
842 // Not identified as anything of interest to us.
845 out:
850 }
851 }
854 /*--------------------------------------------------------------*/
855 /*--- Disassembly of basic (not super) blocks ---*/
856 /*--------------------------------------------------------------*/
858 /* Disassemble instructions, starting at |&guest_code[delta_IN]|, into |irbb|,
859 and terminate the block properly. At most |n_instrs_allowed_IN| may be
860 disassembled, and this function may choose to disassemble fewer.
862 Also do minimal simplifications on the resulting block, so as to convert the
863 end of the block into something that |analyse_block_end| can reliably
864 recognise.
866 |irbb| will both be modified, and replaced by a new, simplified version,
867 which is returned.
868 */
887 const Int offB_GUEST_IP
888 )
889 {
890 /* This is the max instrs we allow in the block. It starts off at
891 |n_instrs_allowed_IN| but we may choose to reduce it in the case where the
892 instruction disassembler returns an 'is verbose' hint. This is so as to
893 ensure that the JIT doesn't run out of space. See bug 375839 for a
894 motivating example. */
896 /* Process instructions. */
908 /* This is the IP of the instruction we're just about to deal
909 with. */
912 /* This is the irbb statement array index of the first stmt in
913 this insn. That will always be the instruction-mark
914 descriptor. */
917 /* Add an instruction-mark statement. We won't know until after
918 disassembling the instruction how long it instruction is, so
919 just put in a zero length and we'll fix it up later.
921 On ARM, the least significant bit of the instr address
922 distinguishes ARM vs Thumb instructions. All instructions
923 actually start on at least 2-aligned addresses. So we need
924 to ignore the bottom bit of the insn address when forming the
925 IMark's address field, but put that bottom bit in the delta
926 field, so that comparisons against guest_R15T for Thumb can
927 be done correctly. By inspecting the delta field,
928 instruction processors can determine whether the instruction
929 was originally Thumb or ARM. For more details of this
930 convention, see comments on definition of guest_R15T in
931 libvex_guest_arm.h. */
933 /* Thumb insn => mask out the T bit, but put it in delta */
938 )
939 );
941 /* All other targets: store IP as-is, and set delta to zero. */
946 )
947 );
948 }
953 /* Finally, actually disassemble an instruction. */
955 DisResult dres
960 /* stay sane ... */
962 /* ... disassembled insn length is sane ... */
965 /* If the disassembly function passed us a hint, take note of it. */
967 /* Do nothing */
970 /* The current insn is known to be verbose. Lower the max insns limit
971 if necessary so as to avoid running the JIT out of space in the
972 event that we've encountered the start of a long sequence of them.
973 This is expected to be a very rare event. In any case the remaining
974 limit (in the default setting, 30 insns) is still so high that most
975 blocks will terminate anyway before then. So this is very unlikely
976 to give a perf hit in practice. See bug 375839 for the motivating
977 example. */
980 // Halve the number of allowed insns, but only above 2
983 //vassert(*n_instrs <= n_instrs_allowed);
984 }
985 }
986 }
988 /* Fill in the insn-mark length field. */
996 /* Print the resulting IR, if needed. */
1002 }
1003 }
1005 /* Individual insn disassembly may not mess with irbb->next.
1006 This function is the only place where it can be set. */
1011 /* Individual insn disassembly must finish the IR for each
1012 instruction with an assignment to the guest PC. */
1014 /* it follows that irbb->stmts_used must be > 0 */
1019 /* Really we should also check that the type of the Put'd data
1020 == guest_word_type, but that's a bit expensive. */
1021 }
1023 /* Update the extents entry that we are constructing. */
1024 /* If vex_control.guest_max_insns is required to be < 100 and
1025 each insn is at max 20 bytes long, this limit of 5000 then
1026 seems reasonable since the max possible extent length will be
1027 100 * 20 == 2000. */
1032 /* Advance delta (inconspicuous but very important :-) */
1040 /* We have to stop. See comment above re irbb field
1041 settings here. */
1043 /* irbb->jumpkind must already by Ijk_Boring */
1046 }
1050 /* See comment above re irbb field settings here. */
1058 }
1064 /* irbb->next must now be set, since we've finished the block.
1065 Print it if necessary.*/
1075 }
1077 /* And clean it up. */
1081 }
1084 }
1087 /*--------------------------------------------------------------*/
1088 /*--- Disassembly of traces: helper functions ---*/
1089 /*--------------------------------------------------------------*/
1091 // Swap the side exit and fall through exit for |bb|. Update |be| so as to be
1092 // consistent.
1094 {
1103 // We need to insert a new stmt, just before the exit, that computes 'Not1'
1104 // of the guard condition. Replace |bb->stmts[bb->stmts_used - 1]| by the
1105 // new stmt, and then place |exit| immediately after it.
1114 // Swap the actual destination constants.
1118 }
1120 // And update |be|.
1125 }
1126 }
1133 {
1144 // Adjust *instrs_avail so that, when it becomes zero, we haven't used
1145 // more than 50% of vex_control.guest_max_instrs.
1150 }
1152 }
1154 // Subtract bb_instrs_used from *instrs_avail, clamping at 0 if necessary.
1159 }
1162 }
1164 // Add the extent [base, +len) to |vge|. Asserts if |vge| is already full.
1165 // As an optimisation only, tries to also merge the new extent with the
1166 // previous one, if possible.
1168 {
1176 // Try to merge with the previous extent
1183 //vex_printf("MERGE\n");
1184 }
1185 }
1188 /*--------------------------------------------------------------*/
1189 /*--- Disassembly of traces: main function ---*/
1190 /*--------------------------------------------------------------*/
1192 /* Disassemble a complete basic block, starting at guest_IP_start,
1193 returning a new IRSB. The disassembler may chase across basic
1194 block boundaries if it wishes and if chase_into_ok allows it.
1195 The precise guest address ranges from which code has been taken
1196 are written into vge. guest_IP_sbstart is taken to be the IP in
1197 the guest's address space corresponding to the instruction at
1198 &guest_code[0].
1200 dis_instr_fn is the arch-specific fn to disassemble on function; it
1201 is this that does the real work.
1203 needs_self_check is a callback used to ask the caller which of the
1204 extents, if any, a self check is required for. The returned value
1205 is a bitmask with a 1 in position i indicating that the i'th extent
1206 needs a check. Since there can be at most 3 extents, the returned
1207 values must be between 0 and 7.
1209 The number of extents which did get a self check (0 to 3) is put in
1210 n_sc_extents. The caller already knows this because it told us
1211 which extents to add checks for, via the needs_self_check callback,
1212 but we ship the number back out here for the caller's convenience.
1214 preamble_function is a callback which allows the caller to add
1215 its own IR preamble (following the self-check, if any). May be
1216 NULL. If non-NULL, the IRSB under construction is handed to
1217 this function, which presumably adds IR statements to it. The
1218 callback may optionally complete the block and direct bb_to_IR
1219 not to disassemble any instructions into it; this is indicated
1220 by the callback returning True.
1222 offB_CMADDR and offB_CMLEN are the offsets of guest_CMADDR and
1223 guest_CMLEN. Since this routine has to work for any guest state,
1224 without knowing what it is, those offsets have to passed in.
1226 callback_opaque is a caller-supplied pointer to data which the
1227 callbacks may want to see. Vex has no idea what it is.
1228 (In fact it's a VgInstrumentClosure.)
1229 */
1231 /* Regarding IP updating. dis_instr_fn (that does the guest specific
1232 work of disassembling an individual instruction) must finish the
1233 resulting IR with "PUT(guest_IP) = ". Hence in all cases it must
1234 state the next instruction address.
1236 If the block is to be ended at that point, then this routine
1237 (bb_to_IR) will set up the next/jumpkind/offsIP fields so as to
1238 make a transfer (of the right kind) to "GET(guest_IP)". Hence if
1239 dis_instr_fn generates incorrect IP updates we will see it
1240 immediately (due to jumping to the wrong next guest address).
1242 However it is also necessary to set this up so it can be optimised
1243 nicely. The IRSB exit is defined to update the guest IP, so that
1244 chaining works -- since the chain_me stubs expect the chain-to
1245 address to be in the guest state. Hence what the IRSB next fields
1246 will contain initially is (implicitly)
1248 PUT(guest_IP) [implicitly] = GET(guest_IP) [explicit expr on ::next]
1250 which looks pretty strange at first. Eg so unconditional branch
1251 to some address 0x123456 looks like this:
1253 PUT(guest_IP) = 0x123456; // dis_instr_fn generates this
1254 // the exit
1255 PUT(guest_IP) [implicitly] = GET(guest_IP); exit-Boring
1257 after redundant-GET and -PUT removal by iropt, we get what we want:
1259 // the exit
1260 PUT(guest_IP) [implicitly] = 0x123456; exit-Boring
1262 This makes the IRSB-end case the same as the side-exit case: update
1263 IP, then transfer. There is no redundancy of representation for
1264 the destination, and we use the destination specified by
1265 dis_instr_fn, so any errors it makes show up sooner.
1266 */
1292 /*IN*/ Int szB_GUEST_IP
1293 )
1294 {
1297 /* check sanity .. */
1310 }
1312 /* Initialise all return-by-ref state. */
1319 /* And a new IR superblock to dump the result into. */
1322 /* Leave 21 spaces in which to put the check statements for a self
1323 checking translation (up to 3 extents, and 7 stmts required for
1324 each). We won't know until later the extents and checksums of
1325 the areas, if any, that need to be checked. */
1331 /* If the caller supplied a function to add its own preamble, use
1332 it now. */
1336 /* The callback has completed the IR block without any guest
1337 insns being disassembled into it, so just return it at
1338 this point, even if a self-check was requested - as there
1339 is nothing to self-check. The 21 self-check no-ops will
1340 still be in place, but they are harmless. */
1345 }
1346 }
1348 /* Running state:
1349 irsb the SB we are incrementally constructing
1350 vge associated extents for irsb
1351 instrs_used instrs incorporated in irsb so far
1352 instrs_avail number of instrs we have space for
1353 verbose_mode did we see an 'is verbose' hint at some point?
1354 */
1359 /* Disassemble the initial block until we have to stop. */
1360 {
1372 );
1375 // Update instrs_used, extents, budget.
1380 }
1382 /* Now, see if we can extend the initial block. */
1387 // Reasons to give up immediately:
1388 // User or tool asked us not to chase
1392 // Out of extent slots
1397 // Almost out of available instructions
1402 // Try for an extend. What kind we do depends on how the current trace
1403 // ends.
1404 /* Regarding the use of |sigill_diag| in the extension logic below. This
1405 is a Bool which controls whether or not the individual insn
1406 disassemblers print an error message in the case where they don't
1407 recognise an instruction. Generally speaking this is set to True, but
1408 VEX's client can set it to False if it wants.
1410 Now that we are speculatively chasing both arms of a conditional
1411 branch, this can lead to the following problem: one of those arms
1412 contains an undecodable instruction. That insn is not reached at run
1413 time, because the branch itself tests some CPU hwcaps info (or
1414 whatever) and execution goes down the other path. However, it has the
1415 bad side effect that the speculative disassembly will nevertheless
1416 produce an error message when |sigill_diag| is True.
1418 To avoid this, in calls to |disassemble_basic_block_till_stop| for
1419 speculative code, we pass False instead of |sigill_diag|. Note that
1420 any (unconditional-chase) call to |disassemble_basic_block_till_stop|
1421 that happens after a conditional chase that results in recovery of an
1422 &&-idiom, is still really non-speculative, because the &&-idiom
1423 translation can only happen when both paths lead to the same
1424 continuation point. The result is that we know that the initial BB,
1425 and BBs recovered via chasing an unconditional branch, are sure to be
1426 executed, even if that unconditional branch follows a conditional
1427 branch which got folded into an &&-idiom. So we don't need to change
1428 the |sigill_diag| value used for them. It's only for the
1429 conditional-branch SX and FT disassembly that it must be set to
1430 |False|.
1431 */
1432 BlockEnd irsb_be;
1437 // Try for an extend based on an unconditional branch or call to a known
1438 // destination.
1445 }
1450 IRSB* bb
1458 );
1461 /* Now we have to append 'bb' to 'irsb'. */
1464 // Update instrs_used, extents, budget.
1472 // Try for an extend based on a conditional branch, specifically in the
1473 // hope of identifying and recovering, an "A && B" condition spread across
1474 // two basic blocks.
1476 {
1483 }
1488 }
1493 IRSB* sx_bb
1502 );
1504 BlockEnd sx_be;
1511 }
1516 IRSB* ft_bb
1525 );
1527 BlockEnd ft_be;
1532 /* In order for the transformation to be remotely valid, we need:
1533 - At least one of the sx_bb or ft_bb to be have a Be_Cond end.
1534 - sx_bb and ft_bb definitely don't form a loop.
1535 */
1542 }
1544 // Check for other mutancy:
1545 // irsb ft == sx, or the same for ft itself or sx itself
1553 }
1554 }
1556 /* Now let's see if any of our four cases actually holds (viz, is this
1557 really an && idiom? */
1567 }
1574 }
1576 /* We should only have identified at most one of the four idioms. */
1584 }
1585 }
1586 }
1590 // "Normalise" the data so as to ensure we only have one of the four
1591 // idioms to transform.
1594 # define SWAP(_ty, _aa, _bb) \
1595 do { _ty _tmp = _aa; _aa = _bb; _bb = _tmp; } while (0)
1602 # undef SWAP
1603 }
1606 }
1619 }
1620 // Finally, check the sx block actually is guardable.
1624 }
1625 }
1630 }
1631 // Finally really actually do the transformation.
1632 // 0. remove the last Exit on irsb.
1633 // 1. Add irsb->tyenv->types_used to all the tmps in sx_bb,
1634 // by calling deltaIRStmt on all stmts.
1635 // 2. Guard all stmts in sx_bb on irsb_be.Be.Cond.condSX,
1636 // **including** the last stmt (which must be an Exit). It's
1637 // here that the And1 is generated.
1638 // 3. Copy all guarded stmts to the end of irsb.
1643 // Append sx_bb's tyenv to irsb's
1646 }
1652 }
1658 }
1660 // Update instrs_used, extents, budget.
1666 }
1670 // We don't know any other way to extend the block. Give up.
1673 }
1677 /* We're almost done. The only thing that might need attending to is that
1678 a self-checking preamble may need to be created. If so it gets placed
1679 in the 21 slots reserved above. */
1684 );
1688 }
1691 /*--------------------------------------------------------------*/
1692 /*--- Functions called by self-checking transations ---*/
1693 /*--------------------------------------------------------------*/
1695 /* All of these are CLEAN HELPERs */
1696 /* All of these are CALLED FROM GENERATED CODE */
1698 /* Compute a checksum of host memory at [addr .. addr+len-1], as fast
1699 as possible. All _4al versions assume that the supplied address is
1700 4 aligned. All length values are in 4-byte chunks. These fns
1701 arecalled once for every use of a self-checking translation, so
1702 they needs to be as fast as possible. */
1704 /* --- 32-bit versions, used only on 32-bit hosts --- */
1709 }
1713 {
1716 /* unrolled */
1718 UInt w;
1726 }
1728 UInt w;
1733 }
1735 }
1737 /* Specialised versions of the above function */
1741 {
1744 UInt w;
1748 }
1752 {
1755 UInt w;
1761 }
1765 {
1768 UInt w;
1776 }
1780 {
1783 UInt w;
1790 }
1794 {
1797 UInt w;
1806 }
1810 {
1813 UInt w;
1824 }
1828 {
1831 UInt w;
1844 }
1848 {
1851 UInt w;
1863 }
1867 {
1870 UInt w;
1884 }
1888 {
1891 UInt w;
1907 }
1911 {
1914 UInt w;
1932 }
1936 {
1939 UInt w;
1956 }
1959 /* --- 64-bit versions, used only on 64-bit hosts --- */
1964 }
1968 {
1971 /* unrolled */
1973 ULong w;
1981 }
1983 ULong w;
1988 }
1990 }
1992 /* Specialised versions of the above function */
1996 {
1999 ULong w;
2003 }
2007 {
2010 ULong w;
2016 }
2020 {
2023 ULong w;
2031 }
2035 {
2038 ULong w;
2045 }
2049 {
2052 ULong w;
2061 }
2065 {
2068 ULong w;
2079 }
2083 {
2086 ULong w;
2099 }
2103 {
2106 ULong w;
2118 }
2122 {
2125 ULong w;
2139 }
2143 {
2146 ULong w;
2162 }
2166 {
2169 ULong w;
2187 }
2191 {
2194 ULong w;
2211 }
2213 /*--------------------------------------------------------------------*/
2214 /*--- end guest_generic_bb_to_IR.c ---*/
2215 /*--------------------------------------------------------------------*/