1 #include "libvex_basictypes.h"
4 #include "libvex_guest_mips32.h"
5 #include "libvex_guest_mips64.h"
8 #include "main_globals.h"
9 #include "guest_generic_bb_to_IR.h"
10 #include "guest_mips_defs.h"
11 #include "mips_defs.h"
14 /* Put value to DSPControl register. Expression e is written to DSPControl as
15 is. If only certain bits of DSPControl need to be changed, it should be done
16 before calling putDSPControl(). It could be done by reading DSPControl and
17 ORing it with appropriate mask. */
18 static void putDSPControl(IRExpr
* e
)
21 stmt(IRStmt_Put(offsetof(VexGuestMIPS32State
, guest_DSPControl
), e
));
24 /* Put value to accumulator(helper function for MIPS32 DSP ASE instructions). */
25 static void putAcc(UInt acNo
, IRExpr
* e
)
29 vassert(typeOfIRExpr(irsb
->tyenv
, e
) == Ity_I64
);
30 stmt(IRStmt_Put(accumulatorGuestRegOffset(acNo
), e
));
32 /* If acNo = 0, split value to HI and LO regs in order to maintain compatibility
33 between MIPS32 and MIPS DSP ASE insn sets. */
35 putLO(unop(Iop_64to32
, e
));
36 putHI(unop(Iop_64HIto32
, e
));
39 /*------------------------------------------------------------*/
40 /*--- Disassemble a single DSP ASE instruction ---*/
41 /*------------------------------------------------------------*/
43 static UInt
disDSPInstr_MIPS_WRK_Special ( UInt cins
)
46 UInt rs
, rt
, rd
, function
, ac
, ac_mfhilo
;
50 function
= get_function(cins
);
52 ac_mfhilo
= get_acNo_mfhilo(cins
);
55 case 0x10: { /* MFHI */
56 DIP("mfhi ac%u r%u", ac_mfhilo
, rd
);
57 putIReg(rd
, unop(Iop_64HIto32
, getAcc(ac_mfhilo
)));
61 case 0x11: { /* MTHI */
62 DIP("mthi ac%u r%u", ac
, rs
);
63 t1
= newTemp(Ity_I32
);
64 assign(t1
, unop(Iop_64to32
, getAcc(ac
)));
65 putAcc(ac
, binop(Iop_32HLto64
, getIReg(rs
), mkexpr(t1
)));
69 case 0x12: { /* MFLO */
70 DIP("mflo ac%u r%u", ac_mfhilo
, rd
);
71 putIReg(rd
, unop(Iop_64to32
, getAcc(ac_mfhilo
)));
75 case 0x13: { /* MTLO */
76 DIP("mtlo ac%u r%u", ac
, rs
);
77 t1
= newTemp(Ity_I32
);
78 assign(t1
, unop(Iop_64HIto32
, getAcc(ac
)));
79 putAcc(ac
, binop(Iop_32HLto64
, mkexpr(t1
), getIReg(rs
)));
83 case 0x18: { /* MULT */
84 DIP("mult ac%u r%u, r%u", ac
, rs
, rt
);
85 t1
= newTemp(Ity_I64
);
86 assign(t1
, binop(Iop_MullS32
, mkNarrowTo32(Ity_I32
, getIReg(rs
)),
87 mkNarrowTo32(Ity_I32
, getIReg(rt
))));
88 putAcc(ac
, mkexpr(t1
));
92 case 0x19: { /* MULTU */
93 DIP("multu ac%u r%u, r%u", ac
, rs
, rt
);
94 t1
= newTemp(Ity_I64
);
95 assign(t1
, binop(Iop_MullU32
, mkNarrowTo32(Ity_I32
, getIReg(rs
)),
98 putAcc(ac
, mkexpr(t1
));
107 static UInt
disDSPInstr_MIPS_WRK_Special2 ( UInt cins
)
109 IRTemp t1
= 0, t2
, t3
;
110 UInt rs
, rt
, function
, ac
;
113 function
= get_function(cins
);
117 case 0x00: { /* MADD */
118 DIP("madd ac%u, r%u, r%u", ac
, rs
, rt
);
119 t1
= newTemp(Ity_I64
);
120 t2
= newTemp(Ity_I64
);
121 t3
= newTemp(Ity_I64
);
123 assign(t1
, getAcc(ac
));
124 assign(t2
, binop(Iop_MullS32
, getIReg(rs
), getIReg(rt
)));
125 assign(t3
, binop(Iop_Add64
, mkexpr(t1
), mkexpr(t2
)));
127 putAcc(ac
, mkexpr(t3
));
131 case 0x01: { /* MADDU */
132 DIP("maddu ac%u r%u, r%u", ac
, rs
, rt
);
133 t1
= newTemp(Ity_I64
);
134 t2
= newTemp(Ity_I64
);
135 t3
= newTemp(Ity_I64
);
137 assign(t1
, getAcc(ac
));
138 assign(t2
, binop(Iop_MullU32
, getIReg(rs
), getIReg(rt
)));
139 assign(t3
, binop(Iop_Add64
, mkexpr(t2
), mkexpr(t1
)));
141 putAcc(ac
, mkexpr(t3
));
145 case 0x04: { /* MSUB */
146 DIP("msub ac%u r%u, r%u", ac
, rs
, rt
);
147 t1
= newTemp(Ity_I64
);
148 t2
= newTemp(Ity_I64
);
149 t3
= newTemp(Ity_I64
);
151 assign(t1
, getAcc(ac
));
152 assign(t2
, binop(Iop_MullS32
, getIReg(rs
), getIReg(rt
)));
153 assign(t3
, binop(Iop_Sub64
, mkexpr(t1
), mkexpr(t2
)));
155 putAcc(ac
, mkexpr(t3
));
159 case 0x05: { /* MSUBU */
160 DIP("msubu ac%u r%u, r%u", ac
, rs
, rt
);
161 t1
= newTemp(Ity_I64
);
162 t2
= newTemp(Ity_I64
);
163 t3
= newTemp(Ity_I64
);
165 assign(t1
, getAcc(ac
));
166 assign(t2
, binop(Iop_MullU32
, getIReg(rs
), getIReg(rt
)));
167 assign(t3
, binop(Iop_Sub64
, mkexpr(t1
), mkexpr(t2
)));
169 putAcc(ac
, mkexpr(t3
));
177 static UInt
disDSPInstr_MIPS_WRK_Special3_ABSQ_SPH( UInt cins
)
179 IRTemp t0
, t1
= 0, t2
, t3
, t4
, t5
, t6
, t7
, t8
, t9
, t10
, t11
, t12
, t13
, t14
,
181 UInt rt
, rd
, sa
, dsp_imm
;
186 dsp_imm
= get_dspImm(cins
);
189 case 0x1: { /* ABSQ_S.QB */
190 DIP("absq_s.qb r%u, r%u", rd
, rt
);
192 t0
= newTemp(Ity_I8
);
193 t1
= newTemp(Ity_I1
);
194 t2
= newTemp(Ity_I1
);
195 t3
= newTemp(Ity_I8
);
196 t4
= newTemp(Ity_I8
);
197 t5
= newTemp(Ity_I1
);
198 t6
= newTemp(Ity_I1
);
199 t7
= newTemp(Ity_I8
);
200 t8
= newTemp(Ity_I8
);
201 t9
= newTemp(Ity_I1
);
202 t10
= newTemp(Ity_I1
);
203 t11
= newTemp(Ity_I8
);
204 t12
= newTemp(Ity_I8
);
205 t13
= newTemp(Ity_I1
);
206 t14
= newTemp(Ity_I1
);
207 t15
= newTemp(Ity_I8
);
208 t16
= newTemp(Ity_I32
);
209 t17
= newTemp(Ity_I32
);
211 /* Absolute value of the rightmost byte (bits 7-0). */
212 /* t0 - rightmost byte. */
213 assign(t0
, unop(Iop_16to8
, unop(Iop_32to16
, getIReg(rt
))));
214 /* t1 holds 1 if t0 is equal to 0x80, or 0 otherwise. */
215 assign(t1
, binop(Iop_CmpEQ32
,
216 unop(Iop_8Uto32
, mkexpr(t0
)),
218 /* t2 holds 1 if value in t0 is negative, 0 otherwise. */
219 assign(t2
, unop(Iop_32to1
,
225 /* t3 holds abs(t0). */
226 assign(t3
, IRExpr_ITE(mkexpr(t1
),
228 IRExpr_ITE(mkexpr(t2
),
235 /* Absolute value of bits 15-8. */
236 /* t4 - input byte. */
238 unop(Iop_16HIto8
, unop(Iop_32to16
, getIReg(rt
))));
239 /* t5 holds 1 if t4 is equal to 0x80, or 0 otherwise. */
240 assign(t5
, binop(Iop_CmpEQ32
,
241 unop(Iop_8Uto32
, mkexpr(t4
)),
243 /* t6 holds 1 if value in t4 is negative, 0 otherwise. */
244 assign(t6
, unop(Iop_32to1
,
250 /* t3 holds abs(t4). */
251 assign(t7
, IRExpr_ITE(mkexpr(t5
),
253 IRExpr_ITE(mkexpr(t6
),
260 /* Absolute value of bits 23-15. */
261 /* t8 - input byte. */
263 unop(Iop_16to8
, unop(Iop_32HIto16
, getIReg(rt
))));
264 /* t9 holds 1 if t8 is equal to 0x80, or 0 otherwise. */
265 assign(t9
, binop(Iop_CmpEQ32
,
266 unop(Iop_8Uto32
, mkexpr(t8
)),
268 /* t6 holds 1 if value in t8 is negative, 0 otherwise. */
269 assign(t10
, unop(Iop_32to1
,
275 /* t3 holds abs(t8). */
276 assign(t11
, IRExpr_ITE(mkexpr(t9
),
278 IRExpr_ITE(mkexpr(t10
),
285 /* Absolute value of bits 31-24. */
286 /* t12 - input byte. */
288 unop(Iop_16HIto8
, unop(Iop_32HIto16
, getIReg(rt
))));
289 /* t13 holds 1 if t12 is equal to 0x80, or 0 otherwise. */
290 assign(t13
, binop(Iop_CmpEQ32
,
291 unop(Iop_8Uto32
, mkexpr(t12
)),
293 /* t14 holds 1 if value in t12 is negative, 0 otherwise. */
294 assign(t14
, unop(Iop_32to1
,
300 /* t15 holds abs(t12). */
301 assign(t15
, IRExpr_ITE(mkexpr(t13
),
303 IRExpr_ITE(mkexpr(t14
),
310 /* t16 holds !0 if any of input bytes is 0x80 or 0
316 unop(Iop_1Sto32
, mkexpr(t13
)),
317 unop(Iop_1Sto32
, mkexpr(t9
))),
318 unop(Iop_1Sto32
, mkexpr(t5
))),
319 unop(Iop_1Sto32
, mkexpr(t1
))));
321 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
327 mkU32(0x00100000))));
329 /* t17 = t15|t11|t7|t3 */
332 binop(Iop_8HLto16
, mkexpr(t15
), mkexpr(t11
)),
333 binop(Iop_8HLto16
, mkexpr(t7
), mkexpr(t3
))));
335 putIReg(rd
, mkexpr(t17
));
339 case 0x2: { /* REPL.QB */
340 DIP("repl.qb r%u, %u", rd
, dsp_imm
);
343 putIReg(rd
, mkU32((dsp_imm
<< 24) | (dsp_imm
<< 16) |
344 (dsp_imm
<< 8) | (dsp_imm
)));
348 case 0x3: { /* REPLV.QB */
349 DIP("replv.qb r%u, r%u", rd
, rt
);
351 t0
= newTemp(Ity_I8
);
353 assign(t0
, unop(Iop_32to8
,
354 binop(Iop_And32
, getIReg(rt
), mkU32(0xff))));
357 binop(Iop_8HLto16
, mkexpr(t0
), mkexpr(t0
)),
358 binop(Iop_8HLto16
, mkexpr(t0
), mkexpr(t0
))));
362 case 0x4: { /* PRECEQU.PH.QBL */
363 DIP("precequ.ph.qbl r%u, r%u", rd
, rt
);
366 putIReg(rd
, binop(Iop_Or32
,
380 case 0x5: { /* PRECEQU.PH.QBR */
381 DIP("precequ.ph.qbr r%u, r%u", rd
, rt
);
384 putIReg(rd
, binop(Iop_Or32
,
398 case 0x6: { /* PRECEQU.PH.QBLA */
399 DIP("precequ.ph.qbla r%u, r%u", rd
, rt
);
402 putIReg(rd
, binop(Iop_Or32
,
416 case 0x7: { /* PRECEQU.PH.QBRA */
417 DIP("precequ.ph.qbra r%u, r%u", rd
, rt
);
420 putIReg(rd
, binop(Iop_Or32
,
434 case 0x9: { /* ABSQ_S.PH */
435 DIP("absq_s.ph r%u, r%u", rd
, rt
);
437 t0
= newTemp(Ity_I16
);
438 t1
= newTemp(Ity_I1
);
439 t2
= newTemp(Ity_I1
);
440 t3
= newTemp(Ity_I16
);
441 t4
= newTemp(Ity_I16
);
442 t5
= newTemp(Ity_I1
);
443 t6
= newTemp(Ity_I1
);
444 t7
= newTemp(Ity_I16
);
445 t8
= newTemp(Ity_I32
);
446 t9
= newTemp(Ity_I32
);
448 /* t0 holds lower 16 bits of value in rt. */
449 assign(t0
, unop(Iop_32to16
, getIReg(rt
)));
450 /* t1 holds 1 if t0 is equal to 0x8000. */
451 assign(t1
, binop(Iop_CmpEQ32
,
452 unop(Iop_16Uto32
, mkexpr(t0
)),
454 /* t2 holds 1 if value in t0 is negative, 0 otherwise. */
455 assign(t2
, unop(Iop_32to1
,
461 /* t3 holds abs(t0). */
462 assign(t3
, IRExpr_ITE(mkexpr(t1
),
464 IRExpr_ITE(mkexpr(t2
),
471 /* t4 holds lower 16 bits of value in rt. */
472 assign(t4
, unop(Iop_32HIto16
, getIReg(rt
)));
473 /* t5 holds 1 if t4 is equal to 0x8000. */
474 assign(t5
, binop(Iop_CmpEQ32
,
475 unop(Iop_16Uto32
, mkexpr(t4
)),
477 /* t6 holds 1 if value in t4 is negative, 0 otherwise. */
478 assign(t6
, unop(Iop_32to1
,
484 /* t7 holds abs(t4). */
485 assign(t7
, IRExpr_ITE(mkexpr(t5
),
487 IRExpr_ITE(mkexpr(t6
),
493 /* If any of the two input halfwords is equal 0x8000,
494 set bit 20 in DSPControl register. */
495 assign(t8
, binop(Iop_Or32
,
496 unop(Iop_1Sto32
, mkexpr(t5
)),
497 unop(Iop_1Sto32
, mkexpr(t1
))));
499 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
505 mkU32(0x00100000))));
508 assign(t9
, binop(Iop_16HLto32
, mkexpr(t7
), mkexpr(t3
)));
510 putIReg(rd
, mkexpr(t9
));
514 case 0xA: { /* REPL.PH */
515 DIP("repl.ph r%u, %u", rd
, dsp_imm
);
517 UShort immediate
= extend_s_10to16(dsp_imm
);
519 putIReg(rd
, mkU32(immediate
<< 16 | immediate
));
523 case 0xB: { /* REPLV.PH */
524 DIP("replv.ph r%u, r%u", rd
, rt
);
527 putIReg(rd
, binop(Iop_16HLto32
,
528 unop(Iop_32to16
, getIReg(rt
)),
529 unop(Iop_32to16
, getIReg(rt
))));
533 case 0xC: { /* PRECEQ.W.PHL */
534 DIP("preceq.w.phl r%u, r%u", rd
, rt
);
536 putIReg(rd
, binop(Iop_And32
,
542 case 0xD: { /* PRECEQ.W.PHR */
543 DIP("preceq.w.phr r%u, r%u", rd
, rt
);
545 putIReg(rd
, binop(Iop_16HLto32
,
546 unop(Iop_32to16
, getIReg(rt
)),
551 case 0x11: { /* ABSQ_S.W */
552 DIP("absq_s.w r%u, r%u", rd
, rt
);
554 t0
= newTemp(Ity_I1
);
555 t1
= newTemp(Ity_I1
);
556 t2
= newTemp(Ity_I32
);
559 binop(Iop_CmpEQ32
, getIReg(rt
), mkU32(0x80000000)));
561 putDSPControl(IRExpr_ITE(mkexpr(t0
),
567 assign(t1
, binop(Iop_CmpLT32S
, getIReg(rt
), mkU32(0x0)));
569 assign(t2
, IRExpr_ITE(mkexpr(t0
),
571 IRExpr_ITE(mkexpr(t1
),
577 putIReg(rd
, mkexpr(t2
));
581 case 0x1B: { /* BITREV */
582 DIP("bitrev r%u, r%u", rd
, rt
);
584 /* 32bit reversal as seen on Bit Twiddling Hacks site
585 http://graphics.stanford.edu/~seander/bithacks.html
586 section ReverseParallel */
587 t1
= newTemp(Ity_I32
);
588 t2
= newTemp(Ity_I32
);
589 t3
= newTemp(Ity_I32
);
590 t4
= newTemp(Ity_I32
);
591 t5
= newTemp(Ity_I32
);
593 assign(t1
, binop(Iop_Or32
,
604 assign(t2
, binop(Iop_Or32
,
615 assign(t3
, binop(Iop_Or32
,
626 assign(t4
, binop(Iop_Or32
,
637 assign(t5
, binop(Iop_Or32
,
644 putIReg(rd
, binop(Iop_Shr32
,
650 case 0x1C: { /* PRECEU.PH.QBL */
651 DIP("preceu.ph.qbl r%u, r%u", rd
, rt
);
654 putIReg(rd
, binop(Iop_Or32
,
668 case 0x1E: { /* PRECEU.PH.QBLA */
669 DIP("preceu.ph.qbla r%u, r%u", rd
, rt
);
672 putIReg(rd
, binop(Iop_Or32
,
686 case 0x1D: { /* PRECEU.PH.QBR */
687 DIP("preceu.ph.qbr r%u, r%u", rd
, rt
);
690 putIReg(rd
, binop(Iop_Or32
,
698 mkU32(0x000000ff))));
702 case 0x1F: { /* PRECEU.PH.QBRA */
703 DIP("preceu.ph.qbra r%u, r%u", rd
, rt
);
706 putIReg(rd
, binop(Iop_Or32
,
712 mkU32(0x000000ff))));
723 static UInt
disDSPInstr_MIPS_WRK_Special3_EXTR_W( UInt cins
)
725 IRTemp t0
, t1
= 0, t2
, t3
, t4
, t5
, t6
, t7
, t8
, t9
, t10
, t11
, t12
, t13
, t14
,
727 UInt rs
, rt
, rd
, sa
, ac
, rddsp_mask
,
735 rddsp_mask
= get_rddspMask(cins
);
736 wrdsp_mask
= get_wrdspMask(cins
);
737 shift
= get_shift(cins
);
740 case 0x0: { /* EXTR.W */
741 DIP("extr.w r%u, ac%u, %u", rt
, ac
, rs
);
743 t0
= newTemp(Ity_I64
);
744 t1
= newTemp(Ity_I64
);
745 t2
= newTemp(Ity_I32
);
746 t3
= newTemp(Ity_I1
);
747 t4
= newTemp(Ity_I1
);
748 t5
= newTemp(Ity_I1
);
749 t6
= newTemp(Ity_I1
);
750 t7
= newTemp(Ity_I32
);
751 t8
= newTemp(Ity_I64
);
752 t9
= newTemp(Ity_I64
);
753 t10
= newTemp(Ity_I1
);
754 t11
= newTemp(Ity_I1
);
755 t12
= newTemp(Ity_I1
);
756 t13
= newTemp(Ity_I1
);
757 t14
= newTemp(Ity_I32
);
759 assign(t0
, getAcc(ac
));
762 assign(t1
, mkexpr(t0
));
764 assign(t1
, binop(Iop_Sar64
, mkexpr(t0
), mkU8(rs
)));
767 /* Check if bits 63..31 of the result in t1 aren't 0. */
768 assign(t3
, binop(Iop_CmpNE32
,
772 assign(t4
, binop(Iop_CmpNE32
,
778 /* Check if bits 63..31 of the result in t1 aren't
780 assign(t5
, binop(Iop_CmpNE32
,
784 assign(t6
, binop(Iop_CmpNE32
,
790 /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP
792 assign(t7
, binop(Iop_And32
,
794 unop(Iop_1Sto32
, mkexpr(t3
)),
795 unop(Iop_1Sto32
, mkexpr(t4
))),
797 unop(Iop_1Sto32
, mkexpr(t5
)),
798 unop(Iop_1Sto32
, mkexpr(t6
)))));
799 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
807 /* If the last discarded bit is 1, there would be carry
808 when rounding, otherwise there wouldn't. We use that
809 fact and just add the value of the last discarded bit
810 to the least sifgnificant bit of the shifted value
813 assign(t8
, mkU64(0x0ULL
));
815 assign(t8
, binop(Iop_And64
,
822 assign(t9
, binop(Iop_Add64
, mkexpr(t1
), mkexpr(t8
)));
824 /* Repeat previous steps for the rounded value. */
825 assign(t10
, binop(Iop_CmpNE32
,
829 assign(t11
, binop(Iop_CmpNE32
,
836 assign(t12
, binop(Iop_CmpNE32
,
840 assign(t13
, binop(Iop_CmpNE32
,
847 assign(t14
, binop(Iop_And32
,
849 unop(Iop_1Sto32
, mkexpr(t10
)),
850 unop(Iop_1Sto32
, mkexpr(t11
))),
852 unop(Iop_1Sto32
, mkexpr(t12
)),
853 unop(Iop_1Sto32
, mkexpr(t13
)))));
854 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
863 putIReg(rt
, unop(Iop_64to32
, mkexpr(t0
)));
865 putIReg(rt
, unop(Iop_64to32
, mkexpr(t1
)));
871 case 0x1: { /* EXTRV.W */
872 DIP("extrv.w r%u, ac%u, r%u", rt
, ac
, rs
);
874 t0
= newTemp(Ity_I64
);
875 t1
= newTemp(Ity_I64
);
876 t2
= newTemp(Ity_I32
);
877 t3
= newTemp(Ity_I1
);
878 t4
= newTemp(Ity_I1
);
879 t5
= newTemp(Ity_I1
);
880 t6
= newTemp(Ity_I1
);
881 t7
= newTemp(Ity_I32
);
882 t8
= newTemp(Ity_I64
);
883 t9
= newTemp(Ity_I64
);
884 t10
= newTemp(Ity_I1
);
885 t11
= newTemp(Ity_I1
);
886 t12
= newTemp(Ity_I1
);
887 t13
= newTemp(Ity_I1
);
888 t14
= newTemp(Ity_I32
);
889 t15
= newTemp(Ity_I8
);
891 assign(t15
, unop(Iop_32to8
,
895 assign(t0
, getAcc(ac
));
896 assign(t1
, binop(Iop_Sar64
, mkexpr(t0
), mkexpr(t15
)));
897 putIReg(rt
, IRExpr_ITE(binop(Iop_CmpEQ32
,
901 unop(Iop_64to32
, mkexpr(t0
)),
902 unop(Iop_64to32
, mkexpr(t1
))));
904 /* Check if bits 63..31 of the result in t1 aren't 0. */
905 assign(t3
, binop(Iop_CmpNE32
,
909 assign(t4
, binop(Iop_CmpNE32
,
915 /* Check if bits 63..31 of the result in t1 aren't
917 assign(t5
, binop(Iop_CmpNE32
,
921 assign(t6
, binop(Iop_CmpNE32
,
927 /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP
929 assign(t7
, binop(Iop_And32
,
931 unop(Iop_1Sto32
, mkexpr(t3
)),
932 unop(Iop_1Sto32
, mkexpr(t4
))),
934 unop(Iop_1Sto32
, mkexpr(t5
)),
935 unop(Iop_1Sto32
, mkexpr(t6
)))));
936 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
944 /* If the last discarded bit is 1, there would be carry
945 when rounding, otherwise there wouldn't. We use that
946 fact and just add the value of the last discarded bit
947 to the least sifgnificant bit of the shifted value
950 IRExpr_ITE(binop(Iop_CmpEQ32
,
965 assign(t9
, binop(Iop_Add64
, mkexpr(t1
), mkexpr(t8
)));
967 /* Repeat previous steps for the rounded value. */
968 assign(t10
, binop(Iop_CmpNE32
,
972 assign(t11
, binop(Iop_CmpNE32
,
979 assign(t12
, binop(Iop_CmpNE32
,
983 assign(t13
, binop(Iop_CmpNE32
,
990 assign(t14
, binop(Iop_And32
,
992 unop(Iop_1Sto32
, mkexpr(t10
)),
993 unop(Iop_1Sto32
, mkexpr(t11
))),
995 unop(Iop_1Sto32
, mkexpr(t12
)),
996 unop(Iop_1Sto32
, mkexpr(t13
)))));
997 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
1007 case 0x2: { /* EXTP */
1008 DIP("extp r%u, ac%u, %u", rt
, ac
, rs
);
1010 t0
= newTemp(Ity_I64
);
1011 t1
= newTemp(Ity_I32
);
1012 t2
= newTemp(Ity_I1
);
1013 t3
= newTemp(Ity_I1
);
1014 t4
= newTemp(Ity_I8
);
1015 t5
= newTemp(Ity_I64
);
1016 t6
= newTemp(Ity_I64
);
1017 t7
= newTemp(Ity_I32
);
1019 assign(t0
, getAcc(ac
));
1020 /* Extract pos field of DSPControl register. */
1021 assign(t1
, binop(Iop_And32
, getDSPControl(), mkU32(0x3f)));
1023 /* Check if (pos - size) >= 0 [size <= pos]
1025 put 1 to EFI field of DSPControl register
1027 extract bits from acc and put 0 to EFI field of
1029 assign(t2
, binop(Iop_CmpLT32U
, mkexpr(t1
), mkU32(rs
)));
1031 putDSPControl(IRExpr_ITE(mkexpr(t2
),
1039 mkU32(0xffffbfff))));
1041 /* If pos <= 31, shift right the value from the acc
1042 (pos-size) times and take (size+1) bits from the least
1043 significant positions. Otherwise, shift left the value
1044 (63-pos) times, take (size+1) bits from the most
1045 significant positions and shift right (31-size) times.*/
1046 assign(t3
, binop(Iop_CmpLE32U
, mkexpr(t1
), mkU32(31)));
1049 IRExpr_ITE(mkexpr(t3
),
1052 mkexpr(t1
), mkU32(rs
))),
1055 mkU32(63), mkexpr(t1
)))));
1057 assign(t5
, IRExpr_ITE(mkexpr(t3
),
1059 mkexpr(t0
), mkexpr(t4
)),
1061 mkexpr(t0
), mkexpr(t4
))));
1063 /* t6 holds a mask for bit extraction */
1065 IRExpr_ITE(mkexpr(t3
),
1068 mkU64(0xffffffffffffffffULL
),
1072 mkU64(0xffffffffffffffffULL
),
1075 assign(t7
, IRExpr_ITE(mkexpr(t3
),
1087 putIReg(rt
, mkexpr(t7
));
1091 case 0x3: { /* EXTPV */
1092 DIP("extpv r%u, ac%u, r%u", rt
, ac
, rs
);
1094 t0
= newTemp(Ity_I64
);
1095 t1
= newTemp(Ity_I32
);
1096 t2
= newTemp(Ity_I1
);
1097 t3
= newTemp(Ity_I1
);
1098 t4
= newTemp(Ity_I8
);
1099 t5
= newTemp(Ity_I64
);
1100 t6
= newTemp(Ity_I64
);
1101 t7
= newTemp(Ity_I32
);
1102 t8
= newTemp(Ity_I32
);
1104 assign(t8
, binop(Iop_And32
, getIReg(rs
), mkU32(0x1f)));
1105 assign(t0
, getAcc(ac
));
1106 /* Extract pos field of DSPControl register. */
1107 assign(t1
, binop(Iop_And32
, getDSPControl(), mkU32(0x3f)));
1109 /* Check if (pos - size) >= 0 [size <= pos]
1111 put 1 to EFI field of DSPControl register
1113 extract bits from acc and put 0 to EFI field of
1115 assign(t2
, binop(Iop_CmpLT32U
, mkexpr(t1
), mkexpr(t8
)));
1117 putDSPControl(IRExpr_ITE(mkexpr(t2
),
1125 mkU32(0xffffbfff))));
1127 /* If pos <= 31, shift right the value from the acc
1128 (pos-size) times and take (size+1) bits from the least
1129 significant positions. Otherwise, shift left the value
1130 (63-pos) times, take (size+1) bits from the most
1131 significant positions and shift right (31-size)
1133 assign(t3
, binop(Iop_CmpLE32U
, mkexpr(t1
), mkU32(31)));
1136 IRExpr_ITE(mkexpr(t3
),
1139 mkexpr(t1
), mkexpr(t8
))),
1142 mkU32(63), mkexpr(t1
)))));
1144 assign(t5
, IRExpr_ITE(mkexpr(t3
),
1146 mkexpr(t0
), mkexpr(t4
)),
1148 mkexpr(t0
), mkexpr(t4
))));
1150 /* t6 holds a mask for bit extraction. */
1152 IRExpr_ITE(mkexpr(t3
),
1155 mkU64(0xffffffffffffffffULL
),
1162 mkU64(0xffffffffffffffffULL
),
1168 assign(t7
, IRExpr_ITE(mkexpr(t3
),
1183 putIReg(rt
, mkexpr(t7
));
1187 case 0x4: { /* EXTR_R.W */
1188 DIP("extr_r.w r%u, ac%u, %u", rt
, ac
, rs
);
1190 t0
= newTemp(Ity_I64
);
1191 t1
= newTemp(Ity_I64
);
1192 t2
= newTemp(Ity_I32
);
1193 t3
= newTemp(Ity_I1
);
1194 t4
= newTemp(Ity_I1
);
1195 t5
= newTemp(Ity_I1
);
1196 t6
= newTemp(Ity_I1
);
1197 t7
= newTemp(Ity_I32
);
1198 t8
= newTemp(Ity_I64
);
1199 t9
= newTemp(Ity_I64
);
1200 t10
= newTemp(Ity_I1
);
1201 t11
= newTemp(Ity_I1
);
1202 t12
= newTemp(Ity_I1
);
1203 t13
= newTemp(Ity_I1
);
1204 t14
= newTemp(Ity_I32
);
1205 t15
= newTemp(Ity_I64
);
1206 t16
= newTemp(Ity_I1
);
1208 assign(t0
, getAcc(ac
));
1209 assign(t16
, binop(Iop_CmpEQ32
,
1212 assign(t1
, IRExpr_ITE(mkexpr(t16
),
1217 /* If the last discarded bit is 1, there would be carry
1218 when rounding, otherwise there wouldn't. We use that
1219 fact and just add the value of the last discarded bit
1220 to the least significant bit of the shifted value
1222 assign(t15
, binop(Iop_Shr64
,
1232 IRExpr_ITE(mkexpr(t16
),
1236 mkU64(0x0000000000000001ULL
))));
1237 assign(t9
, binop(Iop_Add64
, mkexpr(t1
), mkexpr(t8
)));
1238 putIReg(rt
, unop(Iop_64to32
, mkexpr(t9
)));
1240 /* Check if bits 63..31 of the result in t1 aren't 0. */
1241 assign(t3
, binop(Iop_CmpNE32
,
1245 assign(t4
, binop(Iop_CmpNE32
,
1252 /* Check if bits 63..31 of the result in t1 aren't
1254 assign(t5
, binop(Iop_CmpNE32
,
1257 mkU32(0xffffffff)));
1258 assign(t6
, binop(Iop_CmpNE32
,
1263 mkU32(0x80000000)));
1264 /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP
1265 control register. */
1266 assign(t7
, binop(Iop_And32
,
1268 unop(Iop_1Sto32
, mkexpr(t3
)),
1269 unop(Iop_1Sto32
, mkexpr(t4
))),
1271 unop(Iop_1Sto32
, mkexpr(t5
)),
1272 unop(Iop_1Sto32
, mkexpr(t6
)))));
1273 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
1281 /* Repeat previous steps for the rounded value. */
1282 assign(t10
, binop(Iop_CmpNE32
,
1286 assign(t11
, binop(Iop_CmpNE32
,
1293 assign(t12
, binop(Iop_CmpNE32
,
1296 mkU32(0xffffffff)));
1297 assign(t13
, binop(Iop_CmpNE32
,
1302 mkU32(0x80000000)));
1304 assign(t14
, binop(Iop_And32
,
1306 unop(Iop_1Sto32
, mkexpr(t10
)),
1307 unop(Iop_1Sto32
, mkexpr(t11
))),
1309 unop(Iop_1Sto32
, mkexpr(t12
)),
1310 unop(Iop_1Sto32
, mkexpr(t13
)))));
1311 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
1321 case 0x5: { /* EXTRV_R.W */
1322 DIP("extrv_r.w r%u, ac%u, r%u", rt
, ac
, rs
);
1324 t0
= newTemp(Ity_I64
);
1325 t1
= newTemp(Ity_I64
);
1326 t2
= newTemp(Ity_I32
);
1327 t3
= newTemp(Ity_I1
);
1328 t4
= newTemp(Ity_I1
);
1329 t5
= newTemp(Ity_I1
);
1330 t6
= newTemp(Ity_I1
);
1331 t7
= newTemp(Ity_I32
);
1332 t8
= newTemp(Ity_I64
);
1333 t9
= newTemp(Ity_I64
);
1334 t10
= newTemp(Ity_I1
);
1335 t11
= newTemp(Ity_I1
);
1336 t12
= newTemp(Ity_I1
);
1337 t13
= newTemp(Ity_I1
);
1338 t14
= newTemp(Ity_I32
);
1339 t15
= newTemp(Ity_I8
);
1341 assign(t15
, unop(Iop_32to8
,
1345 assign(t0
, getAcc(ac
));
1346 assign(t1
, binop(Iop_Sar64
, mkexpr(t0
), mkexpr(t15
)));
1348 /* Check if bits 63..31 of the result in t1 aren't 0. */
1349 assign(t3
, binop(Iop_CmpNE32
,
1353 assign(t4
, binop(Iop_CmpNE32
,
1359 /* Check if bits 63..31 of the result in t1 aren't
1361 assign(t5
, binop(Iop_CmpNE32
,
1364 mkU32(0xffffffff)));
1365 assign(t6
, binop(Iop_CmpNE32
,
1370 mkU32(0x80000000)));
1371 /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP
1372 control register. */
1373 assign(t7
, binop(Iop_And32
,
1375 unop(Iop_1Sto32
, mkexpr(t3
)),
1376 unop(Iop_1Sto32
, mkexpr(t4
))),
1378 unop(Iop_1Sto32
, mkexpr(t5
)),
1379 unop(Iop_1Sto32
, mkexpr(t6
)))));
1380 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
1388 /* If the last discarded bit is 1, there would be carry
1389 when rounding, otherwise there wouldn't. We use that
1390 fact and just add the value of the last discarded bit
1391 to the least sifgnificant bit of the shifted value
1394 IRExpr_ITE(binop(Iop_CmpEQ32
,
1409 assign(t9
, binop(Iop_Add64
, mkexpr(t1
), mkexpr(t8
)));
1410 /* Put rounded value in destination register. */
1411 putIReg(rt
, unop(Iop_64to32
, mkexpr(t9
)));
1413 /* Repeat previous steps for the rounded value. */
1414 assign(t10
, binop(Iop_CmpNE32
,
1418 assign(t11
, binop(Iop_CmpNE32
,
1425 assign(t12
, binop(Iop_CmpNE32
,
1428 mkU32(0xffffffff)));
1429 assign(t13
, binop(Iop_CmpNE32
,
1434 mkU32(0x80000000)));
1436 assign(t14
, binop(Iop_And32
,
1438 unop(Iop_1Sto32
, mkexpr(t10
)),
1439 unop(Iop_1Sto32
, mkexpr(t11
))),
1441 unop(Iop_1Sto32
, mkexpr(t12
)),
1442 unop(Iop_1Sto32
, mkexpr(t13
)))));
1443 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
1453 case 0x6: { /* EXTR_RS.W */
1454 DIP("extr_rs.w r%u, ac%u, %u", rt
, ac
, rs
);
1456 t0
= newTemp(Ity_I64
);
1457 t1
= newTemp(Ity_I64
);
1458 t2
= newTemp(Ity_I32
);
1459 t3
= newTemp(Ity_I1
);
1460 t4
= newTemp(Ity_I1
);
1461 t5
= newTemp(Ity_I1
);
1462 t6
= newTemp(Ity_I1
);
1463 t7
= newTemp(Ity_I32
);
1464 t8
= newTemp(Ity_I64
);
1465 t9
= newTemp(Ity_I64
);
1466 t10
= newTemp(Ity_I1
);
1467 t11
= newTemp(Ity_I1
);
1468 t12
= newTemp(Ity_I1
);
1469 t13
= newTemp(Ity_I1
);
1470 t14
= newTemp(Ity_I32
);
1471 t16
= newTemp(Ity_I32
);
1473 assign(t0
, getAcc(ac
));
1476 assign(t1
, mkexpr(t0
));
1478 assign(t1
, binop(Iop_Sar64
, mkexpr(t0
), mkU8(rs
)));
1481 /* Check if bits 63..31 of the result in t1 aren't 0. */
1482 assign(t3
, binop(Iop_CmpNE32
,
1486 assign(t4
, binop(Iop_CmpNE32
,
1492 /* Check if bits 63..31 of the result in t1 aren't
1494 assign(t5
, binop(Iop_CmpNE32
,
1497 mkU32(0xffffffff)));
1498 assign(t6
, binop(Iop_CmpNE32
,
1503 mkU32(0x80000000)));
1504 /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP
1505 control register. */
1506 assign(t7
, binop(Iop_And32
,
1508 unop(Iop_1Sto32
, mkexpr(t3
)),
1509 unop(Iop_1Sto32
, mkexpr(t4
))),
1511 unop(Iop_1Sto32
, mkexpr(t5
)),
1512 unop(Iop_1Sto32
, mkexpr(t6
)))));
1513 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
1521 /* If the last discarded bit is 1, there would be carry
1522 when rounding, otherwise there wouldn't. We use that
1523 fact and just add the value of the last discarded bit
1524 to the least sifgnificant bit of the shifted value
1527 assign(t8
, mkU64(0x0ULL
));
1529 assign(t8
, binop(Iop_And64
,
1536 assign(t9
, binop(Iop_Add64
, mkexpr(t1
), mkexpr(t8
)));
1538 /* Repeat previous steps for the rounded value. */
1539 assign(t10
, binop(Iop_CmpNE32
,
1543 assign(t11
, binop(Iop_CmpNE32
,
1550 assign(t12
, binop(Iop_CmpNE32
,
1553 mkU32(0xffffffff)));
1554 assign(t13
, binop(Iop_CmpNE32
,
1559 mkU32(0x80000000)));
1561 assign(t14
, binop(Iop_And32
,
1563 unop(Iop_1Sto32
, mkexpr(t10
)),
1564 unop(Iop_1Sto32
, mkexpr(t11
))),
1566 unop(Iop_1Sto32
, mkexpr(t12
)),
1567 unop(Iop_1Sto32
, mkexpr(t13
)))));
1568 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
1576 assign(t16
, binop(Iop_And32
,
1579 mkU32(0x80000000)));
1580 putIReg(rt
, IRExpr_ITE(binop(Iop_CmpNE32
,
1583 IRExpr_ITE(binop(Iop_CmpEQ32
,
1588 unop(Iop_64to32
, mkexpr(t9
))));
1592 case 0x7: { /* EXTRV_RS.W */
1593 DIP("extrv_rs.w r%u, ac%u, r%u", rt
, ac
, rs
);
1595 t0
= newTemp(Ity_I64
);
1596 t1
= newTemp(Ity_I64
);
1597 t2
= newTemp(Ity_I32
);
1598 t3
= newTemp(Ity_I1
);
1599 t4
= newTemp(Ity_I1
);
1600 t5
= newTemp(Ity_I1
);
1601 t6
= newTemp(Ity_I1
);
1602 t7
= newTemp(Ity_I32
);
1603 t8
= newTemp(Ity_I64
);
1604 t9
= newTemp(Ity_I64
);
1605 t10
= newTemp(Ity_I1
);
1606 t11
= newTemp(Ity_I1
);
1607 t12
= newTemp(Ity_I1
);
1608 t13
= newTemp(Ity_I1
);
1609 t14
= newTemp(Ity_I32
);
1610 t15
= newTemp(Ity_I32
);
1611 t16
= newTemp(Ity_I32
);
1612 t17
= newTemp(Ity_I1
);
1614 assign(t15
, binop(Iop_And32
,
1617 assign(t17
, binop(Iop_CmpEQ32
,
1620 assign(t0
, getAcc(ac
));
1621 assign(t1
, IRExpr_ITE(mkexpr(t17
),
1628 /* Check if bits 63..31 of the result in t1 aren't 0. */
1629 assign(t3
, binop(Iop_CmpNE32
,
1633 assign(t4
, binop(Iop_CmpNE32
,
1639 /* Check if bits 63..31 of the result in t1 aren't
1641 assign(t5
, binop(Iop_CmpNE32
,
1644 mkU32(0xffffffff)));
1645 assign(t6
, binop(Iop_CmpNE32
,
1650 mkU32(0x80000000)));
1651 /* If bits 63..31 aren't 0 nor 0x1ffffffff, set DSP
1652 control register. */
1653 assign(t7
, binop(Iop_And32
,
1655 unop(Iop_1Sto32
, mkexpr(t3
)),
1656 unop(Iop_1Sto32
, mkexpr(t4
))),
1658 unop(Iop_1Sto32
, mkexpr(t5
)),
1659 unop(Iop_1Sto32
, mkexpr(t6
)))));
1660 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
1668 /* If the last discarded bit is 1, there would be carry
1669 when rounding, otherwise there wouldn't. We use that
1670 fact and just add the value of the last discarded bit
1671 to the least sifgnificant bit of the shifted value
1674 IRExpr_ITE(mkexpr(t17
),
1685 assign(t9
, binop(Iop_Add64
, mkexpr(t1
), mkexpr(t8
)));
1687 /* Repeat previous steps for the rounded value. */
1688 assign(t10
, binop(Iop_CmpNE32
,
1692 assign(t11
, binop(Iop_CmpNE32
,
1699 assign(t12
, binop(Iop_CmpNE32
,
1702 mkU32(0xffffffff)));
1703 assign(t13
, binop(Iop_CmpNE32
,
1708 mkU32(0x80000000)));
1710 assign(t14
, binop(Iop_And32
,
1712 unop(Iop_1Sto32
, mkexpr(t10
)),
1713 unop(Iop_1Sto32
, mkexpr(t11
))),
1715 unop(Iop_1Sto32
, mkexpr(t12
)),
1716 unop(Iop_1Sto32
, mkexpr(t13
)))));
1717 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
1725 assign(t16
, binop(Iop_And32
,
1728 mkU32(0x80000000)));
1729 putIReg(rt
, IRExpr_ITE(binop(Iop_CmpNE32
,
1732 IRExpr_ITE(binop(Iop_CmpEQ32
,
1737 unop(Iop_64to32
, mkexpr(t9
))));
1741 case 0xA: { /* EXTPDP */
1742 DIP("extpdp r%u, ac%u, %u", rt
, ac
, rs
);
1744 t0
= newTemp(Ity_I64
);
1745 t1
= newTemp(Ity_I32
);
1746 t2
= newTemp(Ity_I1
);
1747 t3
= newTemp(Ity_I1
);
1748 t4
= newTemp(Ity_I8
);
1749 t5
= newTemp(Ity_I64
);
1750 t6
= newTemp(Ity_I64
);
1751 t7
= newTemp(Ity_I32
);
1752 t8
= newTemp(Ity_I32
);
1754 assign(t0
, getAcc(ac
));
1755 /* Extract pos field of DSPControl register. */
1756 assign(t1
, binop(Iop_And32
, getDSPControl(), mkU32(0x3f)));
1758 /* Check if (pos - size) >= 0 [size <= pos]
1760 put 1 to EFI field of DSPControl register
1762 extract bits from acc and put 0 to EFI field of
1764 assign(t2
, binop(Iop_CmpLT32U
, mkexpr(t1
), mkU32(rs
)));
1766 assign(t8
, binop(Iop_Or32
,
1777 putDSPControl(IRExpr_ITE(mkexpr(t2
),
1785 /* If pos <= 31, shift right the value from the acc
1786 (pos-size) times and take (size+1) bits from the least
1787 significant positions. Otherwise, shift left the value
1788 (63-pos) times, take (size+1) bits from the most
1789 significant positions and shift right (31-size) times.
1791 assign(t3
, binop(Iop_CmpLE32U
, mkexpr(t1
), mkU32(31)));
1794 IRExpr_ITE(mkexpr(t3
),
1797 mkexpr(t1
), mkU32(rs
))),
1800 mkU32(63), mkexpr(t1
)))));
1802 assign(t5
, IRExpr_ITE(mkexpr(t3
),
1804 mkexpr(t0
), mkexpr(t4
)),
1806 mkexpr(t0
), mkexpr(t4
))));
1808 /* t6 holds a mask for bit extraction. */
1810 IRExpr_ITE(mkexpr(t3
),
1813 mkU64(0xffffffffffffffffULL
),
1817 mkU64(0xffffffffffffffffULL
),
1820 assign(t7
, IRExpr_ITE(mkexpr(t3
),
1832 putIReg(rt
, mkexpr(t7
));
1836 case 0xB: { /* EXTPDPV */
1837 DIP("extpdpv r%u, ac%u, r%u", rt
, ac
, rs
);
1839 t0
= newTemp(Ity_I64
);
1840 t1
= newTemp(Ity_I32
);
1841 t2
= newTemp(Ity_I1
);
1842 t3
= newTemp(Ity_I1
);
1843 t4
= newTemp(Ity_I8
);
1844 t5
= newTemp(Ity_I64
);
1845 t6
= newTemp(Ity_I64
);
1846 t7
= newTemp(Ity_I32
);
1847 t8
= newTemp(Ity_I32
);
1848 t9
= newTemp(Ity_I32
);
1850 assign(t8
, binop(Iop_And32
, getIReg(rs
), mkU32(0x1f)));
1851 assign(t0
, getAcc(ac
));
1852 /* Extract pos field of DSPControl register. */
1853 assign(t1
, binop(Iop_And32
, getDSPControl(), mkU32(0x3f)));
1855 /* Check if (pos - size) >= 0 [size <= pos]
1857 put 1 to EFI field of DSPControl register
1859 extract bits from acc and put 0 to EFI field of
1861 assign(t2
, binop(Iop_CmpLT32U
, mkexpr(t1
), mkexpr(t8
)));
1863 assign(t9
, binop(Iop_Or32
,
1876 putDSPControl(IRExpr_ITE(mkexpr(t2
),
1884 /* If pos <= 31, shift right the value from the acc
1885 (pos-size) times and take (size+1) bits from the least
1886 significant positions. Otherwise, shift left the value
1887 (63-pos) times, take (size+1) bits from the most
1888 significant positions and shift right (31-size) times.
1890 assign(t3
, binop(Iop_CmpLE32U
, mkexpr(t1
), mkU32(31)));
1893 IRExpr_ITE(mkexpr(t3
),
1896 mkexpr(t1
), mkexpr(t8
))),
1899 mkU32(63), mkexpr(t1
)))));
1901 assign(t5
, IRExpr_ITE(mkexpr(t3
),
1903 mkexpr(t0
), mkexpr(t4
)),
1905 mkexpr(t0
), mkexpr(t4
))));
1907 /* t6 holds a mask for bit extraction. */
1909 IRExpr_ITE(mkexpr(t3
),
1912 mkU64(0xffffffffffffffffULL
),
1919 mkU64(0xffffffffffffffffULL
),
1925 assign(t7
, IRExpr_ITE(mkexpr(t3
),
1940 putIReg(rt
, mkexpr(t7
));
1944 case 0xE: { /* EXTR_S.H */
1945 DIP("extr_s.h r%u, ac%u, %u", rt
, ac
, rs
);
1947 t0
= newTemp(Ity_I64
);
1948 t1
= newTemp(Ity_I64
);
1949 t2
= newTemp(Ity_I32
);
1950 t3
= newTemp(Ity_I64
);
1951 t4
= newTemp(Ity_I32
);
1952 t5
= newTemp(Ity_I32
);
1953 t6
= newTemp(Ity_I64
);
1954 t7
= newTemp(Ity_I32
);
1956 assign(t0
, getAcc(ac
));
1958 assign(t1
, binop(Iop_Sar64
, mkexpr(t0
), mkU8(rs
)));
1960 assign(t2
, binop(Iop_Or32
,
1961 getDSPControl(), mkU32(0x00800000)));
1963 assign(t5
, binop(Iop_And32
,
1966 mkU32(0x80000000)));
1967 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
1972 mkU32(0x80000000))),
1976 /* Check if t1 > 0x7fff ((t1 - 0x7fff) > 0)
1977 1. subtract 0x7fff from t1
1978 2. if the resulting number is positive (sign bit = 0)
1979 and any of the other bits is 1, the value is > 0. */
1980 assign(t3
, binop(Iop_Sub64
,
1982 mkU64(0x0000000000007fffULL
)));
1983 assign(t4
, binop(Iop_And32
,
1991 mkU32(0x7fffffff)))),
2004 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
2011 /* Check if t1<0xffffffffffff8000 (0xffffffffffff8000-t1)>0
2012 1. subtract t1 from 0xffffffffffff8000
2013 2. if the resulting number is positive (sign bit = 0)
2014 and any of the other bits is 1, the value is > 0 */
2015 assign(t6
, binop(Iop_Sub64
,
2016 mkU64(0xffffffffffff8000ULL
),
2018 assign(t7
, binop(Iop_And32
,
2026 mkU32(0x7fffffff)))),
2039 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
2046 putIReg(rt
, IRExpr_ITE(binop(Iop_CmpNE32
,
2050 IRExpr_ITE(binop(Iop_CmpNE32
,
2059 case 0xF: { /* EXTRV_S.H */
2060 DIP("extrv_s.h r%u, ac%u, %u", rt
, ac
, rs
);
2062 t0
= newTemp(Ity_I64
);
2063 t1
= newTemp(Ity_I64
);
2064 t2
= newTemp(Ity_I32
);
2065 t3
= newTemp(Ity_I64
);
2066 t4
= newTemp(Ity_I32
);
2067 t5
= newTemp(Ity_I32
);
2068 t6
= newTemp(Ity_I64
);
2069 t7
= newTemp(Ity_I32
);
2071 assign(t0
, getAcc(ac
));
2073 assign(t1
, binop(Iop_Sar64
,
2080 assign(t2
, binop(Iop_Or32
,
2081 getDSPControl(), mkU32(0x00800000)));
2083 assign(t5
, binop(Iop_And32
,
2086 mkU32(0x80000000)));
2087 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
2092 mkU32(0x80000000))),
2096 /* Check if t1 > 0x7fff ((t1 - 0x7fff) > 0)
2097 1. subtract 0x7fff from t1
2098 2. if the resulting number is positive (sign bit = 0)
2099 and any of the other bits is 1, the value is > 0. */
2100 assign(t3
, binop(Iop_Sub64
,
2102 mkU64(0x0000000000007fffULL
)));
2103 assign(t4
, binop(Iop_And32
,
2111 mkU32(0x7fffffff)))),
2124 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
2131 /* Check if t1<0xffffffffffff8000 (0xffffffffffff8000-t1)>0
2132 1. subtract t1 from 0xffffffffffff8000
2133 2. if the resulting number is positive (sign bit = 0)
2134 and any of the other bits is 1, the value is > 0 */
2135 assign(t6
, binop(Iop_Sub64
,
2136 mkU64(0xffffffffffff8000ULL
),
2138 assign(t7
, binop(Iop_And32
,
2146 mkU32(0x7fffffff)))),
2159 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
2166 putIReg(rt
, IRExpr_ITE(binop(Iop_CmpNE32
,
2170 IRExpr_ITE(binop(Iop_CmpNE32
,
2179 case 0x12: { /* RDDSP*/
2180 DIP("rddsp r%u, mask 0x%x", rd
, rddsp_mask
);
2183 putIReg(rd
, mkU32(0x0));
2185 if ((rddsp_mask
& 0x1) == 0x1) {
2186 /* Read pos field (bits 5-0) of DSPControl register. */
2187 putIReg(rd
, binop(Iop_Or32
,
2191 mkU32(0x0000003F))));
2194 if ((rddsp_mask
& 0x2) == 0x2) {
2195 /* Read scount field (bits 12-7) of DSPControl
2197 putIReg(rd
, binop(Iop_Or32
,
2201 mkU32(0x00001F80))));
2204 if ((rddsp_mask
& 0x4) == 0x4) {
2205 /* Read C field (bit 13) of DSPControl register. */
2206 putIReg(rd
, binop(Iop_Or32
,
2210 mkU32(0x00002000))));
2213 if ((rddsp_mask
& 0x8) == 0x8) {
2214 /* Read outflag field (bit s 23-16) of DSPControl
2216 putIReg(rd
, binop(Iop_Or32
,
2220 mkU32(0x00FF0000))));
2223 if ((rddsp_mask
& 0x10) == 0x10) {
2224 /* Read ccond field (bits 31-24) of DSPControl
2226 putIReg(rd
, binop(Iop_Or32
,
2230 mkU32(0xFF000000))));
2233 if ((rddsp_mask
& 0x20) == 0x20) {
2234 /* Read EFI field (bit 14) of DSPControl register. */
2235 putIReg(rd
, binop(Iop_Or32
,
2239 mkU32(0x00004000))));
2242 if ((rddsp_mask
& 0x3f) == 0x3f) {
2243 /* Read all fields of DSPControl register. */
2244 putIReg(rd
, getDSPControl());
2250 case 0x13: { /* WRDSP */
2251 DIP("wrdsp r%u, mask 0x%x", rs
, wrdsp_mask
);
2254 if ((wrdsp_mask
& 0x3f) == 0x3f) {
2255 /* If mips64 put all fields of rs, except bit 15 and bit
2256 6, to DSPControl register, otherwise put all except
2257 bits 15, 6 and bits 31..28. */
2258 putDSPControl(mode64
?
2261 mkU32(0xffff7fbf)) :
2264 mkU32(0x0fff7fbf)));
2266 if ((wrdsp_mask
& 0x1) == 0x1) {
2267 /* Put bits 5-0 of rs to DSPControl register pos
2269 putDSPControl(binop(Iop_Or32
,
2275 mkU32(0x0000003F))));
2278 if ((wrdsp_mask
& 0x2) == 0x2) {
2279 /* Put bits 12-7 of rs to DSPControl scount field. */
2280 putDSPControl(binop(Iop_Or32
,
2286 mkU32(0x00001F80))));
2289 if ((wrdsp_mask
& 0x4) == 0x4) {
2290 /* Put bit 13 of rs to DSPControl register C
2292 putDSPControl(binop(Iop_Or32
,
2298 mkU32(0x00002000))));
2301 if ((wrdsp_mask
& 0x8) == 0x8) {
2302 /* Put bits 23-16 of rs to DSPControl reg outflag
2304 putDSPControl(binop(Iop_Or32
,
2310 mkU32(0x00FF0000))));
2313 if ((wrdsp_mask
& 0x10) == 0x10) {
2314 /* Put bits 31-24 of rs to DSPControl reg ccond
2316 putDSPControl(binop(Iop_Or32
,
2322 mode64
? mkU32(0xFF000000)
2323 : mkU32(0x0F000000))
2328 if ((wrdsp_mask
& 0x20) == 0x20) {
2329 /* Put bit 14 of rs to DSPControl register EFI
2331 putDSPControl(binop(Iop_Or32
,
2337 mkU32(0x00004000))));
2344 case 0x1A: { /* SHILO */
2345 DIP("shilo ac%u, %u", ac
, shift
);
2347 t0
= newTemp(Ity_I64
);
2348 t1
= newTemp(Ity_I64
);
2350 assign(t0
, getAcc(ac
));
2352 putAcc(ac
, mkexpr(t0
));
2354 if (0x20 == (shift
& 0x3f)) {
2355 putAcc(ac
, binop(Iop_32HLto64
,
2356 unop(Iop_64to32
, mkexpr(t0
)),
2358 } else if (0x20 == (shift
& 0x20)) {
2359 assign(t1
, binop(Iop_Shl64
,
2367 putAcc(ac
, mkexpr(t1
));
2369 assign(t1
, binop(Iop_Shr64
, mkexpr(t0
), mkU8(shift
)));
2371 putAcc(ac
, mkexpr(t1
));
2377 case 0x1B: { /* SHILOV */
2378 DIP("shilov ac%u, r%u", ac
, rs
);
2380 t0
= newTemp(Ity_I64
);
2381 t1
= newTemp(Ity_I32
);
2382 t2
= newTemp(Ity_I1
);
2383 t3
= newTemp(Ity_I64
);
2384 t4
= newTemp(Ity_I64
);
2386 assign(t0
, getAcc(ac
));
2387 assign(t1
, binop(Iop_And32
, getIReg(rs
), mkU32(0x3f)));
2388 assign(t2
, binop(Iop_CmpEQ32
, mkexpr(t1
), mkU32(0x20)));
2389 assign(t3
, binop(Iop_Shl64
,
2396 assign(t4
, binop(Iop_Shr64
,
2402 IRExpr_ITE(mkexpr(t2
),
2404 unop(Iop_64to32
, mkexpr(t0
)),
2406 IRExpr_ITE(binop(Iop_CmpEQ32
,
2416 case 0x1F: { /* MTHLIP */
2417 DIP("mthlip r%u, ac%u", rs
, ac
);
2419 t0
= newTemp(Ity_I64
);
2420 t1
= newTemp(Ity_I32
);
2422 assign(t0
, getAcc(ac
));
2423 putAcc(ac
, binop(Iop_32HLto64
,
2424 unop(Iop_64to32
, mkexpr(t0
)),
2426 assign(t1
, binop(Iop_And32
, getDSPControl(), mkU32(0x3f)));
2427 putDSPControl(IRExpr_ITE(binop(Iop_CmpLE32U
,
2436 mkU32(0xffffffc0))),
2443 mkU32(0xffffffc0)))));
2454 static UInt
disDSPInstr_MIPS_WRK_Special3_LX( UInt cins
)
2457 UInt rs
, rt
, rd
, sa
;
2465 case 0x0: { /* LWX */
2466 DIP("lwx r%u, r%u(r%u)", rd
, rt
, rs
);
2468 t0
= newTemp(Ity_I32
);
2470 assign(t0
, binop(Iop_Add32
, getIReg(rt
), getIReg(rs
)));
2472 putIReg(rd
, load(Ity_I32
, mkexpr(t0
)));
2476 case 0x4: { /* LHX */
2477 DIP("lhx r%u, r%u(r%u)", rd
, rt
, rs
);
2479 t0
= newTemp(Ity_I32
);
2481 assign(t0
, binop(Iop_Add32
, getIReg(rt
), getIReg(rs
)));
2483 putIReg(rd
, unop(Iop_16Sto32
, load(Ity_I16
, mkexpr(t0
))));
2487 case 0x6: { /* LBUX */
2488 DIP("lbux r%u, r%u(r%u)", rd
, rt
, rs
);
2490 t0
= newTemp(Ity_I32
);
2492 assign(t0
, binop(Iop_Add32
, getIReg(rt
), getIReg(rs
)));
2494 putIReg(rd
, unop(Iop_8Uto32
, load(Ity_I8
, mkexpr(t0
))));
2505 static UInt
disDSPInstr_MIPS_WRK_Special3_INSV( UInt cins
)
2507 IRTemp t0
, t1
= 0, t2
, t3
, t6
, t7
, t8
;
2515 case 0x0: { /* INSV */
2516 DIP("insv r%u, r%u", rt
, rs
);
2519 t0
= newTemp(Ity_I32
);
2520 t1
= newTemp(Ity_I32
);
2521 t2
= newTemp(Ity_I8
);
2522 t3
= newTemp(Ity_I8
);
2523 t6
= newTemp(Ity_I32
);
2524 t7
= newTemp(Ity_I32
);
2525 t8
= newTemp(Ity_I32
);
2527 /* t0 <- pos field of DSPControl register. */
2528 assign(t0
, binop(Iop_And32
, getDSPControl(), mkU32(0x3f)));
2529 /* t1 <- scount field of DSPControl register. */
2530 assign(t1
, binop(Iop_Shr32
,
2536 assign(t2
, unop(Iop_32to8
,
2541 /* 32-(pos+size) most significant bits of rt. */
2542 assign(t6
, binop(Iop_Shl32
,
2548 assign(t3
, unop(Iop_32to8
,
2552 /* Pos least significant bits of rt. */
2553 assign(t7
, binop(Iop_Shr32
,
2559 /* Size least significant bits of rs,
2560 shifted to appropriate position. */
2561 assign(t8
, binop(Iop_Shl32
,
2572 putIReg(rt
, IRExpr_ITE(binop(Iop_CmpEQ32
,
2575 IRExpr_ITE(binop(Iop_CmpEQ32
,
2582 IRExpr_ITE(binop(Iop_CmpEQ32
,
2604 static UInt
disDSPInstr_MIPS_WRK_Special3_ADDU_QB( UInt cins
)
2606 IRTemp t0
, t1
= 0, t2
, t3
, t4
, t5
, t6
, t7
, t8
, t9
, t10
, t11
, t12
;
2607 UInt rs
, rt
, rd
, sa
;
2615 case 0x00: { /* ADDU.QB */
2616 DIP("addu.qb r%u, r%u, r%u", rd
, rs
, rt
);
2618 t0
= newTemp(Ity_I32
);
2619 t1
= newTemp(Ity_I1
);
2620 t2
= newTemp(Ity_I32
);
2621 t3
= newTemp(Ity_I1
);
2622 t4
= newTemp(Ity_I32
);
2623 t5
= newTemp(Ity_I1
);
2624 t6
= newTemp(Ity_I32
);
2625 t7
= newTemp(Ity_I1
);
2626 t8
= newTemp(Ity_I32
);
2628 /* Add rightmost bytes of rs and rt. */
2633 unop(Iop_32to16
, getIReg(rs
)))),
2636 unop(Iop_32to16
, getIReg(rt
))))));
2637 /* t1 will be 1 if there is overflow, 0 otherwise. */
2638 assign(t1
, binop(Iop_CmpEQ32
,
2642 mkU32(0x00000100)));
2644 /* Add bits 15-8 of rs and rt. */
2649 unop(Iop_32to16
, getIReg(rs
)))),
2652 unop(Iop_32to16
, getIReg(rt
))))));
2653 /* t3 will be 1 if there is overflow, 0 otherwise. */
2654 assign(t3
, binop(Iop_CmpEQ32
,
2658 mkU32(0x00000100)));
2660 /* Add bits 15-8 of rs and rt. */
2665 unop(Iop_32HIto16
, getIReg(rs
)))),
2668 unop(Iop_32HIto16
, getIReg(rt
))))));
2669 /* t5 will be 1 if there is overflow, 0 otherwise. */
2670 assign(t5
, binop(Iop_CmpEQ32
,
2674 mkU32(0x00000100)));
2676 /* Add bits 15-8 of rs and rt. */
2681 unop(Iop_32HIto16
, getIReg(rs
)))),
2684 unop(Iop_32HIto16
, getIReg(rt
))))));
2685 /* t7 will be 1 if there is overflow, 0 otherwise. */
2686 assign(t7
, binop(Iop_CmpEQ32
,
2690 mkU32(0x00000100)));
2696 unop(Iop_1Sto32
, mkexpr(t7
)),
2697 unop(Iop_1Sto32
, mkexpr(t5
))),
2698 unop(Iop_1Sto32
, mkexpr(t3
))),
2699 unop(Iop_1Sto32
, mkexpr(t1
))));
2701 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
2707 mkU32(0x00100000))));
2709 putIReg(rd
, binop(Iop_16HLto32
,
2711 unop(Iop_32to8
, mkexpr(t6
)),
2712 unop(Iop_32to8
, mkexpr(t4
))),
2714 unop(Iop_32to8
, mkexpr(t2
)),
2715 unop(Iop_32to8
, mkexpr(t0
)))));
2719 case 0x1: { /* SUBU.QB */
2720 DIP("subu.qb r%u, r%u, r%u", rd
, rs
, rt
);
2722 t0
= newTemp(Ity_I32
);
2723 t1
= newTemp(Ity_I1
);
2724 t2
= newTemp(Ity_I32
);
2725 t3
= newTemp(Ity_I1
);
2726 t4
= newTemp(Ity_I32
);
2727 t5
= newTemp(Ity_I1
);
2728 t6
= newTemp(Ity_I32
);
2729 t7
= newTemp(Ity_I1
);
2730 t8
= newTemp(Ity_I32
);
2732 /* Subtract rightmost bytes of rs and rt. */
2737 unop(Iop_32to16
, getIReg(rs
)))),
2740 unop(Iop_32to16
, getIReg(rt
))))));
2741 /* t1 will be 1 if there is overflow, 0 otherwise. */
2742 assign(t1
, binop(Iop_CmpEQ32
,
2746 mkU32(0x00000100)));
2748 /* Subtract bits 15-8 of rs and rt. */
2753 unop(Iop_32to16
, getIReg(rs
)))),
2756 unop(Iop_32to16
, getIReg(rt
))))));
2757 /* t3 will be 1 if there is overflow, 0 otherwise. */
2758 assign(t3
, binop(Iop_CmpEQ32
,
2762 mkU32(0x00000100)));
2764 /* Subtract bits 15-8 of rs and rt. */
2769 unop(Iop_32HIto16
, getIReg(rs
)))),
2772 unop(Iop_32HIto16
, getIReg(rt
))))));
2773 /* t5 will be 1 if there is overflow, 0 otherwise. */
2774 assign(t5
, binop(Iop_CmpEQ32
,
2778 mkU32(0x00000100)));
2780 /* Subtract bits 15-8 of rs and rt. */
2785 unop(Iop_32HIto16
, getIReg(rs
)))),
2788 unop(Iop_32HIto16
, getIReg(rt
))))));
2789 /* t7 will be 1 if there is overflow, 0 otherwise. */
2790 assign(t7
, binop(Iop_CmpEQ32
,
2794 mkU32(0x00000100)));
2796 assign(t8
, binop(Iop_Or32
,
2799 unop(Iop_1Sto32
, mkexpr(t7
)),
2800 unop(Iop_1Sto32
, mkexpr(t5
))),
2801 unop(Iop_1Sto32
, mkexpr(t3
))),
2802 unop(Iop_1Sto32
, mkexpr(t1
))));
2804 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
2810 mkU32(0x00100000))));
2812 putIReg(rd
, binop(Iop_16HLto32
,
2814 unop(Iop_32to8
, mkexpr(t6
)),
2815 unop(Iop_32to8
, mkexpr(t4
))),
2817 unop(Iop_32to8
, mkexpr(t2
)),
2818 unop(Iop_32to8
, mkexpr(t0
)))));
2822 case 0x04: { /* ADDU_S.QB */
2823 DIP("addu_s.qb r%u, r%u, r%u", rd
, rs
, rt
);
2825 t0
= newTemp(Ity_I32
);
2826 t1
= newTemp(Ity_I1
);
2827 t2
= newTemp(Ity_I8
);
2828 t3
= newTemp(Ity_I32
);
2829 t4
= newTemp(Ity_I1
);
2830 t5
= newTemp(Ity_I8
);
2831 t6
= newTemp(Ity_I32
);
2832 t7
= newTemp(Ity_I1
);
2833 t8
= newTemp(Ity_I8
);
2834 t9
= newTemp(Ity_I32
);
2835 t10
= newTemp(Ity_I1
);
2836 t11
= newTemp(Ity_I8
);
2837 t12
= newTemp(Ity_I32
);
2839 /* Add rightmost bytes of rs and rt. */
2844 unop(Iop_32to16
, getIReg(rs
)))),
2847 unop(Iop_32to16
, getIReg(rt
))))));
2848 /* t1 will be 1 if there is overflow, 0 otherwise. */
2849 assign(t1
, binop(Iop_CmpEQ32
,
2853 mkU32(0x00000100)));
2854 /* Saturate if necessary. */
2855 assign(t2
, IRExpr_ITE(mkexpr(t1
),
2857 unop(Iop_32to8
, mkexpr(t0
))));
2859 /* Add bits 15-8 of rs and rt. */
2864 unop(Iop_32to16
, getIReg(rs
)))),
2867 unop(Iop_32to16
, getIReg(rt
))))));
2868 /* t4 will be 1 if there is overflow, 0 otherwise. */
2869 assign(t4
, binop(Iop_CmpEQ32
,
2873 mkU32(0x00000100)));
2874 /* Saturate if necessary. */
2875 assign(t5
, IRExpr_ITE(mkexpr(t4
),
2877 unop(Iop_32to8
, mkexpr(t3
))));
2879 /* Add bits 15-8 of rs and rt. */
2884 unop(Iop_32HIto16
, getIReg(rs
)))),
2887 unop(Iop_32HIto16
, getIReg(rt
))))));
2888 /* t7 will be 1 if there is overflow, 0 otherwise. */
2889 assign(t7
, binop(Iop_CmpEQ32
,
2893 mkU32(0x00000100)));
2894 /* Saturate if necessary. */
2895 assign(t8
, IRExpr_ITE(mkexpr(t7
),
2897 unop(Iop_32to8
, mkexpr(t6
))));
2899 /* Add bits 15-8 of rs and rt. */
2904 unop(Iop_32HIto16
, getIReg(rs
)))),
2907 unop(Iop_32HIto16
, getIReg(rt
))))));
2908 /* t10 will be 1 if there is overflow, 0 otherwise. */
2909 assign(t10
, binop(Iop_CmpEQ32
,
2913 mkU32(0x00000100)));
2914 /* Saturate if necessary. */
2915 assign(t11
, IRExpr_ITE(mkexpr(t10
),
2917 unop(Iop_32to8
, mkexpr(t9
))));
2923 unop(Iop_1Sto32
, mkexpr(t10
)),
2924 unop(Iop_1Sto32
, mkexpr(t7
))),
2925 unop(Iop_1Sto32
, mkexpr(t4
))),
2926 unop(Iop_1Sto32
, mkexpr(t1
))));
2928 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
2934 mkU32(0x00100000))));
2938 binop(Iop_8HLto16
, mkexpr(t11
), mkexpr(t8
)),
2939 binop(Iop_8HLto16
, mkexpr(t5
), mkexpr(t2
))));
2943 case 0x05: { /* SUBU_S.QB */
2944 DIP("subu_s.qb r%u, r%u, r%u", rd
, rs
, rt
);
2946 t1
= newTemp(Ity_I32
);
2947 t2
= newTemp(Ity_I1
);
2948 t3
= newTemp(Ity_I1
);
2949 t4
= newTemp(Ity_I1
);
2950 t5
= newTemp(Ity_I1
);
2951 t6
= newTemp(Ity_I32
);
2952 t7
= newTemp(Ity_I32
);
2953 t8
= newTemp(Ity_I32
);
2954 t9
= newTemp(Ity_I32
);
2956 /* Use C function to easily calculate the result
2957 and write it in the register more conveniently
2958 Underflow is checked using step by step subtraction. */
2959 assign(t1
, binop(Iop_QSub8Ux4
, getIReg(rs
), getIReg(rt
)));
2961 /* Subtract each byte of rs and rt. */
2966 unop(Iop_32to16
, getIReg(rs
)))),
2969 unop(Iop_32to16
, getIReg(rt
))))));
2974 unop(Iop_32to16
, getIReg(rs
)))),
2977 unop(Iop_32to16
, getIReg(rt
))))));
2982 unop(Iop_32HIto16
, getIReg(rs
)))),
2985 unop(Iop_32HIto16
, getIReg(rt
))))));
2990 unop(Iop_32HIto16
, getIReg(rs
)))),
2993 unop(Iop_32HIto16
, getIReg(rt
))))));
2995 /* Put 1 to bit 20 in DSPControl if there is underflow
2997 assign(t2
, binop(Iop_CmpEQ32
,
3001 mkU32(0x00000100)));
3002 putDSPControl(IRExpr_ITE(mkexpr(t2
),
3007 assign(t3
, binop(Iop_CmpEQ32
,
3011 mkU32(0x00000100)));
3012 putDSPControl(IRExpr_ITE(mkexpr(t3
),
3017 assign(t4
, binop(Iop_CmpEQ32
,
3021 mkU32(0x00000100)));
3022 putDSPControl(IRExpr_ITE(mkexpr(t4
),
3027 assign(t5
, binop(Iop_CmpEQ32
,
3031 mkU32(0x00000100)));
3032 putDSPControl(IRExpr_ITE(mkexpr(t5
),
3037 putIReg(rd
, mkexpr(t1
));
3041 case 0x6: { /* MULEU_S.PH.QBL */
3042 DIP("muleu_s.ph.qbl r%u, r%u, r%u", rd
, rs
, rt
);
3044 t0
= newTemp(Ity_I32
);
3045 t1
= newTemp(Ity_I32
);
3046 t2
= newTemp(Ity_I1
);
3047 t3
= newTemp(Ity_I1
);
3057 unop(Iop_32HIto16
, getIReg(rt
))))));
3066 unop(Iop_32to16
, getIReg(rt
))))));
3068 assign(t2
, binop(Iop_CmpNE32
,
3072 mkU32(0x03ff0000))));
3073 assign(t3
, binop(Iop_CmpNE32
,
3077 mkU32(0x03ff0000))));
3078 putDSPControl(IRExpr_ITE(mkexpr(t2
),
3082 IRExpr_ITE(mkexpr(t3
),
3089 IRExpr_ITE(mkexpr(t2
),
3091 unop(Iop_32to16
, mkexpr(t0
))),
3092 IRExpr_ITE(mkexpr(t3
),
3094 unop(Iop_32to16
, mkexpr(t1
)))));
3098 case 0x7: { /* MULEU_S.PH.QBR */
3099 DIP("muleu_s.ph.qbr r%u, r%u, r%u", rd
, rs
, rt
);
3101 t0
= newTemp(Ity_I32
);
3102 t1
= newTemp(Ity_I32
);
3103 t2
= newTemp(Ity_I1
);
3104 t3
= newTemp(Ity_I1
);
3106 assign(t0
, unop(Iop_64to32
,
3115 assign(t1
, unop(Iop_64to32
,
3125 assign(t2
, binop(Iop_CmpNE32
,
3129 mkU32(0x03ff0000))));
3130 assign(t3
, binop(Iop_CmpNE32
,
3134 mkU32(0x03ff0000))));
3135 putDSPControl(IRExpr_ITE(mkexpr(t2
),
3139 IRExpr_ITE(mkexpr(t3
),
3144 putIReg(rd
, binop(Iop_16HLto32
,
3145 IRExpr_ITE(mkexpr(t2
),
3149 IRExpr_ITE(mkexpr(t3
),
3156 case 0x08: { /* ADDU.PH */
3157 DIP("addu.ph r%u, r%u, r%u", rd
, rs
, rt
);
3159 t0
= newTemp(Ity_I32
);
3160 t1
= newTemp(Ity_I1
);
3161 t2
= newTemp(Ity_I32
);
3162 t3
= newTemp(Ity_I1
);
3164 /* Add lower halves. */
3165 assign(t0
, binop(Iop_Add32
,
3167 unop(Iop_32to16
, getIReg(rs
))),
3169 unop(Iop_32to16
, getIReg(rt
)))));
3171 /* Detect overflow. */
3172 assign(t1
, binop(Iop_CmpLT32U
,
3174 unop(Iop_32to16
, mkexpr(t0
))),
3176 unop(Iop_32to16
, getIReg(rs
)))));
3178 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3184 /* Add higher halves. */
3185 assign(t2
, binop(Iop_Add32
,
3187 unop(Iop_32HIto16
, getIReg(rs
))),
3189 unop(Iop_32HIto16
, getIReg(rt
)))));
3191 /* Detect overflow. */
3192 assign(t3
, binop(Iop_CmpLT32U
,
3194 unop(Iop_32to16
, mkexpr(t2
))),
3199 putDSPControl(IRExpr_ITE(mkexpr(t3
),
3205 putIReg(rd
, binop(Iop_16HLto32
,
3206 unop(Iop_32to16
, mkexpr(t2
)),
3207 unop(Iop_32to16
, mkexpr(t0
))));
3211 case 0x9: { /* SUBU.PH */
3212 DIP("subu.ph r%u, r%u, r%u", rd
, rs
, rt
);
3214 t0
= newTemp(Ity_I32
);
3215 t1
= newTemp(Ity_I1
);
3216 t2
= newTemp(Ity_I32
);
3217 t3
= newTemp(Ity_I1
);
3219 /* Substract lower halves. */
3220 assign(t0
, binop(Iop_Sub32
,
3222 unop(Iop_32to16
, getIReg(rs
))),
3224 unop(Iop_32to16
, getIReg(rt
)))));
3226 /* Detect underflow. */
3227 assign(t1
, binop(Iop_CmpNE32
,
3233 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3239 /* Subtract higher halves. */
3240 assign(t2
, binop(Iop_Sub32
,
3242 unop(Iop_32HIto16
, getIReg(rs
))),
3244 unop(Iop_32HIto16
, getIReg(rt
)))));
3246 /* Detect underflow. */
3247 assign(t3
, binop(Iop_CmpNE32
,
3253 putDSPControl(IRExpr_ITE(mkexpr(t3
),
3259 putIReg(rd
, binop(Iop_16HLto32
,
3260 unop(Iop_32to16
, mkexpr(t2
)),
3261 unop(Iop_32to16
, mkexpr(t0
))));
3265 case 0xA: { /* ADDQ.PH */
3266 DIP("addq.ph r%u, r%u, r%u", rd
, rs
, rt
);
3268 t0
= newTemp(Ity_I32
);
3269 t1
= newTemp(Ity_I1
);
3270 t2
= newTemp(Ity_I32
);
3271 t3
= newTemp(Ity_I1
);
3272 t6
= newTemp(Ity_I32
);
3273 t7
= newTemp(Ity_I32
);
3275 /* Add lower halves. */
3276 assign(t0
, binop(Iop_Add32
,
3278 unop(Iop_32to16
, getIReg(rs
))),
3280 unop(Iop_32to16
, getIReg(rt
)))));
3282 /* Bit 16 of the result. */
3283 assign(t6
, binop(Iop_And32
,
3285 unop(Iop_32HIto16
, mkexpr(t0
))),
3287 /* Detect overflow. */
3288 assign(t1
, binop(Iop_CmpNE32
,
3296 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3302 /* Add higher halves. */
3303 assign(t2
, binop(Iop_Add32
,
3305 unop(Iop_32HIto16
, getIReg(rs
))),
3307 unop(Iop_32HIto16
, getIReg(rt
)))));
3309 /* Bit 16 of the result. */
3310 assign(t7
, binop(Iop_And32
,
3312 unop(Iop_32HIto16
, mkexpr(t2
))),
3314 /* Detect overflow. */
3315 assign(t3
, binop(Iop_CmpNE32
,
3323 putDSPControl(IRExpr_ITE(mkexpr(t3
),
3329 putIReg(rd
, binop(Iop_16HLto32
,
3330 unop(Iop_32to16
, mkexpr(t2
)),
3331 unop(Iop_32to16
, mkexpr(t0
))));
3335 case 0xB: { /* SUBQ.PH */
3336 DIP("subq.ph r%u, r%u, r%u", rd
, rs
, rt
);
3338 t0
= newTemp(Ity_I32
);
3339 t1
= newTemp(Ity_I1
);
3340 t2
= newTemp(Ity_I32
);
3341 t3
= newTemp(Ity_I1
);
3342 t6
= newTemp(Ity_I32
);
3343 t7
= newTemp(Ity_I32
);
3345 /* Subtract lower halves. */
3346 assign(t0
, binop(Iop_Sub32
,
3348 unop(Iop_32to16
, getIReg(rs
))),
3350 unop(Iop_32to16
, getIReg(rt
)))));
3352 /* Bit 16 of the result. */
3353 assign(t6
, binop(Iop_And32
,
3355 unop(Iop_32HIto16
, mkexpr(t0
))),
3357 /* Compare the signs of input value and the result. */
3358 assign(t1
, binop(Iop_CmpNE32
,
3366 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3372 /* Subtract higher halves. */
3373 assign(t2
, binop(Iop_Sub32
,
3375 unop(Iop_32HIto16
, getIReg(rs
))),
3377 unop(Iop_32HIto16
, getIReg(rt
)))));
3379 /* Bit 16 of the result. */
3380 assign(t7
, binop(Iop_And32
,
3382 unop(Iop_32HIto16
, mkexpr(t2
))),
3384 /* Compare the signs of input value and the result. */
3385 assign(t3
, binop(Iop_CmpNE32
,
3393 putDSPControl(IRExpr_ITE(mkexpr(t3
),
3399 putIReg(rd
, binop(Iop_16HLto32
,
3400 unop(Iop_32to16
, mkexpr(t2
)),
3401 unop(Iop_32to16
, mkexpr(t0
))));
3405 case 0xC: { /* ADDU_S.PH */
3406 DIP("addu_s.ph r%u, r%u, r%u", rd
, rs
, rt
);
3408 t0
= newTemp(Ity_I32
);
3409 t1
= newTemp(Ity_I1
);
3410 t2
= newTemp(Ity_I32
);
3411 t3
= newTemp(Ity_I1
);
3413 /* Add lower halves. */
3414 assign(t0
, binop(Iop_Add32
,
3416 unop(Iop_32to16
, getIReg(rs
))),
3418 unop(Iop_32to16
, getIReg(rt
)))));
3420 /* Detect overflow. */
3421 assign(t1
, binop(Iop_CmpLT32U
,
3423 unop(Iop_32to16
, mkexpr(t0
))),
3425 unop(Iop_32to16
, getIReg(rs
)))));
3427 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3433 /* Add higher halves. */
3434 assign(t2
, binop(Iop_Add32
,
3436 unop(Iop_32HIto16
, getIReg(rs
))),
3438 unop(Iop_32HIto16
, getIReg(rt
)))));
3440 /* Detect overflow. */
3441 assign(t3
, binop(Iop_CmpLT32U
,
3443 unop(Iop_32to16
, mkexpr(t2
))),
3445 unop(Iop_32HIto16
, getIReg(rs
)))));
3447 putDSPControl(IRExpr_ITE(mkexpr(t3
),
3453 putIReg(rd
, binop(Iop_16HLto32
,
3454 IRExpr_ITE(mkexpr(t3
),
3458 IRExpr_ITE(mkexpr(t1
),
3465 case 0xD: { /* SUBU_S.PH */
3466 DIP("subu_s.ph r%u, r%u, r%u", rd
, rs
, rt
);
3468 t0
= newTemp(Ity_I32
);
3469 t1
= newTemp(Ity_I1
);
3470 t2
= newTemp(Ity_I32
);
3471 t3
= newTemp(Ity_I1
);
3473 /* Subtract lower halves. */
3474 assign(t0
, binop(Iop_Sub32
,
3476 unop(Iop_32to16
, getIReg(rs
))),
3478 unop(Iop_32to16
, getIReg(rt
)))));
3480 /* Detect underflow. */
3481 assign(t1
, binop(Iop_CmpNE32
,
3483 mkexpr(t0
), mkU32(0x00010000)),
3486 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3492 /* Subtract higher halves. */
3493 assign(t2
, binop(Iop_Sub32
,
3495 unop(Iop_32HIto16
, getIReg(rs
))),
3497 unop(Iop_32HIto16
, getIReg(rt
)))));
3499 /* Detect underflow. */
3500 assign(t3
, binop(Iop_CmpNE32
,
3502 mkexpr(t2
), mkU32(0x00010000)),
3505 putDSPControl(IRExpr_ITE(mkexpr(t3
),
3513 IRExpr_ITE(mkexpr(t3
),
3515 unop(Iop_32to16
, mkexpr(t2
))),
3516 IRExpr_ITE(mkexpr(t1
),
3518 unop(Iop_32to16
, mkexpr(t0
)))));
3522 case 0xE: { /* ADDQ_S.PH */
3523 DIP("addq_s.ph r%u r%u, r%u", rd
, rs
, rt
);
3525 t0
= newTemp(Ity_I32
);
3526 t1
= newTemp(Ity_I1
);
3527 t2
= newTemp(Ity_I32
);
3528 t3
= newTemp(Ity_I1
);
3529 t4
= newTemp(Ity_I16
);
3530 t5
= newTemp(Ity_I16
);
3531 t6
= newTemp(Ity_I32
);
3532 t7
= newTemp(Ity_I32
);
3534 /* Add lower halves. */
3535 assign(t0
, binop(Iop_Add32
,
3537 unop(Iop_32to16
, getIReg(rs
))),
3539 unop(Iop_32to16
, getIReg(rt
)))));
3541 /* Bit 16 of the result. */
3542 assign(t6
, binop(Iop_And32
,
3544 unop(Iop_32HIto16
, mkexpr(t0
))),
3546 /* Detect overflow. */
3547 assign(t1
, binop(Iop_CmpNE32
,
3555 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3560 /* Saturate if needed. */
3561 assign(t4
, IRExpr_ITE(mkexpr(t1
),
3562 IRExpr_ITE(binop(Iop_CmpEQ32
,
3567 unop(Iop_32to16
, mkexpr(t0
))));
3569 /* Add higher halves. */
3570 assign(t2
, binop(Iop_Add32
,
3572 unop(Iop_32HIto16
, getIReg(rs
))),
3574 unop(Iop_32HIto16
, getIReg(rt
)))));
3576 /* Bit 16 of the result. */
3577 assign(t7
, binop(Iop_And32
,
3579 unop(Iop_32HIto16
, mkexpr(t2
))),
3581 /* Detect overflow. */
3582 assign(t3
, binop(Iop_CmpNE32
,
3590 putDSPControl(IRExpr_ITE(mkexpr(t3
),
3595 /* Saturate if needed. */
3596 assign(t5
, IRExpr_ITE(mkexpr(t3
),
3597 IRExpr_ITE(binop(Iop_CmpEQ32
,
3602 unop(Iop_32to16
, mkexpr(t2
))));
3604 putIReg(rd
, binop(Iop_16HLto32
, mkexpr(t5
), mkexpr(t4
)));
3608 case 0xF: { /* SUBQ_S.PH */
3609 DIP("subq_s.ph r%u r%u, r%u", rd
, rs
, rt
);
3611 t0
= newTemp(Ity_I32
);
3612 t1
= newTemp(Ity_I1
);
3613 t2
= newTemp(Ity_I32
);
3614 t3
= newTemp(Ity_I1
);
3615 t4
= newTemp(Ity_I16
);
3616 t5
= newTemp(Ity_I16
);
3617 t6
= newTemp(Ity_I32
);
3618 t7
= newTemp(Ity_I32
);
3620 /* Subtract lower halves. */
3621 assign(t0
, binop(Iop_Sub32
,
3623 unop(Iop_32to16
, getIReg(rs
))),
3625 unop(Iop_32to16
, getIReg(rt
)))));
3627 /* Bit 16 of the result. */
3628 assign(t6
, binop(Iop_And32
,
3630 unop(Iop_32HIto16
, mkexpr(t0
))),
3632 /* Detect overflow or underflow. */
3633 assign(t1
, binop(Iop_CmpNE32
,
3641 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3646 /* Saturate if needed. */
3647 assign(t4
, IRExpr_ITE(mkexpr(t1
),
3648 IRExpr_ITE(binop(Iop_CmpEQ32
,
3653 unop(Iop_32to16
, mkexpr(t0
))));
3655 /* Subtract higher halves. */
3656 assign(t2
, binop(Iop_Sub32
,
3658 unop(Iop_32HIto16
, getIReg(rs
))),
3660 unop(Iop_32HIto16
, getIReg(rt
)))));
3662 /* Bit 16 of the result. */
3663 assign(t7
, binop(Iop_And32
,
3665 unop(Iop_32HIto16
, mkexpr(t2
))),
3667 /* Detect overflow or underflow. */
3668 assign(t3
, binop(Iop_CmpNE32
,
3676 putDSPControl(IRExpr_ITE(mkexpr(t3
),
3681 /* Saturate if needed. */
3682 assign(t5
, IRExpr_ITE(mkexpr(t3
),
3683 IRExpr_ITE(binop(Iop_CmpEQ32
,
3688 unop(Iop_32to16
, mkexpr(t2
))));
3690 putIReg(rd
, binop(Iop_16HLto32
, mkexpr(t5
), mkexpr(t4
)));
3694 case 0x10: { /* ADDSC */
3695 DIP("addsc r%u, r%u, r%u", rd
, rs
, rt
);
3697 t0
= newTemp(Ity_I64
);
3698 t1
= newTemp(Ity_I1
);
3700 /* The carry bit result out of the addition operation is
3701 written to bit 13(the c field) of the DSPControl reg. */
3702 assign(t0
, binop(Iop_Add64
,
3703 unop(Iop_32Uto64
, getIReg(rs
)),
3704 unop(Iop_32Uto64
, getIReg(rt
))));
3706 assign(t1
, binop(Iop_CmpEQ32
,
3708 unop(Iop_64HIto32
, mkexpr(t0
)),
3711 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3717 mkU32(0xffffdfff))));
3719 putIReg(rd
, unop(Iop_64to32
, mkexpr(t0
)));
3723 case 0x11: { /* ADDWC */
3724 DIP("addwc r%u, r%u, r%u", rd
, rs
, rt
);
3726 t0
= newTemp(Ity_I32
);
3727 t1
= newTemp(Ity_I64
);
3728 t2
= newTemp(Ity_I32
);
3729 t3
= newTemp(Ity_I32
);
3730 t4
= newTemp(Ity_I1
);
3732 /* Get carry bit from DSPControl register. */
3733 assign(t0
, binop(Iop_Shr32
,
3738 assign(t1
, binop(Iop_Add64
,
3739 unop(Iop_32Sto64
, getIReg(rs
)),
3745 /* Extract bits 32 and 31. */
3746 assign(t2
, binop(Iop_And32
,
3747 unop(Iop_64HIto32
, mkexpr(t1
)),
3749 assign(t3
, binop(Iop_Shr32
,
3751 unop(Iop_64to32
, mkexpr(t1
)),
3754 assign(t4
, binop(Iop_CmpNE32
, mkexpr(t2
), mkexpr(t3
)));
3756 putDSPControl(IRExpr_ITE(mkexpr(t4
),
3761 putIReg(rd
, unop(Iop_64to32
, mkexpr(t1
)));
3765 case 0x12: { /* MODSUB */
3766 DIP("modsub r%u, r%u, r%u", rd
, rs
, rt
);
3768 t0
= newTemp(Ity_I32
);
3769 t1
= newTemp(Ity_I32
);
3770 t2
= newTemp(Ity_I32
);
3776 unop(Iop_32to16
, getIReg(rt
)))));
3778 /* lastindex_15..0 */
3783 unop(Iop_32HIto16
, getIReg(rt
))),
3785 unop(Iop_32to16
, getIReg(rt
))))));
3788 IRExpr_ITE(binop(Iop_CmpEQ32
,
3793 getIReg(rs
), mkexpr(t0
))));
3794 putIReg(rd
, mkexpr(t2
));
3798 case 0x14: { /* RADDU.W.QB */
3799 DIP("raddu.w.qb r%u, r%u", rd
, rs
);
3801 putIReg(rd
, binop(Iop_Add32
,
3823 case 0x16: { /* ADDQ_S.W */
3824 DIP("addq_s.w r%u, r%u, r%u", rd
, rs
, rt
);
3826 t0
= newTemp(Ity_I64
);
3827 t1
= newTemp(Ity_I1
);
3828 t2
= newTemp(Ity_I32
);
3830 assign(t0
, binop(Iop_Add64
,
3831 unop(Iop_32Sto64
, getIReg(rs
)),
3832 unop(Iop_32Sto64
, getIReg(rt
))));
3834 assign(t2
, binop(Iop_And32
,
3835 unop(Iop_64HIto32
, mkexpr(t0
)),
3837 assign(t1
, binop(Iop_CmpNE32
,
3840 unop(Iop_64to32
, mkexpr(t0
)),
3845 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3851 putIReg(rd
, IRExpr_ITE(mkexpr(t1
),
3852 IRExpr_ITE(binop(Iop_CmpEQ32
,
3857 unop(Iop_64to32
, mkexpr(t0
))));
3861 case 0x17: { /* SUBQ_S.W */
3862 DIP("subq_s.w r%u, r%u, r%u", rd
, rs
, rt
);
3864 t0
= newTemp(Ity_I64
);
3865 t1
= newTemp(Ity_I1
);
3866 t2
= newTemp(Ity_I32
);
3868 assign(t0
, binop(Iop_Sub64
,
3869 unop(Iop_32Sto64
, getIReg(rs
)),
3870 unop(Iop_32Sto64
, getIReg(rt
))));
3872 assign(t2
, binop(Iop_And32
,
3873 unop(Iop_64HIto32
, mkexpr(t0
)),
3875 assign(t1
, binop(Iop_CmpNE32
,
3878 unop(Iop_64to32
, mkexpr(t0
)),
3883 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3889 putIReg(rd
, IRExpr_ITE(mkexpr(t1
),
3890 IRExpr_ITE(binop(Iop_CmpEQ32
,
3895 unop(Iop_64to32
, mkexpr(t0
))));
3899 case 0x1C: { /* MULEQ_S.W.PHL */
3900 DIP("muleq_s.w.phl r%u, r%u, r%u", rd
, rs
, rt
);
3902 t0
= newTemp(Ity_I32
);
3903 t1
= newTemp(Ity_I1
);
3904 t2
= newTemp(Ity_I1
);
3905 t3
= newTemp(Ity_I32
);
3911 unop(Iop_32HIto16
, getIReg(rt
))),
3913 unop(Iop_32HIto16
, getIReg(rs
)))),
3915 assign(t1
, binop(Iop_CmpEQ32
,
3919 mkU32(0x80000000)));
3920 assign(t2
, binop(Iop_CmpEQ32
,
3924 mkU32(0x80000000)));
3925 assign(t3
, IRExpr_ITE(mkexpr(t1
),
3926 IRExpr_ITE(mkexpr(t2
),
3932 putDSPControl(mkexpr(t3
));
3934 putIReg(rd
, IRExpr_ITE(mkexpr(t1
),
3935 IRExpr_ITE(mkexpr(t2
),
3942 case 0x1D: { /* MULEQ_S.W.PHR */
3943 DIP("muleq_s.w.phr r%u, r%u, r%u", rd
, rs
, rt
);
3945 t0
= newTemp(Ity_I32
);
3946 t1
= newTemp(Ity_I1
);
3947 t2
= newTemp(Ity_I1
);
3953 unop(Iop_32to16
, getIReg(rt
))),
3955 unop(Iop_32to16
, getIReg(rs
)))),
3957 assign(t1
, binop(Iop_CmpEQ32
,
3962 assign(t2
, binop(Iop_CmpEQ32
,
3967 putDSPControl(IRExpr_ITE(mkexpr(t1
),
3968 IRExpr_ITE(mkexpr(t2
),
3975 putIReg(rd
, IRExpr_ITE(mkexpr(t1
),
3976 IRExpr_ITE(mkexpr(t2
),
3983 case 0x1E: { /* MULQ_S.PH */
3984 DIP("mulq_s.ph r%u, r%u, r%u", rd
, rs
, rt
);
3986 t0
= newTemp(Ity_I32
);
3987 t1
= newTemp(Ity_I32
);
3988 t2
= newTemp(Ity_I16
);
3989 t3
= newTemp(Ity_I16
);
3990 t5
= newTemp(Ity_I32
);
3991 t6
= newTemp(Ity_I32
);
3992 t7
= newTemp(Ity_I32
);
3993 t8
= newTemp(Ity_I32
);
3996 unop(Iop_16Sto32
, unop(Iop_32to16
, getIReg(rs
))));
3998 unop(Iop_16Sto32
, unop(Iop_32to16
, getIReg(rt
))));
4001 unop(Iop_16Sto32
, unop(Iop_32HIto16
, getIReg(rs
))));
4003 unop(Iop_16Sto32
, unop(Iop_32HIto16
, getIReg(rt
))));
4005 assign(t0
, binop(Iop_And32
,
4018 assign(t1
, binop(Iop_And32
,
4032 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
4042 assign(t2
, unop(Iop_32HIto16
,
4049 assign(t3
, unop(Iop_32HIto16
,
4056 putIReg(rd
, binop(Iop_16HLto32
,
4057 IRExpr_ITE(binop(Iop_CmpEQ32
,
4062 IRExpr_ITE(binop(Iop_CmpEQ32
,
4070 case 0x1F: { /* MULQ_RS.PH */
4071 DIP("mulq_rs.ph r%u, r%u, r%u", rd
, rs
, rt
);
4073 t0
= newTemp(Ity_I32
);
4074 t1
= newTemp(Ity_I1
);
4075 t2
= newTemp(Ity_I1
);
4076 t3
= newTemp(Ity_I16
);
4077 t4
= newTemp(Ity_I32
);
4078 t5
= newTemp(Ity_I1
);
4079 t6
= newTemp(Ity_I1
);
4080 t7
= newTemp(Ity_I16
);
4082 /* Multiply and round lower halfwords. */
4083 assign(t0
, binop(Iop_Add32
,
4093 mkU32(0x00008000)));
4094 assign(t1
, binop(Iop_CmpEQ32
,
4096 getIReg(rt
), mkU32(0xffff)),
4098 assign(t2
, binop(Iop_CmpEQ32
,
4100 getIReg(rs
), mkU32(0xffff)),
4102 putDSPControl(IRExpr_ITE(mkexpr(t1
),
4103 IRExpr_ITE(mkexpr(t2
),
4110 assign(t3
, IRExpr_ITE(mkexpr(t1
),
4111 IRExpr_ITE(mkexpr(t2
),
4115 unop(Iop_32HIto16
, mkexpr(t0
))));
4117 /* Multiply and round higher halfwords. */
4118 assign(t4
, binop(Iop_Add32
,
4128 mkU32(0x00008000)));
4129 assign(t5
, binop(Iop_CmpEQ32
,
4133 mkU32(0x80000000)));
4134 assign(t6
, binop(Iop_CmpEQ32
,
4138 mkU32(0x80000000)));
4139 putDSPControl(IRExpr_ITE(mkexpr(t5
),
4140 IRExpr_ITE(mkexpr(t6
),
4146 assign(t7
, IRExpr_ITE(mkexpr(t5
),
4147 IRExpr_ITE(mkexpr(t6
),
4151 unop(Iop_32HIto16
, mkexpr(t4
))));
4153 putIReg(rd
, binop(Iop_16HLto32
, mkexpr(t7
), mkexpr(t3
)));
4164 static UInt
disDSPInstr_MIPS_WRK_Special3_CMPU_EQ_QB( UInt cins
)
4166 IRTemp t0
, t1
= 0, t2
, t3
, t4
, t5
, t6
, t7
, t8
, t9
, t10
, t11
, t12
, t13
, t14
,
4168 UInt rs
, rt
, rd
, sa
;
4176 case 0x0: { /* CMPU.EQ.QB */
4177 DIP("cmpu.eq.qb r%u, r%u", rs
, rt
);
4179 t1
= newTemp(Ity_I1
);
4180 t2
= newTemp(Ity_I1
);
4181 t3
= newTemp(Ity_I1
);
4182 t4
= newTemp(Ity_I1
);
4186 binop(Iop_And32
, getIReg(rs
), mkU32(0xff)),
4187 binop(Iop_And32
, getIReg(rt
), mkU32(0xff))));
4188 putDSPControl(IRExpr_ITE(mkexpr(t1
),
4194 mkU32(0xfeffffff))));
4196 assign(t2
, binop(Iop_CmpEQ32
,
4205 putDSPControl(IRExpr_ITE(mkexpr(t2
),
4211 mkU32(0xfdffffff))));
4213 assign(t3
, binop(Iop_CmpEQ32
,
4222 putDSPControl(IRExpr_ITE(mkexpr(t3
),
4228 mkU32(0xfbffffff))));
4230 assign(t4
, binop(Iop_CmpEQ32
,
4239 putDSPControl(IRExpr_ITE(mkexpr(t4
),
4245 mkU32(0xf7ffffff))));
4249 case 0x1: { /* CMPU.LT.QB */
4250 DIP("cmpu.lt.qb r%u, r%u", rs
, rt
);
4252 t1
= newTemp(Ity_I1
);
4253 t2
= newTemp(Ity_I1
);
4254 t3
= newTemp(Ity_I1
);
4255 t4
= newTemp(Ity_I1
);
4257 assign(t1
, binop(Iop_CmpLT32U
,
4266 putDSPControl(IRExpr_ITE(mkexpr(t1
),
4272 mkU32(0xfeffffff))));
4274 assign(t2
, binop(Iop_CmpLT32U
,
4283 putDSPControl(IRExpr_ITE(mkexpr(t2
),
4289 mkU32(0xfdffffff))));
4291 assign(t3
, binop(Iop_CmpLT32U
,
4300 putDSPControl(IRExpr_ITE(mkexpr(t3
),
4306 mkU32(0xfbffffff))));
4308 assign(t4
, binop(Iop_CmpLT32U
,
4317 putDSPControl(IRExpr_ITE(mkexpr(t4
),
4323 mkU32(0xf7ffffff))));
4327 case 0x2: { /* CMPU.LE.QB */
4328 DIP("cmpu.le.qb r%u, r%u", rs
, rt
);
4330 t1
= newTemp(Ity_I1
);
4331 t2
= newTemp(Ity_I1
);
4332 t3
= newTemp(Ity_I1
);
4333 t4
= newTemp(Ity_I1
);
4335 assign(t1
, binop(Iop_CmpLE32U
,
4344 putDSPControl(IRExpr_ITE(mkexpr(t1
),
4350 mkU32(0xfeffffff))));
4352 assign(t2
, binop(Iop_CmpLE32U
,
4361 putDSPControl(IRExpr_ITE(mkexpr(t2
),
4367 mkU32(0xfdffffff))));
4369 assign(t3
, binop(Iop_CmpLE32U
,
4378 putDSPControl(IRExpr_ITE(mkexpr(t3
),
4384 mkU32(0xfbffffff))));
4386 assign(t4
, binop(Iop_CmpLE32U
,
4395 putDSPControl(IRExpr_ITE(mkexpr(t4
),
4401 mkU32(0xf7ffffff))));
4405 case 0x3: { /* PICK.QB */
4406 DIP("pick.qb r%u, r%u, r%u", rd
, rs
, rt
);
4408 t0
= newTemp(Ity_I32
);
4409 t1
= newTemp(Ity_I8
);
4410 t2
= newTemp(Ity_I8
);
4411 t3
= newTemp(Ity_I8
);
4412 t4
= newTemp(Ity_I8
);
4414 assign(t0
, getDSPControl());
4415 assign(t1
, IRExpr_ITE(binop(Iop_CmpNE32
,
4426 assign(t2
, IRExpr_ITE(binop(Iop_CmpNE32
,
4432 unop(Iop_32to16
, getIReg(rs
))),
4436 assign(t3
, IRExpr_ITE(binop(Iop_CmpNE32
,
4447 assign(t4
, IRExpr_ITE(binop(Iop_CmpNE32
,
4460 binop(Iop_8HLto16
, mkexpr(t4
), mkexpr(t3
)),
4461 binop(Iop_8HLto16
, mkexpr(t2
), mkexpr(t1
))));
4465 case 0x4: { /* CMPGU.EQ.QB */
4466 DIP("cmpgu.eq.qb r%u, r%u, r%u", rd
, rs
, rt
);
4468 t1
= newTemp(Ity_I1
);
4469 t2
= newTemp(Ity_I1
);
4470 t3
= newTemp(Ity_I1
);
4471 t4
= newTemp(Ity_I1
);
4472 t5
= newTemp(Ity_I32
);
4473 t6
= newTemp(Ity_I32
);
4474 t7
= newTemp(Ity_I32
);
4475 t8
= newTemp(Ity_I32
);
4477 assign(t1
, binop(Iop_CmpEQ32
,
4480 unop(Iop_32to16
, getIReg(rs
)))),
4485 assign(t5
, IRExpr_ITE(mkexpr(t1
),
4486 mkU32(0x00000001), mkU32(0)));
4488 assign(t2
, binop(Iop_CmpEQ32
,
4491 unop(Iop_32to16
, getIReg(rs
)))),
4496 assign(t6
, IRExpr_ITE(mkexpr(t2
),
4497 mkU32(0x00000002), mkU32(0)));
4499 assign(t3
, binop(Iop_CmpEQ32
,
4508 assign(t7
, IRExpr_ITE(mkexpr(t3
),
4509 mkU32(0x00000004), mkU32(0)));
4511 assign(t4
, binop(Iop_CmpEQ32
,
4520 assign(t8
, IRExpr_ITE(mkexpr(t4
),
4521 mkU32(0x00000008), mkU32(0)));
4523 putIReg(rd
, binop(Iop_Or32
,
4526 mkexpr(t5
), mkexpr(t6
)),
4532 case 0x5: { /* CMPGU.LT.QB */
4533 DIP("cmpgu.lt.qb r%u, r%u, r%u", rd
, rs
, rt
);
4535 t1
= newTemp(Ity_I1
);
4536 t2
= newTemp(Ity_I1
);
4537 t3
= newTemp(Ity_I1
);
4538 t4
= newTemp(Ity_I1
);
4539 t5
= newTemp(Ity_I32
);
4540 t6
= newTemp(Ity_I32
);
4541 t7
= newTemp(Ity_I32
);
4542 t8
= newTemp(Ity_I32
);
4544 assign(t1
, binop(Iop_CmpLT32U
,
4547 unop(Iop_32to16
, getIReg(rs
)))),
4552 assign(t5
, IRExpr_ITE(mkexpr(t1
),
4553 mkU32(0x00000001), mkU32(0)));
4555 assign(t2
, binop(Iop_CmpLT32U
,
4558 unop(Iop_32to16
, getIReg(rs
)))),
4563 assign(t6
, IRExpr_ITE(mkexpr(t2
),
4564 mkU32(0x00000002), mkU32(0)));
4566 assign(t3
, binop(Iop_CmpLT32U
,
4575 assign(t7
, IRExpr_ITE(mkexpr(t3
),
4576 mkU32(0x00000004), mkU32(0)));
4578 assign(t4
, binop(Iop_CmpLT32U
,
4587 assign(t8
, IRExpr_ITE(mkexpr(t4
),
4588 mkU32(0x00000008), mkU32(0)));
4589 putIReg(rd
, binop(Iop_Or32
,
4592 mkexpr(t5
), mkexpr(t6
)),
4598 case 0x6: { /* CMPGU.LE.QB */
4599 DIP("cmpgu.le.qb r%u, r%u, r%u", rd
, rs
, rt
);
4601 t1
= newTemp(Ity_I1
);
4602 t2
= newTemp(Ity_I1
);
4603 t3
= newTemp(Ity_I1
);
4604 t4
= newTemp(Ity_I1
);
4605 t5
= newTemp(Ity_I32
);
4606 t6
= newTemp(Ity_I32
);
4607 t7
= newTemp(Ity_I32
);
4608 t8
= newTemp(Ity_I32
);
4610 assign(t1
, binop(Iop_CmpLE32U
,
4613 unop(Iop_32to16
, getIReg(rs
)))),
4618 assign(t5
, IRExpr_ITE(mkexpr(t1
),
4619 mkU32(0x00000001), mkU32(0)));
4621 assign(t2
, binop(Iop_CmpLE32U
,
4624 unop(Iop_32to16
, getIReg(rs
)))),
4629 assign(t6
, IRExpr_ITE(mkexpr(t2
),
4630 mkU32(0x00000002), mkU32(0)));
4632 assign(t3
, binop(Iop_CmpLE32U
,
4641 assign(t7
, IRExpr_ITE(mkexpr(t3
),
4642 mkU32(0x00000004), mkU32(0)));
4644 assign(t4
, binop(Iop_CmpLE32U
,
4653 assign(t8
, IRExpr_ITE(mkexpr(t4
),
4654 mkU32(0x00000008), mkU32(0)));
4655 putIReg(rd
, binop(Iop_Or32
,
4658 mkexpr(t5
), mkexpr(t6
)),
4664 case 0x8: { /* CMP.EQ.PH */
4665 DIP("cmp.eq.ph r%u, r%u", rs
, rt
);
4667 t1
= newTemp(Ity_I1
);
4668 t2
= newTemp(Ity_I1
);
4670 assign(t1
, binop(Iop_CmpEQ16
,
4671 unop(Iop_32to16
, getIReg(rs
)),
4672 unop(Iop_32to16
, getIReg(rt
))));
4673 putDSPControl(IRExpr_ITE(mkexpr(t1
),
4679 mkU32(0xfeffffff))));
4680 assign(t2
, binop(Iop_CmpEQ16
,
4681 unop(Iop_32HIto16
, getIReg(rs
)),
4682 unop(Iop_32HIto16
, getIReg(rt
))));
4683 putDSPControl(IRExpr_ITE(mkexpr(t2
),
4689 mkU32(0xfdffffff))));
4693 case 0x9: { /* CMP.LT.PH */
4694 DIP("cmp.lt.ph r%u, r%u", rs
, rt
);
4696 t1
= newTemp(Ity_I1
);
4697 t2
= newTemp(Ity_I1
);
4699 assign(t1
, binop(Iop_CmpLT32S
,
4701 unop(Iop_32to16
, getIReg(rs
))),
4703 unop(Iop_32to16
, getIReg(rt
)))));
4704 putDSPControl(IRExpr_ITE(mkexpr(t1
),
4710 mkU32(0xfeffffff))));
4712 assign(t2
, binop(Iop_CmpLT32S
,
4714 unop(Iop_32HIto16
, getIReg(rs
))),
4716 unop(Iop_32HIto16
, getIReg(rt
)))));
4717 putDSPControl(IRExpr_ITE(mkexpr(t2
),
4723 mkU32(0xfdffffff))));
4727 case 0xA: { /* CMP.LE.PH */
4728 DIP("cmp.le.ph r%u, r%u", rs
, rt
);
4730 t1
= newTemp(Ity_I1
);
4731 t2
= newTemp(Ity_I1
);
4733 assign(t1
, binop(Iop_CmpLE32S
,
4735 unop(Iop_32to16
, getIReg(rs
))),
4737 unop(Iop_32to16
, getIReg(rt
)))));
4738 putDSPControl(IRExpr_ITE(mkexpr(t1
),
4744 mkU32(0xfeffffff))));
4746 assign(t2
, binop(Iop_CmpLE32S
,
4748 unop(Iop_32HIto16
, getIReg(rs
))),
4750 unop(Iop_32HIto16
, getIReg(rt
)))));
4751 putDSPControl(IRExpr_ITE(mkexpr(t2
),
4757 mkU32(0xfdffffff))));
4761 case 0xB: { /* PICK.PH */
4762 DIP("pick.qb r%u, r%u, r%u", rd
, rs
, rt
);
4764 t0
= newTemp(Ity_I32
);
4765 t1
= newTemp(Ity_I16
);
4766 t2
= newTemp(Ity_I16
);
4768 assign(t0
, getDSPControl());
4770 assign(t1
, IRExpr_ITE(binop(Iop_CmpNE32
,
4775 unop(Iop_32to16
, getIReg(rs
)),
4776 unop(Iop_32to16
, getIReg(rt
))));
4778 assign(t2
, IRExpr_ITE(binop(Iop_CmpNE32
,
4783 unop(Iop_32HIto16
, getIReg(rs
)),
4784 unop(Iop_32HIto16
, getIReg(rt
))));
4786 putIReg(rd
, binop(Iop_16HLto32
, mkexpr(t2
), mkexpr(t1
)));
4790 case 0xC: { /* PRECRQ.QB.PH */
4791 DIP("precrq.qb.ph r%u, r%u, %u", rd
, rs
, rt
);
4797 unop(Iop_32HIto16
, getIReg(rs
))),
4799 unop(Iop_32to16
, getIReg(rs
)))),
4802 unop(Iop_32HIto16
, getIReg(rt
))),
4804 unop(Iop_32to16
, getIReg(rt
))))));
4808 case 0xD: { /* PRECR.QB.PH */
4809 DIP("precr.qb.ph r%u, r%u, r%u", rd
, rs
, rt
);
4816 unop(Iop_32HIto16
, getIReg(rs
))),
4818 unop(Iop_32to16
, getIReg(rs
)))),
4821 unop(Iop_32HIto16
, getIReg(rt
))),
4823 unop(Iop_32to16
, getIReg(rt
))))));
4827 case 0xF: { /* PRECRQU_S.QB.PH */
4828 DIP("precrqu_s.qb.ph r%u, r%u, %u", rd
, rs
, rt
);
4830 t0
= newTemp(Ity_I8
);
4831 t1
= newTemp(Ity_I8
);
4832 t2
= newTemp(Ity_I8
);
4833 t3
= newTemp(Ity_I8
);
4834 t4
= newTemp(Ity_I8
);
4835 t5
= newTemp(Ity_I32
);
4836 t6
= newTemp(Ity_I1
);
4837 t7
= newTemp(Ity_I8
);
4838 t8
= newTemp(Ity_I1
);
4839 t9
= newTemp(Ity_I32
);
4840 t10
= newTemp(Ity_I8
);
4841 t11
= newTemp(Ity_I1
);
4842 t12
= newTemp(Ity_I32
);
4843 t13
= newTemp(Ity_I8
);
4844 t14
= newTemp(Ity_I1
);
4845 t15
= newTemp(Ity_I32
);
4847 assign(t4
, IRExpr_ITE(binop(Iop_CmpLT32U
,
4860 assign(t0
, IRExpr_ITE(binop(Iop_CmpEQ32
,
4869 assign(t5
, binop(Iop_And32
,
4873 mkU32(0x00008000)));
4874 assign(t6
, binop(Iop_CmpLT32U
,
4881 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
4884 IRExpr_ITE(mkexpr(t6
),
4892 mkU32(0x00400000))));
4894 assign(t7
, IRExpr_ITE(binop(Iop_CmpLT32U
,
4907 assign(t1
, IRExpr_ITE(binop(Iop_CmpEQ32
,
4916 assign(t8
, binop(Iop_CmpEQ32
,
4923 assign(t9
, IRExpr_ITE(binop(Iop_CmpLT32U
,
4934 putDSPControl(IRExpr_ITE(mkexpr(t8
),
4938 mkU32(0x00400000))));
4940 assign(t10
, IRExpr_ITE(binop(Iop_CmpLT32U
,
4953 assign(t2
, IRExpr_ITE(binop(Iop_CmpEQ32
,
4962 assign(t11
, binop(Iop_CmpEQ32
,
4969 assign(t12
, IRExpr_ITE(binop(Iop_CmpLT32U
,
4980 putDSPControl(IRExpr_ITE(mkexpr(t11
),
4984 mkU32(0x00400000))));
4986 assign(t13
, IRExpr_ITE(binop(Iop_CmpLT32U
,
4999 assign(t3
, IRExpr_ITE(binop(Iop_CmpEQ32
,
5008 assign(t14
, binop(Iop_CmpEQ32
,
5015 assign(t15
, IRExpr_ITE(binop(Iop_CmpLT32U
,
5026 putDSPControl(IRExpr_ITE(mkexpr(t14
),
5030 mkU32(0x00400000))));
5032 putIReg(rd
, binop(Iop_16HLto32
,
5034 mkexpr(t1
), mkexpr(t0
)),
5036 mkexpr(t3
), mkexpr(t2
))));
5040 case 0x14: { /* PRECRQ.PH.W */
5041 DIP("precrq.ph.w r%u, r%u, %u", rd
, rs
, rt
);
5043 putIReg(rd
, binop(Iop_16HLto32
,
5044 unop(Iop_32HIto16
, getIReg(rs
)),
5045 unop(Iop_32HIto16
, getIReg(rt
))));
5049 case 0x15: { /* PRECRQ_RS.PH.W */
5050 DIP("precrq_rs.ph.w r%u, r%u, %u", rd
, rs
, rt
);
5052 t0
= newTemp(Ity_I64
);
5053 t1
= newTemp(Ity_I1
);
5054 t2
= newTemp(Ity_I32
);
5055 t3
= newTemp(Ity_I64
);
5056 t4
= newTemp(Ity_I1
);
5057 t5
= newTemp(Ity_I32
);
5059 assign(t0
, binop(Iop_Add64
,
5067 mkU64(0x0000000000008000ULL
)));
5068 assign(t1
, binop(Iop_CmpNE32
,
5070 unop(Iop_64HIto32
, mkexpr(t0
)),
5074 unop(Iop_64to32
, mkexpr(t0
)),
5077 assign(t2
, IRExpr_ITE(mkexpr(t1
),
5079 unop(Iop_64to32
, mkexpr(t0
))));
5080 putDSPControl(IRExpr_ITE(mkexpr(t1
),
5085 assign(t3
, binop(Iop_Add64
,
5093 mkU64(0x0000000000008000ULL
)));
5094 assign(t4
, binop(Iop_CmpNE32
,
5096 unop(Iop_64HIto32
, mkexpr(t3
)),
5100 unop(Iop_64to32
, mkexpr(t3
)),
5103 assign(t5
, IRExpr_ITE(mkexpr(t4
),
5105 unop(Iop_64to32
, mkexpr(t3
))));
5106 putDSPControl(IRExpr_ITE(mkexpr(t4
),
5111 putIReg(rd
, binop(Iop_16HLto32
,
5112 unop(Iop_32HIto16
, mkexpr(t2
)),
5113 unop(Iop_32HIto16
, mkexpr(t5
))));
5117 case 0x1E: { /* PRECR_SRA.PH.W */
5118 DIP("precr_sra.ph.w r%u, r%u, %u", rt
, rs
, rd
);
5122 putIReg(rt
, binop(Iop_16HLto32
,
5123 unop(Iop_32to16
, getIReg(rt
)),
5124 unop(Iop_32to16
, getIReg(rs
))));
5126 putIReg(rt
, binop(Iop_16HLto32
,
5127 unop(Iop_32to16
, binop(Iop_Sar32
,
5130 unop(Iop_32to16
, binop(Iop_Sar32
,
5138 case 0x1F: { /* PRECR_SRA_R.PH.W */
5139 DIP("precr_sra_r.ph.w r%u, r%u, %u", rt
, rs
, rd
);
5142 t0
= newTemp(Ity_I32
);
5143 t1
= newTemp(Ity_I32
);
5146 putIReg(rt
, binop(Iop_16HLto32
,
5147 unop(Iop_32to16
, getIReg(rt
)),
5148 unop(Iop_32to16
, getIReg(rs
))));
5150 assign(t0
, binop(Iop_Shr32
,
5157 assign(t1
, binop(Iop_Shr32
,
5164 putIReg(rt
, binop(Iop_16HLto32
,
5165 unop(Iop_32to16
, mkexpr(t0
)),
5166 unop(Iop_32to16
, mkexpr(t1
))));
5172 case 0xE: { /* PACKRL.PH */
5173 DIP("packrl.ph r%u, r%u, r%u", rd
, rs
, rt
);
5176 putIReg(rd
, binop(Iop_16HLto32
,
5177 unop(Iop_32to16
, getIReg(rs
)),
5178 unop(Iop_32HIto16
, getIReg(rt
))));
5182 case 0x18: { /* CMPGDU.EQ.QB */
5183 DIP("cmpgdu.eq.qb r%u, r%u, r%u", rd
, rs
, rt
);
5185 t1
= newTemp(Ity_I1
);
5186 t2
= newTemp(Ity_I1
);
5187 t3
= newTemp(Ity_I1
);
5188 t4
= newTemp(Ity_I1
);
5189 t5
= newTemp(Ity_I32
);
5190 t6
= newTemp(Ity_I32
);
5191 t7
= newTemp(Ity_I32
);
5192 t8
= newTemp(Ity_I32
);
5198 unop(Iop_32to16
, getIReg(rs
)))),
5201 unop(Iop_32to16
, getIReg(rt
))))));
5202 assign(t5
, IRExpr_ITE(mkexpr(t1
),
5203 mkU32(0x00000001), mkU32(0)));
5204 putDSPControl(IRExpr_ITE(mkexpr(t1
),
5210 mkU32(0xfeffffff))));
5212 assign(t2
, binop(Iop_CmpEQ32
,
5215 unop(Iop_32to16
, getIReg(rs
)))),
5220 assign(t6
, IRExpr_ITE(mkexpr(t2
),
5221 mkU32(0x00000002), mkU32(0)));
5222 putDSPControl(IRExpr_ITE(mkexpr(t2
),
5228 mkU32(0xfdffffff))));
5230 assign(t3
, binop(Iop_CmpEQ32
,
5239 assign(t7
, IRExpr_ITE(mkexpr(t3
),
5240 mkU32(0x00000004), mkU32(0)));
5241 putDSPControl(IRExpr_ITE(mkexpr(t3
),
5247 mkU32(0xfbffffff))));
5249 assign(t4
, binop(Iop_CmpEQ32
,
5258 assign(t8
, IRExpr_ITE(mkexpr(t4
),
5259 mkU32(0x00000008), mkU32(0)));
5260 putDSPControl(IRExpr_ITE(mkexpr(t4
),
5266 mkU32(0xf7ffffff))));
5268 putIReg(rd
, binop(Iop_Or32
,
5271 mkexpr(t5
), mkexpr(t6
)),
5277 case 0x19: { /* CMPGDU.LT.QB */
5278 DIP("cmpgdu.lt.qb r%u, r%u, r%u", rd
, rs
, rt
);
5280 t1
= newTemp(Ity_I1
);
5281 t2
= newTemp(Ity_I1
);
5282 t3
= newTemp(Ity_I1
);
5283 t4
= newTemp(Ity_I1
);
5284 t5
= newTemp(Ity_I32
);
5285 t6
= newTemp(Ity_I32
);
5286 t7
= newTemp(Ity_I32
);
5287 t8
= newTemp(Ity_I32
);
5289 assign(t1
, binop(Iop_CmpLT32U
,
5292 unop(Iop_32to16
, getIReg(rs
)))),
5297 assign(t5
, IRExpr_ITE(mkexpr(t1
),
5298 mkU32(0x00000001), mkU32(0)));
5299 putDSPControl(IRExpr_ITE(mkexpr(t1
),
5305 mkU32(0xfeffffff))));
5307 assign(t2
, binop(Iop_CmpLT32U
,
5310 unop(Iop_32to16
, getIReg(rs
)))),
5315 assign(t6
, IRExpr_ITE(mkexpr(t2
),
5316 mkU32(0x00000002), mkU32(0)));
5317 putDSPControl(IRExpr_ITE(mkexpr(t2
),
5323 mkU32(0xfdffffff))));
5325 assign(t3
, binop(Iop_CmpLT32U
,
5334 assign(t7
, IRExpr_ITE(mkexpr(t3
),
5335 mkU32(0x00000004), mkU32(0)));
5336 putDSPControl(IRExpr_ITE(mkexpr(t3
),
5342 mkU32(0xfbffffff))));
5344 assign(t4
, binop(Iop_CmpLT32U
,
5353 assign(t8
, IRExpr_ITE(mkexpr(t4
),
5354 mkU32(0x00000008), mkU32(0)));
5355 putDSPControl(IRExpr_ITE(mkexpr(t4
),
5361 mkU32(0xf7ffffff))));
5363 putIReg(rd
, binop(Iop_Or32
,
5366 mkexpr(t5
), mkexpr(t6
)),
5372 case 0x1A: { /* CMPGDU.LE.QB */
5373 DIP("cmpgdu.le.qb r%u, r%u, r%u", rd
, rs
, rt
);
5375 t1
= newTemp(Ity_I1
);
5376 t2
= newTemp(Ity_I1
);
5377 t3
= newTemp(Ity_I1
);
5378 t4
= newTemp(Ity_I1
);
5379 t5
= newTemp(Ity_I32
);
5380 t6
= newTemp(Ity_I32
);
5381 t7
= newTemp(Ity_I32
);
5382 t8
= newTemp(Ity_I32
);
5384 assign(t1
, binop(Iop_CmpLE32U
,
5387 unop(Iop_32to16
, getIReg(rs
)))),
5392 assign(t5
, IRExpr_ITE(mkexpr(t1
),
5395 putDSPControl(IRExpr_ITE(mkexpr(t1
),
5401 mkU32(0xfeffffff))));
5403 assign(t2
, binop(Iop_CmpLE32U
,
5406 unop(Iop_32to16
, getIReg(rs
)))),
5411 assign(t6
, IRExpr_ITE(mkexpr(t2
),
5412 mkU32(0x00000002), mkU32(0)));
5413 putDSPControl(IRExpr_ITE(mkexpr(t2
),
5419 mkU32(0xfdffffff))));
5421 assign(t3
, binop(Iop_CmpLE32U
,
5430 assign(t7
, IRExpr_ITE(mkexpr(t3
),
5431 mkU32(0x00000004), mkU32(0)));
5432 putDSPControl(IRExpr_ITE(mkexpr(t3
),
5438 mkU32(0xfbffffff))));
5440 assign(t4
, binop(Iop_CmpLE32U
,
5449 assign(t8
, IRExpr_ITE(mkexpr(t4
),
5450 mkU32(0x00000008), mkU32(0)));
5451 putDSPControl(IRExpr_ITE(mkexpr(t4
),
5457 mkU32(0xf7ffffff))));
5459 putIReg(rd
, binop(Iop_Or32
,
5462 mkexpr(t5
), mkexpr(t6
)),
5475 static UInt
disDSPInstr_MIPS_WRK_Special3_SHLL_QB( UInt cins
)
5477 IRTemp t0
, t1
= 0, t2
, t3
, t4
, t5
, t6
, t7
, t8
, t9
, t10
, t11
, t12
, t13
, t14
,
5479 UInt rs
, rt
, rd
, sa
;
5488 case 0x0: { /* SHLL.QB */
5489 DIP("shll.qb r%u, r%u, %u", rd
, rt
, rs
);
5491 t0
= newTemp(Ity_I32
);
5492 t1
= newTemp(Ity_I1
);
5493 t2
= newTemp(Ity_I1
);
5494 t3
= newTemp(Ity_I32
);
5495 t4
= newTemp(Ity_I1
);
5496 t5
= newTemp(Ity_I1
);
5497 t6
= newTemp(Ity_I32
);
5498 t7
= newTemp(Ity_I1
);
5499 t8
= newTemp(Ity_I1
);
5500 t9
= newTemp(Ity_I1
);
5501 t10
= newTemp(Ity_I1
);
5504 putIReg(rd
, getIReg(rt
));
5506 /* Shift bits 7..0 and 23..16. */
5507 assign(t0
, binop(Iop_Shl32
,
5512 assign(t1
, binop(Iop_CmpNE32
,
5516 mkU32(0x00000000)));
5517 assign(t2
, binop(Iop_CmpNE32
,
5521 mkU32(0xff000000)));
5522 assign(t7
, binop(Iop_CmpNE32
,
5526 mkU32(0x00000000)));
5527 assign(t8
, binop(Iop_CmpNE32
,
5532 /* Shift bits 15..8 and 31..24. */
5533 assign(t3
, binop(Iop_Shl32
,
5540 assign(t4
, binop(Iop_CmpNE32
,
5544 mkU32(0x00000000)));
5545 assign(t5
, binop(Iop_CmpNE32
,
5549 mkU32(0xff000000)));
5550 assign(t9
, binop(Iop_CmpNE32
,
5554 mkU32(0x00000000)));
5555 assign(t10
, binop(Iop_CmpNE32
,
5559 mkU32(0x0000ff00)));
5561 assign(t6
, binop(Iop_Or32
,
5585 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
5592 putIReg(rd
, binop(Iop_Or32
,
5600 mkU32(0x00ff00ff))));
5606 case 0x3: { /* SHRL.QB */
5607 DIP("shrl.qb r%u, r%u, %u", rd
, rt
, rs
);
5609 t0
= newTemp(Ity_I32
);
5610 t1
= newTemp(Ity_I8
);
5611 t2
= newTemp(Ity_I32
);
5612 t3
= newTemp(Ity_I8
);
5613 t4
= newTemp(Ity_I32
);
5614 t5
= newTemp(Ity_I8
);
5615 t6
= newTemp(Ity_I32
);
5616 t7
= newTemp(Ity_I8
);
5617 t9
= newTemp(Ity_I32
);
5619 assign(t9
, binop(Iop_And32
, getIReg(rs
), mkU32(0x7)));
5620 assign(t0
, unop(Iop_8Uto32
,
5622 unop(Iop_32to16
, getIReg(rt
)))));
5623 assign(t1
, unop(Iop_32to8
,
5626 unop(Iop_32to8
, mkexpr(t9
)))));
5628 assign(t2
, unop(Iop_8Uto32
,
5630 unop(Iop_32to16
, getIReg(rt
)))));
5631 assign(t3
, unop(Iop_32to8
,
5634 unop(Iop_32to8
, mkexpr(t9
)))));
5636 assign(t4
, unop(Iop_8Uto32
,
5638 unop(Iop_32HIto16
, getIReg(rt
)))));
5639 assign(t5
, unop(Iop_32to8
,
5642 unop(Iop_32to8
, mkexpr(t9
)))));
5644 assign(t6
, unop(Iop_8Uto32
,
5646 unop(Iop_32HIto16
, getIReg(rt
)))));
5647 assign(t7
, unop(Iop_32to8
,
5650 unop(Iop_32to8
, mkexpr(t9
)))));
5651 putIReg(rd
, IRExpr_ITE(binop(Iop_CmpEQ32
,
5665 case 0x2: { /* SHLLV.QB */
5666 DIP("shllv.qb r%u, r%u, r%u", rd
, rt
, rs
);
5668 t0
= newTemp(Ity_I32
);
5669 t1
= newTemp(Ity_I1
);
5670 t2
= newTemp(Ity_I1
);
5671 t3
= newTemp(Ity_I32
);
5672 t4
= newTemp(Ity_I1
);
5673 t5
= newTemp(Ity_I1
);
5674 t6
= newTemp(Ity_I32
);
5675 t7
= newTemp(Ity_I1
);
5676 t8
= newTemp(Ity_I1
);
5677 t9
= newTemp(Ity_I1
);
5678 t10
= newTemp(Ity_I1
);
5679 t11
= newTemp(Ity_I8
);
5681 assign(t11
, unop(Iop_32to8
,
5685 /* Shift bits 7..0 and 23..16. */
5686 assign(t0
, binop(Iop_Shl32
,
5691 assign(t1
, binop(Iop_CmpNE32
,
5695 mkU32(0x00000000)));
5696 assign(t2
, binop(Iop_CmpNE32
,
5700 mkU32(0xff000000)));
5701 assign(t7
, binop(Iop_CmpNE32
,
5705 mkU32(0x00000000)));
5706 assign(t8
, binop(Iop_CmpNE32
,
5711 /* Shift bits 15..8 and 31..24. */
5712 assign(t3
, binop(Iop_Shl32
,
5719 assign(t4
, binop(Iop_CmpNE32
,
5723 mkU32(0x00000000)));
5724 assign(t5
, binop(Iop_CmpNE32
,
5728 mkU32(0xff000000)));
5729 assign(t9
, binop(Iop_CmpNE32
,
5733 mkU32(0x00000000)));
5734 assign(t10
, binop(Iop_CmpNE32
,
5738 mkU32(0x0000ff00)));
5740 assign(t6
, binop(Iop_Or32
,
5764 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
5771 putIReg(rd
, IRExpr_ITE(binop(Iop_CmpEQ32
,
5772 unop(Iop_8Uto32
, mkexpr(t11
)),
5783 mkU32(0x00ff00ff)))));
5787 case 0x1: { /* SHRLV.QB */
5788 DIP("shrlv.qb r%u, r%u, r%u", rd
, rt
, rs
);
5790 t0
= newTemp(Ity_I8
);
5791 t1
= newTemp(Ity_I8
);
5792 t2
= newTemp(Ity_I8
);
5793 t3
= newTemp(Ity_I8
);
5795 assign(t0
, unop(Iop_32to8
,
5798 unop(Iop_32to8
, getIReg(rt
))),
5800 assign(t1
, unop(Iop_32to8
,
5807 assign(t2
, unop(Iop_32to8
,
5814 assign(t3
, unop(Iop_32to8
,
5823 binop(Iop_8HLto16
, mkexpr(t3
), mkexpr(t2
)),
5824 binop(Iop_8HLto16
, mkexpr(t1
), mkexpr(t0
))));
5828 case 0x4: { /* SHRA.QB */
5829 DIP("shra.qb r%u, r%u, %u", rd
, rt
, rs
);
5831 t0
= newTemp(Ity_I32
);
5832 t1
= newTemp(Ity_I32
);
5833 t2
= newTemp(Ity_I32
);
5834 t3
= newTemp(Ity_I32
);
5835 t4
= newTemp(Ity_I32
);
5836 t5
= newTemp(Ity_I32
);
5837 t6
= newTemp(Ity_I32
);
5838 t7
= newTemp(Ity_I32
);
5839 t8
= newTemp(Ity_I32
);
5840 t9
= newTemp(Ity_I32
);
5841 t10
= newTemp(Ity_I32
);
5842 t11
= newTemp(Ity_I32
);
5844 /* ========== GPR[rt]_31..24 ========== */
5848 unop(Iop_32HIto16
, getIReg(rt
)))));
5850 binop(Iop_Shr32
, mkexpr(t1
), mkU8(rs
)));
5856 IRExpr_ITE(binop(Iop_CmpEQ32
,
5864 binop(Iop_Sub8
, mkU8(0x8), mkU8(rs
)))));
5866 /* ========== GPR[rt]_23..16 ========== */
5870 unop(Iop_32HIto16
, getIReg(rt
)))));
5871 assign(t5
, binop(Iop_Shr32
, mkexpr(t4
), mkU8(rs
)));
5877 IRExpr_ITE(binop(Iop_CmpEQ32
,
5885 binop(Iop_Sub8
, mkU8(0x8), mkU8(rs
)))));
5887 /* ========== GPR[rt]_15..8 ========== */
5891 unop(Iop_32to16
, getIReg(rt
)))));
5892 assign(t8
, binop(Iop_Shr32
, mkexpr(t7
), mkU8(rs
)));
5898 IRExpr_ITE(binop(Iop_CmpEQ32
,
5906 binop(Iop_Sub8
, mkU8(0x8), mkU8(rs
)))));
5908 /* ========== GPR[rt]_7..0 ========== */
5912 unop(Iop_32to16
, getIReg(rt
)))));
5913 assign(t11
, binop(Iop_Shr32
, mkexpr(t10
), mkU8(rs
)));
5919 IRExpr_ITE(binop(Iop_CmpEQ32
,
5927 binop(Iop_Sub8
, mkU8(0x8), mkU8(rs
)))));
5932 unop(Iop_32to8
, mkexpr(t0
)),
5933 unop(Iop_32to8
, mkexpr(t3
))),
5935 unop(Iop_32to8
, mkexpr(t6
)),
5936 unop(Iop_32to8
, mkexpr(t9
)))));
5940 case 0x5: { /* SHRA_R.QB */
5941 DIP("shra_r.qb r%u, r%u, %u", rd
, rt
, rs
);
5943 t0
= newTemp(Ity_I32
);
5944 t1
= newTemp(Ity_I8
);
5945 t2
= newTemp(Ity_I32
);
5946 t3
= newTemp(Ity_I8
);
5947 t4
= newTemp(Ity_I32
);
5948 t5
= newTemp(Ity_I8
);
5949 t6
= newTemp(Ity_I32
);
5950 t7
= newTemp(Ity_I8
);
5953 putIReg(rd
, getIReg(rt
));
5955 assign(t0
, unop(Iop_8Sto32
,
5957 unop(Iop_32to16
, getIReg(rt
)))));
5958 assign(t1
, unop(Iop_32to8
,
5967 assign(t2
, unop(Iop_8Sto32
,
5969 unop(Iop_32to16
, getIReg(rt
)))));
5970 assign(t3
, unop(Iop_32to8
,
5979 assign(t4
, unop(Iop_8Sto32
,
5981 unop(Iop_32HIto16
, getIReg(rt
)))));
5982 assign(t5
, unop(Iop_32to8
,
5991 assign(t6
, unop(Iop_8Sto32
,
5993 unop(Iop_32HIto16
, getIReg(rt
)))));
5994 assign(t7
, unop(Iop_32to8
,
6002 putIReg(rd
, binop(Iop_16HLto32
,
6004 mkexpr(t7
), mkexpr(t5
)),
6006 mkexpr(t3
), mkexpr(t1
))));
6012 case 0x6: { /* SHRAV.QB */
6013 DIP("shrav.qb r%u, r%u, %u", rd
, rt
, rs
);
6016 t0
= newTemp(Ity_I32
);
6017 t1
= newTemp(Ity_I32
);
6018 t2
= newTemp(Ity_I32
);
6020 t3
= newTemp(Ity_I32
);
6021 t4
= newTemp(Ity_I32
);
6022 t5
= newTemp(Ity_I32
);
6024 t6
= newTemp(Ity_I32
);
6025 t7
= newTemp(Ity_I32
);
6026 t8
= newTemp(Ity_I32
);
6028 t9
= newTemp(Ity_I32
);
6029 t10
= newTemp(Ity_I32
);
6030 t11
= newTemp(Ity_I32
);
6032 /* ========== GPR[rt]_31..24 ========== */
6036 unop(Iop_32HIto16
, getIReg(rt
)))));
6040 unop(Iop_32to8
, binop(Iop_And32
,
6048 IRExpr_ITE(binop(Iop_CmpEQ32
,
6058 unop(Iop_32to8
, binop(Iop_And32
,
6063 /* ========== GPR[rt]_23..16 ========== */
6067 unop(Iop_32HIto16
, getIReg(rt
)))));
6071 unop(Iop_32to8
, binop(Iop_And32
,
6079 IRExpr_ITE(binop(Iop_CmpEQ32
,
6089 unop(Iop_32to8
, binop(Iop_And32
,
6094 /* ========== GPR[rt]_15..8 ========== */
6098 unop(Iop_32to16
, getIReg(rt
)))));
6102 unop(Iop_32to8
, binop(Iop_And32
,
6110 IRExpr_ITE(binop(Iop_CmpEQ32
,
6120 unop(Iop_32to8
, binop(Iop_And32
,
6125 /* ========== GPR[rt]_7..0 ========== */
6129 unop(Iop_32to16
, getIReg(rt
)))));
6133 unop(Iop_32to8
, binop(Iop_And32
,
6141 IRExpr_ITE(binop(Iop_CmpEQ32
,
6151 unop(Iop_32to8
, binop(Iop_And32
,
6160 IRExpr_ITE(binop(Iop_CmpEQ32
,
6169 IRExpr_ITE(binop(Iop_CmpEQ32
,
6179 IRExpr_ITE(binop(Iop_CmpEQ32
,
6188 IRExpr_ITE(binop(Iop_CmpEQ32
,
6199 case 0x7: { /* SHRAV_R.QB */
6200 DIP("shrav_r.qb r%u, r%u, r%u", rd
, rt
, rs
);
6202 t0
= newTemp(Ity_I32
);
6203 t1
= newTemp(Ity_I8
);
6204 t2
= newTemp(Ity_I32
);
6205 t3
= newTemp(Ity_I8
);
6206 t4
= newTemp(Ity_I32
);
6207 t5
= newTemp(Ity_I8
);
6208 t6
= newTemp(Ity_I32
);
6209 t7
= newTemp(Ity_I8
);
6210 t8
= newTemp(Ity_I8
);
6211 t9
= newTemp(Ity_I32
);
6213 assign(t9
, binop(Iop_And32
, getIReg(rs
), mkU32(0x7)));
6214 assign(t8
, unop(Iop_32to8
,
6215 binop(Iop_Sub32
, mkexpr(t9
), mkU32(0x1))));
6216 assign(t0
, unop(Iop_8Sto32
,
6218 unop(Iop_32to16
, getIReg(rt
)))));
6219 assign(t1
, unop(Iop_32to8
,
6229 assign(t2
, unop(Iop_8Sto32
,
6231 unop(Iop_32to16
, getIReg(rt
)))));
6232 assign(t3
, unop(Iop_32to8
,
6239 unop(Iop_32to8
, mkexpr(t9
)))));
6241 assign(t4
, unop(Iop_8Sto32
,
6243 unop(Iop_32HIto16
, getIReg(rt
)))));
6244 assign(t5
, unop(Iop_32to8
,
6251 unop(Iop_32to8
, mkexpr(t9
)))));
6253 assign(t6
, unop(Iop_8Sto32
,
6255 unop(Iop_32HIto16
, getIReg(rt
)))));
6256 assign(t7
, unop(Iop_32to8
,
6263 unop(Iop_32to8
, mkexpr(t9
)))));
6264 putIReg(rd
, IRExpr_ITE(binop(Iop_CmpEQ32
,
6278 case 0x8: { /* SHLL.PH */
6279 DIP("shll.ph r%u, r%u, %u", rd
, rt
, rs
);
6281 t0
= newTemp(Ity_I32
);
6282 t1
= newTemp(Ity_I32
);
6283 t2
= newTemp(Ity_I32
);
6284 t3
= newTemp(Ity_I32
);
6285 t4
= newTemp(Ity_I32
);
6286 t5
= newTemp(Ity_I32
);
6287 t6
= newTemp(Ity_I32
);
6288 t7
= newTemp(Ity_I32
);
6291 putIReg(rd
, getIReg(rt
));
6293 /* Shift lower 16 bits. */
6294 assign(t0
, binop(Iop_Shl32
,
6296 unop(Iop_32to16
, getIReg(rt
))),
6299 assign(t1
, unop(Iop_1Uto32
,
6305 assign(t2
, unop(Iop_1Uto32
,
6310 mkU32(0xffffffff))));
6311 assign(t3
, binop(Iop_And32
,
6314 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
6321 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
6333 /* Shift higher 16 bits. */
6334 assign(t4
, binop(Iop_Shl32
,
6336 unop(Iop_32HIto16
, getIReg(rt
))),
6339 assign(t5
, unop(Iop_1Uto32
,
6345 assign(t6
, unop(Iop_1Uto32
,
6350 mkU32(0xffffffff))));
6351 assign(t7
, binop(Iop_And32
,
6354 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
6361 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
6368 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
6382 putIReg(rd
, binop(Iop_16HLto32
,
6383 unop(Iop_32to16
, mkexpr(t4
)),
6384 unop(Iop_32to16
, mkexpr(t0
))));
6390 case 0x9: { /* SHRA.PH */
6391 DIP("shra.ph r%u, r%u, %u", rd
, rt
, rs
);
6393 t0
= newTemp(Ity_I32
);
6394 t1
= newTemp(Ity_I32
);
6397 putIReg(rd
, getIReg(rt
));
6399 assign(t0
, binop(Iop_Sar32
,
6401 unop(Iop_32to16
, getIReg(rt
))),
6403 assign(t1
, binop(Iop_Sar32
,
6405 unop(Iop_32HIto16
, getIReg(rt
))),
6407 putIReg(rd
, binop(Iop_16HLto32
,
6408 unop(Iop_32to16
, mkexpr(t1
)),
6409 unop(Iop_32to16
, mkexpr(t0
))));
6415 case 0xA: { /* SHLLV.PH */
6416 DIP("shllv.ph r%u, r%u, r%u", rd
, rt
, rs
);
6418 t0
= newTemp(Ity_I32
);
6419 t2
= newTemp(Ity_I32
);
6420 t3
= newTemp(Ity_I1
);
6421 t4
= newTemp(Ity_I1
);
6422 t5
= newTemp(Ity_I32
);
6423 t6
= newTemp(Ity_I32
);
6424 t7
= newTemp(Ity_I1
);
6425 t8
= newTemp(Ity_I1
);
6426 t9
= newTemp(Ity_I32
);
6427 t10
= newTemp(Ity_I32
);
6428 t11
= newTemp(Ity_I32
);
6429 t12
= newTemp(Ity_I1
);
6430 t13
= newTemp(Ity_I1
);
6432 assign(t0
, binop(Iop_And32
, getIReg(rs
), mkU32(0x0f)));
6434 /* Shift lower 16 bits. */
6435 assign(t2
, binop(Iop_Shl32
,
6437 unop(Iop_32to16
, getIReg(rt
))),
6438 unop(Iop_32to8
, mkexpr(t0
))));
6440 assign(t3
, binop(Iop_CmpNE32
,
6442 unop(Iop_32HIto16
, mkexpr(t2
))),
6443 mkU32(0x00000000)));
6444 assign(t4
, binop(Iop_CmpNE32
,
6446 unop(Iop_32HIto16
, mkexpr(t2
))),
6447 mkU32(0xffffffff)));
6448 assign(t10
, binop(Iop_And32
,
6449 unop(Iop_1Sto32
, mkexpr(t3
)),
6450 unop(Iop_1Sto32
, mkexpr(t4
))));
6451 assign(t5
, binop(Iop_Shr32
,
6456 assign(t12
, binop(Iop_CmpEQ32
,
6464 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
6470 IRExpr_ITE(mkexpr(t12
),
6476 /* Shift higher 16 bits. */
6477 assign(t6
, binop(Iop_Shl32
,
6479 unop(Iop_32HIto16
, getIReg(rt
))),
6480 unop(Iop_32to8
, mkexpr(t0
))));
6482 assign(t7
, binop(Iop_CmpNE32
,
6484 unop(Iop_32HIto16
, mkexpr(t6
))),
6485 mkU32(0x00000000)));
6486 assign(t8
, binop(Iop_CmpNE32
,
6488 unop(Iop_32HIto16
, mkexpr(t6
))),
6489 mkU32(0xffffffff)));
6490 assign(t11
, binop(Iop_And32
,
6491 unop(Iop_1Sto32
, mkexpr(t7
)),
6492 unop(Iop_1Sto32
, mkexpr(t8
))));
6494 assign(t9
, binop(Iop_Shr32
,
6499 assign(t13
, binop(Iop_CmpEQ32
,
6507 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
6513 IRExpr_ITE(mkexpr(t13
),
6520 putIReg(rd
, binop(Iop_16HLto32
,
6521 unop(Iop_32to16
, mkexpr(t6
)),
6522 unop(Iop_32to16
, mkexpr(t2
))));
6526 case 0xB: { /* SHRAV.PH */
6527 DIP("shrav.ph r%u, r%u, r%u", rd
, rt
, rs
);
6529 t0
= newTemp(Ity_I32
);
6530 t1
= newTemp(Ity_I1
);
6531 t2
= newTemp(Ity_I32
);
6532 t3
= newTemp(Ity_I32
);
6534 assign(t0
, binop(Iop_And32
, getIReg(rs
), mkU32(0x0f)));
6535 assign(t1
, binop(Iop_CmpEQ32
, mkexpr(t0
), mkU32(0x0)));
6536 assign(t2
, binop(Iop_Sar32
,
6538 unop(Iop_32to16
, getIReg(rt
))),
6539 unop(Iop_32to8
, mkexpr(t0
))));
6540 assign(t3
, binop(Iop_Sar32
,
6542 unop(Iop_32HIto16
, getIReg(rt
))),
6543 unop(Iop_32to8
, mkexpr(t0
))));
6546 IRExpr_ITE(mkexpr(t1
),
6547 unop(Iop_32HIto16
, getIReg(rt
)),
6548 unop(Iop_32to16
, mkexpr(t3
))),
6549 IRExpr_ITE(mkexpr(t1
),
6550 unop(Iop_32to16
, getIReg(rt
)),
6551 unop(Iop_32to16
, mkexpr(t2
)))));
6555 case 0xC: { /* SHLL_S.PH */
6556 DIP("shll_s.ph r%u, r%u, %u", rd
, rt
, rs
);
6558 t0
= newTemp(Ity_I32
);
6559 t1
= newTemp(Ity_I32
);
6560 t2
= newTemp(Ity_I32
);
6561 t3
= newTemp(Ity_I32
);
6562 t4
= newTemp(Ity_I32
);
6563 t5
= newTemp(Ity_I32
);
6564 t6
= newTemp(Ity_I32
);
6565 t7
= newTemp(Ity_I32
);
6566 t8
= newTemp(Ity_I32
);
6567 t9
= newTemp(Ity_I32
);
6568 t10
= newTemp(Ity_I32
);
6569 t11
= newTemp(Ity_I32
);
6570 t12
= newTemp(Ity_I32
);
6571 t13
= newTemp(Ity_I32
);
6572 t14
= newTemp(Ity_I32
);
6575 putIReg(rd
, getIReg(rt
));
6577 /* Shift lower 16 bits. */
6578 assign(t0
, binop(Iop_Shl32
,
6580 unop(Iop_32to16
, getIReg(rt
))),
6583 assign(t1
, unop(Iop_1Uto32
,
6589 assign(t2
, unop(Iop_1Uto32
,
6594 mkU32(0xffffffff))));
6595 assign(t3
, binop(Iop_And32
,
6598 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
6605 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
6618 IRExpr_ITE(binop(Iop_CmpEQ32
,
6621 IRExpr_ITE(binop(Iop_CmpEQ32
,
6630 mkU32(0x0000ffff))));
6632 IRExpr_ITE(binop(Iop_CmpEQ32
,
6638 mkU32(0x00008000))),
6640 IRExpr_ITE(binop(Iop_CmpEQ32
,
6646 mkU32(0x00008000))));
6647 /* Shift higher 16 bits. */
6648 assign(t4
, binop(Iop_Shl32
,
6650 unop(Iop_32HIto16
, getIReg(rt
))),
6653 assign(t5
, unop(Iop_1Uto32
,
6659 assign(t6
, unop(Iop_1Uto32
,
6664 mkU32(0xffffffff))));
6665 assign(t7
, binop(Iop_And32
,
6668 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
6675 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
6682 assign(t12
, binop(Iop_Shl32
,
6687 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
6696 assign(t13
, IRExpr_ITE(binop(Iop_CmpEQ32
,
6702 mkU32(0x80000000)));
6704 IRExpr_ITE(binop(Iop_CmpEQ32
,
6713 assign(t14
, IRExpr_ITE(binop(Iop_CmpEQ32
,
6719 mkU32(0x80000000)));
6721 IRExpr_ITE(binop(Iop_CmpEQ32
,
6732 putIReg(rd
, binop(Iop_Or32
,
6740 case 0xD: { /* SHRA_R.PH */
6741 DIP("shra.ph r%u, r%u, %u", rd
, rt
, rs
);
6743 t0
= newTemp(Ity_I32
);
6744 t1
= newTemp(Ity_I32
);
6747 putIReg(rd
, getIReg(rt
));
6749 assign(t0
, binop(Iop_Sar32
,
6758 assign(t1
, binop(Iop_Sar32
,
6767 putIReg(rd
, binop(Iop_16HLto32
,
6768 unop(Iop_32to16
, mkexpr(t1
)),
6769 unop(Iop_32to16
, mkexpr(t0
))));
6775 case 0xE: { /* SHLLV_S.PH */
6776 DIP("shllv_s.ph r%u, r%u, r%u", rd
, rt
, rs
);
6778 t0
= newTemp(Ity_I32
);
6779 t2
= newTemp(Ity_I32
);
6780 t3
= newTemp(Ity_I1
);
6781 t4
= newTemp(Ity_I1
);
6782 t5
= newTemp(Ity_I32
);
6783 t6
= newTemp(Ity_I32
);
6784 t7
= newTemp(Ity_I1
);
6785 t8
= newTemp(Ity_I1
);
6786 t9
= newTemp(Ity_I32
);
6787 t10
= newTemp(Ity_I32
);
6788 t11
= newTemp(Ity_I32
);
6789 t12
= newTemp(Ity_I1
);
6790 t13
= newTemp(Ity_I1
);
6791 t14
= newTemp(Ity_I16
);
6792 t15
= newTemp(Ity_I16
);
6793 t16
= newTemp(Ity_I16
);
6794 t17
= newTemp(Ity_I16
);
6796 assign(t0
, binop(Iop_And32
, getIReg(rs
), mkU32(0x0f)));
6798 /* Shift lower 16 bits. */
6799 assign(t2
, binop(Iop_Shl32
,
6801 unop(Iop_32to16
, getIReg(rt
))),
6802 unop(Iop_32to8
, mkexpr(t0
))));
6804 assign(t3
, binop(Iop_CmpNE32
,
6806 unop(Iop_32HIto16
, mkexpr(t2
))),
6807 mkU32(0x00000000)));
6808 assign(t4
, binop(Iop_CmpNE32
,
6810 unop(Iop_32HIto16
, mkexpr(t2
))),
6811 mkU32(0xffffffff)));
6812 assign(t10
, binop(Iop_And32
,
6813 unop(Iop_1Sto32
, mkexpr(t3
)),
6814 unop(Iop_1Sto32
, mkexpr(t4
))));
6815 assign(t5
, binop(Iop_Shr32
,
6820 assign(t12
, binop(Iop_CmpEQ32
,
6828 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
6834 IRExpr_ITE(mkexpr(t12
),
6840 assign(t14
, IRExpr_ITE(binop(Iop_CmpNE32
,
6845 assign(t15
, IRExpr_ITE(binop(Iop_CmpNE32
,
6849 IRExpr_ITE(mkexpr(t12
),
6853 /* Shift higher 16 bits. */
6854 assign(t6
, binop(Iop_Shl32
,
6856 unop(Iop_32HIto16
, getIReg(rt
))),
6857 unop(Iop_32to8
, mkexpr(t0
))));
6859 assign(t7
, binop(Iop_CmpNE32
,
6861 unop(Iop_32HIto16
, mkexpr(t6
))),
6862 mkU32(0x00000000)));
6863 assign(t8
, binop(Iop_CmpNE32
,
6865 unop(Iop_32HIto16
, mkexpr(t6
))),
6866 mkU32(0xffffffff)));
6867 assign(t11
, binop(Iop_And32
,
6868 unop(Iop_1Sto32
, mkexpr(t7
)),
6869 unop(Iop_1Sto32
, mkexpr(t8
))));
6871 assign(t9
, binop(Iop_Shr32
,
6876 assign(t13
, binop(Iop_CmpEQ32
,
6884 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
6890 IRExpr_ITE(mkexpr(t13
),
6897 assign(t16
, IRExpr_ITE(binop(Iop_CmpNE32
,
6902 assign(t17
, IRExpr_ITE(binop(Iop_CmpNE32
,
6906 IRExpr_ITE(mkexpr(t13
),
6911 putIReg(rd
, binop(Iop_16HLto32
, mkexpr(t17
), mkexpr(t15
)));
6915 case 0xF: { /* SHRAV_R.PH */
6916 DIP("shrav_r.ph r%u, r%u, r%u", rd
, rt
, rs
);
6918 t0
= newTemp(Ity_I32
);
6919 t1
= newTemp(Ity_I1
);
6920 t2
= newTemp(Ity_I8
);
6921 t3
= newTemp(Ity_I32
);
6922 t4
= newTemp(Ity_I32
);
6924 assign(t0
, binop(Iop_And32
, getIReg(rs
), mkU32(0x0f)));
6925 assign(t1
, binop(Iop_CmpEQ32
, mkexpr(t0
), mkU32(0x0)));
6926 assign(t2
, unop(Iop_32to8
,
6927 binop(Iop_Sub32
, mkexpr(t0
), mkU32(1))));
6929 assign(t3
, binop(Iop_Sar32
,
6932 unop(Iop_32to16
, getIReg(rt
))),
6936 unop(Iop_32to8
, mkexpr(t0
))));
6937 assign(t4
, binop(Iop_Sar32
,
6945 unop(Iop_32to8
, mkexpr(t0
))));
6947 putIReg(rd
, binop(Iop_16HLto32
,
6948 IRExpr_ITE(mkexpr(t1
),
6953 IRExpr_ITE(mkexpr(t1
),
6954 unop(Iop_32to16
, getIReg(rt
)),
6960 case 0x14: { /* SHLL_S.W */
6961 DIP("shll_s.w r%u, r%u, %u", rd
, rt
, rs
);
6963 t0
= newTemp(Ity_I32
);
6964 t1
= newTemp(Ity_I32
);
6965 t2
= newTemp(Ity_I32
);
6966 t3
= newTemp(Ity_I32
);
6967 t4
= newTemp(Ity_I32
);
6968 t5
= newTemp(Ity_I32
);
6971 putIReg(rd
, getIReg(rt
));
6973 /* t0-bits that will be discarded, sign extended to
6975 assign(t0
, binop(Iop_Sar32
,
6983 assign(t1
, IRExpr_ITE(binop(Iop_CmpEQ32
,
6989 mkU32(0x80000000)));
6991 assign(t2
, binop(Iop_Shl32
, getIReg(rt
), mkU8(rs
)));
6992 assign(t3
, IRExpr_ITE(binop(Iop_CmpEQ32
,
6998 mkU32(0x80000000))),
7002 assign(t4
, IRExpr_ITE(binop(Iop_CmpNE32
,
7005 IRExpr_ITE(binop(Iop_CmpNE32
,
7012 assign(t5
, IRExpr_ITE(binop(Iop_CmpNE32
,
7019 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
7024 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
7036 putIReg(rd
, mkexpr(t4
));
7042 case 0x15: { /* SHRA_R.W */
7043 DIP("shra_r.w r%u, r%u, %u", rd
, rt
, rs
);
7047 putIReg(rd
, getIReg(rt
));
7049 putIReg(rd
, binop(Iop_Add32
,
7051 getIReg(rt
), mkU8(rs
)),
7064 case 0x16: { /* SHLLV_S.W */
7065 DIP("shllv_s.w r%u, r%u, r%u", rd
, rt
, rs
);
7067 t0
= newTemp(Ity_I32
);
7068 t1
= newTemp(Ity_I1
);
7069 t2
= newTemp(Ity_I32
);
7070 t3
= newTemp(Ity_I64
);
7071 t4
= newTemp(Ity_I1
);
7072 t5
= newTemp(Ity_I1
);
7073 t6
= newTemp(Ity_I32
);
7074 t7
= newTemp(Ity_I1
);
7075 t8
= newTemp(Ity_I32
);
7077 /* Check if shift amount is zero. */
7078 assign(t0
, binop(Iop_And32
, getIReg(rs
), mkU32(0x1f)));
7079 assign(t1
, binop(Iop_CmpEQ32
, mkexpr(t0
), mkU32(0x0)));
7081 /* t2 = sign of the input value. */
7082 assign(t2
, binop(Iop_Shr32
,
7087 /* Shift left input value and check for overflow. */
7088 assign(t3
, binop(Iop_Shl64
,
7089 unop(Iop_32Sto64
, getIReg(rt
)),
7090 unop(Iop_32to8
, mkexpr(t0
))));
7091 assign(t4
, binop(Iop_CmpNE32
,
7092 unop(Iop_64HIto32
, mkexpr(t3
)),
7093 mkU32(0x00000000)));
7094 assign(t5
, binop(Iop_CmpNE32
,
7095 unop(Iop_64HIto32
, mkexpr(t3
)),
7096 mkU32(0xffffffff)));
7097 assign(t6
, binop(Iop_And32
,
7098 unop(Iop_1Uto32
, mkexpr(t4
)),
7099 unop(Iop_1Uto32
, mkexpr(t5
))));
7100 assign(t7
, binop(Iop_CmpEQ32
,
7108 unop(Iop_64to32
, mkexpr(t3
)),
7112 putDSPControl(IRExpr_ITE(unop(Iop_32to1
, mkexpr(t6
)),
7116 IRExpr_ITE(mkexpr(t7
),
7123 assign(t8
, IRExpr_ITE(unop(Iop_32to1
,
7126 mkU32(0x7fffffff)));
7127 putIReg(rd
, IRExpr_ITE(unop(Iop_32to1
, mkexpr(t6
)),
7128 IRExpr_ITE(unop(Iop_32to1
,
7132 IRExpr_ITE(mkexpr(t7
),
7139 case 0x17: { /* SHRAV_R.W */
7140 DIP("shrav_r.w r%u, r%u, r%u", rd
, rt
, rs
);
7142 t0
= newTemp(Ity_I32
);
7143 t1
= newTemp(Ity_I1
);
7144 t2
= newTemp(Ity_I8
);
7146 assign(t0
, binop(Iop_And32
, getIReg(rs
), mkU32(0x1f)));
7147 assign(t1
, binop(Iop_CmpEQ32
, mkexpr(t0
), mkU32(0x0)));
7148 assign(t2
, unop(Iop_32to8
,
7149 binop(Iop_Sub32
, mkexpr(t0
), mkU32(1))));
7151 putIReg(rd
, IRExpr_ITE(mkexpr(t1
),
7163 case 0x19: { /* SHRL.PH */
7164 DIP("shrl.ph r%u, r%u, %u", rd
, rt
, rs
);
7166 t0
= newTemp(Ity_I32
);
7167 t1
= newTemp(Ity_I32
);
7168 assign(t0
, binop(Iop_Shr32
,
7170 unop(Iop_32to16
, getIReg(rt
))),
7172 assign(t1
, binop(Iop_Shr32
,
7174 unop(Iop_32HIto16
, getIReg(rt
))),
7176 putIReg(rd
, binop(Iop_16HLto32
,
7177 unop(Iop_32to16
, mkexpr(t1
)),
7178 unop(Iop_32to16
, mkexpr(t0
))));
7182 case 0x1B: { /* SHRLV.PH */
7183 DIP("shrlv.ph r%u, r%u, r%u", rd
, rt
, rs
);
7185 t0
= newTemp(Ity_I32
);
7186 t1
= newTemp(Ity_I1
);
7187 t2
= newTemp(Ity_I32
);
7188 t3
= newTemp(Ity_I32
);
7189 t4
= newTemp(Ity_I16
);
7190 t5
= newTemp(Ity_I16
);
7192 /* Get shift amount from lower 5 bits of rs
7193 and check if it is zero. */
7194 assign(t0
, binop(Iop_And32
, getIReg(rs
), mkU32(0x0f)));
7195 assign(t1
, binop(Iop_CmpEQ32
, mkexpr(t0
), mkU32(0x0)));
7197 assign(t2
, binop(Iop_Shr32
,
7199 unop(Iop_32to16
, getIReg(rt
))),
7200 unop(Iop_32to8
, mkexpr(t0
))));
7201 assign(t3
, binop(Iop_Shr32
,
7203 unop(Iop_32HIto16
, getIReg(rt
))),
7204 unop(Iop_32to8
, mkexpr(t0
))));
7206 assign(t4
, IRExpr_ITE(mkexpr(t1
),
7207 unop(Iop_32HIto16
, getIReg(rt
)),
7208 unop(Iop_32to16
, mkexpr(t3
))));
7209 assign(t5
, IRExpr_ITE(mkexpr(t1
),
7210 unop(Iop_32to16
, getIReg(rt
)),
7211 unop(Iop_32to16
, mkexpr(t2
))));
7212 putIReg(rd
, binop(Iop_16HLto32
, mkexpr(t4
), mkexpr(t5
)));
7223 static UInt
disDSPInstr_MIPS_WRK_Special3_ADDUH_QB( UInt cins
)
7225 IRTemp t0
, t1
= 0, t2
, t3
, t4
, t5
, t6
, t7
, t8
, t9
, t10
, t11
, t12
;
7226 UInt rs
, rt
, rd
, sa
;
7234 case 0x00: { /* ADDUH.QB */
7235 DIP("adduh.qb r%u, r%u, r%u", rd
, rs
, rt
);
7237 t0
= newTemp(Ity_I32
);
7239 assign(t0
, binop(Iop_HAdd8Ux4
, getIReg(rs
), getIReg(rt
)));
7241 putIReg(rd
, mkexpr(t0
));
7245 case 0x1: { /* SUBUH.QB */
7246 DIP("subuh.qb r%u, r%u, r%u", rd
, rs
, rt
);
7248 t0
= newTemp(Ity_I32
);
7250 assign(t0
, binop(Iop_HSub8Ux4
, getIReg(rs
), getIReg(rt
)));
7252 putIReg(rd
, mkexpr(t0
));
7256 case 0x02: { /* ADDUH_R.QB */
7257 DIP("adduh_r.qb r%u, r%u, r%u", rd
, rs
, rt
);
7259 t0
= newTemp(Ity_I32
);
7260 t1
= newTemp(Ity_I32
);
7261 t2
= newTemp(Ity_I8
);
7262 t3
= newTemp(Ity_I32
);
7263 t4
= newTemp(Ity_I32
);
7264 t5
= newTemp(Ity_I8
);
7265 t6
= newTemp(Ity_I32
);
7266 t7
= newTemp(Ity_I32
);
7267 t8
= newTemp(Ity_I8
);
7268 t9
= newTemp(Ity_I32
);
7269 t10
= newTemp(Ity_I32
);
7270 t11
= newTemp(Ity_I8
);
7272 /* Extract input bytes, add values, add 1 and half the
7274 assign(t0
, unop(Iop_8Uto32
,
7276 unop(Iop_32to16
, getIReg(rs
)))));
7277 assign(t1
, unop(Iop_8Uto32
,
7279 unop(Iop_32to16
, getIReg(rt
)))));
7280 assign(t2
, unop(Iop_16to8
,
7290 assign(t3
, unop(Iop_8Uto32
,
7292 unop(Iop_32to16
, getIReg(rs
)))));
7293 assign(t4
, unop(Iop_8Uto32
,
7295 unop(Iop_32to16
, getIReg(rt
)))));
7296 assign(t5
, unop(Iop_16to8
,
7306 assign(t6
, unop(Iop_8Uto32
,
7308 unop(Iop_32HIto16
, getIReg(rs
)))));
7309 assign(t7
, unop(Iop_8Uto32
,
7311 unop(Iop_32HIto16
, getIReg(rt
)))));
7312 assign(t8
, unop(Iop_16to8
,
7322 assign(t9
, unop(Iop_8Uto32
,
7324 unop(Iop_32HIto16
, getIReg(rs
)))));
7325 assign(t10
, unop(Iop_8Uto32
,
7327 unop(Iop_32HIto16
, getIReg(rt
)))));
7328 assign(t11
, unop(Iop_16to8
,
7338 putIReg(rd
, binop(Iop_16HLto32
,
7340 mkexpr(t11
), mkexpr(t8
)),
7342 mkexpr(t5
), mkexpr(t2
))));
7346 case 0x3: { /* SUBUH_R.QB */
7347 DIP("subuh_r.qb r%u, r%u, r%u", rd
, rs
, rt
);
7349 t1
= newTemp(Ity_I32
);
7350 t2
= newTemp(Ity_I32
);
7351 t3
= newTemp(Ity_I32
);
7352 t4
= newTemp(Ity_I32
);
7353 t5
= newTemp(Ity_I32
);
7354 t6
= newTemp(Ity_I32
);
7355 t7
= newTemp(Ity_I32
);
7356 t8
= newTemp(Ity_I32
);
7357 t9
= newTemp(Ity_I8
);
7358 t10
= newTemp(Ity_I8
);
7359 t11
= newTemp(Ity_I8
);
7360 t12
= newTemp(Ity_I8
);
7362 /* Extract each byte of rs and rt. */
7363 assign(t1
, unop(Iop_8Uto32
,
7365 unop(Iop_32to16
, getIReg(rs
)))));
7366 assign(t2
, unop(Iop_8Uto32
,
7368 unop(Iop_32to16
, getIReg(rs
)))));
7369 assign(t3
, unop(Iop_8Uto32
,
7371 unop(Iop_32HIto16
, getIReg(rs
)))));
7372 assign(t4
, unop(Iop_8Uto32
,
7374 unop(Iop_32HIto16
, getIReg(rs
)))));
7376 assign(t5
, unop(Iop_8Uto32
,
7378 unop(Iop_32to16
, getIReg(rt
)))));
7379 assign(t6
, unop(Iop_8Uto32
,
7381 unop(Iop_32to16
, getIReg(rt
)))));
7382 assign(t7
, unop(Iop_8Uto32
,
7384 unop(Iop_32HIto16
, getIReg(rt
)))));
7385 assign(t8
, unop(Iop_8Uto32
,
7387 unop(Iop_32HIto16
, getIReg(rt
)))));
7389 /* Add 1 to each resulting byte and half the results. */
7390 assign(t9
, unop(Iop_16to8
,
7399 assign(t10
, unop(Iop_16to8
,
7408 assign(t11
, unop(Iop_16to8
,
7417 assign(t12
, unop(Iop_16to8
,
7427 putIReg(rd
, binop(Iop_16HLto32
,
7429 mkexpr(t12
), mkexpr(t11
)),
7431 mkexpr(t10
), mkexpr(t9
))));
7435 case 0x8: { /* ADDQH.PH */
7436 DIP("addqh.ph r%u, r%u, r%u", rd
, rs
, rt
);
7438 t0
= newTemp(Ity_I32
);
7439 t1
= newTemp(Ity_I16
);
7440 t2
= newTemp(Ity_I32
);
7441 t3
= newTemp(Ity_I16
);
7443 /* Add lower halfs of rs and rt
7444 and right shift the result by 1. */
7445 assign(t0
, binop(Iop_Add32
,
7447 unop(Iop_32to16
, getIReg(rs
))),
7449 unop(Iop_32to16
, getIReg(rt
)))));
7450 assign(t1
, unop(Iop_32to16
,
7456 /* Add higher halfs of rs and rt
7457 and right shift the result by 1. */
7458 assign(t2
, binop(Iop_Add32
,
7460 unop(Iop_32HIto16
, getIReg(rs
))),
7462 unop(Iop_32HIto16
, getIReg(rt
)))));
7463 assign(t3
, unop(Iop_32to16
,
7469 putIReg(rd
, binop(Iop_16HLto32
, mkexpr(t3
), mkexpr(t1
)));
7473 case 0x9: { /* SUBQH.PH */
7474 DIP("subqh.ph r%u, r%u, r%u", rd
, rs
, rt
);
7477 putIReg(rd
, binop(Iop_HSub16Sx2
,
7478 getIReg(rs
), getIReg(rt
)));
7482 case 0xA: {/* ADDQH_R.PH */
7483 DIP("addqh_r.ph r%u, r%u, r%u", rd
, rs
, rt
);
7485 t0
= newTemp(Ity_I32
);
7486 t1
= newTemp(Ity_I16
);
7487 t2
= newTemp(Ity_I32
);
7488 t3
= newTemp(Ity_I16
);
7490 /* Add lower halfs of rs and rt, add 1
7491 and right shift the result by 1. */
7492 assign(t0
, binop(Iop_Add32
,
7494 unop(Iop_32to16
, getIReg(rs
))),
7496 unop(Iop_32to16
, getIReg(rt
)))));
7497 assign(t1
, unop(Iop_32to16
,
7505 /* Add higher halfs of rs and rt, add 1
7506 and right shift the result by 1. */
7507 assign(t2
, binop(Iop_Add32
,
7509 unop(Iop_32HIto16
, getIReg(rs
))),
7511 unop(Iop_32HIto16
, getIReg(rt
)))));
7512 assign(t3
, unop(Iop_32to16
,
7521 putIReg(rd
, binop(Iop_16HLto32
, mkexpr(t3
), mkexpr(t1
)));
7525 case 0xB: { /* SUBQH_R.PH */
7526 DIP("subqh_r.ph r%u, r%u, r%u", rd
, rs
, rt
);
7528 t0
= newTemp(Ity_I32
);
7529 t1
= newTemp(Ity_I16
);
7530 t2
= newTemp(Ity_I32
);
7531 t3
= newTemp(Ity_I16
);
7533 /* Sub lower halfs of rs and rt, add 1
7534 and right shift the result by 1. */
7535 assign(t0
, binop(Iop_Sub32
,
7537 unop(Iop_32to16
, getIReg(rs
))),
7539 unop(Iop_32to16
, getIReg(rt
)))));
7540 assign(t1
, unop(Iop_32to16
,
7548 /* Sub higher halfs of rs and rt, add 1
7549 and right shift the result by 1. */
7550 assign(t2
, binop(Iop_Sub32
,
7552 unop(Iop_32HIto16
, getIReg(rs
))),
7554 unop(Iop_32HIto16
, getIReg(rt
)))));
7555 assign(t3
, unop(Iop_32to16
,
7564 putIReg(rd
, binop(Iop_16HLto32
, mkexpr(t3
), mkexpr(t1
)));
7568 case 0xC: { /* MUL.PH */
7569 DIP("mul.ph r%u, r%u, r%u", rd
, rs
, rt
);
7571 t0
= newTemp(Ity_I32
);
7572 t1
= newTemp(Ity_I32
);
7573 t2
= newTemp(Ity_I32
);
7578 unop(Iop_32HIto16
, getIReg(rs
))),
7580 unop(Iop_32HIto16
, getIReg(rt
)))));
7581 /* DSP Control flag. */
7582 putDSPControl(IRExpr_ITE(unop(Iop_Not1
,
7589 IRExpr_ITE(binop(Iop_CmpLT32S
,
7602 unop(Iop_32to16
, getIReg(rs
))),
7604 unop(Iop_32to16
, getIReg(rt
)))));
7605 /* DSP Control flag. */
7606 putDSPControl(IRExpr_ITE(unop(Iop_Not1
,
7613 IRExpr_ITE(binop(Iop_CmpLT32S
,
7623 assign(t2
, binop(Iop_16HLto32
,
7624 unop(Iop_32to16
, mkexpr(t0
)),
7625 unop(Iop_32to16
, mkexpr(t1
))));
7626 putIReg(rd
, mkexpr(t2
));
7630 case 0xE: { /* MUL_S.PH */
7631 DIP("mul_s.ph r%u r%u, r%u", rd
, rs
, rt
);
7634 t0
= newTemp(Ity_I32
);
7635 t1
= newTemp(Ity_I32
);
7636 t2
= newTemp(Ity_I32
);
7637 t3
= newTemp(Ity_I32
);
7638 t4
= newTemp(Ity_I32
);
7640 /* t0 - signed intermediate result. */
7644 unop(Iop_32HIto16
, getIReg(rs
))),
7646 unop(Iop_32HIto16
, getIReg(rt
)))));
7649 IRExpr_ITE(unop(Iop_Not1
,
7654 IRExpr_ITE(binop(Iop_CmpLT32S
,
7660 /* DSP Control flag. */
7661 putDSPControl(IRExpr_ITE(unop(Iop_Not1
,
7668 IRExpr_ITE(binop(Iop_CmpLT32S
,
7678 /* t2 - signed intermediate result. */
7679 assign(t2
, binop(Iop_Mul32
,
7681 unop(Iop_32to16
, getIReg(rs
))),
7683 unop(Iop_32to16
, getIReg(rt
)))));
7685 assign(t3
, IRExpr_ITE(unop(Iop_Not1
,
7690 IRExpr_ITE(binop(Iop_CmpLT32S
,
7696 /* DSP Control flag. */
7697 putDSPControl(IRExpr_ITE(unop(Iop_Not1
,
7704 IRExpr_ITE(binop(Iop_CmpLT32S
,
7714 assign(t4
, binop(Iop_16HLto32
,
7715 unop(Iop_32to16
, mkexpr(t1
)),
7716 unop(Iop_32to16
, mkexpr(t3
))));
7717 putIReg(rd
, mkexpr(t4
));
7721 case 0x10: { /* ADDQH.W */
7722 DIP("addqh.w r%u, r%u, r%u", rd
, rs
, rt
);
7724 t0
= newTemp(Ity_I64
);
7725 t1
= newTemp(Ity_I64
);
7727 assign(t0
, binop(Iop_Add64
,
7728 unop(Iop_32Sto64
, getIReg(rs
)),
7729 unop(Iop_32Sto64
, getIReg(rt
))));
7730 assign(t1
, binop(Iop_And64
,
7732 mkU64(0x00000001fffffffeULL
)));
7733 putIReg(rd
, unop(Iop_64to32
,
7734 binop(Iop_Shr64
, mkexpr(t1
), mkU8(0x1))));
7738 case 0x11: { /* SUBQH.W */
7739 DIP("subqh.w r%u, r%u, r%u", rd
, rs
, rt
);
7741 t0
= newTemp(Ity_I64
);
7742 t1
= newTemp(Ity_I64
);
7744 assign(t0
, binop(Iop_Sub64
,
7745 unop(Iop_32Sto64
, getIReg(rs
)),
7746 unop(Iop_32Sto64
, getIReg(rt
))));
7747 assign(t1
, binop(Iop_And64
,
7749 mkU64(0x00000001fffffffeULL
)));
7750 putIReg(rd
, unop(Iop_64to32
,
7751 binop(Iop_Shr64
, mkexpr(t1
), mkU8(0x1))));
7755 case 0x12: { /* ADDQH_R.W */
7756 DIP("addqh_r.w r%u, r%u, r%u", rd
, rs
, rt
);
7758 t0
= newTemp(Ity_I64
);
7759 t1
= newTemp(Ity_I64
);
7760 t2
= newTemp(Ity_I64
);
7762 assign(t0
, binop(Iop_Add64
,
7763 unop(Iop_32Sto64
, getIReg(rs
)),
7764 unop(Iop_32Sto64
, getIReg(rt
))));
7765 assign(t1
, binop(Iop_Add64
,
7767 mkU64(0x0000000000000001ULL
)));
7768 assign(t2
, binop(Iop_And64
,
7770 mkU64(0x00000001fffffffeULL
)));
7771 putIReg(rd
, unop(Iop_64to32
,
7772 binop(Iop_Shr64
, mkexpr(t2
), mkU8(0x1))));
7776 case 0x13: { /* SUBQH_R.W */
7777 DIP("subqh_r.w r%u, r%u, r%u", rd
, rs
, rt
);
7779 t0
= newTemp(Ity_I64
);
7780 t1
= newTemp(Ity_I64
);
7781 t2
= newTemp(Ity_I64
);
7783 assign(t0
, binop(Iop_Sub64
,
7784 unop(Iop_32Sto64
, getIReg(rs
)),
7785 unop(Iop_32Sto64
, getIReg(rt
))));
7786 assign(t1
, binop(Iop_Add64
,
7788 mkU64(0x0000000000000001ULL
)));
7789 assign(t2
, binop(Iop_And64
,
7791 mkU64(0x00000001fffffffeULL
)));
7792 putIReg(rd
, unop(Iop_64to32
,
7793 binop(Iop_Shr64
, mkexpr(t2
), mkU8(0x1))));
7797 case 0x16: { /* MULQ_S.W */
7798 DIP("mulq_s.w r%u, r%u, r%u", rd
, rs
, rt
);
7800 t0
= newTemp(Ity_I64
);
7801 t1
= newTemp(Ity_I1
);
7802 t2
= newTemp(Ity_I1
);
7804 assign(t0
, binop(Iop_Shl64
,
7806 getIReg(rt
), getIReg(rs
)),
7808 assign(t1
, binop(Iop_CmpEQ32
,
7809 getIReg(rt
), mkU32(0x80000000)));
7810 assign(t2
, binop(Iop_CmpEQ32
,
7811 getIReg(rs
), mkU32(0x80000000)));
7813 putDSPControl(IRExpr_ITE(mkexpr(t1
),
7814 IRExpr_ITE(mkexpr(t2
),
7821 putIReg(rd
, IRExpr_ITE(mkexpr(t1
),
7822 IRExpr_ITE(mkexpr(t2
),
7826 unop(Iop_64HIto32
, mkexpr(t0
))));
7830 case 0x17: { /* MULQ_RS.W */
7831 DIP("mulq_rs.w r%u, r%u, r%u", rd
, rs
, rt
);
7833 t0
= newTemp(Ity_I64
);
7834 t1
= newTemp(Ity_I1
);
7835 t2
= newTemp(Ity_I1
);
7837 assign(t0
, binop(Iop_Add64
,
7843 mkU64(0x0000000080000000ULL
)));
7845 binop(Iop_CmpEQ32
, getIReg(rt
), mkU32(0x80000000)));
7847 binop(Iop_CmpEQ32
, getIReg(rs
), mkU32(0x80000000)));
7848 putDSPControl(IRExpr_ITE(mkexpr(t1
),
7849 IRExpr_ITE(mkexpr(t2
),
7856 putIReg(rd
, IRExpr_ITE(mkexpr(t1
),
7857 IRExpr_ITE(mkexpr(t2
),
7861 unop(Iop_64HIto32
, mkexpr(t0
))));
7872 static UInt
disDSPInstr_MIPS_WRK_Special3_DPAW_PH( UInt cins
)
7874 IRTemp t0
, t1
= 0, t2
, t3
, t4
, t5
, t6
, t7
, t8
, t9
, t10
;
7875 UInt rs
, rt
, sa
, ac
;
7880 ac
= get_acNo(cins
);
7883 case 0x0: { /* DPA.W.PH */
7884 DIP("dpa.w.ph ac%u, r%u, r%u", ac
, rs
, rt
);
7887 t0
= newTemp(Ity_I64
);
7888 t1
= newTemp(Ity_I64
);
7889 t2
= newTemp(Ity_I64
);
7895 unop(Iop_32HIto16
, getIReg(rs
))),
7897 unop(Iop_32HIto16
, getIReg(rt
))))));
7902 unop(Iop_32to16
, getIReg(rs
))),
7904 unop(Iop_32to16
, getIReg(rt
))))));
7908 binop(Iop_Add64
, mkexpr(t0
), mkexpr(t1
))));
7909 putAcc(ac
, mkexpr(t2
));
7913 case 0x1: { /* DPS.W.PH */
7914 DIP("dps.w.ph ac%u, r%u, r%u", ac
, rs
, rt
);
7917 t0
= newTemp(Ity_I64
);
7918 t1
= newTemp(Ity_I64
);
7919 t2
= newTemp(Ity_I64
);
7925 unop(Iop_32HIto16
, getIReg(rs
))),
7927 unop(Iop_32HIto16
, getIReg(rt
))))));
7932 unop(Iop_32to16
, getIReg(rs
))),
7934 unop(Iop_32to16
, getIReg(rt
))))));
7938 binop(Iop_Add64
, mkexpr(t0
), mkexpr(t1
))));
7939 putAcc(ac
, mkexpr(t2
));
7943 case 0x2: { /* MULSA.W.PH */
7944 DIP("mulsa.w.ph ac%u, r%u, r%u", ac
, rs
, rt
);
7946 t0
= newTemp(Ity_I32
);
7947 t1
= newTemp(Ity_I32
);
7948 t2
= newTemp(Ity_I32
);
7949 t3
= newTemp(Ity_I1
);
7950 t4
= newTemp(Ity_I64
);
7952 assign(t4
, getAcc(ac
));
7953 assign(t0
, binop(Iop_Mul32
,
7955 unop(Iop_32to16
, getIReg(rt
))),
7957 unop(Iop_32to16
, getIReg(rs
)))));
7958 assign(t1
, binop(Iop_Mul32
,
7960 unop(Iop_32HIto16
, getIReg(rt
))),
7962 unop(Iop_32HIto16
, getIReg(rs
)))));
7963 assign(t2
, binop(Iop_Sub32
, mkexpr(t1
), mkexpr(t0
)));
7964 putAcc(ac
, binop(Iop_Add64
,
7966 unop(Iop_32Sto64
, mkexpr(t2
))));
7970 case 0x3: { /* DPAU.H.QBL */
7971 DIP("dpau.h.qbl ac%u, r%u, r%u", ac
, rs
, rt
);
7973 t0
= newTemp(Ity_I32
);
7974 t1
= newTemp(Ity_I32
);
7975 t2
= newTemp(Ity_I64
);
7976 t3
= newTemp(Ity_I64
);
7982 unop(Iop_32HIto16
, getIReg(rs
)))),
7985 unop(Iop_32HIto16
, getIReg(rt
))))));
7990 unop(Iop_32HIto16
, getIReg(rs
)))),
7993 unop(Iop_32HIto16
, getIReg(rt
))))));
8000 binop(Iop_Add64
, getAcc(ac
), mkexpr(t2
)));
8001 putAcc(ac
, mkexpr(t3
));
8005 case 0x4: { /* DPAQ_S.W.PH */
8006 DIP("dpaq_s.w.ph ac%u, r%u, r%u", ac
, rs
, rt
);
8008 t0
= newTemp(Ity_I64
);
8009 t1
= newTemp(Ity_I64
);
8010 t2
= newTemp(Ity_I1
);
8011 t3
= newTemp(Ity_I1
);
8012 t4
= newTemp(Ity_I64
);
8013 t5
= newTemp(Ity_I64
);
8014 t6
= newTemp(Ity_I1
);
8015 t7
= newTemp(Ity_I1
);
8016 t8
= newTemp(Ity_I64
);
8017 t9
= newTemp(Ity_I64
);
8019 assign(t0
, getAcc(ac
));
8021 assign(t1
, binop(Iop_Shl64
,
8030 assign(t2
, binop(Iop_CmpEQ32
,
8032 unop(Iop_32HIto16
, getIReg(rs
))),
8033 mkU32(0x00008000)));
8034 assign(t3
, binop(Iop_CmpEQ32
,
8036 unop(Iop_32HIto16
, getIReg(rt
))),
8037 mkU32(0x00008000)));
8039 IRExpr_ITE(mkexpr(t2
),
8040 IRExpr_ITE(mkexpr(t3
),
8041 mkU64(0x000000007fffffffULL
),
8045 putDSPControl(IRExpr_ITE(mkexpr(t2
),
8046 IRExpr_ITE(mkexpr(t3
),
8057 assign(t5
, binop(Iop_Shl64
,
8060 unop(Iop_32to16
, getIReg(rs
))),
8062 unop(Iop_32to16
, getIReg(rt
)))
8065 assign(t6
, binop(Iop_CmpEQ32
,
8067 unop(Iop_32to16
, getIReg(rs
))),
8068 mkU32(0x00008000)));
8069 assign(t7
, binop(Iop_CmpEQ32
,
8071 unop(Iop_32to16
, getIReg(rt
))),
8072 mkU32(0x00008000)));
8074 IRExpr_ITE(mkexpr(t6
),
8075 IRExpr_ITE(mkexpr(t7
),
8076 mkU64(0x000000007fffffffULL
),
8080 putDSPControl(IRExpr_ITE(mkexpr(t6
),
8081 IRExpr_ITE(mkexpr(t7
),
8092 assign(t9
, binop(Iop_Add64
,
8093 binop(Iop_Add64
, mkexpr(t4
), mkexpr(t8
)),
8095 putAcc(ac
, mkexpr(t9
));
8099 case 0x5: { /* DPSQ_S.W.PH */
8100 DIP("dpsq_s.w.ph ac%u r%u, r%u", ac
, rs
, rt
);
8102 t0
= newTemp(Ity_I64
);
8103 t1
= newTemp(Ity_I64
);
8104 t2
= newTemp(Ity_I1
);
8105 t3
= newTemp(Ity_I1
);
8106 t4
= newTemp(Ity_I64
);
8107 t5
= newTemp(Ity_I64
);
8108 t6
= newTemp(Ity_I1
);
8109 t7
= newTemp(Ity_I1
);
8110 t8
= newTemp(Ity_I64
);
8111 t9
= newTemp(Ity_I64
);
8113 assign(t0
, getAcc(ac
));
8115 assign(t1
, binop(Iop_Shl64
,
8124 assign(t2
, binop(Iop_CmpEQ32
,
8126 unop(Iop_32HIto16
, getIReg(rs
))),
8127 mkU32(0x00008000)));
8128 assign(t3
, binop(Iop_CmpEQ32
,
8130 unop(Iop_32HIto16
, getIReg(rt
))),
8131 mkU32(0x00008000)));
8133 IRExpr_ITE(mkexpr(t2
),
8134 IRExpr_ITE(mkexpr(t3
),
8135 mkU64(0x000000007fffffffULL
),
8139 putDSPControl(IRExpr_ITE(mkexpr(t2
),
8140 IRExpr_ITE(mkexpr(t3
),
8155 unop(Iop_32to16
, getIReg(rs
))),
8157 unop(Iop_32to16
, getIReg(rt
)))),
8159 assign(t6
, binop(Iop_CmpEQ32
,
8161 unop(Iop_32to16
, getIReg(rs
))),
8162 mkU32(0x00008000)));
8163 assign(t7
, binop(Iop_CmpEQ32
,
8165 unop(Iop_32to16
, getIReg(rt
))),
8166 mkU32(0x00008000)));
8168 IRExpr_ITE(mkexpr(t6
),
8169 IRExpr_ITE(mkexpr(t7
),
8170 mkU64(0x000000007fffffffULL
),
8174 putDSPControl(IRExpr_ITE(mkexpr(t6
),
8175 IRExpr_ITE(mkexpr(t7
),
8189 binop(Iop_Add64
, mkexpr(t4
), mkexpr(t8
))));
8190 putAcc(ac
, mkexpr(t9
));
8194 case 0x6: { /* MULSAQ_S.W.PH */
8195 DIP("mulsaq_s.w.ph ac%u r%u, r%u", ac
, rs
, rt
);
8198 t0
= newTemp(Ity_I32
);
8199 t1
= newTemp(Ity_I32
);
8200 t2
= newTemp(Ity_I32
);
8201 t3
= newTemp(Ity_I32
);
8202 t4
= newTemp(Ity_I32
);
8203 t5
= newTemp(Ity_I32
);
8204 t6
= newTemp(Ity_I64
);
8205 t7
= newTemp(Ity_I64
);
8206 t8
= newTemp(Ity_I32
);
8207 t9
= newTemp(Ity_I32
);
8209 assign(t0
, unop(Iop_16Sto32
,
8210 unop(Iop_32HIto16
, getIReg(rs
))));
8211 assign(t1
, unop(Iop_16Sto32
,
8212 unop(Iop_32HIto16
, getIReg(rt
))));
8214 assign(t8
, binop(Iop_And32
,
8227 /* DSPControl_outflag:16+acc <- 1 */
8228 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
8240 IRExpr_ITE(binop(Iop_CmpNE32
,
8241 mkexpr(t8
), mkU32(0x0)),
8245 mkexpr(t0
), mkexpr(t1
)),
8248 assign(t3
, unop(Iop_16Sto32
,
8249 unop(Iop_32to16
, getIReg(rs
))));
8250 assign(t4
, unop(Iop_16Sto32
,
8251 unop(Iop_32to16
, getIReg(rt
))));
8253 assign(t9
, binop(Iop_And32
,
8266 /* DSPControl_outflag:16+acc <- 1 */
8267 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
8278 IRExpr_ITE(binop(Iop_CmpNE32
,
8290 unop(Iop_32Sto64
, mkexpr(t2
)),
8291 unop(Iop_32Sto64
, mkexpr(t5
))));
8293 assign(t7
, binop(Iop_Add64
, getAcc(ac
), mkexpr(t6
)));
8295 putAcc(ac
, mkexpr(t7
));
8299 case 0x7: { /* DPAU.H.QBR */
8300 DIP("dpau.h.qbr ac%u, r%u, r%u", ac
, rs
, rt
);
8302 t0
= newTemp(Ity_I32
);
8303 t1
= newTemp(Ity_I32
);
8304 t2
= newTemp(Ity_I64
);
8305 t3
= newTemp(Ity_I64
);
8311 unop(Iop_32to16
, getIReg(rs
)))),
8314 unop(Iop_32to16
, getIReg(rt
))))));
8319 unop(Iop_32to16
, getIReg(rs
)))),
8322 unop(Iop_32to16
, getIReg(rt
))))));
8323 assign(t2
, unop(Iop_32Uto64
,
8324 binop(Iop_Add32
, mkexpr(t0
), mkexpr(t1
))));
8325 assign(t3
, binop(Iop_Add64
, getAcc(ac
), mkexpr(t2
)));
8326 putAcc(ac
, mkexpr(t3
));
8330 case 0x8: { /* DPAX.W.PH */
8331 DIP("dpax.w.ph ac%u, r%u, r%u", ac
, rs
, rt
);
8333 t0
= newTemp(Ity_I64
);
8334 t1
= newTemp(Ity_I64
);
8335 t2
= newTemp(Ity_I64
);
8341 unop(Iop_32HIto16
, getIReg(rs
))),
8343 unop(Iop_32to16
, getIReg(rt
))))));
8348 unop(Iop_32to16
, getIReg(rs
))),
8350 unop(Iop_32HIto16
, getIReg(rt
))))));
8354 binop(Iop_Add64
, mkexpr(t0
), mkexpr(t1
))));
8355 putAcc(ac
, mkexpr(t2
));
8359 case 0x9: { /* DPSX.W.PH */
8360 DIP("dpsx.w.ph ac%u r%u, r%u", ac
, rs
, rt
);
8363 t0
= newTemp(Ity_I64
);
8364 t1
= newTemp(Ity_I64
);
8365 t2
= newTemp(Ity_I64
);
8371 unop(Iop_32HIto16
, getIReg(rs
))),
8373 unop(Iop_32to16
, getIReg(rt
))))));
8378 unop(Iop_32to16
, getIReg(rs
))),
8380 unop(Iop_32HIto16
, getIReg(rt
))))));
8384 binop(Iop_Add64
, mkexpr(t0
), mkexpr(t1
))));
8385 putAcc(ac
, mkexpr(t2
));
8389 case 0xB: { /* DPSU.H.QBL */
8390 DIP("dpsu.h.qbl ac%u, r%u, r%u", ac
, rs
, rt
);
8393 t0
= newTemp(Ity_I32
);
8394 t1
= newTemp(Ity_I32
);
8395 t2
= newTemp(Ity_I64
);
8396 t3
= newTemp(Ity_I64
);
8402 unop(Iop_32HIto16
, getIReg(rs
)))),
8405 unop(Iop_32HIto16
, getIReg(rt
))))));
8410 unop(Iop_32HIto16
, getIReg(rs
)))),
8413 unop(Iop_32HIto16
, getIReg(rt
))))));
8416 binop(Iop_Add32
, mkexpr(t0
), mkexpr(t1
))));
8418 binop(Iop_Sub64
, getAcc(ac
), mkexpr(t2
)));
8419 putAcc(ac
, mkexpr(t3
));
8423 case 0xC: { /* DPAQ_SA.L.W */
8424 DIP("dpaq_sa.l.w ac%u, r%u, r%u", ac
, rs
, rt
);
8426 t0
= newTemp(Ity_I64
);
8427 t1
= newTemp(Ity_I64
);
8428 t2
= newTemp(Ity_I1
);
8429 t3
= newTemp(Ity_I1
);
8430 t4
= newTemp(Ity_I64
);
8431 t5
= newTemp(Ity_I64
);
8432 t6
= newTemp(Ity_I64
);
8433 t7
= newTemp(Ity_I64
);
8434 t8
= newTemp(Ity_I1
);
8435 t9
= newTemp(Ity_I1
);
8437 assign(t0
, getAcc(ac
));
8439 assign(t1
, binop(Iop_Shl64
,
8441 getIReg(rs
), getIReg(rt
)),
8444 assign(t2
, binop(Iop_CmpEQ32
,
8446 mkU32(0x80000000)));
8447 assign(t3
, binop(Iop_CmpEQ32
,
8449 mkU32(0x80000000)));
8452 IRExpr_ITE(mkexpr(t2
),
8453 IRExpr_ITE(mkexpr(t3
),
8454 mkU64(0x7fffffffffffffffULL
),
8458 putDSPControl(IRExpr_ITE(mkexpr(t2
),
8459 IRExpr_ITE(mkexpr(t3
),
8470 assign(t5
, binop(Iop_Add64
,
8472 unop(Iop_64to32
, mkexpr(t0
))),
8474 unop(Iop_64to32
, mkexpr(t4
)))));
8479 unop(Iop_64HIto32
, mkexpr(t0
))),
8481 unop(Iop_64HIto32
, mkexpr(t4
)))),
8484 unop(Iop_64HIto32
, mkexpr(t5
)),
8486 assign(t7
, binop(Iop_32HLto64
,
8487 unop(Iop_64to32
, mkexpr(t6
)),
8488 unop(Iop_64to32
, mkexpr(t5
))));
8489 assign(t8
, binop(Iop_CmpEQ32
,
8492 unop(Iop_64to32
, mkexpr(t6
)),
8496 unop(Iop_64HIto32
, mkexpr(t6
)),
8497 mkU32(0x00000001))));
8498 assign(t9
, binop(Iop_CmpEQ32
,
8504 putDSPControl(IRExpr_ITE(mkexpr(t8
),
8512 IRExpr_ITE(mkexpr(t8
),
8514 IRExpr_ITE(mkexpr(t9
),
8515 mkU64(0x8000000000000000ULL
),
8516 mkU64(0x7fffffffffffffffULL
)))
8521 case 0xD: { /* DPSQ_SA.L.W */
8522 DIP("dpsq_sa.l.w ac%u, r%u, r%u", ac
, rs
, rt
);
8524 t0
= newTemp(Ity_I64
);
8525 t1
= newTemp(Ity_I64
);
8526 t2
= newTemp(Ity_I1
);
8527 t3
= newTemp(Ity_I1
);
8528 t4
= newTemp(Ity_I64
);
8529 t5
= newTemp(Ity_I64
);
8530 t6
= newTemp(Ity_I64
);
8531 t7
= newTemp(Ity_I64
);
8532 t8
= newTemp(Ity_I1
);
8533 t9
= newTemp(Ity_I1
);
8535 assign(t0
, getAcc(ac
));
8537 assign(t1
, binop(Iop_Shl64
,
8539 getIReg(rs
), getIReg(rt
)),
8542 assign(t2
, binop(Iop_CmpEQ32
,
8544 mkU32(0x80000000)));
8545 assign(t3
, binop(Iop_CmpEQ32
,
8547 mkU32(0x80000000)));
8550 IRExpr_ITE(mkexpr(t2
),
8551 IRExpr_ITE(mkexpr(t3
),
8552 mkU64(0x7fffffffffffffffULL
),
8556 putDSPControl(IRExpr_ITE(mkexpr(t2
),
8557 IRExpr_ITE(mkexpr(t3
),
8568 assign(t5
, binop(Iop_Sub64
,
8570 unop(Iop_64to32
, mkexpr(t0
))),
8572 unop(Iop_64to32
, mkexpr(t4
)))));
8573 assign(t6
, binop(Iop_Sub64
,
8576 unop(Iop_64HIto32
, mkexpr(t0
))
8586 unop(Iop_64HIto32
, mkexpr(t4
)))));
8587 assign(t7
, binop(Iop_32HLto64
,
8588 unop(Iop_64to32
, mkexpr(t6
)),
8589 unop(Iop_64to32
, mkexpr(t5
))));
8590 assign(t8
, binop(Iop_CmpEQ32
,
8593 unop(Iop_64to32
, mkexpr(t6
)),
8597 unop(Iop_64HIto32
, mkexpr(t6
)),
8598 mkU32(0x00000001))));
8599 assign(t9
, binop(Iop_CmpEQ32
,
8601 unop(Iop_64HIto32
, mkexpr(t6
)),
8604 putDSPControl(IRExpr_ITE(mkexpr(t8
),
8612 IRExpr_ITE(mkexpr(t8
),
8614 IRExpr_ITE(mkexpr(t9
),
8615 mkU64(0x8000000000000000ULL
),
8616 mkU64(0x7fffffffffffffffULL
)))
8621 case 0xF: { /* DPSU.H.QBR */
8622 DIP("dpsu.h.qbr ac%u r%u, r%u", ac
, rs
, rt
);
8625 t0
= newTemp(Ity_I32
);
8626 t1
= newTemp(Ity_I32
);
8627 t2
= newTemp(Ity_I64
);
8628 t3
= newTemp(Ity_I64
);
8634 unop(Iop_32to16
, getIReg(rs
)))),
8637 unop(Iop_32to16
, getIReg(rt
))))));
8642 unop(Iop_32to16
, getIReg(rs
)))),
8645 unop(Iop_32to16
, getIReg(rt
))))));
8646 assign(t2
, unop(Iop_32Uto64
,
8647 binop(Iop_Add32
, mkexpr(t0
), mkexpr(t1
))));
8648 assign(t3
, binop(Iop_Sub64
, getAcc(ac
), mkexpr(t2
)));
8649 putAcc(ac
, mkexpr(t3
));
8654 case 0x10: { /* MAQ_SA.W.PHL */
8655 DIP("maq_sa.w.phl ac%u, r%u, r%u", ac
, rs
, rt
);
8657 t0
= newTemp(Ity_I64
);
8658 t1
= newTemp(Ity_I64
);
8659 t2
= newTemp(Ity_I1
);
8660 t3
= newTemp(Ity_I1
);
8661 t4
= newTemp(Ity_I64
);
8662 t5
= newTemp(Ity_I64
);
8663 t6
= newTemp(Ity_I1
);
8664 t7
= newTemp(Ity_I64
);
8666 assign(t0
, getAcc(ac
));
8667 assign(t1
, unop(Iop_32Sto64
,
8678 /* If both input arguments are equal 0x8000, saturate
8679 intermediate product and write to DSPControl register.
8681 assign(t2
, binop(Iop_CmpEQ32
,
8683 unop(Iop_32HIto16
, getIReg(rs
))),
8684 mkU32(0x00008000)));
8685 assign(t3
, binop(Iop_CmpEQ32
,
8687 unop(Iop_32HIto16
, getIReg(rt
))),
8688 mkU32(0x00008000)));
8691 IRExpr_ITE(mkexpr(t2
),
8692 IRExpr_ITE(mkexpr(t3
),
8693 mkU64(0x000000007fffffffULL
),
8697 putDSPControl(IRExpr_ITE(mkexpr(t2
),
8698 IRExpr_ITE(mkexpr(t3
),
8708 /* Add intermediate product and value in the
8710 assign(t5
, binop(Iop_Add64
, mkexpr(t0
), mkexpr(t4
)));
8712 /* Compare bits 31 and 32 of the value in t5. */
8713 assign(t6
, binop(Iop_CmpEQ32
,
8716 unop(Iop_64to32
, mkexpr(t5
)),
8720 unop(Iop_64HIto32
, mkexpr(t5
)),
8722 putDSPControl(IRExpr_ITE(mkexpr(t6
),
8730 IRExpr_ITE(mkexpr(t6
),
8732 IRExpr_ITE(binop(Iop_CmpEQ32
,
8738 mkU64(0x000000007fffffffULL
),
8739 mkU64(0xffffffff80000000ULL
)))
8741 putAcc(ac
, mkexpr(t7
));
8745 case 0x12: { /* MAQ_SA.W.PHR */
8746 DIP("maq_sa.w.phr ac%u, r%u, r%u", ac
, rs
, rt
);
8748 t0
= newTemp(Ity_I64
);
8749 t1
= newTemp(Ity_I64
);
8750 t2
= newTemp(Ity_I1
);
8751 t3
= newTemp(Ity_I1
);
8752 t4
= newTemp(Ity_I64
);
8753 t5
= newTemp(Ity_I64
);
8754 t6
= newTemp(Ity_I1
);
8755 t7
= newTemp(Ity_I64
);
8757 assign(t0
, getAcc(ac
));
8758 assign(t1
, unop(Iop_32Sto64
,
8769 /* If both input arguments are equal 0x8000, saturate
8770 intermediate product and write to DSPControl
8772 assign(t2
, binop(Iop_CmpEQ32
,
8774 unop(Iop_32to16
, getIReg(rs
))),
8775 mkU32(0x00008000)));
8776 assign(t3
, binop(Iop_CmpEQ32
,
8778 unop(Iop_32to16
, getIReg(rt
))),
8779 mkU32(0x00008000)));
8782 IRExpr_ITE(mkexpr(t2
),
8783 IRExpr_ITE(mkexpr(t3
),
8784 mkU64(0x000000007fffffffULL
),
8788 putDSPControl(IRExpr_ITE(mkexpr(t2
),
8789 IRExpr_ITE(mkexpr(t3
),
8799 /* Add intermediate product and value in the
8801 assign(t5
, binop(Iop_Add64
, mkexpr(t0
), mkexpr(t4
)));
8803 /* Compare bits 31 and 32 of the value in t5. */
8804 assign(t6
, binop(Iop_CmpEQ32
,
8807 unop(Iop_64to32
, mkexpr(t5
)),
8811 unop(Iop_64HIto32
, mkexpr(t5
)),
8813 putDSPControl(IRExpr_ITE(mkexpr(t6
),
8821 IRExpr_ITE(mkexpr(t6
),
8823 IRExpr_ITE(binop(Iop_CmpEQ32
,
8829 mkU64(0x000000007fffffffULL
),
8830 mkU64(0xffffffff80000000ULL
)))
8832 putAcc(ac
, mkexpr(t7
));
8836 case 0x14: { /* MAQ_S.W.PHL */
8837 DIP("maq_s.w.phl ac%u, r%u, r%u", ac
, rs
, rt
);
8839 t0
= newTemp(Ity_I32
);
8840 t1
= newTemp(Ity_I32
);
8841 t2
= newTemp(Ity_I32
);
8842 t3
= newTemp(Ity_I1
);
8843 t4
= newTemp(Ity_I32
);
8844 t5
= newTemp(Ity_I64
);
8846 assign(t5
, getAcc(ac
));
8848 assign(t0
, unop(Iop_16Sto32
,
8849 unop(Iop_32HIto16
, getIReg(rs
))));
8850 assign(t1
, unop(Iop_16Sto32
,
8851 unop(Iop_32HIto16
, getIReg(rt
))));
8853 assign(t2
, binop(Iop_And32
,
8867 assign(t3
, binop(Iop_CmpEQ32
, mkexpr(t2
), mkU32(0x0)));
8869 putDSPControl(IRExpr_ITE(mkexpr(t3
),
8877 assign(t4
, unop(Iop_64to32
,
8879 mkexpr(t0
), mkexpr(t1
))));
8880 putAcc(ac
, IRExpr_ITE(mkexpr(t3
),
8890 mkU32(0x7fffffff)))));
8894 case 0x16: { /* MAQ_S.W.PHR */
8895 DIP("maq_s.w.phr ac%u, r%u, r%u", ac
, rs
, rt
);
8897 t0
= newTemp(Ity_I32
);
8898 t1
= newTemp(Ity_I32
);
8899 t2
= newTemp(Ity_I32
);
8900 t3
= newTemp(Ity_I1
);
8901 t4
= newTemp(Ity_I32
);
8902 t5
= newTemp(Ity_I64
);
8904 assign(t5
, getAcc(ac
));
8906 assign(t0
, unop(Iop_16Sto32
,
8907 unop(Iop_32to16
, getIReg(rs
))));
8908 assign(t1
, unop(Iop_16Sto32
,
8909 unop(Iop_32to16
, getIReg(rt
))));
8911 assign(t2
, binop(Iop_And32
,
8925 assign(t3
, binop(Iop_CmpEQ32
, mkexpr(t2
), mkU32(0x0)));
8927 putDSPControl(IRExpr_ITE(mkexpr(t3
),
8935 assign(t4
, unop(Iop_64to32
,
8937 mkexpr(t0
), mkexpr(t1
))));
8938 putAcc(ac
, IRExpr_ITE(mkexpr(t3
),
8948 mkU32(0x7fffffff)))));
8952 case 0x18: { /* DPAQX_S.W.PH */
8953 DIP("dpaqx_s.w.ph ac%u, r%u, r%u", ac
, rs
, rt
);
8955 t0
= newTemp(Ity_I64
);
8956 t1
= newTemp(Ity_I64
);
8957 t2
= newTemp(Ity_I1
);
8958 t3
= newTemp(Ity_I1
);
8959 t4
= newTemp(Ity_I64
);
8960 t5
= newTemp(Ity_I64
);
8961 t6
= newTemp(Ity_I1
);
8962 t7
= newTemp(Ity_I1
);
8963 t8
= newTemp(Ity_I64
);
8964 t9
= newTemp(Ity_I64
);
8966 assign(t0
, getAcc(ac
));
8968 assign(t1
, binop(Iop_Shl64
,
8977 assign(t2
, binop(Iop_CmpEQ32
,
8979 unop(Iop_32HIto16
, getIReg(rs
))),
8980 mkU32(0x00008000)));
8981 assign(t3
, binop(Iop_CmpEQ32
,
8983 unop(Iop_32to16
, getIReg(rt
))),
8984 mkU32(0x00008000)));
8986 IRExpr_ITE(mkexpr(t2
),
8987 IRExpr_ITE(mkexpr(t3
),
8988 mkU64(0x000000007fffffffULL
),
8992 putDSPControl(IRExpr_ITE(mkexpr(t2
),
8993 IRExpr_ITE(mkexpr(t3
),
9002 assign(t5
, binop(Iop_Shl64
,
9011 assign(t6
, binop(Iop_CmpEQ32
,
9013 unop(Iop_32to16
, getIReg(rs
))),
9014 mkU32(0x00008000)));
9015 assign(t7
, binop(Iop_CmpEQ32
,
9017 unop(Iop_32HIto16
, getIReg(rt
))),
9018 mkU32(0x00008000)));
9020 IRExpr_ITE(mkexpr(t6
),
9021 IRExpr_ITE(mkexpr(t7
),
9022 mkU64(0x000000007fffffffULL
),
9026 putDSPControl(IRExpr_ITE(mkexpr(t6
),
9027 IRExpr_ITE(mkexpr(t7
),
9038 assign(t9
, binop(Iop_Add64
,
9039 binop(Iop_Add64
, mkexpr(t4
), mkexpr(t8
)),
9041 putAcc(ac
, mkexpr(t9
));
9045 case 0x19: { /* DPSQX_S.W.PH */
9046 DIP("dpsqx_s.w.ph ac%u, r%u, r%u", ac
, rs
, rt
);
9048 t0
= newTemp(Ity_I64
);
9049 t1
= newTemp(Ity_I64
);
9050 t2
= newTemp(Ity_I1
);
9051 t3
= newTemp(Ity_I1
);
9052 t4
= newTemp(Ity_I64
);
9053 t5
= newTemp(Ity_I64
);
9054 t6
= newTemp(Ity_I1
);
9055 t7
= newTemp(Ity_I1
);
9056 t8
= newTemp(Ity_I64
);
9057 t9
= newTemp(Ity_I64
);
9059 assign(t0
, getAcc(ac
));
9061 assign(t1
, binop(Iop_Shl64
,
9070 assign(t2
, binop(Iop_CmpEQ32
,
9072 unop(Iop_32HIto16
, getIReg(rs
))),
9073 mkU32(0x00008000)));
9074 assign(t3
, binop(Iop_CmpEQ32
,
9076 unop(Iop_32to16
, getIReg(rt
))),
9077 mkU32(0x00008000)));
9079 IRExpr_ITE(mkexpr(t2
),
9080 IRExpr_ITE(mkexpr(t3
),
9081 mkU64(0x000000007fffffffULL
),
9085 putDSPControl(IRExpr_ITE(mkexpr(t2
),
9086 IRExpr_ITE(mkexpr(t3
),
9097 assign(t5
, binop(Iop_Shl64
,
9106 assign(t6
, binop(Iop_CmpEQ32
,
9108 unop(Iop_32to16
, getIReg(rs
))),
9109 mkU32(0x00008000)));
9110 assign(t7
, binop(Iop_CmpEQ32
,
9112 unop(Iop_32HIto16
, getIReg(rt
))),
9113 mkU32(0x00008000)));
9115 IRExpr_ITE(mkexpr(t6
),
9116 IRExpr_ITE(mkexpr(t7
),
9117 mkU64(0x000000007fffffffULL
),
9121 putDSPControl(IRExpr_ITE(mkexpr(t6
),
9122 IRExpr_ITE(mkexpr(t7
),
9133 assign(t9
, binop(Iop_Sub64
,
9135 binop(Iop_Add64
, mkexpr(t4
), mkexpr(t8
))));
9136 putAcc(ac
, mkexpr(t9
));
9140 case 0x1A: { /* DPAQX_SA.W.PH */
9141 DIP("dpaqx_sa.w.ph ac%u, r%u, r%u", ac
, rs
, rt
);
9143 t0
= newTemp(Ity_I64
);
9144 t1
= newTemp(Ity_I64
);
9145 t2
= newTemp(Ity_I1
);
9146 t3
= newTemp(Ity_I1
);
9147 t4
= newTemp(Ity_I64
);
9148 t5
= newTemp(Ity_I64
);
9149 t6
= newTemp(Ity_I1
);
9150 t7
= newTemp(Ity_I1
);
9151 t8
= newTemp(Ity_I64
);
9152 t9
= newTemp(Ity_I64
);
9153 t10
= newTemp(Ity_I32
);
9155 assign(t0
, getAcc(ac
));
9156 /* Calculate the first cross dot product and saturate if
9158 assign(t1
, unop(Iop_32Sto64
,
9169 /* If both input arguments are equal 0x8000, saturate
9170 intermediate product and write to DSPControl
9172 assign(t2
, binop(Iop_CmpEQ32
,
9174 unop(Iop_32HIto16
, getIReg(rs
))),
9175 mkU32(0x00008000)));
9176 assign(t3
, binop(Iop_CmpEQ32
,
9178 unop(Iop_32to16
, getIReg(rt
))),
9179 mkU32(0x00008000)));
9181 assign(t4
, IRExpr_ITE(binop(Iop_CmpNE32
,
9188 mkU64(0x000000007fffffffULL
),
9191 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
9204 /* Calculate second cross dot product and saturate if
9206 assign(t5
, unop(Iop_32Sto64
,
9217 /* If both input arguments are equal 0x8000, saturate
9218 intermediate product and write to DSPControl
9220 assign(t6
, binop(Iop_CmpEQ32
,
9222 unop(Iop_32to16
, getIReg(rs
))),
9223 mkU32(0x00008000)));
9224 assign(t7
, binop(Iop_CmpEQ32
,
9226 unop(Iop_32HIto16
, getIReg(rt
))),
9227 mkU32(0x00008000)));
9229 assign(t8
, IRExpr_ITE(binop(Iop_CmpNE32
,
9236 mkU64(0x000000007fffffffULL
),
9239 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
9252 /* Subtract intermediate products from value in the
9257 binop(Iop_Add64
, mkexpr(t8
), mkexpr(t4
))));
9260 IRExpr_ITE(binop(Iop_CmpEQ32
,
9266 IRExpr_ITE(binop(Iop_CmpNE32
,
9272 mkU64(0x000000007fffffffULL
),
9274 IRExpr_ITE(binop(Iop_CmpNE32
,
9280 mkU64(0xffffffff80000000ULL
),
9282 assign(t10
, IRExpr_ITE(binop(Iop_CmpEQ32
,
9293 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
9307 case 0x1B: { /* DPSQX_SA.W.PH */
9308 DIP("dpsqx_sa.w.ph ac%u, r%u, r%u", ac
, rs
, rt
);
9310 t0
= newTemp(Ity_I64
);
9311 t1
= newTemp(Ity_I64
);
9312 t2
= newTemp(Ity_I1
);
9313 t3
= newTemp(Ity_I1
);
9314 t4
= newTemp(Ity_I64
);
9315 t5
= newTemp(Ity_I64
);
9316 t6
= newTemp(Ity_I1
);
9317 t7
= newTemp(Ity_I1
);
9318 t8
= newTemp(Ity_I64
);
9319 t9
= newTemp(Ity_I64
);
9320 t10
= newTemp(Ity_I32
);
9322 assign(t0
, getAcc(ac
));
9323 /* Calculate the first cross dot product and saturate if
9325 assign(t1
, unop(Iop_32Sto64
,
9336 /* If both input arguments are equal 0x8000, saturate
9337 intermediate product and write to DSPControl
9339 assign(t2
, binop(Iop_CmpEQ32
,
9341 unop(Iop_32HIto16
, getIReg(rs
))),
9342 mkU32(0x00008000)));
9343 assign(t3
, binop(Iop_CmpEQ32
,
9345 unop(Iop_32to16
, getIReg(rt
))),
9346 mkU32(0x00008000)));
9348 assign(t4
, IRExpr_ITE(binop(Iop_CmpNE32
,
9355 mkU64(0x000000007fffffffULL
),
9358 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
9371 /* Calculate second cross dot product and saturate if
9373 assign(t5
, unop(Iop_32Sto64
,
9384 /* If both input arguments are equal 0x8000, saturate
9385 intermediate product and write to DSPControl
9387 assign(t6
, binop(Iop_CmpEQ32
,
9389 unop(Iop_32to16
, getIReg(rs
))),
9390 mkU32(0x00008000)));
9391 assign(t7
, binop(Iop_CmpEQ32
,
9393 unop(Iop_32HIto16
, getIReg(rt
))),
9394 mkU32(0x00008000)));
9396 assign(t8
, IRExpr_ITE(binop(Iop_CmpNE32
,
9403 mkU64(0x000000007fffffffULL
),
9406 putDSPControl(IRExpr_ITE(binop(Iop_CmpNE32
,
9419 /* Subtract intermediate products from value in the
9424 binop(Iop_Add64
, mkexpr(t8
), mkexpr(t4
))));
9427 IRExpr_ITE(binop(Iop_CmpEQ32
,
9433 IRExpr_ITE(binop(Iop_CmpNE32
,
9439 mkU64(0x000000007fffffffULL
),
9441 IRExpr_ITE(binop(Iop_CmpNE32
,
9447 mkU64(0xffffffff80000000ULL
),
9449 assign(t10
, IRExpr_ITE(binop(Iop_CmpEQ32
,
9460 putDSPControl(IRExpr_ITE(binop(Iop_CmpEQ32
,
9481 static UInt
disDSPInstr_MIPS_WRK_Special3_APPEND( UInt cins
)
9483 IRTemp t1
= 0, t2
, t3
;
9484 UInt rs
, rt
, rd
, sa
;
9492 case 0x0: { /* APPEND */
9493 DIP("append r%u, r%u, %u", rt
, rs
, rd
);
9495 t1
= newTemp(Ity_I32
);
9496 t2
= newTemp(Ity_I32
);
9498 assign(t1
, binop(Iop_Shl32
, getIReg(rt
), mkU8(rd
)));
9501 putIReg(rt
, binop(Iop_Or32
,
9505 mkU32(0x7fffffff))));
9506 } else if (1 == rd
) {
9511 getIReg(rs
), mkU32(0x1))));
9516 mkU32(0xffffffff), mkU8(rd
))));
9518 putIReg(rt
, binop(Iop_Or32
,
9521 getIReg(rs
), mkexpr(t2
))));
9527 case 0x1: { /* PREPEND */
9528 DIP("prepend r%u, r%u, %u", rt
, rs
, rd
);
9530 t1
= newTemp(Ity_I32
);
9531 t2
= newTemp(Ity_I32
);
9532 t3
= newTemp(Ity_I32
);
9535 assign(t1
, binop(Iop_Shr32
, getIReg(rt
), mkU8(rd
)));
9538 putIReg(rt
, binop(Iop_Or32
,
9545 } else if (1 == rd
) {
9546 putIReg(rt
, binop(Iop_Or32
,
9554 assign(t2
, binop(Iop_Add32
, mkU32(rd
), mkU32(0x1)));
9556 assign(t3
, unop(Iop_Not32
,
9559 unop(Iop_32to8
, mkexpr(t2
)))));
9561 putIReg(rt
, binop(Iop_Or32
,
9574 case 0x10: { /* BALIGN */
9575 DIP("balign r%u, r%u, %u", rt
, rs
, rd
);
9577 t1
= newTemp(Ity_I32
);
9578 t2
= newTemp(Ity_I32
);
9579 t3
= newTemp(Ity_I32
);
9581 if ((2 != rd
) && (0 != rd
)) {
9582 assign(t1
, binop(Iop_Shl32
,
9584 mkU32(rd
), mkU32(0x3)),
9586 assign(t2
, binop(Iop_Shl32
,
9588 unop(Iop_32to8
, mkexpr(t1
))));
9589 assign(t3
, binop(Iop_Shr32
,
9599 putIReg(rt
, binop(Iop_Or32
, mkexpr(t2
), mkexpr(t3
)));
9612 static UInt
disDSPInstr_MIPS_WRK_Special3( UInt cins
)
9614 switch (get_function(cins
)) {
9615 case 0x12: { /* ABSQ_S.PH */
9616 return disDSPInstr_MIPS_WRK_Special3_ABSQ_SPH(cins
);
9619 case 0x38: { /* EXTR.W */
9620 return disDSPInstr_MIPS_WRK_Special3_EXTR_W(cins
);
9623 case 0xA: { /* LX */
9624 return disDSPInstr_MIPS_WRK_Special3_LX(cins
);
9627 case 0xC: { /* INSV */
9628 return disDSPInstr_MIPS_WRK_Special3_INSV(cins
);
9631 case 0x10: { /* ADDU.QB */
9632 return disDSPInstr_MIPS_WRK_Special3_ADDU_QB(cins
);
9635 case 0x11: { /* CMPU.EQ.QB */
9636 return disDSPInstr_MIPS_WRK_Special3_CMPU_EQ_QB(cins
);
9639 case 0x13: { /* SHLL.QB */
9640 return disDSPInstr_MIPS_WRK_Special3_SHLL_QB(cins
);
9643 case 0x18: { /* ADDUH.QB/MUL.PH */
9644 return disDSPInstr_MIPS_WRK_Special3_ADDUH_QB(cins
);
9647 case 0x30: { /* DPA.W.PH */
9648 return disDSPInstr_MIPS_WRK_Special3_DPAW_PH(cins
);
9651 case 0x31: { /* APPEND */
9652 return disDSPInstr_MIPS_WRK_Special3_APPEND(cins
);
9660 UInt
disDSPInstr_MIPS_WRK ( UInt cins
)
9662 UInt opcode
= get_opcode(cins
);
9665 case 0x00: { /* Special */
9666 return disDSPInstr_MIPS_WRK_Special(cins
);
9669 case 0x1C: { /* Special2 */
9670 return disDSPInstr_MIPS_WRK_Special2(cins
);
9673 case 0x1F: { /* Special3 */
9674 return disDSPInstr_MIPS_WRK_Special3(cins
);