memcheck/tests/ppc64/power_ISA2_07.c

   1 #include <stdio.h>
   2 #include <config.h>
   3
   4 double foo = -1.0;
   5 double FRT1;
   6 double FRT2;
   7
   8 #ifdef HAS_ISA_2_07
   9
  10 /* b0 may be non-zero in lwarx/ldarx Power6 instrs */
  11 void test_reservation()
  12 {
  13
  14    unsigned long RT;
  15    unsigned long base;
  16    unsigned long offset;
  17    unsigned arrB[] = { 0x00112233U, 0x44556677U, 0x8899aabbU, 0xccddeeffU };
  18    int arrH[] __attribute__ ((aligned (2))) = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
  19
  20    /* The lbarx and lharx instructions were "phased in" in ISA 2.06.  That
  21     * means it they may show up in some implementations but not others. They
  22     * are in all ISA 2.08 implementations.
  23     */
  24    base = (unsigned long) &arrB;
  25    offset = ((unsigned long) &arrB[1]) - base;
  26    __asm__ volatile ("ori 20, %0, 0"::"r" (base));
  27    __asm__ volatile ("ori 21, %0, 0"::"r" (offset));
  28    __asm__ volatile ("lbarx %0, 20, 21, 1":"=r" (RT));
  29    printf("lbarx => 0x%lx\n", RT);
  30
  31    base = (unsigned long) &arrH;
  32    offset = ((unsigned long) &arrH[1]) - base;
  33    __asm__ volatile ("ori 20, %0, 0"::"r" (base));
  34    __asm__ volatile ("ori 21, %0, 0"::"r" (offset));
  35    __asm__ volatile ("lharx %0, 20, 21, 1":"=r" (RT));
  36    printf("lharx => 0x%lx\n", RT);
  37 }
  38 #endif
  39
  40 int main(void)
  41 {
  42 #ifdef HAS_ISA_2_07
  43    (void) test_reservation();
  44 #endif
  45
  46    return 0;
  47 }