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none/tests/fdleak_cmsg_supp.supp: Add suppressions for older glibc
[valgrind.git] / none / tests / arm64 / fp_and_simd.c
blob49ece1c77225c4606e6a7602923adcd665f657e5
1
2 #include <stdio.h>
3 #include <assert.h>
4 #include <string.h> // memset
5 #include "simd.h"
6
7 /* ---------------------------------------------------------------- */
8 /* -- Test functions and non-parameterisable test macros -- */
9 /* ---------------------------------------------------------------- */
10
11 void test_UMINV ( void )
12 {
13 int i;
14 V128 block[2];
15
16 /* -- 4s -- */
17
18 for (i = 0; i < 10; i++) {
19 memset(&block, 0x55, sizeof(block));
20 randV128(&block[0], TyS);
21 randV128(&block[1], TyS);
22 __asm__ __volatile__(
23 "ldr q7, [%0, #0] ; "
24 "uminv s8, v7.4s ; "
25 "str q8, [%0, #16] "
26 : : "r"(&block[0]) : "memory", "v7", "v8"
27 );
28 printf("UMINV v8, v7.4s ");
29 showV128(&block[0]); printf(" ");
30 showV128(&block[1]); printf("\n");
31 }
32
33 /* -- 8h -- */
34
35 for (i = 0; i < 10; i++) {
36 memset(&block, 0x55, sizeof(block));
37 randV128(&block[0], TyH);
38 randV128(&block[1], TyH);
39 __asm__ __volatile__(
40 "ldr q7, [%0, #0] ; "
41 "uminv h8, v7.8h ; "
42 "str q8, [%0, #16] "
43 : : "r"(&block[0]) : "memory", "v7", "v8"
44 );
45 printf("UMINV h8, v7.8h ");
46 showV128(&block[0]); printf(" ");
47 showV128(&block[1]); printf("\n");
48 }
49
50 /* -- 4h -- */
51
52 for (i = 0; i < 10; i++) {
53 memset(&block, 0x55, sizeof(block));
54 randV128(&block[0], TyH);
55 randV128(&block[1], TyH);
56 __asm__ __volatile__(
57 "ldr q7, [%0, #0] ; "
58 "uminv h8, v7.4h ; "
59 "str q8, [%0, #16] "
60 : : "r"(&block[0]) : "memory", "v7", "v8"
61 );
62 printf("UMINV h8, v7.4h ");
63 showV128(&block[0]); printf(" ");
64 showV128(&block[1]); printf("\n");
65 }
66
67 /* -- 16b -- */
68
69 for (i = 0; i < 10; i++) {
70 memset(&block, 0x55, sizeof(block));
71 randV128(&block[0], TyB);
72 randV128(&block[1], TyB);
73 __asm__ __volatile__(
74 "ldr q7, [%0, #0] ; "
75 "uminv b8, v7.16b ; "
76 "str q8, [%0, #16] "
77 : : "r"(&block[0]) : "memory", "v7", "v8"
78 );
79 printf("UMINV b8, v7.16b ");
80 showV128(&block[0]); printf(" ");
81 showV128(&block[1]); printf("\n");
82 }
83
84 /* -- 8b -- */
85
86 for (i = 0; i < 10; i++) {
87 memset(&block, 0x55, sizeof(block));
88 randV128(&block[0], TyB);
89 randV128(&block[1], TyB);
90 __asm__ __volatile__(
91 "ldr q7, [%0, #0] ; "
92 "uminv b8, v7.8b ; "
93 "str q8, [%0, #16] "
94 : : "r"(&block[0]) : "memory", "v7", "v8"
95 );
96 printf("UMINV b8, v7.8b ");
97 showV128(&block[0]); printf(" ");
98 showV128(&block[1]); printf("\n");
99 }
100
101 }
102
103
104 void test_UMAXV ( void )
105 {
106 int i;
107 V128 block[2];
108
109 /* -- 4s -- */
110
111 for (i = 0; i < 10; i++) {
112 memset(&block, 0x55, sizeof(block));
113 randV128(&block[0], TyS);
114 randV128(&block[1], TyS);
115 __asm__ __volatile__(
116 "ldr q7, [%0, #0] ; "
117 "umaxv s8, v7.4s ; "
118 "str q8, [%0, #16] "
119 : : "r"(&block[0]) : "memory", "v7", "v8"
120 );
121 printf("UMAXV v8, v7.4s ");
122 showV128(&block[0]); printf(" ");
123 showV128(&block[1]); printf("\n");
124 }
125
126 /* -- 8h -- */
127
128 for (i = 0; i < 10; i++) {
129 memset(&block, 0x55, sizeof(block));
130 randV128(&block[0], TyH);
131 randV128(&block[1], TyH);
132 __asm__ __volatile__(
133 "ldr q7, [%0, #0] ; "
134 "umaxv h8, v7.8h ; "
135 "str q8, [%0, #16] "
136 : : "r"(&block[0]) : "memory", "v7", "v8"
137 );
138 printf("UMAXV h8, v7.8h ");
139 showV128(&block[0]); printf(" ");
140 showV128(&block[1]); printf("\n");
141 }
142
143 /* -- 4h -- */
144
145 for (i = 0; i < 10; i++) {
146 memset(&block, 0x55, sizeof(block));
147 randV128(&block[0], TyH);
148 randV128(&block[1], TyH);
149 __asm__ __volatile__(
150 "ldr q7, [%0, #0] ; "
151 "umaxv h8, v7.4h ; "
152 "str q8, [%0, #16] "
153 : : "r"(&block[0]) : "memory", "v7", "v8"
154 );
155 printf("UMAXV h8, v7.4h ");
156 showV128(&block[0]); printf(" ");
157 showV128(&block[1]); printf("\n");
158 }
159
160 /* -- 16b -- */
161
162 for (i = 0; i < 10; i++) {
163 memset(&block, 0x55, sizeof(block));
164 randV128(&block[0], TyB);
165 randV128(&block[1], TyB);
166 __asm__ __volatile__(
167 "ldr q7, [%0, #0] ; "
168 "umaxv b8, v7.16b ; "
169 "str q8, [%0, #16] "
170 : : "r"(&block[0]) : "memory", "v7", "v8"
171 );
172 printf("UMAXV b8, v7.16b ");
173 showV128(&block[0]); printf(" ");
174 showV128(&block[1]); printf("\n");
175 }
176
177 /* -- 8b -- */
178
179 for (i = 0; i < 10; i++) {
180 memset(&block, 0x55, sizeof(block));
181 randV128(&block[0], TyB);
182 randV128(&block[1], TyB);
183 __asm__ __volatile__(
184 "ldr q7, [%0, #0] ; "
185 "umaxv b8, v7.8b ; "
186 "str q8, [%0, #16] "
187 : : "r"(&block[0]) : "memory", "v7", "v8"
188 );
189 printf("UMAXV b8, v7.8b ");
190 showV128(&block[0]); printf(" ");
191 showV128(&block[1]); printf("\n");
192 }
193
194 }
195
196
197 void test_INS_general ( void )
198 {
199 V128 block[3];
200
201 /* -- D[0..1] -- */
202
203 memset(&block, 0x55, sizeof(block));
204 block[1].u64[0] = randULong(TyD);
205 __asm__ __volatile__(
206 "ldr q7, [%0, #0] ; "
207 "ldr x19, [%0, #16] ; "
208 "ins v7.d[0], x19 ; "
209 "str q7, [%0, #32] "
210 : : "r"(&block[0]) : "memory", "x19", "v7"
211 );
212 printf("INS v7.u64[0],x19 ");
213 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
214 showV128(&block[2]); printf("\n");
215
216 memset(&block, 0x55, sizeof(block));
217 block[1].u64[0] = randULong(TyD);
218 __asm__ __volatile__(
219 "ldr q7, [%0, #0] ; "
220 "ldr x19, [%0, #16] ; "
221 "ins v7.d[1], x19 ; "
222 "str q7, [%0, #32] "
223 : : "r"(&block[0]) : "memory", "x19", "v7"
224 );
225 printf("INS v7.d[1],x19 ");
226 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
227 showV128(&block[2]); printf("\n");
228
229 /* -- S[0..3] -- */
230
231 memset(&block, 0x55, sizeof(block));
232 block[1].u64[0] = randULong(TyS);
233 __asm__ __volatile__(
234 "ldr q7, [%0, #0] ; "
235 "ldr x19, [%0, #16] ; "
236 "ins v7.s[0], w19 ; "
237 "str q7, [%0, #32] "
238 : : "r"(&block[0]) : "memory", "x19", "v7"
239 );
240 printf("INS v7.s[0],x19 ");
241 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
242 showV128(&block[2]); printf("\n");
243
244 memset(&block, 0x55, sizeof(block));
245 block[1].u64[0] = randULong(TyS);
246 __asm__ __volatile__(
247 "ldr q7, [%0, #0] ; "
248 "ldr x19, [%0, #16] ; "
249 "ins v7.s[1], w19 ; "
250 "str q7, [%0, #32] "
251 : : "r"(&block[0]) : "memory", "x19", "v7"
252 );
253 printf("INS v7.s[1],x19 ");
254 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
255 showV128(&block[2]); printf("\n");
256
257 memset(&block, 0x55, sizeof(block));
258 block[1].u64[0] = randULong(TyS);
259 __asm__ __volatile__(
260 "ldr q7, [%0, #0] ; "
261 "ldr x19, [%0, #16] ; "
262 "ins v7.s[2], w19 ; "
263 "str q7, [%0, #32] "
264 : : "r"(&block[0]) : "memory", "x19", "v7"
265 );
266 printf("INS v7.s[2],x19 ");
267 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
268 showV128(&block[2]); printf("\n");
269
270 memset(&block, 0x55, sizeof(block));
271 block[1].u64[0] = randULong(TyS);
272 __asm__ __volatile__(
273 "ldr q7, [%0, #0] ; "
274 "ldr x19, [%0, #16] ; "
275 "ins v7.s[3], w19 ; "
276 "str q7, [%0, #32] "
277 : : "r"(&block[0]) : "memory", "x19", "v7"
278 );
279 printf("INS v7.s[3],x19 ");
280 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
281 showV128(&block[2]); printf("\n");
282
283 /* -- H[0..7] -- */
284
285 memset(&block, 0x55, sizeof(block));
286 block[1].u64[0] = randULong(TyH);
287 __asm__ __volatile__(
288 "ldr q7, [%0, #0] ; "
289 "ldr x19, [%0, #16] ; "
290 "ins v7.h[0], w19 ; "
291 "str q7, [%0, #32] "
292 : : "r"(&block[0]) : "memory", "x19", "v7"
293 );
294 printf("INS v7.h[0],x19 ");
295 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
296 showV128(&block[2]); printf("\n");
297
298 memset(&block, 0x55, sizeof(block));
299 block[1].u64[0] = randULong(TyH);
300 __asm__ __volatile__(
301 "ldr q7, [%0, #0] ; "
302 "ldr x19, [%0, #16] ; "
303 "ins v7.h[1], w19 ; "
304 "str q7, [%0, #32] "
305 : : "r"(&block[0]) : "memory", "x19", "v7"
306 );
307 printf("INS v7.h[1],x19 ");
308 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
309 showV128(&block[2]); printf("\n");
310
311 memset(&block, 0x55, sizeof(block));
312 block[1].u64[0] = randULong(TyH);
313 __asm__ __volatile__(
314 "ldr q7, [%0, #0] ; "
315 "ldr x19, [%0, #16] ; "
316 "ins v7.h[2], w19 ; "
317 "str q7, [%0, #32] "
318 : : "r"(&block[0]) : "memory", "x19", "v7"
319 );
320 printf("INS v7.h[2],x19 ");
321 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
322 showV128(&block[2]); printf("\n");
323
324 memset(&block, 0x55, sizeof(block));
325 block[1].u64[0] = randULong(TyH);
326 __asm__ __volatile__(
327 "ldr q7, [%0, #0] ; "
328 "ldr x19, [%0, #16] ; "
329 "ins v7.h[3], w19 ; "
330 "str q7, [%0, #32] "
331 : : "r"(&block[0]) : "memory", "x19", "v7"
332 );
333 printf("INS v7.h[3],x19 ");
334 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
335 showV128(&block[2]); printf("\n");
336
337 memset(&block, 0x55, sizeof(block));
338 block[1].u64[0] = randULong(TyH);
339 __asm__ __volatile__(
340 "ldr q7, [%0, #0] ; "
341 "ldr x19, [%0, #16] ; "
342 "ins v7.h[4], w19 ; "
343 "str q7, [%0, #32] "
344 : : "r"(&block[0]) : "memory", "x19", "v7"
345 );
346 printf("INS v7.h[4],x19 ");
347 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
348 showV128(&block[2]); printf("\n");
349
350 memset(&block, 0x55, sizeof(block));
351 block[1].u64[0] = randULong(TyH);
352 __asm__ __volatile__(
353 "ldr q7, [%0, #0] ; "
354 "ldr x19, [%0, #16] ; "
355 "ins v7.h[5], w19 ; "
356 "str q7, [%0, #32] "
357 : : "r"(&block[0]) : "memory", "x19", "v7"
358 );
359 printf("INS v7.h[5],x19 ");
360 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
361 showV128(&block[2]); printf("\n");
362
363 memset(&block, 0x55, sizeof(block));
364 block[1].u64[0] = randULong(TyH);
365 __asm__ __volatile__(
366 "ldr q7, [%0, #0] ; "
367 "ldr x19, [%0, #16] ; "
368 "ins v7.h[6], w19 ; "
369 "str q7, [%0, #32] "
370 : : "r"(&block[0]) : "memory", "x19", "v7"
371 );
372 printf("INS v7.h[6],x19 ");
373 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
374 showV128(&block[2]); printf("\n");
375
376 memset(&block, 0x55, sizeof(block));
377 block[1].u64[0] = randULong(TyH);
378 __asm__ __volatile__(
379 "ldr q7, [%0, #0] ; "
380 "ldr x19, [%0, #16] ; "
381 "ins v7.h[7], w19 ; "
382 "str q7, [%0, #32] "
383 : : "r"(&block[0]) : "memory", "x19", "v7"
384 );
385 printf("INS v7.h[7],x19 ");
386 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
387 showV128(&block[2]); printf("\n");
388
389 /* -- B[0,15] -- */
390
391 memset(&block, 0x55, sizeof(block));
392 block[1].u64[0] = randULong(TyB);
393 __asm__ __volatile__(
394 "ldr q7, [%0, #0] ; "
395 "ldr x19, [%0, #16] ; "
396 "ins v7.b[0], w19 ; "
397 "str q7, [%0, #32] "
398 : : "r"(&block[0]) : "memory", "x19", "v7"
399 );
400 printf("INS v7.b[0],x19 ");
401 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
402 showV128(&block[2]); printf("\n");
403
404 memset(&block, 0x55, sizeof(block));
405 block[1].u64[0] = randULong(TyB);
406 __asm__ __volatile__(
407 "ldr q7, [%0, #0] ; "
408 "ldr x19, [%0, #16] ; "
409 "ins v7.b[15], w19 ; "
410 "str q7, [%0, #32] "
411 : : "r"(&block[0]) : "memory", "x19", "v7"
412 );
413 printf("INS v7.b[15],x19 ");
414 showV128(&block[0]); printf(" %016llx ", block[1].u64[0]);
415 showV128(&block[2]); printf("\n");
416 }
417
418
419
420 void test_SMINV ( void )
421 {
422 int i;
423 V128 block[2];
424
425 /* -- 4s -- */
426
427 for (i = 0; i < 10; i++) {
428 memset(&block, 0x55, sizeof(block));
429 randV128(&block[0], TyS);
430 randV128(&block[1], TyS);
431 __asm__ __volatile__(
432 "ldr q7, [%0, #0] ; "
433 "sminv s8, v7.4s ; "
434 "str q8, [%0, #16] "
435 : : "r"(&block[0]) : "memory", "v7", "v8"
436 );
437 printf("SMINV v8, v7.4s ");
438 showV128(&block[0]); printf(" ");
439 showV128(&block[1]); printf("\n");
440 }
441
442 /* -- 8h -- */
443
444 for (i = 0; i < 10; i++) {
445 memset(&block, 0x55, sizeof(block));
446 randV128(&block[0], TyH);
447 randV128(&block[1], TyH);
448 __asm__ __volatile__(
449 "ldr q7, [%0, #0] ; "
450 "sminv h8, v7.8h ; "
451 "str q8, [%0, #16] "
452 : : "r"(&block[0]) : "memory", "v7", "v8"
453 );
454 printf("SMINV h8, v7.8h ");
455 showV128(&block[0]); printf(" ");
456 showV128(&block[1]); printf("\n");
457 }
458
459 /* -- 4h -- */
460
461 for (i = 0; i < 10; i++) {
462 memset(&block, 0x55, sizeof(block));
463 randV128(&block[0], TyH);
464 randV128(&block[1], TyH);
465 __asm__ __volatile__(
466 "ldr q7, [%0, #0] ; "
467 "sminv h8, v7.4h ; "
468 "str q8, [%0, #16] "
469 : : "r"(&block[0]) : "memory", "v7", "v8"
470 );
471 printf("SMINV h8, v7.4h ");
472 showV128(&block[0]); printf(" ");
473 showV128(&block[1]); printf("\n");
474 }
475
476 /* -- 16b -- */
477
478 for (i = 0; i < 10; i++) {
479 memset(&block, 0x55, sizeof(block));
480 randV128(&block[0], TyB);
481 randV128(&block[1], TyB);
482 __asm__ __volatile__(
483 "ldr q7, [%0, #0] ; "
484 "sminv b8, v7.16b ; "
485 "str q8, [%0, #16] "
486 : : "r"(&block[0]) : "memory", "v7", "v8"
487 );
488 printf("SMINV b8, v7.16b ");
489 showV128(&block[0]); printf(" ");
490 showV128(&block[1]); printf("\n");
491 }
492
493 /* -- 8b -- */
494
495 for (i = 0; i < 10; i++) {
496 memset(&block, 0x55, sizeof(block));
497 randV128(&block[0], TyB);
498 randV128(&block[1], TyB);
499 __asm__ __volatile__(
500 "ldr q7, [%0, #0] ; "
501 "sminv b8, v7.8b ; "
502 "str q8, [%0, #16] "
503 : : "r"(&block[0]) : "memory", "v7", "v8"
504 );
505 printf("SMINV b8, v7.8b ");
506 showV128(&block[0]); printf(" ");
507 showV128(&block[1]); printf("\n");
508 }
509
510 }
511
512
513 void test_SMAXV ( void )
514 {
515 int i;
516 V128 block[2];
517
518 /* -- 4s -- */
519
520 for (i = 0; i < 10; i++) {
521 memset(&block, 0x55, sizeof(block));
522 randV128(&block[0], TyS);
523 randV128(&block[1], TyS);
524 __asm__ __volatile__(
525 "ldr q7, [%0, #0] ; "
526 "smaxv s8, v7.4s ; "
527 "str q8, [%0, #16] "
528 : : "r"(&block[0]) : "memory", "v7", "v8"
529 );
530 printf("SMAXV v8, v7.4s ");
531 showV128(&block[0]); printf(" ");
532 showV128(&block[1]); printf("\n");
533 }
534
535 /* -- 8h -- */
536
537 for (i = 0; i < 10; i++) {
538 memset(&block, 0x55, sizeof(block));
539 randV128(&block[0], TyH);
540 randV128(&block[1], TyH);
541 __asm__ __volatile__(
542 "ldr q7, [%0, #0] ; "
543 "smaxv h8, v7.8h ; "
544 "str q8, [%0, #16] "
545 : : "r"(&block[0]) : "memory", "v7", "v8"
546 );
547 printf("SMAXV h8, v7.8h ");
548 showV128(&block[0]); printf(" ");
549 showV128(&block[1]); printf("\n");
550 }
551
552 /* -- 4h -- */
553
554 for (i = 0; i < 10; i++) {
555 memset(&block, 0x55, sizeof(block));
556 randV128(&block[0], TyH);
557 randV128(&block[1], TyH);
558 __asm__ __volatile__(
559 "ldr q7, [%0, #0] ; "
560 "smaxv h8, v7.4h ; "
561 "str q8, [%0, #16] "
562 : : "r"(&block[0]) : "memory", "v7", "v8"
563 );
564 printf("SMAXV h8, v7.4h ");
565 showV128(&block[0]); printf(" ");
566 showV128(&block[1]); printf("\n");
567 }
568
569 /* -- 16b -- */
570
571 for (i = 0; i < 10; i++) {
572 memset(&block, 0x55, sizeof(block));
573 randV128(&block[0], TyB);
574 randV128(&block[1], TyB);
575 __asm__ __volatile__(
576 "ldr q7, [%0, #0] ; "
577 "smaxv b8, v7.16b ; "
578 "str q8, [%0, #16] "
579 : : "r"(&block[0]) : "memory", "v7", "v8"
580 );
581 printf("SMAXV b8, v7.16b ");
582 showV128(&block[0]); printf(" ");
583 showV128(&block[1]); printf("\n");
584 }
585
586 /* -- 8b -- */
587
588 for (i = 0; i < 10; i++) {
589 memset(&block, 0x55, sizeof(block));
590 randV128(&block[0], TyB);
591 randV128(&block[1], TyB);
592 __asm__ __volatile__(
593 "ldr q7, [%0, #0] ; "
594 "smaxv b8, v7.8b ; "
595 "str q8, [%0, #16] "
596 : : "r"(&block[0]) : "memory", "v7", "v8"
597 );
598 printf("SMAXV b8, v7.8b ");
599 showV128(&block[0]); printf(" ");
600 showV128(&block[1]); printf("\n");
601 }
602
603 }
604
605
606 //======== FCCMP_D ========//
607
608 #define GEN_test_FCCMP_D_D_0xF_EQ \
609 __attribute__((noinline)) static void test_FCCMP_D_D_0xF_EQ ( void ) \
610 { \
611 V128 block[4]; \
612 randBlock_Doubles(&block[0], 3); \
613 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
614 showBlock("FCCMP_D_D_0xF_EQ before", &block[0], 4); \
615 __asm__ __volatile__( \
616 "ldr x9, [%0, 48]; msr nzcv, x9; " \
617 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
618 "fccmp d29, d11, #0xf, eq; " \
619 "mrs x9, nzcv; str x9, [%0, 48]; " \
620 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
621 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
622 ); \
623 showBlock("FCCMP_D_D_0xF_EQ after", &block[0], 4); \
624 printf("\n"); \
625 }
626
627 #define GEN_test_FCCMP_D_D_0xF_NE \
628 __attribute__((noinline)) static void test_FCCMP_D_D_0xF_NE ( void ) \
629 { \
630 V128 block[4]; \
631 randBlock_Doubles(&block[0], 3); \
632 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
633 showBlock("FCCMP_D_D_0xF_NE before", &block[0], 4); \
634 __asm__ __volatile__( \
635 "ldr x9, [%0, 48]; msr nzcv, x9; " \
636 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
637 "fccmp d29, d11, #0xf, ne; " \
638 "mrs x9, nzcv; str x9, [%0, 48]; " \
639 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
640 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
641 ); \
642 showBlock("FCCMP_D_D_0xF_NE after", &block[0], 4); \
643 printf("\n"); \
644 }
645
646 #define GEN_test_FCCMP_D_D_0x0_EQ \
647 __attribute__((noinline)) static void test_FCCMP_D_D_0x0_EQ ( void ) \
648 { \
649 V128 block[4]; \
650 randBlock_Doubles(&block[0], 3); \
651 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
652 showBlock("FCCMP_D_D_0x0_EQ before", &block[0], 4); \
653 __asm__ __volatile__( \
654 "ldr x9, [%0, 48]; msr nzcv, x9; " \
655 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
656 "fccmp d29, d11, #0x0, eq; " \
657 "mrs x9, nzcv; str x9, [%0, 48]; " \
658 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
659 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
660 ); \
661 showBlock("FCCMP_D_D_0x0_EQ after", &block[0], 4); \
662 printf("\n"); \
663 }
664
665 #define GEN_test_FCCMP_D_D_0x0_NE \
666 __attribute__((noinline)) static void test_FCCMP_D_D_0x0_NE ( void ) \
667 { \
668 V128 block[4]; \
669 randBlock_Doubles(&block[0], 3); \
670 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
671 showBlock("FCCMP_D_D_0x0_NE before", &block[0], 4); \
672 __asm__ __volatile__( \
673 "ldr x9, [%0, 48]; msr nzcv, x9; " \
674 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
675 "fccmp d29, d11, #0x0, ne; " \
676 "mrs x9, nzcv; str x9, [%0, 48]; " \
677 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
678 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
679 ); \
680 showBlock("FCCMP_D_D_0x0_NE after", &block[0], 4); \
681 printf("\n"); \
682 }
683
684 //======== FCCMP_S ========//
685
686 #define GEN_test_FCCMP_S_S_0xF_EQ \
687 __attribute__((noinline)) static void test_FCCMP_S_S_0xF_EQ ( void ) \
688 { \
689 V128 block[4]; \
690 randBlock_Floats(&block[0], 3); \
691 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
692 showBlock("FCCMP_S_S_0xF_EQ before", &block[0], 4); \
693 __asm__ __volatile__( \
694 "ldr x9, [%0, 48]; msr nzcv, x9; " \
695 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
696 "fccmp s29, s11, #0xf, eq; " \
697 "mrs x9, nzcv; str x9, [%0, 48]; " \
698 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
699 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
700 ); \
701 showBlock("FCCMP_S_S_0xF_EQ after", &block[0], 4); \
702 printf("\n"); \
703 }
704
705 #define GEN_test_FCCMP_S_S_0xF_NE \
706 __attribute__((noinline)) static void test_FCCMP_S_S_0xF_NE ( void ) \
707 { \
708 V128 block[4]; \
709 randBlock_Floats(&block[0], 3); \
710 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
711 showBlock("FCCMP_S_S_0xF_NE before", &block[0], 4); \
712 __asm__ __volatile__( \
713 "ldr x9, [%0, 48]; msr nzcv, x9; " \
714 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
715 "fccmp s29, s11, #0xf, ne; " \
716 "mrs x9, nzcv; str x9, [%0, 48]; " \
717 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
718 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
719 ); \
720 showBlock("FCCMP_S_S_0xF_NE after", &block[0], 4); \
721 printf("\n"); \
722 }
723
724 #define GEN_test_FCCMP_S_S_0x0_EQ \
725 __attribute__((noinline)) static void test_FCCMP_S_S_0x0_EQ ( void ) \
726 { \
727 V128 block[4]; \
728 randBlock_Floats(&block[0], 3); \
729 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
730 showBlock("FCCMP_S_S_0x0_EQ before", &block[0], 4); \
731 __asm__ __volatile__( \
732 "ldr x9, [%0, 48]; msr nzcv, x9; " \
733 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
734 "fccmp s29, s11, #0x0, eq; " \
735 "mrs x9, nzcv; str x9, [%0, 48]; " \
736 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
737 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
738 ); \
739 showBlock("FCCMP_S_S_0x0_EQ after", &block[0], 4); \
740 printf("\n"); \
741 }
742
743 #define GEN_test_FCCMP_S_S_0x0_NE \
744 __attribute__((noinline)) static void test_FCCMP_S_S_0x0_NE ( void ) \
745 { \
746 V128 block[4]; \
747 randBlock_Floats(&block[0], 3); \
748 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
749 showBlock("FCCMP_S_S_0x0_NE before", &block[0], 4); \
750 __asm__ __volatile__( \
751 "ldr x9, [%0, 48]; msr nzcv, x9; " \
752 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
753 "fccmp s29, s11, #0x0, ne; " \
754 "mrs x9, nzcv; str x9, [%0, 48]; " \
755 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
756 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
757 ); \
758 showBlock("FCCMP_S_S_0x0_NE after", &block[0], 4); \
759 printf("\n"); \
760 }
761
762 //======== FCCMPE_D ========//
763
764 #define GEN_test_FCCMPE_D_D_0xF_EQ \
765 __attribute__((noinline)) static void test_FCCMPE_D_D_0xF_EQ ( void ) \
766 { \
767 V128 block[4]; \
768 randBlock_Doubles(&block[0], 3); \
769 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
770 showBlock("FCCMPE_D_D_0xF_EQ before", &block[0], 4); \
771 __asm__ __volatile__( \
772 "ldr x9, [%0, 48]; msr nzcv, x9; " \
773 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
774 "fccmpe d29, d11, #0xf, eq; " \
775 "mrs x9, nzcv; str x9, [%0, 48]; " \
776 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
777 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
778 ); \
779 showBlock("FCCMPE_D_D_0xF_EQ after", &block[0], 4); \
780 printf("\n"); \
781 }
782
783 #define GEN_test_FCCMPE_D_D_0xF_NE \
784 __attribute__((noinline)) static void test_FCCMPE_D_D_0xF_NE ( void ) \
785 { \
786 V128 block[4]; \
787 randBlock_Doubles(&block[0], 3); \
788 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
789 showBlock("FCCMPE_D_D_0xF_NE before", &block[0], 4); \
790 __asm__ __volatile__( \
791 "ldr x9, [%0, 48]; msr nzcv, x9; " \
792 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
793 "fccmpe d29, d11, #0xf, ne; " \
794 "mrs x9, nzcv; str x9, [%0, 48]; " \
795 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
796 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
797 ); \
798 showBlock("FCCMPE_D_D_0xF_NE after", &block[0], 4); \
799 printf("\n"); \
800 }
801
802 #define GEN_test_FCCMPE_D_D_0x0_EQ \
803 __attribute__((noinline)) static void test_FCCMPE_D_D_0x0_EQ ( void ) \
804 { \
805 V128 block[4]; \
806 randBlock_Doubles(&block[0], 3); \
807 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
808 showBlock("FCCMPE_D_D_0x0_EQ before", &block[0], 4); \
809 __asm__ __volatile__( \
810 "ldr x9, [%0, 48]; msr nzcv, x9; " \
811 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
812 "fccmpe d29, d11, #0x0, eq; " \
813 "mrs x9, nzcv; str x9, [%0, 48]; " \
814 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
815 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
816 ); \
817 showBlock("FCCMPE_D_D_0x0_EQ after", &block[0], 4); \
818 printf("\n"); \
819 }
820
821 #define GEN_test_FCCMPE_D_D_0x0_NE \
822 __attribute__((noinline)) static void test_FCCMPE_D_D_0x0_NE ( void ) \
823 { \
824 V128 block[4]; \
825 randBlock_Doubles(&block[0], 3); \
826 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
827 showBlock("FCCMPE_D_D_0x0_NE before", &block[0], 4); \
828 __asm__ __volatile__( \
829 "ldr x9, [%0, 48]; msr nzcv, x9; " \
830 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
831 "fccmpe d29, d11, #0x0, ne; " \
832 "mrs x9, nzcv; str x9, [%0, 48]; " \
833 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
834 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
835 ); \
836 showBlock("FCCMPE_D_D_0x0_NE after", &block[0], 4); \
837 printf("\n"); \
838 }
839
840 //======== FCCMPE_S ========//
841
842 #define GEN_test_FCCMPE_S_S_0xF_EQ \
843 __attribute__((noinline)) static void test_FCCMPE_S_S_0xF_EQ ( void ) \
844 { \
845 V128 block[4]; \
846 randBlock_Floats(&block[0], 3); \
847 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
848 showBlock("FCCMP_S_S_0xF_EQ before", &block[0], 4); \
849 __asm__ __volatile__( \
850 "ldr x9, [%0, 48]; msr nzcv, x9; " \
851 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
852 "fccmpe s29, s11, #0xf, eq; " \
853 "mrs x9, nzcv; str x9, [%0, 48]; " \
854 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
855 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
856 ); \
857 showBlock("FCCMPE_S_S_0xF_EQ after", &block[0], 4); \
858 printf("\n"); \
859 }
860
861 #define GEN_test_FCCMPE_S_S_0xF_NE \
862 __attribute__((noinline)) static void test_FCCMPE_S_S_0xF_NE ( void ) \
863 { \
864 V128 block[4]; \
865 randBlock_Floats(&block[0], 3); \
866 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
867 showBlock("FCCMPE_S_S_0xF_NE before", &block[0], 4); \
868 __asm__ __volatile__( \
869 "ldr x9, [%0, 48]; msr nzcv, x9; " \
870 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
871 "fccmpe s29, s11, #0xf, ne; " \
872 "mrs x9, nzcv; str x9, [%0, 48]; " \
873 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
874 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
875 ); \
876 showBlock("FCCMPE_S_S_0xF_NE after", &block[0], 4); \
877 printf("\n"); \
878 }
879
880 #define GEN_test_FCCMPE_S_S_0x0_EQ \
881 __attribute__((noinline)) static void test_FCCMPE_S_S_0x0_EQ ( void ) \
882 { \
883 V128 block[4]; \
884 randBlock_Floats(&block[0], 3); \
885 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
886 showBlock("FCCMP_S_S_0x0_EQ before", &block[0], 4); \
887 __asm__ __volatile__( \
888 "ldr x9, [%0, 48]; msr nzcv, x9; " \
889 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
890 "fccmpe s29, s11, #0x0, eq; " \
891 "mrs x9, nzcv; str x9, [%0, 48]; " \
892 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
893 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
894 ); \
895 showBlock("FCCMPE_S_S_0x0_EQ after", &block[0], 4); \
896 printf("\n"); \
897 }
898
899 #define GEN_test_FCCMPE_S_S_0x0_NE \
900 __attribute__((noinline)) static void test_FCCMPE_S_S_0x0_NE ( void ) \
901 { \
902 V128 block[4]; \
903 randBlock_Floats(&block[0], 3); \
904 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
905 showBlock("FCCMP_S_S_0x0_NE before", &block[0], 4); \
906 __asm__ __volatile__( \
907 "ldr x9, [%0, 48]; msr nzcv, x9; " \
908 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
909 "fccmpe s29, s11, #0x0, ne; " \
910 "mrs x9, nzcv; str x9, [%0, 48]; " \
911 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
912 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
913 ); \
914 showBlock("FCCMPE_S_S_0x0_NE after", &block[0], 4); \
915 printf("\n"); \
916 }
917
918 //======== FCMEQ_D_D_D ========//
919
920 #define GEN_test_FCMEQ_D_D_D \
921 __attribute__((noinline)) static void test_FCMEQ_D_D_D ( void ) \
922 { \
923 V128 block[4]; \
924 randBlock_Doubles(&block[0], 3); \
925 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
926 showBlock("FCMEQ_D_D_D before", &block[0], 4); \
927 __asm__ __volatile__( \
928 "ldr x9, [%0, 48]; msr nzcv, x9; " \
929 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
930 "fcmeq d29, d11, d9; " \
931 "mrs x9, nzcv; str x9, [%0, 48]; " \
932 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
933 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
934 ); \
935 showBlock("FCMEQ_D_D_D after", &block[0], 4); \
936 printf("\n"); \
937 }
938
939 //======== FCMEQ_S_S_S ========//
940
941 #define GEN_test_FCMEQ_S_S_S \
942 __attribute__((noinline)) static void test_FCMEQ_S_S_S ( void ) \
943 { \
944 V128 block[4]; \
945 randBlock_Floats(&block[0], 3); \
946 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
947 showBlock("FCMEQ_S_S_S before", &block[0], 4); \
948 __asm__ __volatile__( \
949 "ldr x9, [%0, 48]; msr nzcv, x9; " \
950 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
951 "fcmeq s29, s11, s9; " \
952 "mrs x9, nzcv; str x9, [%0, 48]; " \
953 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
954 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
955 ); \
956 showBlock("FCMEQ_S_S_S after", &block[0], 4); \
957 printf("\n"); \
958 }
959
960 //======== FCMGE_D_D_D ========//
961
962 #define GEN_test_FCMGE_D_D_D \
963 __attribute__((noinline)) static void test_FCMGE_D_D_D ( void ) \
964 { \
965 V128 block[4]; \
966 randBlock_Doubles(&block[0], 3); \
967 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
968 showBlock("FCMGE_D_D_D before", &block[0], 4); \
969 __asm__ __volatile__( \
970 "ldr x9, [%0, 48]; msr nzcv, x9; " \
971 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
972 "fcmge d29, d11, d9; " \
973 "mrs x9, nzcv; str x9, [%0, 48]; " \
974 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
975 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
976 ); \
977 showBlock("FCMGE_D_D_D after", &block[0], 4); \
978 printf("\n"); \
979 }
980
981 //======== FCMGE_S_S_S ========//
982
983 #define GEN_test_FCMGE_S_S_S \
984 __attribute__((noinline)) static void test_FCMGE_S_S_S ( void ) \
985 { \
986 V128 block[4]; \
987 randBlock_Floats(&block[0], 3); \
988 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
989 showBlock("FCMGE_S_S_S before", &block[0], 4); \
990 __asm__ __volatile__( \
991 "ldr x9, [%0, 48]; msr nzcv, x9; " \
992 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
993 "fcmge s29, s11, s9; " \
994 "mrs x9, nzcv; str x9, [%0, 48]; " \
995 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
996 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
997 ); \
998 showBlock("FCMGE_S_S_S after", &block[0], 4); \
999 printf("\n"); \
1000 }
1001
1002 //======== FCMGT_D_D_D ========//
1003
1004 #define GEN_test_FCMGT_D_D_D \
1005 __attribute__((noinline)) static void test_FCMGT_D_D_D ( void ) \
1006 { \
1007 V128 block[4]; \
1008 randBlock_Doubles(&block[0], 3); \
1009 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1010 showBlock("FCMGT_D_D_D before", &block[0], 4); \
1011 __asm__ __volatile__( \
1012 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1013 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1014 "fcmgt d29, d11, d9; " \
1015 "mrs x9, nzcv; str x9, [%0, 48]; " \
1016 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1017 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1018 ); \
1019 showBlock("FCMGT_D_D_D after", &block[0], 4); \
1020 printf("\n"); \
1021 }
1022
1023 //======== FCMGT_S_S_S ========//
1024
1025 #define GEN_test_FCMGT_S_S_S \
1026 __attribute__((noinline)) static void test_FCMGT_S_S_S ( void ) \
1027 { \
1028 V128 block[4]; \
1029 randBlock_Floats(&block[0], 3); \
1030 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1031 showBlock("FCMGT_S_S_S before", &block[0], 4); \
1032 __asm__ __volatile__( \
1033 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1034 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1035 "fcmgt s29, s11, s9; " \
1036 "mrs x9, nzcv; str x9, [%0, 48]; " \
1037 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1038 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1039 ); \
1040 showBlock("FCMGT_S_S_S after", &block[0], 4); \
1041 printf("\n"); \
1042 }
1043
1044 //======== FACGT_D_D_D ========//
1045
1046 #define GEN_test_FACGT_D_D_D \
1047 __attribute__((noinline)) static void test_FACGT_D_D_D ( void ) \
1048 { \
1049 V128 block[4]; \
1050 randBlock_Doubles(&block[0], 3); \
1051 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1052 showBlock("FACGT_D_D_D before", &block[0], 4); \
1053 __asm__ __volatile__( \
1054 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1055 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1056 "facgt d29, d11, d9; " \
1057 "mrs x9, nzcv; str x9, [%0, 48]; " \
1058 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1059 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1060 ); \
1061 showBlock("FACGT_D_D_D after", &block[0], 4); \
1062 printf("\n"); \
1063 }
1064
1065 //======== FACGT_S_S_S ========//
1066
1067 #define GEN_test_FACGT_S_S_S \
1068 __attribute__((noinline)) static void test_FACGT_S_S_S ( void ) \
1069 { \
1070 V128 block[4]; \
1071 randBlock_Floats(&block[0], 3); \
1072 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1073 showBlock("FACGT_S_S_S before", &block[0], 4); \
1074 __asm__ __volatile__( \
1075 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1076 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1077 "facgt s29, s11, s9; " \
1078 "mrs x9, nzcv; str x9, [%0, 48]; " \
1079 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1080 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1081 ); \
1082 showBlock("FACGT_S_S_S after", &block[0], 4); \
1083 printf("\n"); \
1084 }
1085
1086 //======== FACGE_D_D_D ========//
1087
1088 #define GEN_test_FACGE_D_D_D \
1089 __attribute__((noinline)) static void test_FACGE_D_D_D ( void ) \
1090 { \
1091 V128 block[4]; \
1092 randBlock_Doubles(&block[0], 3); \
1093 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1094 showBlock("FACGE_D_D_D before", &block[0], 4); \
1095 __asm__ __volatile__( \
1096 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1097 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1098 "facge d29, d11, d9; " \
1099 "mrs x9, nzcv; str x9, [%0, 48]; " \
1100 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1101 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1102 ); \
1103 showBlock("FACGE_D_D_D after", &block[0], 4); \
1104 printf("\n"); \
1105 }
1106
1107 //======== FACGE_S_S_S ========//
1108
1109 #define GEN_test_FACGE_S_S_S \
1110 __attribute__((noinline)) static void test_FACGE_S_S_S ( void ) \
1111 { \
1112 V128 block[4]; \
1113 randBlock_Floats(&block[0], 3); \
1114 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1115 showBlock("FACGE_S_S_S before", &block[0], 4); \
1116 __asm__ __volatile__( \
1117 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1118 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1119 "facge s29, s11, s9; " \
1120 "mrs x9, nzcv; str x9, [%0, 48]; " \
1121 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1122 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1123 ); \
1124 showBlock("FACGE_S_S_S after", &block[0], 4); \
1125 printf("\n"); \
1126 }
1127
1128 //======== FCMEQ_D_D_Z ========//
1129
1130 #define GEN_test_FCMEQ_D_D_Z \
1131 __attribute__((noinline)) static void test_FCMEQ_D_D_Z ( void ) \
1132 { \
1133 V128 block[4]; \
1134 randBlock_Doubles(&block[0], 3); \
1135 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1136 showBlock("FCMEQ_D_D_Z before", &block[0], 4); \
1137 __asm__ __volatile__( \
1138 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1139 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1140 "fcmeq d29, d11, #0; " \
1141 "mrs x9, nzcv; str x9, [%0, 48]; " \
1142 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1143 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1144 ); \
1145 showBlock("FCMEQ_D_D_Z after", &block[0], 4); \
1146 printf("\n"); \
1147 }
1148
1149 //======== FCMEQ_S_S_Z ========//
1150
1151 #define GEN_test_FCMEQ_S_S_Z \
1152 __attribute__((noinline)) static void test_FCMEQ_S_S_Z ( void ) \
1153 { \
1154 V128 block[4]; \
1155 randBlock_Floats(&block[0], 3); \
1156 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1157 showBlock("FCMEQ_S_S_Z before", &block[0], 4); \
1158 __asm__ __volatile__( \
1159 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1160 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1161 "fcmeq s29, s11, #0; " \
1162 "mrs x9, nzcv; str x9, [%0, 48]; " \
1163 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1164 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1165 ); \
1166 showBlock("FCMEQ_S_S_Z after", &block[0], 4); \
1167 printf("\n"); \
1168 }
1169
1170 //======== FCMGE_D_D_Z ========//
1171
1172 #define GEN_test_FCMGE_D_D_Z \
1173 __attribute__((noinline)) static void test_FCMGE_D_D_Z ( void ) \
1174 { \
1175 V128 block[4]; \
1176 randBlock_Doubles(&block[0], 3); \
1177 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1178 showBlock("FCMGE_D_D_Z before", &block[0], 4); \
1179 __asm__ __volatile__( \
1180 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1181 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1182 "fcmge d29, d11, #0; " \
1183 "mrs x9, nzcv; str x9, [%0, 48]; " \
1184 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1185 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1186 ); \
1187 showBlock("FCMGE_D_D_Z after", &block[0], 4); \
1188 printf("\n"); \
1189 }
1190
1191 //======== FCMGE_S_S_Z ========//
1192
1193 #define GEN_test_FCMGE_S_S_Z \
1194 __attribute__((noinline)) static void test_FCMGE_S_S_Z ( void ) \
1195 { \
1196 V128 block[4]; \
1197 randBlock_Floats(&block[0], 3); \
1198 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1199 showBlock("FCMGE_S_S_Z before", &block[0], 4); \
1200 __asm__ __volatile__( \
1201 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1202 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1203 "fcmge s29, s11, #0; " \
1204 "mrs x9, nzcv; str x9, [%0, 48]; " \
1205 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1206 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1207 ); \
1208 showBlock("FCMGE_S_S_Z after", &block[0], 4); \
1209 printf("\n"); \
1210 }
1211
1212 //======== FCMGT_D_D_Z ========//
1213
1214 #define GEN_test_FCMGT_D_D_Z \
1215 __attribute__((noinline)) static void test_FCMGT_D_D_Z ( void ) \
1216 { \
1217 V128 block[4]; \
1218 randBlock_Doubles(&block[0], 3); \
1219 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1220 showBlock("FCMGT_D_D_Z before", &block[0], 4); \
1221 __asm__ __volatile__( \
1222 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1223 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1224 "fcmgt d29, d11, #0; " \
1225 "mrs x9, nzcv; str x9, [%0, 48]; " \
1226 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1227 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1228 ); \
1229 showBlock("FCMGT_D_D_Z after", &block[0], 4); \
1230 printf("\n"); \
1231 }
1232
1233 //======== FCMGT_S_S_Z ========//
1234
1235 #define GEN_test_FCMGT_S_S_Z \
1236 __attribute__((noinline)) static void test_FCMGT_S_S_Z ( void ) \
1237 { \
1238 V128 block[4]; \
1239 randBlock_Floats(&block[0], 3); \
1240 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1241 showBlock("FCMGT_S_S_Z before", &block[0], 4); \
1242 __asm__ __volatile__( \
1243 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1244 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1245 "fcmgt s29, s11, #0; " \
1246 "mrs x9, nzcv; str x9, [%0, 48]; " \
1247 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1248 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1249 ); \
1250 showBlock("FCMGT_S_S_Z after", &block[0], 4); \
1251 printf("\n"); \
1252 }
1253
1254 //======== FCMLE_D_D_Z ========//
1255
1256 #define GEN_test_FCMLE_D_D_Z \
1257 __attribute__((noinline)) static void test_FCMLE_D_D_Z ( void ) \
1258 { \
1259 V128 block[4]; \
1260 randBlock_Doubles(&block[0], 3); \
1261 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1262 showBlock("FCMLE_D_D_Z before", &block[0], 4); \
1263 __asm__ __volatile__( \
1264 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1265 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1266 "fcmle d29, d11, #0; " \
1267 "mrs x9, nzcv; str x9, [%0, 48]; " \
1268 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1269 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1270 ); \
1271 showBlock("FCMLE_D_D_Z after", &block[0], 4); \
1272 printf("\n"); \
1273 }
1274
1275 //======== FCMLE_S_S_Z ========//
1276
1277 #define GEN_test_FCMLE_S_S_Z \
1278 __attribute__((noinline)) static void test_FCMLE_S_S_Z ( void ) \
1279 { \
1280 V128 block[4]; \
1281 randBlock_Floats(&block[0], 3); \
1282 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1283 showBlock("FCMLE_S_S_Z before", &block[0], 4); \
1284 __asm__ __volatile__( \
1285 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1286 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1287 "fcmle s29, s11, #0; " \
1288 "mrs x9, nzcv; str x9, [%0, 48]; " \
1289 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1290 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1291 ); \
1292 showBlock("FCMLE_S_S_Z after", &block[0], 4); \
1293 printf("\n"); \
1294 }
1295
1296 //======== FCMLT_D_D_Z ========//
1297
1298 #define GEN_test_FCMLT_D_D_Z \
1299 __attribute__((noinline)) static void test_FCMLT_D_D_Z ( void ) \
1300 { \
1301 V128 block[4]; \
1302 randBlock_Doubles(&block[0], 3); \
1303 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1304 showBlock("FCMLT_D_D_Z before", &block[0], 4); \
1305 __asm__ __volatile__( \
1306 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1307 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1308 "fcmlt d29, d11, #0; " \
1309 "mrs x9, nzcv; str x9, [%0, 48]; " \
1310 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1311 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1312 ); \
1313 showBlock("FCMLT_D_D_Z after", &block[0], 4); \
1314 printf("\n"); \
1315 }
1316
1317 //======== FCMLT_S_S_Z ========//
1318
1319 #define GEN_test_FCMLT_S_S_Z \
1320 __attribute__((noinline)) static void test_FCMLT_S_S_Z ( void ) \
1321 { \
1322 V128 block[4]; \
1323 randBlock_Floats(&block[0], 3); \
1324 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1325 showBlock("FCMLT_S_S_Z before", &block[0], 4); \
1326 __asm__ __volatile__( \
1327 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1328 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1329 "fcmlt s29, s11, #0; " \
1330 "mrs x9, nzcv; str x9, [%0, 48]; " \
1331 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1332 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1333 ); \
1334 showBlock("FCMLT_S_S_Z after", &block[0], 4); \
1335 printf("\n"); \
1336 }
1337
1338 //======== FCMP_D_D ========//
1339
1340 #define GEN_test_FCMP_D_D \
1341 __attribute__((noinline)) static void test_FCMP_D_D ( void ) \
1342 { \
1343 V128 block[4]; \
1344 randBlock_Doubles(&block[0], 3); \
1345 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1346 showBlock("FCMP_D_D before", &block[0], 4); \
1347 __asm__ __volatile__( \
1348 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1349 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1350 "fcmp d29, d11; " \
1351 "mrs x9, nzcv; str x9, [%0, 48]; " \
1352 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1353 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1354 ); \
1355 showBlock("FCMP_D_D after", &block[0], 4); \
1356 printf("\n"); \
1357 }
1358
1359 //======== FCMP_S_S ========//
1360
1361 #define GEN_test_FCMP_S_S \
1362 __attribute__((noinline)) static void test_FCMP_S_S ( void ) \
1363 { \
1364 V128 block[4]; \
1365 randBlock_Floats(&block[0], 3); \
1366 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1367 showBlock("FCMP_S_S before", &block[0], 4); \
1368 __asm__ __volatile__( \
1369 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1370 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1371 "fcmp s29, s11; " \
1372 "mrs x9, nzcv; str x9, [%0, 48]; " \
1373 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1374 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1375 ); \
1376 showBlock("FCMP_S_S after", &block[0], 4); \
1377 printf("\n"); \
1378 }
1379
1380 //======== FCMPE_D_D ========//
1381
1382 #define GEN_test_FCMPE_D_D \
1383 __attribute__((noinline)) static void test_FCMPE_D_D ( void ) \
1384 { \
1385 V128 block[4]; \
1386 randBlock_Doubles(&block[0], 3); \
1387 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1388 showBlock("FCMPE_D_D before", &block[0], 4); \
1389 __asm__ __volatile__( \
1390 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1391 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1392 "fcmpe d29, d11; " \
1393 "mrs x9, nzcv; str x9, [%0, 48]; " \
1394 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1395 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1396 ); \
1397 showBlock("FCMPE_D_D after", &block[0], 4); \
1398 printf("\n"); \
1399 }
1400
1401 //======== FCMPE_S_S ========//
1402
1403 #define GEN_test_FCMPE_S_S \
1404 __attribute__((noinline)) static void test_FCMPE_S_S ( void ) \
1405 { \
1406 V128 block[4]; \
1407 randBlock_Floats(&block[0], 3); \
1408 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1409 showBlock("FCMPE_S_S before", &block[0], 4); \
1410 __asm__ __volatile__( \
1411 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1412 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1413 "fcmpe s29, s11; " \
1414 "mrs x9, nzcv; str x9, [%0, 48]; " \
1415 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1416 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1417 ); \
1418 showBlock("FCMPE_S_S after", &block[0], 4); \
1419 printf("\n"); \
1420 }
1421
1422 //======== FCMP_D_Z ========//
1423
1424 #define GEN_test_FCMP_D_Z \
1425 __attribute__((noinline)) static void test_FCMP_D_Z ( void ) \
1426 { \
1427 V128 block[4]; \
1428 randBlock_Doubles(&block[0], 3); \
1429 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1430 showBlock("FCMP_D_Z before", &block[0], 4); \
1431 __asm__ __volatile__( \
1432 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1433 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1434 "fcmp d29, #0.0; " \
1435 "mrs x9, nzcv; str x9, [%0, 48]; " \
1436 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1437 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1438 ); \
1439 showBlock("FCMP_D_Z after", &block[0], 4); \
1440 printf("\n"); \
1441 }
1442
1443 //======== FCMP_S_Z ========//
1444
1445 #define GEN_test_FCMP_S_Z \
1446 __attribute__((noinline)) static void test_FCMP_S_Z ( void ) \
1447 { \
1448 V128 block[4]; \
1449 randBlock_Floats(&block[0], 3); \
1450 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1451 showBlock("FCMP_S_Z before", &block[0], 4); \
1452 __asm__ __volatile__( \
1453 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1454 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1455 "fcmp s29, #0.0; " \
1456 "mrs x9, nzcv; str x9, [%0, 48]; " \
1457 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1458 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1459 ); \
1460 showBlock("FCMP_S_Z after", &block[0], 4); \
1461 printf("\n"); \
1462 }
1463
1464 //======== FCMPE_D_Z ========//
1465
1466 #define GEN_test_FCMPE_D_Z \
1467 __attribute__((noinline)) static void test_FCMPE_D_Z ( void ) \
1468 { \
1469 V128 block[4]; \
1470 randBlock_Doubles(&block[0], 3); \
1471 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1472 showBlock("FCMPE_D_Z before", &block[0], 4); \
1473 __asm__ __volatile__( \
1474 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1475 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1476 "fcmpe d29, #0.0; " \
1477 "mrs x9, nzcv; str x9, [%0, 48]; " \
1478 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1479 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1480 ); \
1481 showBlock("FCMPE_D_Z after", &block[0], 4); \
1482 printf("\n"); \
1483 }
1484
1485 //======== FCMPE_S_Z ========//
1486
1487 #define GEN_test_FCMPE_S_Z \
1488 __attribute__((noinline)) static void test_FCMPE_S_Z ( void ) \
1489 { \
1490 V128 block[4]; \
1491 randBlock_Floats(&block[0], 3); \
1492 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1493 showBlock("FCMPE_S_Z before", &block[0], 4); \
1494 __asm__ __volatile__( \
1495 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1496 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1497 "fcmpe s29, #0.0; " \
1498 "mrs x9, nzcv; str x9, [%0, 48]; " \
1499 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1500 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1501 ); \
1502 showBlock("FCMPE_S_Z after", &block[0], 4); \
1503 printf("\n"); \
1504 }
1505
1506 //======== FCSEL_D_D_D_EQ ========//
1507
1508 #define GEN_test_FCSEL_D_D_D_EQ \
1509 __attribute__((noinline)) static void test_FCSEL_D_D_D_EQ ( void ) \
1510 { \
1511 V128 block[4]; \
1512 randBlock_Doubles(&block[0], 3); \
1513 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1514 showBlock("FCSEL_D_D_D_EQ before", &block[0], 4); \
1515 __asm__ __volatile__( \
1516 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1517 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1518 "fcsel d29, d11, d9, eq; " \
1519 "mrs x9, nzcv; str x9, [%0, 48]; " \
1520 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1521 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1522 ); \
1523 showBlock("FCSEL_D_D_D_EQ after", &block[0], 4); \
1524 printf("\n"); \
1525 }
1526
1527 //======== FCSEL_D_D_D_NE ========//
1528
1529 #define GEN_test_FCSEL_D_D_D_NE \
1530 __attribute__((noinline)) static void test_FCSEL_D_D_D_NE ( void ) \
1531 { \
1532 V128 block[4]; \
1533 randBlock_Doubles(&block[0], 3); \
1534 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1535 showBlock("FCSEL_D_D_D_NE before", &block[0], 4); \
1536 __asm__ __volatile__( \
1537 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1538 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1539 "fcsel d29, d11, d9, ne; " \
1540 "mrs x9, nzcv; str x9, [%0, 48]; " \
1541 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1542 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1543 ); \
1544 showBlock("FCSEL_D_D_D_NE after", &block[0], 4); \
1545 printf("\n"); \
1546 }
1547
1548 //======== FCSEL_S_S_S_EQ ========//
1549
1550 #define GEN_test_FCSEL_S_S_S_EQ \
1551 __attribute__((noinline)) static void test_FCSEL_S_S_S_EQ ( void ) \
1552 { \
1553 V128 block[4]; \
1554 randBlock_Doubles(&block[0], 3); \
1555 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1556 showBlock("FCSEL_S_S_S_EQ before", &block[0], 4); \
1557 __asm__ __volatile__( \
1558 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1559 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1560 "fcsel s29, s11, s9, eq; " \
1561 "mrs x9, nzcv; str x9, [%0, 48]; " \
1562 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1563 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1564 ); \
1565 showBlock("FCSEL_S_S_S_EQ after", &block[0], 4); \
1566 printf("\n"); \
1567 }
1568
1569 //======== FCSEL_S_S_S_NE ========//
1570
1571 #define GEN_test_FCSEL_S_S_S_NE \
1572 __attribute__((noinline)) static void test_FCSEL_S_S_S_NE ( void ) \
1573 { \
1574 V128 block[4]; \
1575 randBlock_Doubles(&block[0], 3); \
1576 block[3].u64[0] = dup4x16(0x5); block[3].u64[1] = dup4x16(0xA); \
1577 showBlock("FCSEL_S_S_S_NE before", &block[0], 4); \
1578 __asm__ __volatile__( \
1579 "ldr x9, [%0, 48]; msr nzcv, x9; " \
1580 "ldr q29, [%0, #0]; ldr q11, [%0, #16]; ldr q9, [%0, #32]; " \
1581 "fcsel s29, s11, s9, ne; " \
1582 "mrs x9, nzcv; str x9, [%0, 48]; " \
1583 "str q29, [%0, #0]; str q11, [%0, #16]; str q9, [%0, #32]; " \
1584 ::"r"(&block[0]) : "x9","cc","memory","v9","v11","v29" \
1585 ); \
1586 showBlock("FCSEL_S_S_S_NE after", &block[0], 4); \
1587 printf("\n"); \
1588 }
1589
1590
1591 /* ---------------------------------------------------------------- */
1592 /* -- Tests, in the same order that they appear in main() -- */
1593 /* ---------------------------------------------------------------- */
1594
1595 // ======================== FP ========================
1596
1597 GEN_TWOVEC_TEST(fabs_d_d, "fabs d22, d23", 22, 23)
1598 GEN_TWOVEC_TEST(fabs_s_s, "fabs s22, s23", 22, 23)
1599 GEN_TWOVEC_TEST(fabs_2d_2d, "fabs v22.2d, v23.2d", 22, 23)
1600 GEN_TWOVEC_TEST(fabs_4s_4s, "fabs v22.4s, v23.4s", 22, 23)
1601 GEN_TWOVEC_TEST(fabs_2s_2s, "fabs v22.2s, v23.2s", 22, 23)
1602
1603 GEN_TWOVEC_TEST(fneg_d_d, "fneg d22, d23", 22, 23)
1604 GEN_TWOVEC_TEST(fneg_s_s, "fneg s22, s23", 22, 23)
1605 GEN_TWOVEC_TEST(fneg_2d_2d, "fneg v22.2d, v23.2d", 22, 23)
1606 GEN_TWOVEC_TEST(fneg_4s_4s, "fneg v22.4s, v23.4s", 22, 23)
1607 GEN_TWOVEC_TEST(fneg_2s_2s, "fneg v22.2s, v23.2s", 22, 23)
1608
1609 GEN_TWOVEC_TEST(fsqrt_d_d, "fsqrt d22, d23", 22, 23)
1610 GEN_TWOVEC_TEST(fsqrt_s_s, "fsqrt s22, s23", 22, 23)
1611 GEN_TWOVEC_TEST(fsqrt_2d_2d, "fsqrt v22.2d, v23.2d", 22, 23)
1612 GEN_TWOVEC_TEST(fsqrt_4s_4s, "fsqrt v22.4s, v23.4s", 22, 23)
1613 GEN_TWOVEC_TEST(fsqrt_2s_2s, "fsqrt v22.2s, v23.2s", 22, 23)
1614
1615 GEN_THREEVEC_TEST(fadd_d_d_d, "fadd d2, d11, d29", 2, 11, 29)
1616 GEN_THREEVEC_TEST(fadd_s_s_s, "fadd s2, s11, s29", 2, 11, 29)
1617 GEN_THREEVEC_TEST(fsub_d_d_d, "fsub d2, d11, d29", 2, 11, 29)
1618 GEN_THREEVEC_TEST(fsub_s_s_s, "fsub s2, s11, s29", 2, 11, 29)
1619
1620 GEN_BINARY_TEST(fadd, 2d, 2d, 2d)
1621 GEN_BINARY_TEST(fadd, 4s, 4s, 4s)
1622 GEN_BINARY_TEST(fadd, 2s, 2s, 2s)
1623 GEN_BINARY_TEST(fsub, 2d, 2d, 2d)
1624 GEN_BINARY_TEST(fsub, 4s, 4s, 4s)
1625 GEN_BINARY_TEST(fsub, 2s, 2s, 2s)
1626
1627 GEN_THREEVEC_TEST(fabd_d_d_d, "fabd d2, d11, d29", 2, 11, 29)
1628 GEN_THREEVEC_TEST(fabd_s_s_s, "fabd s2, s11, s29", 2, 11, 29)
1629 GEN_BINARY_TEST(fabd, 2d, 2d, 2d)
1630 GEN_BINARY_TEST(fabd, 4s, 4s, 4s)
1631 GEN_BINARY_TEST(fabd, 2s, 2s, 2s)
1632
1633 GEN_TWOVEC_TEST(faddp_d_2d, "faddp d2, v23.2d", 2, 23)
1634 GEN_TWOVEC_TEST(faddp_s_2s, "faddp s2, v23.2s", 2, 23)
1635 GEN_THREEVEC_TEST(faddp_2d_2d_2d, "faddp v2.2d, v23.2d, v11.2d", 2, 23, 11)
1636 GEN_THREEVEC_TEST(faddp_4s_4s_4s, "faddp v2.4s, v23.4s, v11.4s", 2, 23, 11)
1637 GEN_THREEVEC_TEST(faddp_2s_2s_2s, "faddp v2.2s, v23.2s, v11.2s", 2, 23, 11)
1638
1639 GEN_test_FCCMP_D_D_0xF_EQ
1640 GEN_test_FCCMP_D_D_0xF_NE
1641 GEN_test_FCCMP_D_D_0x0_EQ
1642 GEN_test_FCCMP_D_D_0x0_NE
1643 GEN_test_FCCMP_S_S_0xF_EQ
1644 GEN_test_FCCMP_S_S_0xF_NE
1645 GEN_test_FCCMP_S_S_0x0_EQ
1646 GEN_test_FCCMP_S_S_0x0_NE
1647 GEN_test_FCCMPE_D_D_0xF_EQ
1648 GEN_test_FCCMPE_D_D_0xF_NE
1649 GEN_test_FCCMPE_D_D_0x0_EQ
1650 GEN_test_FCCMPE_D_D_0x0_NE
1651 GEN_test_FCCMPE_S_S_0xF_EQ
1652 GEN_test_FCCMPE_S_S_0xF_NE
1653 GEN_test_FCCMPE_S_S_0x0_EQ
1654 GEN_test_FCCMPE_S_S_0x0_NE
1655
1656 GEN_test_FCMEQ_D_D_D
1657 GEN_test_FCMEQ_S_S_S
1658 GEN_test_FCMGE_D_D_D
1659 GEN_test_FCMGE_S_S_S
1660 GEN_test_FCMGT_D_D_D
1661 GEN_test_FCMGT_S_S_S
1662 GEN_test_FACGT_D_D_D
1663 GEN_test_FACGT_S_S_S
1664 GEN_test_FACGE_D_D_D
1665 GEN_test_FACGE_S_S_S
1666
1667 GEN_THREEVEC_TEST(fcmeq_2d_2d_2d, "fcmeq v2.2d, v23.2d, v11.2d", 2, 23, 11)
1668 GEN_THREEVEC_TEST(fcmeq_4s_4s_4s, "fcmeq v2.4s, v23.4s, v11.4s", 2, 23, 11)
1669 GEN_THREEVEC_TEST(fcmeq_2s_2s_2s, "fcmeq v2.2s, v23.2s, v11.2s", 2, 23, 11)
1670 GEN_THREEVEC_TEST(fcmge_2d_2d_2d, "fcmge v2.2d, v23.2d, v11.2d", 2, 23, 11)
1671 GEN_THREEVEC_TEST(fcmge_4s_4s_4s, "fcmge v2.4s, v23.4s, v11.4s", 2, 23, 11)
1672 GEN_THREEVEC_TEST(fcmge_2s_2s_2s, "fcmge v2.2s, v23.2s, v11.2s", 2, 23, 11)
1673 GEN_THREEVEC_TEST(fcmgt_2d_2d_2d, "fcmgt v2.2d, v23.2d, v11.2d", 2, 23, 11)
1674 GEN_THREEVEC_TEST(fcmgt_4s_4s_4s, "fcmgt v2.4s, v23.4s, v11.4s", 2, 23, 11)
1675 GEN_THREEVEC_TEST(fcmgt_2s_2s_2s, "fcmgt v2.2s, v23.2s, v11.2s", 2, 23, 11)
1676 GEN_THREEVEC_TEST(facge_2d_2d_2d, "facge v2.2d, v23.2d, v11.2d", 2, 23, 11)
1677 GEN_THREEVEC_TEST(facge_4s_4s_4s, "facge v2.4s, v23.4s, v11.4s", 2, 23, 11)
1678 GEN_THREEVEC_TEST(facge_2s_2s_2s, "facge v2.2s, v23.2s, v11.2s", 2, 23, 11)
1679 GEN_THREEVEC_TEST(facgt_2d_2d_2d, "facgt v2.2d, v23.2d, v11.2d", 2, 23, 11)
1680 GEN_THREEVEC_TEST(facgt_4s_4s_4s, "facgt v2.4s, v23.4s, v11.4s", 2, 23, 11)
1681 GEN_THREEVEC_TEST(facgt_2s_2s_2s, "facgt v2.2s, v23.2s, v11.2s", 2, 23, 11)
1682
1683 GEN_test_FCMEQ_D_D_Z
1684 GEN_test_FCMEQ_S_S_Z
1685 GEN_test_FCMGE_D_D_Z
1686 GEN_test_FCMGE_S_S_Z
1687 GEN_test_FCMGT_D_D_Z
1688 GEN_test_FCMGT_S_S_Z
1689 GEN_test_FCMLE_D_D_Z
1690 GEN_test_FCMLE_S_S_Z
1691 GEN_test_FCMLT_D_D_Z
1692 GEN_test_FCMLT_S_S_Z
1693
1694 GEN_TWOVEC_TEST(fcmeq_z_2d_2d, "fcmeq v2.2d, v23.2d, #0", 2, 23)
1695 GEN_TWOVEC_TEST(fcmeq_z_4s_4s, "fcmeq v2.4s, v23.4s, #0", 2, 23)
1696 GEN_TWOVEC_TEST(fcmeq_z_2s_2s, "fcmeq v2.2s, v23.2s, #0", 2, 23)
1697 GEN_TWOVEC_TEST(fcmge_z_2d_2d, "fcmge v2.2d, v23.2d, #0", 2, 23)
1698 GEN_TWOVEC_TEST(fcmge_z_4s_4s, "fcmge v2.4s, v23.4s, #0", 2, 23)
1699 GEN_TWOVEC_TEST(fcmge_z_2s_2s, "fcmge v2.2s, v23.2s, #0", 2, 23)
1700 GEN_TWOVEC_TEST(fcmgt_z_2d_2d, "fcmgt v2.2d, v23.2d, #0", 2, 23)
1701 GEN_TWOVEC_TEST(fcmgt_z_4s_4s, "fcmgt v2.4s, v23.4s, #0", 2, 23)
1702 GEN_TWOVEC_TEST(fcmgt_z_2s_2s, "fcmgt v2.2s, v23.2s, #0", 2, 23)
1703 GEN_TWOVEC_TEST(fcmle_z_2d_2d, "fcmle v2.2d, v23.2d, #0", 2, 23)
1704 GEN_TWOVEC_TEST(fcmle_z_4s_4s, "fcmle v2.4s, v23.4s, #0", 2, 23)
1705 GEN_TWOVEC_TEST(fcmle_z_2s_2s, "fcmle v2.2s, v23.2s, #0", 2, 23)
1706 GEN_TWOVEC_TEST(fcmlt_z_2d_2d, "fcmlt v2.2d, v23.2d, #0", 2, 23)
1707 GEN_TWOVEC_TEST(fcmlt_z_4s_4s, "fcmlt v2.4s, v23.4s, #0", 2, 23)
1708 GEN_TWOVEC_TEST(fcmlt_z_2s_2s, "fcmlt v2.2s, v23.2s, #0", 2, 23)
1709
1710 GEN_test_FCMP_D_Z
1711 GEN_test_FCMP_S_Z
1712 GEN_test_FCMPE_D_Z
1713 GEN_test_FCMPE_S_Z
1714 GEN_test_FCMP_D_D
1715 GEN_test_FCMP_S_S
1716 GEN_test_FCMPE_D_D
1717 GEN_test_FCMPE_S_S
1718
1719 GEN_test_FCSEL_D_D_D_EQ
1720 GEN_test_FCSEL_D_D_D_NE
1721 GEN_test_FCSEL_S_S_S_EQ
1722 GEN_test_FCSEL_S_S_S_NE
1723
1724 GEN_THREEVEC_TEST(fdiv_d_d_d, "fdiv d2, d11, d29", 2, 11, 29)
1725 GEN_THREEVEC_TEST(fdiv_s_s_s, "fdiv s2, s11, s29", 2, 11, 29)
1726 GEN_BINARY_TEST(fdiv, 2d, 2d, 2d)
1727 GEN_BINARY_TEST(fdiv, 4s, 4s, 4s)
1728 GEN_BINARY_TEST(fdiv, 2s, 2s, 2s)
1729
1730 GEN_FOURVEC_TEST(fmadd_d_d_d_d, "fmadd d2, d11, d29, d3", 2, 11, 29, 3)
1731 GEN_FOURVEC_TEST(fmadd_s_s_s_s, "fmadd s2, s11, s29, s3", 2, 11, 29, 3)
1732 GEN_FOURVEC_TEST(fnmadd_d_d_d_d, "fnmadd d2, d11, d29, d3", 2, 11, 29, 3)
1733 GEN_FOURVEC_TEST(fnmadd_s_s_s_s, "fnmadd s2, s11, s29, s3", 2, 11, 29, 3)
1734 GEN_FOURVEC_TEST(fmsub_d_d_d_d, "fmsub d2, d11, d29, d3", 2, 11, 29, 3)
1735 GEN_FOURVEC_TEST(fmsub_s_s_s_s, "fmsub s2, s11, s29, s3", 2, 11, 29, 3)
1736 GEN_FOURVEC_TEST(fnmsub_d_d_d_d, "fnmsub d2, d11, d29, d3", 2, 11, 29, 3)
1737 GEN_FOURVEC_TEST(fnmsub_s_s_s_s, "fnmsub s2, s11, s29, s3", 2, 11, 29, 3)
1738
1739 GEN_THREEVEC_TEST(fnmul_d_d_d, "fnmul d2, d11, d29", 2, 11, 29)
1740 GEN_THREEVEC_TEST(fnmul_s_s_s, "fnmul s2, s11, s29", 2, 11, 29)
1741
1742 GEN_THREEVEC_TEST(fmax_d_d_d, "fmax d2, d11, d29", 2, 11, 29)
1743 GEN_THREEVEC_TEST(fmax_s_s_s, "fmax s2, s11, s29", 2, 11, 29)
1744 GEN_THREEVEC_TEST(fmin_d_d_d, "fmin d2, d11, d29", 2, 11, 29)
1745 GEN_THREEVEC_TEST(fmin_s_s_s, "fmin s2, s11, s29", 2, 11, 29)
1746 GEN_THREEVEC_TEST(fmaxnm_d_d_d, "fmaxnm d2, d11, d29", 2, 11, 29)
1747 GEN_THREEVEC_TEST(fmaxnm_s_s_s, "fmaxnm s2, s11, s29", 2, 11, 29)
1748 GEN_THREEVEC_TEST(fminnm_d_d_d, "fminnm d2, d11, d29", 2, 11, 29)
1749 GEN_THREEVEC_TEST(fminnm_s_s_s, "fminnm s2, s11, s29", 2, 11, 29)
1750
1751 GEN_THREEVEC_TEST(fmax_2d_2d_2d, "fmax v2.2d, v23.2d, v11.2d", 2, 23, 11)
1752 GEN_THREEVEC_TEST(fmax_4s_4s_4s, "fmax v2.4s, v23.4s, v11.4s", 2, 23, 11)
1753 GEN_THREEVEC_TEST(fmax_2s_2s_2s, "fmax v2.2s, v23.2s, v11.2s", 2, 23, 11)
1754 GEN_THREEVEC_TEST(fmin_2d_2d_2d, "fmin v2.2d, v23.2d, v11.2d", 2, 23, 11)
1755 GEN_THREEVEC_TEST(fmin_4s_4s_4s, "fmin v2.4s, v23.4s, v11.4s", 2, 23, 11)
1756 GEN_THREEVEC_TEST(fmin_2s_2s_2s, "fmin v2.2s, v23.2s, v11.2s", 2, 23, 11)
1757 GEN_THREEVEC_TEST(fmaxnm_2d_2d_2d, "fmaxnm v2.2d, v23.2d, v11.2d", 2, 23, 11)
1758 GEN_THREEVEC_TEST(fmaxnm_4s_4s_4s, "fmaxnm v2.4s, v23.4s, v11.4s", 2, 23, 11)
1759 GEN_THREEVEC_TEST(fmaxnm_2s_2s_2s, "fmaxnm v2.2s, v23.2s, v11.2s", 2, 23, 11)
1760 GEN_THREEVEC_TEST(fminnm_2d_2d_2d, "fminnm v2.2d, v23.2d, v11.2d", 2, 23, 11)
1761 GEN_THREEVEC_TEST(fminnm_4s_4s_4s, "fminnm v2.4s, v23.4s, v11.4s", 2, 23, 11)
1762 GEN_THREEVEC_TEST(fminnm_2s_2s_2s, "fminnm v2.2s, v23.2s, v11.2s", 2, 23, 11)
1763
1764 GEN_TWOVEC_TEST(fmaxnmp_d_2d, "fmaxnmp d2, v23.2d", 2, 23)
1765 GEN_TWOVEC_TEST(fmaxnmp_s_2s, "fmaxnmp s2, v23.2s", 2, 23)
1766 GEN_TWOVEC_TEST(fminnmp_d_2d, "fminnmp d2, v23.2d", 2, 23)
1767 GEN_TWOVEC_TEST(fminnmp_s_2s, "fminnmp s2, v23.2s", 2, 23)
1768
1769 GEN_THREEVEC_TEST(fmaxnmp_2d_2d_2d, "fmaxnmp v2.2d, v23.2d, v11.2d", 2, 23, 11)
1770 GEN_THREEVEC_TEST(fmaxnmp_4s_4s_4s, "fmaxnmp v2.4s, v23.4s, v11.4s", 2, 23, 11)
1771 GEN_THREEVEC_TEST(fmaxnmp_2s_2s_2s, "fmaxnmp v2.2s, v23.2s, v11.2s", 2, 23, 11)
1772 GEN_THREEVEC_TEST(fminnmp_2d_2d_2d, "fminnmp v2.2d, v23.2d, v11.2d", 2, 23, 11)
1773 GEN_THREEVEC_TEST(fminnmp_4s_4s_4s, "fminnmp v2.4s, v23.4s, v11.4s", 2, 23, 11)
1774 GEN_THREEVEC_TEST(fminnmp_2s_2s_2s, "fminnmp v2.2s, v23.2s, v11.2s", 2, 23, 11)
1775
1776 GEN_TWOVEC_TEST(fmaxnmv_s_4s, "fmaxnmv s2, v23.4s", 2, 23)
1777 GEN_TWOVEC_TEST(fminnmv_s_4s, "fminnmv s2, v23.4s", 2, 23)
1778
1779 GEN_TWOVEC_TEST(fmaxp_d_2d, "fmaxp d2, v23.2d", 2, 23)
1780 GEN_TWOVEC_TEST(fmaxp_s_2s, "fmaxp s2, v23.2s", 2, 23)
1781 GEN_TWOVEC_TEST(fminp_d_2d, "fminp d2, v23.2d", 2, 23)
1782 GEN_TWOVEC_TEST(fminp_s_2s, "fminp s2, v23.2s", 2, 23)
1783
1784 GEN_THREEVEC_TEST(fmaxp_2d_2d_2d, "fmaxp v2.2d, v23.2d, v11.2d", 2, 23, 11)
1785 GEN_THREEVEC_TEST(fmaxp_4s_4s_4s, "fmaxp v2.4s, v23.4s, v11.4s", 2, 23, 11)
1786 GEN_THREEVEC_TEST(fmaxp_2s_2s_2s, "fmaxp v2.2s, v23.2s, v11.2s", 2, 23, 11)
1787 GEN_THREEVEC_TEST(fminp_2d_2d_2d, "fminp v2.2d, v23.2d, v11.2d", 2, 23, 11)
1788 GEN_THREEVEC_TEST(fminp_4s_4s_4s, "fminp v2.4s, v23.4s, v11.4s", 2, 23, 11)
1789 GEN_THREEVEC_TEST(fminp_2s_2s_2s, "fminp v2.2s, v23.2s, v11.2s", 2, 23, 11)
1790
1791 GEN_TWOVEC_TEST(fmaxv_s_4s, "fmaxv s2, v23.4s", 2, 23)
1792 GEN_TWOVEC_TEST(fminv_s_4s, "fminv s2, v23.4s", 2, 23)
1793
1794 GEN_THREEVEC_TEST(fmla_2d_2d_2d, "fmla v2.2d, v23.2d, v11.2d", 2, 23, 11)
1795 GEN_THREEVEC_TEST(fmla_4s_4s_4s, "fmla v2.4s, v23.4s, v11.4s", 2, 23, 11)
1796 GEN_THREEVEC_TEST(fmla_2s_2s_2s, "fmla v2.2s, v23.2s, v11.2s", 2, 23, 11)
1797 GEN_THREEVEC_TEST(fmls_2d_2d_2d, "fmls v2.2d, v23.2d, v11.2d", 2, 23, 11)
1798 GEN_THREEVEC_TEST(fmls_4s_4s_4s, "fmls v2.4s, v23.4s, v11.4s", 2, 23, 11)
1799 GEN_THREEVEC_TEST(fmls_2s_2s_2s, "fmls v2.2s, v23.2s, v11.2s", 2, 23, 11)
1800
1801 GEN_THREEVEC_TEST(fmla_d_d_d0, "fmla d2, d11, v29.d[0]", 2, 11, 29)
1802 GEN_THREEVEC_TEST(fmla_d_d_d1, "fmla d2, d11, v29.d[1]", 2, 11, 29)
1803 GEN_THREEVEC_TEST(fmla_s_s_s0, "fmla s2, s11, v29.s[0]", 2, 11, 29)
1804 GEN_THREEVEC_TEST(fmla_s_s_s3, "fmla s2, s11, v29.s[3]", 2, 11, 29)
1805 GEN_THREEVEC_TEST(fmls_d_d_d0, "fmls d2, d11, v29.d[0]", 2, 11, 29)
1806 GEN_THREEVEC_TEST(fmls_d_d_d1, "fmls d2, d11, v29.d[1]", 2, 11, 29)
1807 GEN_THREEVEC_TEST(fmls_s_s_s0, "fmls s2, s11, v29.s[0]", 2, 11, 29)
1808 GEN_THREEVEC_TEST(fmls_s_s_s3, "fmls s2, s11, v29.s[3]", 2, 11, 29)
1809
1810 GEN_THREEVEC_TEST(fmla_2d_2d_d0, "fmla v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
1811 GEN_THREEVEC_TEST(fmla_2d_2d_d1, "fmla v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
1812 GEN_THREEVEC_TEST(fmla_4s_4s_s0, "fmla v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
1813 GEN_THREEVEC_TEST(fmla_4s_4s_s3, "fmla v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
1814 GEN_THREEVEC_TEST(fmla_2s_2s_s0, "fmla v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
1815 GEN_THREEVEC_TEST(fmla_2s_2s_s3, "fmla v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
1816
1817 GEN_THREEVEC_TEST(fmls_2d_2d_d0, "fmls v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
1818 GEN_THREEVEC_TEST(fmls_2d_2d_d1, "fmls v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
1819 GEN_THREEVEC_TEST(fmls_4s_4s_s0, "fmls v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
1820 GEN_THREEVEC_TEST(fmls_4s_4s_s3, "fmls v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
1821 GEN_THREEVEC_TEST(fmls_2s_2s_s0, "fmls v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
1822 GEN_THREEVEC_TEST(fmls_2s_2s_s3, "fmls v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
1823
1824 GEN_TWOVEC_TEST(fmov_2d_imm_01, "fmov v22.2d, #0.125", 22, 23)
1825 GEN_TWOVEC_TEST(fmov_2d_imm_02, "fmov v22.2d, #-4.0", 22, 23)
1826 GEN_TWOVEC_TEST(fmov_2d_imm_03, "fmov v22.2d, #1.0", 22, 23)
1827 GEN_TWOVEC_TEST(fmov_4s_imm_01, "fmov v22.4s, #0.125", 22, 23)
1828 GEN_TWOVEC_TEST(fmov_4s_imm_02, "fmov v22.4s, #-4.0", 22, 23)
1829 GEN_TWOVEC_TEST(fmov_4s_imm_03, "fmov v22.4s, #1.0", 22, 23)
1830 GEN_TWOVEC_TEST(fmov_2s_imm_01, "fmov v22.2s, #0.125", 22, 23)
1831 GEN_TWOVEC_TEST(fmov_2s_imm_02, "fmov v22.2s, #-4.0", 22, 23)
1832 GEN_TWOVEC_TEST(fmov_2s_imm_03, "fmov v22.2s, #1.0", 22, 23)
1833
1834 GEN_TWOVEC_TEST(fmov_d_d, "fmov d22, d23", 22, 23)
1835 GEN_TWOVEC_TEST(fmov_s_s, "fmov s22, s23", 22, 23)
1836
1837 GEN_ONEINT_ONEVEC_TEST(fmov_s_w, "fmov s7, w15", 15, 7)
1838 GEN_ONEINT_ONEVEC_TEST(fmov_d_x, "fmov d7, x15", 15, 7)
1839 GEN_ONEINT_ONEVEC_TEST(fmov_d1_x, "fmov v7.d[1], x15", 15, 7)
1840 GEN_ONEINT_ONEVEC_TEST(fmov_w_s, "fmov w15, s7", 15, 7)
1841 GEN_ONEINT_ONEVEC_TEST(fmov_x_d, "fmov x15, d7", 15, 7)
1842 GEN_ONEINT_ONEVEC_TEST(fmov_x_d1, "fmov x15, v7.d[1]", 15, 7)
1843
1844 /* overkill -- don't need two vecs, only one */
1845 GEN_TWOVEC_TEST(fmov_d_imm_01, "fmov d22, #0.125", 22, 23)
1846 GEN_TWOVEC_TEST(fmov_d_imm_02, "fmov d22, #-4.0", 22, 23)
1847 GEN_TWOVEC_TEST(fmov_d_imm_03, "fmov d22, #1.0", 22, 23)
1848 GEN_TWOVEC_TEST(fmov_s_imm_01, "fmov s22, #0.125", 22, 23)
1849 GEN_TWOVEC_TEST(fmov_s_imm_02, "fmov s22, #-4.0", 22, 23)
1850 GEN_TWOVEC_TEST(fmov_s_imm_03, "fmov s22, #-1.0", 22, 23)
1851
1852 GEN_THREEVEC_TEST(fmul_d_d_d0, "fmul d2, d11, v29.d[0]", 2, 11, 29)
1853 GEN_THREEVEC_TEST(fmul_d_d_d1, "fmul d2, d11, v29.d[1]", 2, 11, 29)
1854 GEN_THREEVEC_TEST(fmul_s_s_s0, "fmul s2, s11, v29.s[0]", 2, 11, 29)
1855 GEN_THREEVEC_TEST(fmul_s_s_s3, "fmul s2, s11, v29.s[3]", 2, 11, 29)
1856
1857 GEN_THREEVEC_TEST(fmul_2d_2d_d0, "fmul v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
1858 GEN_THREEVEC_TEST(fmul_2d_2d_d1, "fmul v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
1859 GEN_THREEVEC_TEST(fmul_4s_4s_s0, "fmul v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
1860 GEN_THREEVEC_TEST(fmul_4s_4s_s3, "fmul v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
1861 GEN_THREEVEC_TEST(fmul_2s_2s_s0, "fmul v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
1862 GEN_THREEVEC_TEST(fmul_2s_2s_s3, "fmul v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
1863
1864 GEN_THREEVEC_TEST(fmul_d_d_d, "fmul d2, d11, d29", 2, 11, 29)
1865 GEN_THREEVEC_TEST(fmul_s_s_s, "fmul s2, s11, s29", 2, 11, 29)
1866 GEN_THREEVEC_TEST(fmul_2d_2d_2d, "fmul v2.2d, v11.2d, v29.2d", 2, 11, 29)
1867 GEN_THREEVEC_TEST(fmul_4s_4s_4s, "fmul v2.4s, v11.4s, v29.4s", 2, 11, 29)
1868 GEN_THREEVEC_TEST(fmul_2s_2s_2s, "fmul v2.2s, v11.2s, v29.2s", 2, 11, 29)
1869
1870 GEN_THREEVEC_TEST(fmulx_d_d_d0, "fmulx d2, d11, v29.d[0]", 2, 11, 29)
1871 GEN_THREEVEC_TEST(fmulx_d_d_d1, "fmulx d2, d11, v29.d[1]", 2, 11, 29)
1872 GEN_THREEVEC_TEST(fmulx_s_s_s0, "fmulx s2, s11, v29.s[0]", 2, 11, 29)
1873 GEN_THREEVEC_TEST(fmulx_s_s_s3, "fmulx s2, s11, v29.s[3]", 2, 11, 29)
1874 GEN_THREEVEC_TEST(fmulx_2d_2d_d0, "fmulx v2.2d, v11.2d, v29.d[0]", 2, 11, 29)
1875 GEN_THREEVEC_TEST(fmulx_2d_2d_d1, "fmulx v2.2d, v11.2d, v29.d[1]", 2, 11, 29)
1876 GEN_THREEVEC_TEST(fmulx_4s_4s_s0, "fmulx v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
1877 GEN_THREEVEC_TEST(fmulx_4s_4s_s3, "fmulx v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
1878 GEN_THREEVEC_TEST(fmulx_2s_2s_s0, "fmulx v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
1879 GEN_THREEVEC_TEST(fmulx_2s_2s_s3, "fmulx v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
1880
1881 GEN_THREEVEC_TEST(fmulx_d_d_d, "fmulx d2, d11, d29", 2, 11, 29)
1882 GEN_THREEVEC_TEST(fmulx_s_s_s, "fmulx s2, s11, s29", 2, 11, 29)
1883 GEN_THREEVEC_TEST(fmulx_2d_2d_2d, "fmulx v2.2d, v11.2d, v29.2d", 2, 11, 29)
1884 GEN_THREEVEC_TEST(fmulx_4s_4s_4s, "fmulx v2.4s, v11.4s, v29.4s", 2, 11, 29)
1885 GEN_THREEVEC_TEST(fmulx_2s_2s_2s, "fmulx v2.2s, v11.2s, v29.2s", 2, 11, 29)
1886
1887 GEN_TWOVEC_TEST(frecpe_d_d, "frecpe d22, d23", 22, 23)
1888 GEN_TWOVEC_TEST(frecpe_s_s, "frecpe s22, s23", 22, 23)
1889 GEN_TWOVEC_TEST(frecpe_2d_2d, "frecpe v22.2d, v23.2d", 22, 23)
1890 GEN_TWOVEC_TEST(frecpe_4s_4s, "frecpe v22.4s, v23.4s", 22, 23)
1891 GEN_TWOVEC_TEST(frecpe_2s_2s, "frecpe v22.2s, v23.2s", 22, 23)
1892
1893 GEN_THREEVEC_TEST(frecps_d_d_d, "frecps d2, d11, d29", 2, 11, 29)
1894 GEN_THREEVEC_TEST(frecps_s_s_s, "frecps s2, s11, s29", 2, 11, 29)
1895 GEN_THREEVEC_TEST(frecps_2d_2d_2d, "frecps v2.2d, v11.2d, v29.2d", 2, 11, 29)
1896 GEN_THREEVEC_TEST(frecps_4s_4s_4s, "frecps v2.4s, v11.4s, v29.4s", 2, 11, 29)
1897 GEN_THREEVEC_TEST(frecps_2s_2s_2s, "frecps v2.2s, v11.2s, v29.2s", 2, 11, 29)
1898
1899 GEN_TWOVEC_TEST(frecpx_d_d, "frecpx d22, d23", 22, 23)
1900 GEN_TWOVEC_TEST(frecpx_s_s, "frecpx s22, s23", 22, 23)
1901
1902 GEN_TWOVEC_TEST(frinta_d_d, "frinta d22, d23", 22, 23)
1903 GEN_TWOVEC_TEST(frinta_s_s, "frinta s22, s23", 22, 23)
1904 GEN_TWOVEC_TEST(frinti_d_d, "frinti d22, d23", 22, 23)
1905 GEN_TWOVEC_TEST(frinti_s_s, "frinti s22, s23", 22, 23)
1906 GEN_TWOVEC_TEST(frintm_d_d, "frintm d22, d23", 22, 23)
1907 GEN_TWOVEC_TEST(frintm_s_s, "frintm s22, s23", 22, 23)
1908 GEN_TWOVEC_TEST(frintn_d_d, "frintn d22, d23", 22, 23)
1909 GEN_TWOVEC_TEST(frintn_s_s, "frintn s22, s23", 22, 23)
1910 GEN_TWOVEC_TEST(frintp_d_d, "frintp d22, d23", 22, 23)
1911 GEN_TWOVEC_TEST(frintp_s_s, "frintp s22, s23", 22, 23)
1912 GEN_TWOVEC_TEST(frintx_d_d, "frintx d22, d23", 22, 23)
1913 GEN_TWOVEC_TEST(frintx_s_s, "frintx s22, s23", 22, 23)
1914 GEN_TWOVEC_TEST(frintz_d_d, "frintz d22, d23", 22, 23)
1915 GEN_TWOVEC_TEST(frintz_s_s, "frintz s22, s23", 22, 23)
1916
1917 GEN_TWOVEC_TEST(frinta_2d_2d, "frinta v2.2d, v11.2d", 2, 11)
1918 GEN_TWOVEC_TEST(frinta_4s_4s, "frinta v2.4s, v11.4s", 2, 11)
1919 GEN_TWOVEC_TEST(frinta_2s_2s, "frinta v2.2s, v11.2s", 2, 11)
1920 GEN_TWOVEC_TEST(frinti_2d_2d, "frinti v2.2d, v11.2d", 2, 11)
1921 GEN_TWOVEC_TEST(frinti_4s_4s, "frinti v2.4s, v11.4s", 2, 11)
1922 GEN_TWOVEC_TEST(frinti_2s_2s, "frinti v2.2s, v11.2s", 2, 11)
1923 GEN_TWOVEC_TEST(frintm_2d_2d, "frintm v2.2d, v11.2d", 2, 11)
1924 GEN_TWOVEC_TEST(frintm_4s_4s, "frintm v2.4s, v11.4s", 2, 11)
1925 GEN_TWOVEC_TEST(frintm_2s_2s, "frintm v2.2s, v11.2s", 2, 11)
1926 GEN_TWOVEC_TEST(frintn_2d_2d, "frintn v2.2d, v11.2d", 2, 11)
1927 GEN_TWOVEC_TEST(frintn_4s_4s, "frintn v2.4s, v11.4s", 2, 11)
1928 GEN_TWOVEC_TEST(frintn_2s_2s, "frintn v2.2s, v11.2s", 2, 11)
1929 GEN_TWOVEC_TEST(frintp_2d_2d, "frintp v2.2d, v11.2d", 2, 11)
1930 GEN_TWOVEC_TEST(frintp_4s_4s, "frintp v2.4s, v11.4s", 2, 11)
1931 GEN_TWOVEC_TEST(frintp_2s_2s, "frintp v2.2s, v11.2s", 2, 11)
1932 GEN_TWOVEC_TEST(frintx_2d_2d, "frintx v2.2d, v11.2d", 2, 11)
1933 GEN_TWOVEC_TEST(frintx_4s_4s, "frintx v2.4s, v11.4s", 2, 11)
1934 GEN_TWOVEC_TEST(frintx_2s_2s, "frintx v2.2s, v11.2s", 2, 11)
1935 GEN_TWOVEC_TEST(frintz_2d_2d, "frintz v2.2d, v11.2d", 2, 11)
1936 GEN_TWOVEC_TEST(frintz_4s_4s, "frintz v2.4s, v11.4s", 2, 11)
1937 GEN_TWOVEC_TEST(frintz_2s_2s, "frintz v2.2s, v11.2s", 2, 11)
1938
1939 GEN_TWOVEC_TEST(frsqrte_d_d, "frsqrte d22, d23", 22, 23)
1940 GEN_TWOVEC_TEST(frsqrte_s_s, "frsqrte s22, s23", 22, 23)
1941 GEN_TWOVEC_TEST(frsqrte_2d_2d, "frsqrte v22.2d, v23.2d", 22, 23)
1942 GEN_TWOVEC_TEST(frsqrte_4s_4s, "frsqrte v22.4s, v23.4s", 22, 23)
1943 GEN_TWOVEC_TEST(frsqrte_2s_2s, "frsqrte v22.2s, v23.2s", 22, 23)
1944
1945 GEN_THREEVEC_TEST(frsqrts_d_d_d, "frsqrts d2, d11, d29", 2, 11, 29)
1946 GEN_THREEVEC_TEST(frsqrts_s_s_s, "frsqrts s2, s11, s29", 2, 11, 29)
1947 GEN_THREEVEC_TEST(frsqrts_2d_2d_2d, "frsqrts v2.2d, v11.2d, v29.2d", 2, 11, 29)
1948 GEN_THREEVEC_TEST(frsqrts_4s_4s_4s, "frsqrts v2.4s, v11.4s, v29.4s", 2, 11, 29)
1949 GEN_THREEVEC_TEST(frsqrts_2s_2s_2s, "frsqrts v2.2s, v11.2s, v29.2s", 2, 11, 29)
1950
1951 // ======================== CONV ========================
1952
1953 GEN_TWOVEC_TEST(fcvt_s_h, "fcvt s7, h16", 7, 16)
1954 GEN_TWOVEC_TEST(fcvt_d_h, "fcvt d7, h16", 7, 16)
1955 GEN_TWOVEC_TEST(fcvt_h_s, "fcvt h7, s16", 7, 16)
1956 GEN_TWOVEC_TEST(fcvt_d_s, "fcvt d7, s16", 7, 16)
1957 GEN_TWOVEC_TEST(fcvt_h_d, "fcvt h7, d16", 7, 16)
1958 GEN_TWOVEC_TEST(fcvt_s_d, "fcvt s7, d16", 7, 16)
1959
1960 GEN_TWOVEC_TEST(fcvtl_4s_4h, "fcvtl v11.4s, v29.4h", 11, 29)
1961 GEN_TWOVEC_TEST(fcvtl_4s_8h, "fcvtl2 v11.4s, v29.8h", 11, 29)
1962 GEN_TWOVEC_TEST(fcvtl_2d_2s, "fcvtl v11.2d, v29.2s", 11, 29)
1963 GEN_TWOVEC_TEST(fcvtl_2d_4s, "fcvtl2 v11.2d, v29.4s", 11, 29)
1964
1965 GEN_TWOVEC_TEST(fcvtn_4h_4s, "fcvtn v22.4h, v23.4s", 22, 23)
1966 GEN_TWOVEC_TEST(fcvtn_8h_4s, "fcvtn2 v22.8h, v23.4s", 22, 23)
1967 GEN_TWOVEC_TEST(fcvtn_2s_2d, "fcvtn v22.2s, v23.2d", 22, 23)
1968 GEN_TWOVEC_TEST(fcvtn_4s_2d, "fcvtn2 v22.4s, v23.2d", 22, 23)
1969
1970 GEN_TWOVEC_TEST(fcvtas_d_d, "fcvtas d10, d21", 10, 21)
1971 GEN_TWOVEC_TEST(fcvtau_d_d, "fcvtau d21, d10", 21, 10)
1972 GEN_TWOVEC_TEST(fcvtas_s_s, "fcvtas s10, s21", 10, 21)
1973 GEN_TWOVEC_TEST(fcvtau_s_s, "fcvtau s21, s10", 21, 10)
1974 GEN_TWOVEC_TEST(fcvtas_2d_2d, "fcvtas v10.2d, v21.2d", 10, 21)
1975 GEN_TWOVEC_TEST(fcvtau_2d_2d, "fcvtau v10.2d, v21.2d", 10, 21)
1976 GEN_TWOVEC_TEST(fcvtas_4s_4s, "fcvtas v10.4s, v21.4s", 10, 21)
1977 GEN_TWOVEC_TEST(fcvtau_4s_4s, "fcvtau v10.4s, v21.4s", 10, 21)
1978 GEN_TWOVEC_TEST(fcvtas_2s_2s, "fcvtas v10.2s, v21.2s", 10, 21)
1979 GEN_TWOVEC_TEST(fcvtau_2s_2s, "fcvtau v10.2s, v21.2s", 10, 21)
1980 GEN_ONEINT_ONEVEC_TEST(fcvtas_w_s, "fcvtas w21, s10", 21, 10)
1981 GEN_ONEINT_ONEVEC_TEST(fcvtau_w_s, "fcvtau w21, s10", 21, 10)
1982 GEN_ONEINT_ONEVEC_TEST(fcvtas_x_s, "fcvtas x21, s10", 21, 10)
1983 GEN_ONEINT_ONEVEC_TEST(fcvtau_x_s, "fcvtau x21, s10", 21, 10)
1984 GEN_ONEINT_ONEVEC_TEST(fcvtas_w_d, "fcvtas w21, d10", 21, 10)
1985 GEN_ONEINT_ONEVEC_TEST(fcvtau_w_d, "fcvtau w21, d10", 21, 10)
1986 GEN_ONEINT_ONEVEC_TEST(fcvtas_x_d, "fcvtas x21, d10", 21, 10)
1987 GEN_ONEINT_ONEVEC_TEST(fcvtau_x_d, "fcvtau x21, d10", 21, 10)
1988
1989 GEN_TWOVEC_TEST(fcvtms_d_d, "fcvtms d10, d21", 10, 21)
1990 GEN_TWOVEC_TEST(fcvtmu_d_d, "fcvtmu d21, d10", 21, 10)
1991 GEN_TWOVEC_TEST(fcvtms_s_s, "fcvtms s10, s21", 10, 21)
1992 GEN_TWOVEC_TEST(fcvtmu_s_s, "fcvtmu s21, s10", 21, 10)
1993 GEN_TWOVEC_TEST(fcvtms_2d_2d, "fcvtms v10.2d, v21.2d", 10, 21)
1994 GEN_TWOVEC_TEST(fcvtmu_2d_2d, "fcvtmu v10.2d, v21.2d", 10, 21)
1995 GEN_TWOVEC_TEST(fcvtms_4s_4s, "fcvtms v10.4s, v21.4s", 10, 21)
1996 GEN_TWOVEC_TEST(fcvtmu_4s_4s, "fcvtmu v10.4s, v21.4s", 10, 21)
1997 GEN_TWOVEC_TEST(fcvtms_2s_2s, "fcvtms v10.2s, v21.2s", 10, 21)
1998 GEN_TWOVEC_TEST(fcvtmu_2s_2s, "fcvtmu v10.2s, v21.2s", 10, 21)
1999 GEN_ONEINT_ONEVEC_TEST(fcvtms_w_s, "fcvtms w21, s10", 21, 10)
2000 GEN_ONEINT_ONEVEC_TEST(fcvtmu_w_s, "fcvtmu w21, s10", 21, 10)
2001 GEN_ONEINT_ONEVEC_TEST(fcvtms_x_s, "fcvtms x21, s10", 21, 10)
2002 GEN_ONEINT_ONEVEC_TEST(fcvtmu_x_s, "fcvtmu x21, s10", 21, 10)
2003 GEN_ONEINT_ONEVEC_TEST(fcvtms_w_d, "fcvtms w21, d10", 21, 10)
2004 GEN_ONEINT_ONEVEC_TEST(fcvtmu_w_d, "fcvtmu w21, d10", 21, 10)
2005 GEN_ONEINT_ONEVEC_TEST(fcvtms_x_d, "fcvtms x21, d10", 21, 10)
2006 GEN_ONEINT_ONEVEC_TEST(fcvtmu_x_d, "fcvtmu x21, d10", 21, 10)
2007
2008 GEN_TWOVEC_TEST(fcvtns_d_d, "fcvtns d10, d21", 10, 21)
2009 GEN_TWOVEC_TEST(fcvtnu_d_d, "fcvtnu d21, d10", 21, 10)
2010 GEN_TWOVEC_TEST(fcvtns_s_s, "fcvtns s10, s21", 10, 21)
2011 GEN_TWOVEC_TEST(fcvtnu_s_s, "fcvtnu s21, s10", 21, 10)
2012 GEN_TWOVEC_TEST(fcvtns_2d_2d, "fcvtns v10.2d, v21.2d", 10, 21)
2013 GEN_TWOVEC_TEST(fcvtnu_2d_2d, "fcvtnu v10.2d, v21.2d", 10, 21)
2014 GEN_TWOVEC_TEST(fcvtns_4s_4s, "fcvtns v10.4s, v21.4s", 10, 21)
2015 GEN_TWOVEC_TEST(fcvtnu_4s_4s, "fcvtnu v10.4s, v21.4s", 10, 21)
2016 GEN_TWOVEC_TEST(fcvtns_2s_2s, "fcvtns v10.2s, v21.2s", 10, 21)
2017 GEN_TWOVEC_TEST(fcvtnu_2s_2s, "fcvtnu v10.2s, v21.2s", 10, 21)
2018 GEN_ONEINT_ONEVEC_TEST(fcvtns_w_s, "fcvtns w21, s10", 21, 10)
2019 GEN_ONEINT_ONEVEC_TEST(fcvtnu_w_s, "fcvtnu w21, s10", 21, 10)
2020 GEN_ONEINT_ONEVEC_TEST(fcvtns_x_s, "fcvtns x21, s10", 21, 10)
2021 GEN_ONEINT_ONEVEC_TEST(fcvtnu_x_s, "fcvtnu x21, s10", 21, 10)
2022 GEN_ONEINT_ONEVEC_TEST(fcvtns_w_d, "fcvtns w21, d10", 21, 10)
2023 GEN_ONEINT_ONEVEC_TEST(fcvtnu_w_d, "fcvtnu w21, d10", 21, 10)
2024 GEN_ONEINT_ONEVEC_TEST(fcvtns_x_d, "fcvtns x21, d10", 21, 10)
2025 GEN_ONEINT_ONEVEC_TEST(fcvtnu_x_d, "fcvtnu x21, d10", 21, 10)
2026
2027 GEN_TWOVEC_TEST(fcvtps_d_d, "fcvtps d10, d21", 10, 21)
2028 GEN_TWOVEC_TEST(fcvtpu_d_d, "fcvtpu d21, d10", 21, 10)
2029 GEN_TWOVEC_TEST(fcvtps_s_s, "fcvtps s10, s21", 10, 21)
2030 GEN_TWOVEC_TEST(fcvtpu_s_s, "fcvtpu s21, s10", 21, 10)
2031 GEN_TWOVEC_TEST(fcvtps_2d_2d, "fcvtps v10.2d, v21.2d", 10, 21)
2032 GEN_TWOVEC_TEST(fcvtpu_2d_2d, "fcvtpu v10.2d, v21.2d", 10, 21)
2033 GEN_TWOVEC_TEST(fcvtps_4s_4s, "fcvtps v10.4s, v21.4s", 10, 21)
2034 GEN_TWOVEC_TEST(fcvtpu_4s_4s, "fcvtpu v10.4s, v21.4s", 10, 21)
2035 GEN_TWOVEC_TEST(fcvtps_2s_2s, "fcvtps v10.2s, v21.2s", 10, 21)
2036 GEN_TWOVEC_TEST(fcvtpu_2s_2s, "fcvtpu v10.2s, v21.2s", 10, 21)
2037 GEN_ONEINT_ONEVEC_TEST(fcvtps_w_s, "fcvtps w21, s10", 21, 10)
2038 GEN_ONEINT_ONEVEC_TEST(fcvtpu_w_s, "fcvtpu w21, s10", 21, 10)
2039 GEN_ONEINT_ONEVEC_TEST(fcvtps_x_s, "fcvtps x21, s10", 21, 10)
2040 GEN_ONEINT_ONEVEC_TEST(fcvtpu_x_s, "fcvtpu x21, s10", 21, 10)
2041 GEN_ONEINT_ONEVEC_TEST(fcvtps_w_d, "fcvtps w21, d10", 21, 10)
2042 GEN_ONEINT_ONEVEC_TEST(fcvtpu_w_d, "fcvtpu w21, d10", 21, 10)
2043 GEN_ONEINT_ONEVEC_TEST(fcvtps_x_d, "fcvtps x21, d10", 21, 10)
2044 GEN_ONEINT_ONEVEC_TEST(fcvtpu_x_d, "fcvtpu x21, d10", 21, 10)
2045
2046 GEN_TWOVEC_TEST(fcvtzs_d_d, "fcvtzs d10, d21", 10, 21)
2047 GEN_TWOVEC_TEST(fcvtzu_d_d, "fcvtzu d21, d10", 21, 10)
2048 GEN_TWOVEC_TEST(fcvtzs_s_s, "fcvtzs s10, s21", 10, 21)
2049 GEN_TWOVEC_TEST(fcvtzu_s_s, "fcvtzu s21, s10", 21, 10)
2050 GEN_TWOVEC_TEST(fcvtzs_2d_2d, "fcvtzs v10.2d, v21.2d", 10, 21)
2051 GEN_TWOVEC_TEST(fcvtzu_2d_2d, "fcvtzu v10.2d, v21.2d", 10, 21)
2052 GEN_TWOVEC_TEST(fcvtzs_4s_4s, "fcvtzs v10.4s, v21.4s", 10, 21)
2053 GEN_TWOVEC_TEST(fcvtzu_4s_4s, "fcvtzu v10.4s, v21.4s", 10, 21)
2054 GEN_TWOVEC_TEST(fcvtzs_2s_2s, "fcvtzs v10.2s, v21.2s", 10, 21)
2055 GEN_TWOVEC_TEST(fcvtzu_2s_2s, "fcvtzu v10.2s, v21.2s", 10, 21)
2056 GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_s, "fcvtzs w21, s10", 21, 10)
2057 GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_s, "fcvtzu w21, s10", 21, 10)
2058 GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_s, "fcvtzs x21, s10", 21, 10)
2059 GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_s, "fcvtzu x21, s10", 21, 10)
2060 GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_d, "fcvtzs w21, d10", 21, 10)
2061 GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_d, "fcvtzu w21, d10", 21, 10)
2062 GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_d, "fcvtzs x21, d10", 21, 10)
2063 GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_d, "fcvtzu x21, d10", 21, 10)
2064
2065 GEN_TWOVEC_TEST(fcvtzs_d_d_fbits1, "fcvtzs d10, d21, #1", 10, 21)
2066 GEN_TWOVEC_TEST(fcvtzs_d_d_fbits32, "fcvtzs d10, d21, #32", 10, 21)
2067 GEN_TWOVEC_TEST(fcvtzs_d_d_fbits64, "fcvtzs d10, d21, #64", 10, 21)
2068 GEN_TWOVEC_TEST(fcvtzu_d_d_fbits1, "fcvtzu d10, d21, #1", 10, 21)
2069 GEN_TWOVEC_TEST(fcvtzu_d_d_fbits32, "fcvtzu d10, d21, #32", 10, 21)
2070 GEN_TWOVEC_TEST(fcvtzu_d_d_fbits64, "fcvtzu d10, d21, #64", 10, 21)
2071 GEN_TWOVEC_TEST(fcvtzs_s_s_fbits1, "fcvtzs s10, s21, #1", 10, 21)
2072 GEN_TWOVEC_TEST(fcvtzs_s_s_fbits16, "fcvtzs s10, s21, #16", 10, 21)
2073 GEN_TWOVEC_TEST(fcvtzs_s_s_fbits32, "fcvtzs s10, s21, #32", 10, 21)
2074 GEN_TWOVEC_TEST(fcvtzu_s_s_fbits1, "fcvtzu s10, s21, #1", 10, 21)
2075 GEN_TWOVEC_TEST(fcvtzu_s_s_fbits16, "fcvtzu s10, s21, #16", 10, 21)
2076 GEN_TWOVEC_TEST(fcvtzu_s_s_fbits32, "fcvtzu s10, s21, #32", 10, 21)
2077 GEN_TWOVEC_TEST(fcvtzs_2d_2d_fbits1, "fcvtzs v10.2d, v21.2d, #1", 10, 21)
2078 GEN_TWOVEC_TEST(fcvtzs_2d_2d_fbits32, "fcvtzs v10.2d, v21.2d, #32", 10, 21)
2079 GEN_TWOVEC_TEST(fcvtzs_2d_2d_fbits64, "fcvtzs v10.2d, v21.2d, #64", 10, 21)
2080 GEN_TWOVEC_TEST(fcvtzu_2d_2d_fbits1, "fcvtzu v10.2d, v21.2d, #1", 10, 21)
2081 GEN_TWOVEC_TEST(fcvtzu_2d_2d_fbits32, "fcvtzu v10.2d, v21.2d, #32", 10, 21)
2082 GEN_TWOVEC_TEST(fcvtzu_2d_2d_fbits64, "fcvtzu v10.2d, v21.2d, #64", 10, 21)
2083 GEN_TWOVEC_TEST(fcvtzs_4s_4s_fbits1, "fcvtzs v10.4s, v21.4s, #1", 10, 21)
2084 GEN_TWOVEC_TEST(fcvtzs_4s_4s_fbits16, "fcvtzs v10.4s, v21.4s, #16", 10, 21)
2085 GEN_TWOVEC_TEST(fcvtzs_4s_4s_fbits32, "fcvtzs v10.4s, v21.4s, #32", 10, 21)
2086 GEN_TWOVEC_TEST(fcvtzu_4s_4s_fbits1, "fcvtzu v10.4s, v21.4s, #1", 10, 21)
2087 GEN_TWOVEC_TEST(fcvtzu_4s_4s_fbits16, "fcvtzu v10.4s, v21.4s, #16", 10, 21)
2088 GEN_TWOVEC_TEST(fcvtzu_4s_4s_fbits32, "fcvtzu v10.4s, v21.4s, #32", 10, 21)
2089 GEN_TWOVEC_TEST(fcvtzs_2s_2s_fbits1, "fcvtzs v10.2s, v21.2s, #1", 10, 21)
2090 GEN_TWOVEC_TEST(fcvtzs_2s_2s_fbits16, "fcvtzs v10.2s, v21.2s, #16", 10, 21)
2091 GEN_TWOVEC_TEST(fcvtzs_2s_2s_fbits32, "fcvtzs v10.2s, v21.2s, #32", 10, 21)
2092 GEN_TWOVEC_TEST(fcvtzu_2s_2s_fbits1, "fcvtzu v10.2s, v21.2s, #1", 10, 21)
2093 GEN_TWOVEC_TEST(fcvtzu_2s_2s_fbits16, "fcvtzu v10.2s, v21.2s, #16", 10, 21)
2094 GEN_TWOVEC_TEST(fcvtzu_2s_2s_fbits32, "fcvtzu v10.2s, v21.2s, #32", 10, 21)
2095 GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_s_fbits1, "fcvtzs w21, s10, #1", 21, 10)
2096 GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_s_fbits16, "fcvtzs w21, s10, #16", 21, 10)
2097 GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_s_fbits32, "fcvtzs w21, s10, #32", 21, 10)
2098 GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_s_fbits1, "fcvtzu w21, s10, #1", 21, 10)
2099 GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_s_fbits16, "fcvtzu w21, s10, #16", 21, 10)
2100 GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_s_fbits32, "fcvtzu w21, s10, #32", 21, 10)
2101 GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_s_fbits1, "fcvtzs x21, s10, #1", 21, 10)
2102 GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_s_fbits32, "fcvtzs x21, s10, #32", 21, 10)
2103 GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_s_fbits64, "fcvtzs x21, s10, #64", 21, 10)
2104 GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_s_fbits1, "fcvtzu x21, s10, #1", 21, 10)
2105 GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_s_fbits32, "fcvtzu x21, s10, #32", 21, 10)
2106 GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_s_fbits64, "fcvtzu x21, s10, #64", 21, 10)
2107 GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_d_fbits1, "fcvtzs w21, d10, #1", 21, 10)
2108 GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_d_fbits16, "fcvtzs w21, d10, #16", 21, 10)
2109 GEN_ONEINT_ONEVEC_TEST(fcvtzs_w_d_fbits32, "fcvtzs w21, d10, #32", 21, 10)
2110 GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_d_fbits1, "fcvtzu w21, d10, #1", 21, 10)
2111 GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_d_fbits16, "fcvtzu w21, d10, #16", 21, 10)
2112 GEN_ONEINT_ONEVEC_TEST(fcvtzu_w_d_fbits32, "fcvtzu w21, d10, #32", 21, 10)
2113 GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_d_fbits1, "fcvtzs x21, d10, #1", 21, 10)
2114 GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_d_fbits32, "fcvtzs x21, d10, #32", 21, 10)
2115 GEN_ONEINT_ONEVEC_TEST(fcvtzs_x_d_fbits64, "fcvtzs x21, d10, #64", 21, 10)
2116 GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_d_fbits1, "fcvtzu x21, d10, #1", 21, 10)
2117 GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_d_fbits32, "fcvtzu x21, d10, #32", 21, 10)
2118 GEN_ONEINT_ONEVEC_TEST(fcvtzu_x_d_fbits64, "fcvtzu x21, d10, #64", 21, 10)
2119
2120 GEN_TWOVEC_TEST(fcvtxn_s_d, "fcvtxn s10, d21", 10, 21)
2121 GEN_TWOVEC_TEST(fcvtxn_2s_2d, "fcvtxn v10.2s, v21.2d", 10, 21)
2122 GEN_TWOVEC_TEST(fcvtxn_4s_2d, "fcvtxn2 v10.4s, v21.2d", 10, 21)
2123
2124 GEN_TWOVEC_TEST(scvtf_d_d_fbits1, "scvtf d10, d21 , #1", 10, 21)
2125 GEN_TWOVEC_TEST(scvtf_d_d_fbits32, "scvtf d10, d21 , #32", 10, 21)
2126 GEN_TWOVEC_TEST(scvtf_d_d_fbits64, "scvtf d10, d21 , #64", 10, 21)
2127 GEN_TWOVEC_TEST(ucvtf_d_d_fbits1, "ucvtf d21, d10 , #1", 21, 10)
2128 GEN_TWOVEC_TEST(ucvtf_d_d_fbits32, "ucvtf d21, d10 , #32", 21, 10)
2129 GEN_TWOVEC_TEST(ucvtf_d_d_fbits64, "ucvtf d21, d10 , #64", 21, 10)
2130 GEN_TWOVEC_TEST(scvtf_s_s_fbits1, "scvtf s10, s21 , #1", 10, 21)
2131 GEN_TWOVEC_TEST(scvtf_s_s_fbits16, "scvtf s10, s21 , #16", 10, 21)
2132 GEN_TWOVEC_TEST(scvtf_s_s_fbits32, "scvtf s10, s21 , #32", 10, 21)
2133 GEN_TWOVEC_TEST(ucvtf_s_s_fbits1, "ucvtf s21, s10 , #1", 21, 10)
2134 GEN_TWOVEC_TEST(ucvtf_s_s_fbits16, "ucvtf s21, s10 , #16", 21, 10)
2135 GEN_TWOVEC_TEST(ucvtf_s_s_fbits32, "ucvtf s21, s10 , #32", 21, 10)
2136 GEN_TWOVEC_TEST(scvtf_2d_2d_fbits1, "scvtf v10.2d, v21.2d, #1", 10, 21)
2137 GEN_TWOVEC_TEST(scvtf_2d_2d_fbits32, "scvtf v10.2d, v21.2d, #32", 10, 21)
2138 GEN_TWOVEC_TEST(scvtf_2d_2d_fbits64, "scvtf v10.2d, v21.2d, #64", 10, 21)
2139 GEN_TWOVEC_TEST(ucvtf_2d_2d_fbits1, "ucvtf v10.2d, v21.2d, #1", 10, 21)
2140 GEN_TWOVEC_TEST(ucvtf_2d_2d_fbits32, "ucvtf v10.2d, v21.2d, #32", 10, 21)
2141 GEN_TWOVEC_TEST(ucvtf_2d_2d_fbits64, "ucvtf v10.2d, v21.2d, #64", 10, 21)
2142 GEN_TWOVEC_TEST(scvtf_4s_4s_fbits1, "scvtf v10.4s, v21.4s, #1", 10, 21)
2143 GEN_TWOVEC_TEST(scvtf_4s_4s_fbits16, "scvtf v10.4s, v21.4s, #16", 10, 21)
2144 GEN_TWOVEC_TEST(scvtf_4s_4s_fbits32, "scvtf v10.4s, v21.4s, #32", 10, 21)
2145 GEN_TWOVEC_TEST(ucvtf_4s_4s_fbits1, "ucvtf v10.4s, v21.4s, #1", 10, 21)
2146 GEN_TWOVEC_TEST(ucvtf_4s_4s_fbits16, "ucvtf v10.4s, v21.4s, #16", 10, 21)
2147 GEN_TWOVEC_TEST(ucvtf_4s_4s_fbits32, "ucvtf v10.4s, v21.4s, #32", 10, 21)
2148 GEN_TWOVEC_TEST(scvtf_2s_2s_fbits1, "scvtf v10.2s, v21.2s, #1", 10, 21)
2149 GEN_TWOVEC_TEST(scvtf_2s_2s_fbits16, "scvtf v10.2s, v21.2s, #16", 10, 21)
2150 GEN_TWOVEC_TEST(scvtf_2s_2s_fbits32, "scvtf v10.2s, v21.2s, #32", 10, 21)
2151 GEN_TWOVEC_TEST(ucvtf_2s_2s_fbits1, "ucvtf v10.2s, v21.2s, #1", 10, 21)
2152 GEN_TWOVEC_TEST(ucvtf_2s_2s_fbits16, "ucvtf v10.2s, v21.2s, #16", 10, 21)
2153 GEN_TWOVEC_TEST(ucvtf_2s_2s_fbits32, "ucvtf v10.2s, v21.2s, #32", 10, 21)
2154
2155 GEN_TWOVEC_TEST(scvtf_d_d, "scvtf d10, d21", 10, 21)
2156 GEN_TWOVEC_TEST(ucvtf_d_d, "ucvtf d21, d10", 21, 10)
2157 GEN_TWOVEC_TEST(scvtf_s_s, "scvtf s10, s21", 10, 21)
2158 GEN_TWOVEC_TEST(ucvtf_s_s, "ucvtf s21, s10", 21, 10)
2159 GEN_TWOVEC_TEST(scvtf_2d_2d, "scvtf v10.2d, v21.2d", 10, 21)
2160 GEN_TWOVEC_TEST(ucvtf_2d_2d, "ucvtf v10.2d, v21.2d", 10, 21)
2161 GEN_TWOVEC_TEST(scvtf_4s_4s, "scvtf v10.4s, v21.4s", 10, 21)
2162 GEN_TWOVEC_TEST(ucvtf_4s_4s, "ucvtf v10.4s, v21.4s", 10, 21)
2163 GEN_TWOVEC_TEST(scvtf_2s_2s, "scvtf v10.2s, v21.2s", 10, 21)
2164 GEN_TWOVEC_TEST(ucvtf_2s_2s, "ucvtf v10.2s, v21.2s", 10, 21)
2165
2166 GEN_ONEINT_ONEVEC_TEST(scvtf_s_w_fbits1, "scvtf s7, w15, #1", 15, 7)
2167 GEN_ONEINT_ONEVEC_TEST(scvtf_s_w_fbits16, "scvtf s7, w15, #16", 15, 7)
2168 GEN_ONEINT_ONEVEC_TEST(scvtf_s_w_fbits32, "scvtf s7, w15, #32", 15, 7)
2169 GEN_ONEINT_ONEVEC_TEST(scvtf_d_w_fbits1, "scvtf d7, w15, #1", 15, 7)
2170 GEN_ONEINT_ONEVEC_TEST(scvtf_d_w_fbits16, "scvtf d7, w15, #16", 15, 7)
2171 GEN_ONEINT_ONEVEC_TEST(scvtf_d_w_fbits32, "scvtf d7, w15, #32", 15, 7)
2172 GEN_ONEINT_ONEVEC_TEST(scvtf_s_x_fbits1, "scvtf s7, x15, #1", 15, 7)
2173 GEN_ONEINT_ONEVEC_TEST(scvtf_s_x_fbits32, "scvtf s7, x15, #32", 15, 7)
2174 GEN_ONEINT_ONEVEC_TEST(scvtf_s_x_fbits64, "scvtf s7, x15, #64", 15, 7)
2175 GEN_ONEINT_ONEVEC_TEST(scvtf_d_x_fbits1, "scvtf d7, x15, #1", 15, 7)
2176 GEN_ONEINT_ONEVEC_TEST(scvtf_d_x_fbits32, "scvtf d7, x15, #32", 15, 7)
2177 GEN_ONEINT_ONEVEC_TEST(scvtf_d_x_fbits64, "scvtf d7, x15, #64", 15, 7)
2178 GEN_ONEINT_ONEVEC_TEST(ucvtf_s_w_fbits1, "ucvtf s7, w15, #1", 15, 7)
2179 GEN_ONEINT_ONEVEC_TEST(ucvtf_s_w_fbits16, "ucvtf s7, w15, #16", 15, 7)
2180 GEN_ONEINT_ONEVEC_TEST(ucvtf_s_w_fbits32, "ucvtf s7, w15, #32", 15, 7)
2181 GEN_ONEINT_ONEVEC_TEST(ucvtf_d_w_fbits1, "ucvtf d7, w15, #1", 15, 7)
2182 GEN_ONEINT_ONEVEC_TEST(ucvtf_d_w_fbits16, "ucvtf d7, w15, #16", 15, 7)
2183 GEN_ONEINT_ONEVEC_TEST(ucvtf_d_w_fbits32, "ucvtf d7, w15, #32", 15, 7)
2184 GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x_fbits1, "ucvtf s7, x15, #1", 15, 7)
2185 GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x_fbits32, "ucvtf s7, x15, #32", 15, 7)
2186 GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x_fbits64, "ucvtf s7, x15, #64", 15, 7)
2187 GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x_fbits1, "ucvtf d7, x15, #1", 15, 7)
2188 GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x_fbits32, "ucvtf d7, x15, #32", 15, 7)
2189 GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x_fbits64, "ucvtf d7, x15, #64", 15, 7)
2190
2191 GEN_ONEINT_ONEVEC_TEST(scvtf_s_w, "scvtf s7, w15", 15, 7)
2192 GEN_ONEINT_ONEVEC_TEST(scvtf_d_w, "scvtf d7, w15", 15, 7)
2193 GEN_ONEINT_ONEVEC_TEST(scvtf_s_x, "scvtf s7, x15", 15, 7)
2194 GEN_ONEINT_ONEVEC_TEST(scvtf_d_x, "scvtf d7, x15", 15, 7)
2195 GEN_ONEINT_ONEVEC_TEST(ucvtf_s_w, "ucvtf s7, w15", 15, 7)
2196 GEN_ONEINT_ONEVEC_TEST(ucvtf_d_w, "ucvtf d7, w15", 15, 7)
2197 GEN_ONEINT_ONEVEC_TEST(ucvtf_s_x, "ucvtf s7, x15", 15, 7)
2198 GEN_ONEINT_ONEVEC_TEST(ucvtf_d_x, "ucvtf d7, x15", 15, 7)
2199
2200 // ======================== INT ========================
2201
2202 GEN_TWOVEC_TEST(abs_d_d, "abs d22, d23", 22, 23)
2203 GEN_TWOVEC_TEST(neg_d_d, "neg d22, d23", 22, 23)
2204
2205 GEN_UNARY_TEST(abs, 2d, 2d)
2206 GEN_UNARY_TEST(abs, 4s, 4s)
2207 GEN_UNARY_TEST(abs, 2s, 2s)
2208 GEN_UNARY_TEST(abs, 8h, 8h)
2209 GEN_UNARY_TEST(abs, 4h, 4h)
2210 GEN_UNARY_TEST(abs, 16b, 16b)
2211 GEN_UNARY_TEST(abs, 8b, 8b)
2212 GEN_UNARY_TEST(neg, 2d, 2d)
2213 GEN_UNARY_TEST(neg, 4s, 4s)
2214 GEN_UNARY_TEST(neg, 2s, 2s)
2215 GEN_UNARY_TEST(neg, 8h, 8h)
2216 GEN_UNARY_TEST(neg, 4h, 4h)
2217 GEN_UNARY_TEST(neg, 16b, 16b)
2218 GEN_UNARY_TEST(neg, 8b, 8b)
2219
2220 GEN_THREEVEC_TEST(add_d_d_d, "add d21, d22, d23", 21, 22, 23)
2221 GEN_THREEVEC_TEST(sub_d_d_d, "sub d21, d22, d23", 21, 22, 23)
2222
2223 GEN_BINARY_TEST(add, 2d, 2d, 2d)
2224 GEN_BINARY_TEST(add, 4s, 4s, 4s)
2225 GEN_BINARY_TEST(add, 2s, 2s, 2s)
2226 GEN_BINARY_TEST(add, 8h, 8h, 8h)
2227 GEN_BINARY_TEST(add, 4h, 4h, 4h)
2228 GEN_BINARY_TEST(add, 16b, 16b, 16b)
2229 GEN_BINARY_TEST(add, 8b, 8b, 8b)
2230 GEN_BINARY_TEST(sub, 2d, 2d, 2d)
2231 GEN_BINARY_TEST(sub, 4s, 4s, 4s)
2232 GEN_BINARY_TEST(sub, 2s, 2s, 2s)
2233 GEN_BINARY_TEST(sub, 8h, 8h, 8h)
2234 GEN_BINARY_TEST(sub, 4h, 4h, 4h)
2235 GEN_BINARY_TEST(sub, 16b, 16b, 16b)
2236 GEN_BINARY_TEST(sub, 8b, 8b, 8b)
2237
2238 GEN_BINARY_TEST(addhn, 2s, 2d, 2d)
2239 GEN_BINARY_TEST(addhn2, 4s, 2d, 2d)
2240 GEN_BINARY_TEST(addhn, 4h, 4s, 4s)
2241 GEN_BINARY_TEST(addhn2, 8h, 4s, 4s)
2242 GEN_BINARY_TEST(addhn, 8b, 8h, 8h)
2243 GEN_BINARY_TEST(addhn2, 16b, 8h, 8h)
2244 GEN_BINARY_TEST(subhn, 2s, 2d, 2d)
2245 GEN_BINARY_TEST(subhn2, 4s, 2d, 2d)
2246 GEN_BINARY_TEST(subhn, 4h, 4s, 4s)
2247 GEN_BINARY_TEST(subhn2, 8h, 4s, 4s)
2248 GEN_BINARY_TEST(subhn, 8b, 8h, 8h)
2249 GEN_BINARY_TEST(subhn2, 16b, 8h, 8h)
2250 GEN_BINARY_TEST(raddhn, 2s, 2d, 2d)
2251 GEN_BINARY_TEST(raddhn2, 4s, 2d, 2d)
2252 GEN_BINARY_TEST(raddhn, 4h, 4s, 4s)
2253 GEN_BINARY_TEST(raddhn2, 8h, 4s, 4s)
2254 GEN_BINARY_TEST(raddhn, 8b, 8h, 8h)
2255 GEN_BINARY_TEST(raddhn2, 16b, 8h, 8h)
2256 GEN_BINARY_TEST(rsubhn, 2s, 2d, 2d)
2257 GEN_BINARY_TEST(rsubhn2, 4s, 2d, 2d)
2258 GEN_BINARY_TEST(rsubhn, 4h, 4s, 4s)
2259 GEN_BINARY_TEST(rsubhn2, 8h, 4s, 4s)
2260 GEN_BINARY_TEST(rsubhn, 8b, 8h, 8h)
2261 GEN_BINARY_TEST(rsubhn2, 16b, 8h, 8h)
2262
2263 GEN_TWOVEC_TEST(addp_d_2d, "addp d22, v23.2d", 22, 23)
2264
2265 GEN_BINARY_TEST(addp, 2d, 2d, 2d)
2266 GEN_BINARY_TEST(addp, 4s, 4s, 4s)
2267 GEN_BINARY_TEST(addp, 2s, 2s, 2s)
2268 GEN_BINARY_TEST(addp, 8h, 8h, 8h)
2269 GEN_BINARY_TEST(addp, 4h, 4h, 4h)
2270 GEN_BINARY_TEST(addp, 16b, 16b, 16b)
2271 GEN_BINARY_TEST(addp, 8b, 8b, 8b)
2272
2273 GEN_TWOVEC_TEST(addv_s_4s, "addv s22, v23.4s", 22, 23)
2274 GEN_TWOVEC_TEST(addv_h_8h, "addv h22, v23.8h", 22, 23)
2275 GEN_TWOVEC_TEST(addv_h_4h, "addv h22, v23.4h", 22, 23)
2276 GEN_TWOVEC_TEST(addv_b_16b, "addv b22, v23.16b", 22, 23)
2277 GEN_TWOVEC_TEST(addv_b_8b, "addv b22, v23.8b", 22, 23)
2278
2279 GEN_BINARY_TEST(and, 16b, 16b, 16b)
2280 GEN_BINARY_TEST(and, 8b, 8b, 8b)
2281 GEN_BINARY_TEST(bic, 16b, 16b, 16b)
2282 GEN_BINARY_TEST(bic, 8b, 8b, 8b)
2283 GEN_BINARY_TEST(orr, 16b, 16b, 16b)
2284 GEN_BINARY_TEST(orr, 8b, 8b, 8b)
2285 GEN_BINARY_TEST(orn, 16b, 16b, 16b)
2286 GEN_BINARY_TEST(orn, 8b, 8b, 8b)
2287
2288 /* overkill -- don't need two vecs, only one */
2289 GEN_TWOVEC_TEST(orr_8h_0x5A_lsl0, "orr v22.8h, #0x5A, LSL #0", 22, 23)
2290 GEN_TWOVEC_TEST(orr_8h_0xA5_lsl8, "orr v22.8h, #0xA5, LSL #8", 22, 23)
2291 GEN_TWOVEC_TEST(orr_4h_0x5A_lsl0, "orr v22.4h, #0x5A, LSL #0", 22, 23)
2292 GEN_TWOVEC_TEST(orr_4h_0xA5_lsl8, "orr v22.4h, #0xA5, LSL #8", 22, 23)
2293 GEN_TWOVEC_TEST(orr_4s_0x5A_lsl0, "orr v22.4s, #0x5A, LSL #0", 22, 23)
2294 GEN_TWOVEC_TEST(orr_4s_0x6B_lsl8, "orr v22.4s, #0x6B, LSL #8", 22, 23)
2295 GEN_TWOVEC_TEST(orr_4s_0x49_lsl16, "orr v22.4s, #0x49, LSL #16", 22, 23)
2296 GEN_TWOVEC_TEST(orr_4s_0x3D_lsl24, "orr v22.4s, #0x3D, LSL #24", 22, 23)
2297 GEN_TWOVEC_TEST(orr_2s_0x5A_lsl0, "orr v22.2s, #0x5A, LSL #0", 22, 23)
2298 GEN_TWOVEC_TEST(orr_2s_0x6B_lsl8, "orr v22.2s, #0x6B, LSL #8", 22, 23)
2299 GEN_TWOVEC_TEST(orr_2s_0x49_lsl16, "orr v22.2s, #0x49, LSL #16", 22, 23)
2300 GEN_TWOVEC_TEST(orr_2s_0x3D_lsl24, "orr v22.2s, #0x3D, LSL #24", 22, 23)
2301 GEN_TWOVEC_TEST(bic_8h_0x5A_lsl0, "bic v22.8h, #0x5A, LSL #0", 22, 23)
2302 GEN_TWOVEC_TEST(bic_8h_0xA5_lsl8, "bic v22.8h, #0xA5, LSL #8", 22, 23)
2303 GEN_TWOVEC_TEST(bic_4h_0x5A_lsl0, "bic v22.4h, #0x5A, LSL #0", 22, 23)
2304 GEN_TWOVEC_TEST(bic_4h_0xA5_lsl8, "bic v22.4h, #0xA5, LSL #8", 22, 23)
2305 GEN_TWOVEC_TEST(bic_4s_0x5A_lsl0, "bic v22.4s, #0x5A, LSL #0", 22, 23)
2306 GEN_TWOVEC_TEST(bic_4s_0x6B_lsl8, "bic v22.4s, #0x6B, LSL #8", 22, 23)
2307 GEN_TWOVEC_TEST(bic_4s_0x49_lsl16, "bic v22.4s, #0x49, LSL #16", 22, 23)
2308 GEN_TWOVEC_TEST(bic_4s_0x3D_lsl24, "bic v22.4s, #0x3D, LSL #24", 22, 23)
2309 GEN_TWOVEC_TEST(bic_2s_0x5A_lsl0, "bic v22.2s, #0x5A, LSL #0", 22, 23)
2310 GEN_TWOVEC_TEST(bic_2s_0x6B_lsl8, "bic v22.2s, #0x6B, LSL #8", 22, 23)
2311 GEN_TWOVEC_TEST(bic_2s_0x49_lsl16, "bic v22.2s, #0x49, LSL #16", 22, 23)
2312 GEN_TWOVEC_TEST(bic_2s_0x3D_lsl24, "bic v22.2s, #0x3D, LSL #24", 22, 23)
2313
2314 GEN_BINARY_TEST(bif, 16b, 16b, 16b)
2315 GEN_BINARY_TEST(bif, 8b, 8b, 8b)
2316 GEN_BINARY_TEST(bit, 16b, 16b, 16b)
2317 GEN_BINARY_TEST(bit, 8b, 8b, 8b)
2318 GEN_BINARY_TEST(bsl, 16b, 16b, 16b)
2319 GEN_BINARY_TEST(bsl, 8b, 8b, 8b)
2320 GEN_BINARY_TEST(eor, 16b, 16b, 16b)
2321 GEN_BINARY_TEST(eor, 8b, 8b, 8b)
2322
2323 GEN_UNARY_TEST(cls, 4s, 4s)
2324 GEN_UNARY_TEST(cls, 2s, 2s)
2325 GEN_UNARY_TEST(cls, 8h, 8h)
2326 GEN_UNARY_TEST(cls, 4h, 4h)
2327 GEN_UNARY_TEST(cls, 16b, 16b)
2328 GEN_UNARY_TEST(cls, 8b, 8b)
2329 GEN_UNARY_TEST(clz, 4s, 4s)
2330 GEN_UNARY_TEST(clz, 2s, 2s)
2331 GEN_UNARY_TEST(clz, 8h, 8h)
2332 GEN_UNARY_TEST(clz, 4h, 4h)
2333 GEN_UNARY_TEST(clz, 16b, 16b)
2334 GEN_UNARY_TEST(clz, 8b, 8b)
2335
2336 GEN_THREEVEC_TEST(cmeq_d_d_d, "cmeq d2, d11, d29", 2, 11, 29)
2337 GEN_THREEVEC_TEST(cmge_d_d_d, "cmge d2, d11, d29", 2, 11, 29)
2338 GEN_THREEVEC_TEST(cmgt_d_d_d, "cmgt d2, d11, d29", 2, 11, 29)
2339 GEN_THREEVEC_TEST(cmhi_d_d_d, "cmhi d2, d11, d29", 2, 11, 29)
2340 GEN_THREEVEC_TEST(cmhs_d_d_d, "cmhs d2, d11, d29", 2, 11, 29)
2341 GEN_THREEVEC_TEST(cmtst_d_d_d, "cmtst d2, d11, d29", 2, 11, 29)
2342
2343 GEN_BINARY_TEST(cmeq, 2d, 2d, 2d)
2344 GEN_BINARY_TEST(cmeq, 4s, 4s, 4s)
2345 GEN_BINARY_TEST(cmeq, 2s, 2s, 2s)
2346 GEN_BINARY_TEST(cmeq, 8h, 8h, 8h)
2347 GEN_BINARY_TEST(cmeq, 4h, 4h, 4h)
2348 GEN_BINARY_TEST(cmeq, 16b, 16b, 16b)
2349 GEN_BINARY_TEST(cmeq, 8b, 8b, 8b)
2350 GEN_BINARY_TEST(cmge, 2d, 2d, 2d)
2351 GEN_BINARY_TEST(cmge, 4s, 4s, 4s)
2352 GEN_BINARY_TEST(cmge, 2s, 2s, 2s)
2353 GEN_BINARY_TEST(cmge, 8h, 8h, 8h)
2354 GEN_BINARY_TEST(cmge, 4h, 4h, 4h)
2355 GEN_BINARY_TEST(cmge, 16b, 16b, 16b)
2356 GEN_BINARY_TEST(cmge, 8b, 8b, 8b)
2357 GEN_BINARY_TEST(cmgt, 2d, 2d, 2d)
2358 GEN_BINARY_TEST(cmgt, 4s, 4s, 4s)
2359 GEN_BINARY_TEST(cmgt, 2s, 2s, 2s)
2360 GEN_BINARY_TEST(cmgt, 8h, 8h, 8h)
2361 GEN_BINARY_TEST(cmgt, 4h, 4h, 4h)
2362 GEN_BINARY_TEST(cmgt, 16b, 16b, 16b)
2363 GEN_BINARY_TEST(cmgt, 8b, 8b, 8b)
2364 GEN_BINARY_TEST(cmhi, 2d, 2d, 2d)
2365 GEN_BINARY_TEST(cmhi, 4s, 4s, 4s)
2366 GEN_BINARY_TEST(cmhi, 2s, 2s, 2s)
2367 GEN_BINARY_TEST(cmhi, 8h, 8h, 8h)
2368 GEN_BINARY_TEST(cmhi, 4h, 4h, 4h)
2369 GEN_BINARY_TEST(cmhi, 16b, 16b, 16b)
2370 GEN_BINARY_TEST(cmhi, 8b, 8b, 8b)
2371 GEN_BINARY_TEST(cmhs, 2d, 2d, 2d)
2372 GEN_BINARY_TEST(cmhs, 4s, 4s, 4s)
2373 GEN_BINARY_TEST(cmhs, 2s, 2s, 2s)
2374 GEN_BINARY_TEST(cmhs, 8h, 8h, 8h)
2375 GEN_BINARY_TEST(cmhs, 4h, 4h, 4h)
2376 GEN_BINARY_TEST(cmhs, 16b, 16b, 16b)
2377 GEN_BINARY_TEST(cmhs, 8b, 8b, 8b)
2378 GEN_BINARY_TEST(cmtst, 2d, 2d, 2d)
2379 GEN_BINARY_TEST(cmtst, 4s, 4s, 4s)
2380 GEN_BINARY_TEST(cmtst, 2s, 2s, 2s)
2381 GEN_BINARY_TEST(cmtst, 8h, 8h, 8h)
2382 GEN_BINARY_TEST(cmtst, 4h, 4h, 4h)
2383 GEN_BINARY_TEST(cmtst, 16b, 16b, 16b)
2384 GEN_BINARY_TEST(cmtst, 8b, 8b, 8b)
2385
2386 GEN_TWOVEC_TEST(cmeq_zero_d_d, "cmeq d2, d11, #0", 2, 11)
2387 GEN_TWOVEC_TEST(cmge_zero_d_d, "cmge d2, d11, #0", 2, 11)
2388 GEN_TWOVEC_TEST(cmgt_zero_d_d, "cmgt d2, d11, #0", 2, 11)
2389 GEN_TWOVEC_TEST(cmle_zero_d_d, "cmle d2, d11, #0", 2, 11)
2390 GEN_TWOVEC_TEST(cmlt_zero_d_d, "cmlt d2, d11, #0", 2, 11)
2391
2392 GEN_TWOVEC_TEST(cmeq_zero_2d_2d, "cmeq v5.2d, v22.2d, #0", 5, 22)
2393 GEN_TWOVEC_TEST(cmeq_zero_4s_4s, "cmeq v5.4s, v22.4s, #0", 5, 22)
2394 GEN_TWOVEC_TEST(cmeq_zero_2s_2s, "cmeq v5.2s, v22.2s, #0", 5, 22)
2395 GEN_TWOVEC_TEST(cmeq_zero_8h_8h, "cmeq v5.8h, v22.8h, #0", 5, 22)
2396 GEN_TWOVEC_TEST(cmeq_zero_4h_4h, "cmeq v5.4h, v22.4h, #0", 5, 22)
2397 GEN_TWOVEC_TEST(cmeq_zero_16b_16b, "cmeq v5.16b, v22.16b, #0", 5, 22)
2398 GEN_TWOVEC_TEST(cmeq_zero_8b_8b, "cmeq v5.8b, v22.8b, #0", 5, 22)
2399 GEN_TWOVEC_TEST(cmge_zero_2d_2d, "cmge v5.2d, v22.2d, #0", 5, 22)
2400 GEN_TWOVEC_TEST(cmge_zero_4s_4s, "cmge v5.4s, v22.4s, #0", 5, 22)
2401 GEN_TWOVEC_TEST(cmge_zero_2s_2s, "cmge v5.2s, v22.2s, #0", 5, 22)
2402 GEN_TWOVEC_TEST(cmge_zero_8h_8h, "cmge v5.8h, v22.8h, #0", 5, 22)
2403 GEN_TWOVEC_TEST(cmge_zero_4h_4h, "cmge v5.4h, v22.4h, #0", 5, 22)
2404 GEN_TWOVEC_TEST(cmge_zero_16b_16b, "cmge v5.16b, v22.16b, #0", 5, 22)
2405 GEN_TWOVEC_TEST(cmge_zero_8b_8b, "cmge v5.8b, v22.8b, #0", 5, 22)
2406 GEN_TWOVEC_TEST(cmgt_zero_2d_2d, "cmgt v5.2d, v22.2d, #0", 5, 22)
2407 GEN_TWOVEC_TEST(cmgt_zero_4s_4s, "cmgt v5.4s, v22.4s, #0", 5, 22)
2408 GEN_TWOVEC_TEST(cmgt_zero_2s_2s, "cmgt v5.2s, v22.2s, #0", 5, 22)
2409 GEN_TWOVEC_TEST(cmgt_zero_8h_8h, "cmgt v5.8h, v22.8h, #0", 5, 22)
2410 GEN_TWOVEC_TEST(cmgt_zero_4h_4h, "cmgt v5.4h, v22.4h, #0", 5, 22)
2411 GEN_TWOVEC_TEST(cmgt_zero_16b_16b, "cmgt v5.16b, v22.16b, #0", 5, 22)
2412 GEN_TWOVEC_TEST(cmgt_zero_8b_8b, "cmgt v5.8b, v22.8b, #0", 5, 22)
2413 GEN_TWOVEC_TEST(cmle_zero_2d_2d, "cmle v5.2d, v22.2d, #0", 5, 22)
2414 GEN_TWOVEC_TEST(cmle_zero_4s_4s, "cmle v5.4s, v22.4s, #0", 5, 22)
2415 GEN_TWOVEC_TEST(cmle_zero_2s_2s, "cmle v5.2s, v22.2s, #0", 5, 22)
2416 GEN_TWOVEC_TEST(cmle_zero_8h_8h, "cmle v5.8h, v22.8h, #0", 5, 22)
2417 GEN_TWOVEC_TEST(cmle_zero_4h_4h, "cmle v5.4h, v22.4h, #0", 5, 22)
2418 GEN_TWOVEC_TEST(cmle_zero_16b_16b, "cmle v5.16b, v22.16b, #0", 5, 22)
2419 GEN_TWOVEC_TEST(cmle_zero_8b_8b, "cmle v5.8b, v22.8b, #0", 5, 22)
2420 GEN_TWOVEC_TEST(cmlt_zero_2d_2d, "cmlt v5.2d, v22.2d, #0", 5, 22)
2421 GEN_TWOVEC_TEST(cmlt_zero_4s_4s, "cmlt v5.4s, v22.4s, #0", 5, 22)
2422 GEN_TWOVEC_TEST(cmlt_zero_2s_2s, "cmlt v5.2s, v22.2s, #0", 5, 22)
2423 GEN_TWOVEC_TEST(cmlt_zero_8h_8h, "cmlt v5.8h, v22.8h, #0", 5, 22)
2424 GEN_TWOVEC_TEST(cmlt_zero_4h_4h, "cmlt v5.4h, v22.4h, #0", 5, 22)
2425 GEN_TWOVEC_TEST(cmlt_zero_16b_16b, "cmlt v5.16b, v22.16b, #0", 5, 22)
2426 GEN_TWOVEC_TEST(cmlt_zero_8b_8b, "cmlt v5.8b, v22.8b, #0", 5, 22)
2427
2428 GEN_UNARY_TEST(cnt, 16b, 16b)
2429 GEN_UNARY_TEST(cnt, 8b, 8b)
2430
2431 GEN_TWOVEC_TEST(dup_d_d0, "dup d22, v23.d[0]", 22, 23)
2432 GEN_TWOVEC_TEST(dup_d_d1, "dup d22, v23.d[1]", 22, 23)
2433 GEN_TWOVEC_TEST(dup_s_s0, "dup s22, v23.s[0]", 22, 23)
2434 GEN_TWOVEC_TEST(dup_s_s3, "dup s22, v23.s[3]", 22, 23)
2435 GEN_TWOVEC_TEST(dup_h_h0, "dup h22, v23.h[0]", 22, 23)
2436 GEN_TWOVEC_TEST(dup_h_h6, "dup h22, v23.h[6]", 22, 23)
2437 GEN_TWOVEC_TEST(dup_b_b0, "dup b0, v23.b[0]", 22, 23)
2438 GEN_TWOVEC_TEST(dup_b_b13, "dup b13, v23.b[13]", 22, 23)
2439
2440 GEN_TWOVEC_TEST(dup_2d_d0, "dup v9.2d, v17.d[0]", 9, 17)
2441 GEN_TWOVEC_TEST(dup_2d_d1, "dup v9.2d, v17.d[1]", 9, 17)
2442 GEN_TWOVEC_TEST(dup_4s_s0, "dup v9.4s, v17.s[0]", 9, 17)
2443 GEN_TWOVEC_TEST(dup_4s_s3, "dup v9.4s, v17.s[3]", 9, 17)
2444 GEN_TWOVEC_TEST(dup_2s_s0, "dup v9.2s, v17.s[0]", 9, 17)
2445 GEN_TWOVEC_TEST(dup_2s_s2, "dup v9.2s, v17.s[2]", 9, 17)
2446 GEN_TWOVEC_TEST(dup_8h_h0, "dup v9.8h, v17.h[0]", 9, 17)
2447 GEN_TWOVEC_TEST(dup_8h_h6, "dup v9.8h, v17.h[6]", 9, 17)
2448 GEN_TWOVEC_TEST(dup_4h_h1, "dup v9.4h, v17.h[1]", 9, 17)
2449 GEN_TWOVEC_TEST(dup_4h_h5, "dup v9.4h, v17.h[5]", 9, 17)
2450 GEN_TWOVEC_TEST(dup_16b_b2, "dup v9.16b, v17.b[2]", 9, 17)
2451 GEN_TWOVEC_TEST(dup_16b_b12, "dup v9.16b, v17.b[12]", 9, 17)
2452 GEN_TWOVEC_TEST(dup_8b_b3, "dup v9.8b, v17.b[3]", 9, 17)
2453 GEN_TWOVEC_TEST(dup_8b_b13, "dup v9.8b, v17.b[13]", 9, 17)
2454
2455 GEN_TWOVEC_TEST(dup_2d_x, "mov x10, v17.d[0]; dup v9.2d, x10", 9, 17)
2456 GEN_TWOVEC_TEST(dup_4s_w, "mov x10, v17.d[0]; dup v9.4s, w10", 9, 17)
2457 GEN_TWOVEC_TEST(dup_2s_w, "mov x10, v17.d[0]; dup v9.2s, w10", 9, 17)
2458 GEN_TWOVEC_TEST(dup_8h_w, "mov x10, v17.d[0]; dup v9.8h, w10", 9, 17)
2459 GEN_TWOVEC_TEST(dup_4h_w, "mov x10, v17.d[0]; dup v9.4h, w10", 9, 17)
2460 GEN_TWOVEC_TEST(dup_16b_w, "mov x10, v17.d[0]; dup v9.16b, w10", 9, 17)
2461 GEN_TWOVEC_TEST(dup_8b_w, "mov x10, v17.d[0]; dup v9.8b, w10", 9, 17)
2462
2463 GEN_THREEVEC_TEST(ext_16b_16b_16b_0x0,
2464 "ext v2.16b, v11.16b, v29.16b, #0", 2, 11, 29)
2465 GEN_THREEVEC_TEST(ext_16b_16b_16b_0x1,
2466 "ext v2.16b, v11.16b, v29.16b, #1", 2, 11, 29)
2467 GEN_THREEVEC_TEST(ext_16b_16b_16b_0x2,
2468 "ext v2.16b, v11.16b, v29.16b, #2", 2, 11, 29)
2469 GEN_THREEVEC_TEST(ext_16b_16b_16b_0x3,
2470 "ext v2.16b, v11.16b, v29.16b, #3", 2, 11, 29)
2471 GEN_THREEVEC_TEST(ext_16b_16b_16b_0x4,
2472 "ext v2.16b, v11.16b, v29.16b, #4", 2, 11, 29)
2473 GEN_THREEVEC_TEST(ext_16b_16b_16b_0x5,
2474 "ext v2.16b, v11.16b, v29.16b, #5", 2, 11, 29)
2475 GEN_THREEVEC_TEST(ext_16b_16b_16b_0x6,
2476 "ext v2.16b, v11.16b, v29.16b, #6", 2, 11, 29)
2477 GEN_THREEVEC_TEST(ext_16b_16b_16b_0x7,
2478 "ext v2.16b, v11.16b, v29.16b, #7", 2, 11, 29)
2479 GEN_THREEVEC_TEST(ext_16b_16b_16b_0x8,
2480 "ext v2.16b, v11.16b, v29.16b, #8", 2, 11, 29)
2481 GEN_THREEVEC_TEST(ext_16b_16b_16b_0x9,
2482 "ext v2.16b, v11.16b, v29.16b, #9", 2, 11, 29)
2483 GEN_THREEVEC_TEST(ext_16b_16b_16b_0xA,
2484 "ext v2.16b, v11.16b, v29.16b, #10", 2, 11, 29)
2485 GEN_THREEVEC_TEST(ext_16b_16b_16b_0xB,
2486 "ext v2.16b, v11.16b, v29.16b, #11", 2, 11, 29)
2487 GEN_THREEVEC_TEST(ext_16b_16b_16b_0xC,
2488 "ext v2.16b, v11.16b, v29.16b, #12", 2, 11, 29)
2489 GEN_THREEVEC_TEST(ext_16b_16b_16b_0xD,
2490 "ext v2.16b, v11.16b, v29.16b, #13", 2, 11, 29)
2491 GEN_THREEVEC_TEST(ext_16b_16b_16b_0xE,
2492 "ext v2.16b, v11.16b, v29.16b, #14", 2, 11, 29)
2493 GEN_THREEVEC_TEST(ext_16b_16b_16b_0xF,
2494 "ext v2.16b, v11.16b, v29.16b, #15", 2, 11, 29)
2495 GEN_THREEVEC_TEST(ext_8b_8b_8b_0x0,
2496 "ext v2.8b, v11.8b, v29.8b, #0", 2, 11, 29)
2497 GEN_THREEVEC_TEST(ext_8b_8b_8b_0x1,
2498 "ext v2.8b, v11.8b, v29.8b, #1", 2, 11, 29)
2499 GEN_THREEVEC_TEST(ext_8b_8b_8b_0x2,
2500 "ext v2.8b, v11.8b, v29.8b, #2", 2, 11, 29)
2501 GEN_THREEVEC_TEST(ext_8b_8b_8b_0x3,
2502 "ext v2.8b, v11.8b, v29.8b, #3", 2, 11, 29)
2503 GEN_THREEVEC_TEST(ext_8b_8b_8b_0x4,
2504 "ext v2.8b, v11.8b, v29.8b, #4", 2, 11, 29)
2505 GEN_THREEVEC_TEST(ext_8b_8b_8b_0x5,
2506 "ext v2.8b, v11.8b, v29.8b, #5", 2, 11, 29)
2507 GEN_THREEVEC_TEST(ext_8b_8b_8b_0x6,
2508 "ext v2.8b, v11.8b, v29.8b, #6", 2, 11, 29)
2509 GEN_THREEVEC_TEST(ext_8b_8b_8b_0x7,
2510 "ext v2.8b, v11.8b, v29.8b, #7", 2, 11, 29)
2511
2512 GEN_TWOVEC_TEST(ins_d0_d0, "ins v3.d[0], v24.d[0]", 3, 24)
2513 GEN_TWOVEC_TEST(ins_d0_d1, "ins v3.d[0], v24.d[1]", 3, 24)
2514 GEN_TWOVEC_TEST(ins_d1_d0, "ins v3.d[1], v24.d[0]", 3, 24)
2515 GEN_TWOVEC_TEST(ins_d1_d1, "ins v3.d[1], v24.d[1]", 3, 24)
2516 GEN_TWOVEC_TEST(ins_s0_s2, "ins v3.s[0], v24.s[2]", 3, 24)
2517 GEN_TWOVEC_TEST(ins_s3_s0, "ins v3.s[3], v24.s[0]", 3, 24)
2518 GEN_TWOVEC_TEST(ins_s2_s1, "ins v3.s[2], v24.s[1]", 3, 24)
2519 GEN_TWOVEC_TEST(ins_s1_s3, "ins v3.s[1], v24.s[3]", 3, 24)
2520 GEN_TWOVEC_TEST(ins_h0_h6, "ins v3.h[0], v24.h[6]", 3, 24)
2521 GEN_TWOVEC_TEST(ins_h7_h0, "ins v3.h[7], v24.h[0]", 3, 24)
2522 GEN_TWOVEC_TEST(ins_h6_h1, "ins v3.h[6], v24.h[1]", 3, 24)
2523 GEN_TWOVEC_TEST(ins_h1_h7, "ins v3.h[1], v24.h[7]", 3, 24)
2524 GEN_TWOVEC_TEST(ins_b0_b14, "ins v3.b[0], v24.b[14]", 3, 24)
2525 GEN_TWOVEC_TEST(ins_b15_b8, "ins v3.b[15], v24.b[8]", 3, 24)
2526 GEN_TWOVEC_TEST(ins_b13_b9, "ins v3.b[13], v24.b[9]", 3, 24)
2527 GEN_TWOVEC_TEST(ins_b5_b12, "ins v3.b[5], v24.b[12]", 3, 24)
2528
2529 // test_INS_general is a handwritten function
2530
2531 GEN_THREEVEC_TEST(mla_4s_4s_s0, "mla v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
2532 GEN_THREEVEC_TEST(mla_4s_4s_s3, "mla v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
2533 GEN_THREEVEC_TEST(mla_2s_2s_s0, "mla v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
2534 GEN_THREEVEC_TEST(mla_2s_2s_s3, "mla v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
2535 // For the 'h' version of these, Rm can only be <= 15 (!)
2536 GEN_THREEVEC_TEST(mla_8h_8h_h1, "mla v2.8h, v11.8h, v2.h[1]", 2, 11, 9)
2537 GEN_THREEVEC_TEST(mla_8h_8h_h5, "mla v2.8h, v11.8h, v2.h[5]", 2, 11, 9)
2538 GEN_THREEVEC_TEST(mla_4h_4h_h2, "mla v2.4h, v11.4h, v2.h[2]", 2, 11, 9)
2539 GEN_THREEVEC_TEST(mla_4h_4h_h7, "mla v2.4h, v11.4h, v2.h[7]", 2, 11, 9)
2540 GEN_THREEVEC_TEST(mls_4s_4s_s0, "mls v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
2541 GEN_THREEVEC_TEST(mls_4s_4s_s3, "mls v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
2542 GEN_THREEVEC_TEST(mls_2s_2s_s0, "mls v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
2543 GEN_THREEVEC_TEST(mls_2s_2s_s3, "mls v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
2544 // For the 'h' version of these, Rm can only be <= 15 (!)
2545 GEN_THREEVEC_TEST(mls_8h_8h_h1, "mls v2.8h, v11.8h, v2.h[1]", 2, 11, 9)
2546 GEN_THREEVEC_TEST(mls_8h_8h_h5, "mls v2.8h, v11.8h, v2.h[5]", 2, 11, 9)
2547 GEN_THREEVEC_TEST(mls_4h_4h_h2, "mls v2.4h, v11.4h, v2.h[2]", 2, 11, 9)
2548 GEN_THREEVEC_TEST(mls_4h_4h_h7, "mls v2.4h, v11.4h, v2.h[7]", 2, 11, 9)
2549 GEN_THREEVEC_TEST(mul_4s_4s_s0, "mul v2.4s, v11.4s, v29.s[0]", 2, 11, 29)
2550 GEN_THREEVEC_TEST(mul_4s_4s_s3, "mul v2.4s, v11.4s, v29.s[3]", 2, 11, 29)
2551 GEN_THREEVEC_TEST(mul_2s_2s_s0, "mul v2.2s, v11.2s, v29.s[0]", 2, 11, 29)
2552 GEN_THREEVEC_TEST(mul_2s_2s_s3, "mul v2.2s, v11.2s, v29.s[3]", 2, 11, 29)
2553 // For the 'h' version of these, Rm can only be <= 15 (!)
2554 GEN_THREEVEC_TEST(mul_8h_8h_h1, "mul v2.8h, v11.8h, v2.h[1]", 2, 11, 9)
2555 GEN_THREEVEC_TEST(mul_8h_8h_h5, "mul v2.8h, v11.8h, v2.h[5]", 2, 11, 9)
2556 GEN_THREEVEC_TEST(mul_4h_4h_h2, "mul v2.4h, v11.4h, v2.h[2]", 2, 11, 9)
2557 GEN_THREEVEC_TEST(mul_4h_4h_h7, "mul v2.4h, v11.4h, v2.h[7]", 2, 11, 9)
2558
2559 GEN_BINARY_TEST(mla, 4s, 4s, 4s)
2560 GEN_BINARY_TEST(mla, 2s, 2s, 2s)
2561 GEN_BINARY_TEST(mla, 8h, 8h, 8h)
2562 GEN_BINARY_TEST(mla, 4h, 4h, 4h)
2563 GEN_BINARY_TEST(mla, 16b, 16b, 16b)
2564 GEN_BINARY_TEST(mla, 8b, 8b, 8b)
2565 GEN_BINARY_TEST(mls, 4s, 4s, 4s)
2566 GEN_BINARY_TEST(mls, 2s, 2s, 2s)
2567 GEN_BINARY_TEST(mls, 8h, 8h, 8h)
2568 GEN_BINARY_TEST(mls, 4h, 4h, 4h)
2569 GEN_BINARY_TEST(mls, 16b, 16b, 16b)
2570 GEN_BINARY_TEST(mls, 8b, 8b, 8b)
2571 GEN_BINARY_TEST(mul, 4s, 4s, 4s)
2572 GEN_BINARY_TEST(mul, 2s, 2s, 2s)
2573 GEN_BINARY_TEST(mul, 8h, 8h, 8h)
2574 GEN_BINARY_TEST(mul, 4h, 4h, 4h)
2575 GEN_BINARY_TEST(mul, 16b, 16b, 16b)
2576 GEN_BINARY_TEST(mul, 8b, 8b, 8b)
2577
2578 /* overkill -- don't need two vecs, only one */
2579 GEN_TWOVEC_TEST(movi_16b_0x9C_lsl0, "movi v22.16b, #0x9C", 22, 23)
2580 GEN_TWOVEC_TEST(movi_8b_0x8B_lsl0, "movi v22.8b, #0x8B", 22, 23)
2581
2582 GEN_TWOVEC_TEST(movi_8h_0x5A_lsl0, "movi v22.8h, #0x5A, LSL #0", 22, 23)
2583 GEN_TWOVEC_TEST(movi_8h_0xA5_lsl8, "movi v22.8h, #0xA5, LSL #8", 22, 23)
2584 GEN_TWOVEC_TEST(movi_4h_0x5A_lsl0, "movi v22.4h, #0x5A, LSL #0", 22, 23)
2585 GEN_TWOVEC_TEST(movi_4h_0xA5_lsl8, "movi v22.4h, #0xA5, LSL #8", 22, 23)
2586 GEN_TWOVEC_TEST(mvni_8h_0x5A_lsl0, "mvni v22.8h, #0x5A, LSL #0", 22, 23)
2587 GEN_TWOVEC_TEST(mvni_8h_0xA5_lsl8, "mvni v22.8h, #0xA5, LSL #8", 22, 23)
2588 GEN_TWOVEC_TEST(mvni_4h_0x5A_lsl0, "mvni v22.4h, #0x5A, LSL #0", 22, 23)
2589 GEN_TWOVEC_TEST(mvni_4h_0xA5_lsl8, "mvni v22.4h, #0xA5, LSL #8", 22, 23)
2590
2591 GEN_TWOVEC_TEST(movi_4s_0x5A_lsl0, "movi v22.4s, #0x5A, LSL #0", 22, 23)
2592 GEN_TWOVEC_TEST(movi_4s_0x6B_lsl8, "movi v22.4s, #0x6B, LSL #8", 22, 23)
2593 GEN_TWOVEC_TEST(movi_4s_0x49_lsl16, "movi v22.4s, #0x49, LSL #16", 22, 23)
2594 GEN_TWOVEC_TEST(movi_4s_0x3D_lsl24, "movi v22.4s, #0x3D, LSL #24", 22, 23)
2595 GEN_TWOVEC_TEST(movi_2s_0x5A_lsl0, "movi v22.2s, #0x5A, LSL #0", 22, 23)
2596 GEN_TWOVEC_TEST(movi_2s_0x6B_lsl8, "movi v22.2s, #0x6B, LSL #8", 22, 23)
2597 GEN_TWOVEC_TEST(movi_2s_0x49_lsl16, "movi v22.2s, #0x49, LSL #16", 22, 23)
2598 GEN_TWOVEC_TEST(movi_2s_0x3D_lsl24, "movi v22.2s, #0x3D, LSL #24", 22, 23)
2599 GEN_TWOVEC_TEST(mvni_4s_0x5A_lsl0, "mvni v22.4s, #0x5A, LSL #0", 22, 23)
2600 GEN_TWOVEC_TEST(mvni_4s_0x6B_lsl8, "mvni v22.4s, #0x6B, LSL #8", 22, 23)
2601 GEN_TWOVEC_TEST(mvni_4s_0x49_lsl16, "mvni v22.4s, #0x49, LSL #16", 22, 23)
2602 GEN_TWOVEC_TEST(mvni_4s_0x3D_lsl24, "mvni v22.4s, #0x3D, LSL #24", 22, 23)
2603 GEN_TWOVEC_TEST(mvni_2s_0x5A_lsl0, "mvni v22.2s, #0x5A, LSL #0", 22, 23)
2604 GEN_TWOVEC_TEST(mvni_2s_0x6B_lsl8, "mvni v22.2s, #0x6B, LSL #8", 22, 23)
2605 GEN_TWOVEC_TEST(mvni_2s_0x49_lsl16, "mvni v22.2s, #0x49, LSL #16", 22, 23)
2606 GEN_TWOVEC_TEST(mvni_2s_0x3D_lsl24, "mvni v22.2s, #0x3D, LSL #24", 22, 23)
2607
2608 /* overkill -- don't need two vecs, only one */
2609 GEN_TWOVEC_TEST(movi_4s_0x6B_msl8, "movi v22.4s, #0x6B, MSL #8", 22, 23)
2610 GEN_TWOVEC_TEST(movi_4s_0x94_msl16, "movi v22.4s, #0x94, MSL #16", 22, 23)
2611 GEN_TWOVEC_TEST(movi_2s_0x7A_msl8, "movi v22.2s, #0x7A, MSL #8", 22, 23)
2612 GEN_TWOVEC_TEST(movi_2s_0xA5_msl16, "movi v22.2s, #0xA5, MSL #16", 22, 23)
2613 GEN_TWOVEC_TEST(mvni_4s_0x6B_msl8, "mvni v22.4s, #0x6B, MSL #8", 22, 23)
2614 GEN_TWOVEC_TEST(mvni_4s_0x94_msl16, "mvni v22.4s, #0x94, MSL #16", 22, 23)
2615 GEN_TWOVEC_TEST(mvni_2s_0x7A_msl8, "mvni v22.2s, #0x7A, MSL #8", 22, 23)
2616 GEN_TWOVEC_TEST(mvni_2s_0xA5_msl16, "mvni v22.2s, #0xA5, MSL #16", 22, 23)
2617
2618 GEN_TWOVEC_TEST(movi_d_0xA5, "movi d22, #0xFF00FF0000FF00FF", 22, 23)
2619 GEN_TWOVEC_TEST(movi_2d_0xB4, "movi v22.2d, #0xFF00FFFF00FF0000", 22, 23)
2620
2621 GEN_UNARY_TEST(not, 16b, 16b)
2622 GEN_UNARY_TEST(not, 8b, 8b)
2623
2624 GEN_BINARY_TEST(pmul, 16b, 16b, 16b)
2625 GEN_BINARY_TEST(pmul, 8b, 8b, 8b)
2626
2627 GEN_BINARY_TEST(pmull, 8h, 8b, 8b)
2628 GEN_BINARY_TEST(pmull2, 8h, 16b, 16b)
2629 GEN_BINARY_TEST(pmull, 1q, 1d, 1d)
2630 GEN_BINARY_TEST(pmull2, 1q, 2d, 2d)
2631
2632 GEN_UNARY_TEST(rbit, 16b, 16b)
2633 GEN_UNARY_TEST(rbit, 8b, 8b)
2634 GEN_UNARY_TEST(rev16, 16b, 16b)
2635 GEN_UNARY_TEST(rev16, 8b, 8b)
2636 GEN_UNARY_TEST(rev32, 16b, 16b)
2637 GEN_UNARY_TEST(rev32, 8b, 8b)
2638 GEN_UNARY_TEST(rev32, 8h, 8h)
2639 GEN_UNARY_TEST(rev32, 4h, 4h)
2640 GEN_UNARY_TEST(rev64, 16b, 16b)
2641 GEN_UNARY_TEST(rev64, 8b, 8b)
2642 GEN_UNARY_TEST(rev64, 8h, 8h)
2643 GEN_UNARY_TEST(rev64, 4h, 4h)
2644 GEN_UNARY_TEST(rev64, 4s, 4s)
2645 GEN_UNARY_TEST(rev64, 2s, 2s)
2646
2647 GEN_BINARY_TEST(saba, 4s, 4s, 4s)
2648 GEN_BINARY_TEST(saba, 2s, 2s, 2s)
2649 GEN_BINARY_TEST(saba, 8h, 8h, 8h)
2650 GEN_BINARY_TEST(saba, 4h, 4h, 4h)
2651 GEN_BINARY_TEST(saba, 16b, 16b, 16b)
2652 GEN_BINARY_TEST(saba, 8b, 8b, 8b)
2653 GEN_BINARY_TEST(uaba, 4s, 4s, 4s)
2654 GEN_BINARY_TEST(uaba, 2s, 2s, 2s)
2655 GEN_BINARY_TEST(uaba, 8h, 8h, 8h)
2656 GEN_BINARY_TEST(uaba, 4h, 4h, 4h)
2657 GEN_BINARY_TEST(uaba, 16b, 16b, 16b)
2658 GEN_BINARY_TEST(uaba, 8b, 8b, 8b)
2659
2660 GEN_THREEVEC_TEST(sabal_2d_2s_2s, "sabal v2.2d, v11.2s, v29.2s", 2, 11, 29)
2661 GEN_THREEVEC_TEST(sabal2_2d_4s_4s, "sabal2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
2662 GEN_THREEVEC_TEST(sabal_4s_4h_4h, "sabal v2.4s, v11.4h, v29.4h", 2, 11, 29)
2663 GEN_THREEVEC_TEST(sabal2_4s_8h_8h, "sabal2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
2664 GEN_THREEVEC_TEST(sabal_8h_8b_8b, "sabal v2.8h, v11.8b, v29.8b", 2, 11, 29)
2665 GEN_THREEVEC_TEST(sabal2_8h_16b_16b,
2666 "sabal2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
2667 GEN_THREEVEC_TEST(uabal_2d_2s_2s, "uabal v2.2d, v11.2s, v29.2s", 2, 11, 29)
2668 GEN_THREEVEC_TEST(uabal2_2d_4s_4s, "uabal2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
2669 GEN_THREEVEC_TEST(uabal_4s_4h_4h, "uabal v2.4s, v11.4h, v29.4h", 2, 11, 29)
2670 GEN_THREEVEC_TEST(uabal2_4s_8h_8h, "uabal2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
2671 GEN_THREEVEC_TEST(uabal_8h_8b_8b, "uabal v2.8h, v11.8b, v29.8b", 2, 11, 29)
2672 GEN_THREEVEC_TEST(uabal2_8h_16b_16b,
2673 "uabal2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
2674
2675 GEN_THREEVEC_TEST(sabd_4s_4s_4s, "sabd v2.4s, v11.4s, v29.4s", 2, 11, 29)
2676 GEN_THREEVEC_TEST(sabd_2s_2s_2s, "sabd v2.2s, v11.2s, v29.2s", 2, 11, 29)
2677 GEN_THREEVEC_TEST(sabd_8h_8h_8h, "sabd v2.8h, v11.8h, v29.8h", 2, 11, 29)
2678 GEN_THREEVEC_TEST(sabd_4h_4h_4h, "sabd v2.4h, v11.4h, v29.4h", 2, 11, 29)
2679 GEN_THREEVEC_TEST(sabd_16b_16b_16b, "sabd v2.16b, v11.16b, v29.16b", 2, 11, 29)
2680 GEN_THREEVEC_TEST(sabd_8b_8b_8b, "sabd v2.8b, v11.8b, v29.8b", 2, 11, 29)
2681 GEN_THREEVEC_TEST(uabd_4s_4s_4s, "uabd v2.4s, v11.4s, v29.4s", 2, 11, 29)
2682 GEN_THREEVEC_TEST(uabd_2s_2s_2s, "uabd v2.2s, v11.2s, v29.2s", 2, 11, 29)
2683 GEN_THREEVEC_TEST(uabd_8h_8h_8h, "uabd v2.8h, v11.8h, v29.8h", 2, 11, 29)
2684 GEN_THREEVEC_TEST(uabd_4h_4h_4h, "uabd v2.4h, v11.4h, v29.4h", 2, 11, 29)
2685 GEN_THREEVEC_TEST(uabd_16b_16b_16b, "uabd v2.16b, v11.16b, v29.16b", 2, 11, 29)
2686 GEN_THREEVEC_TEST(uabd_8b_8b_8b, "uabd v2.8b, v11.8b, v29.8b", 2, 11, 29)
2687
2688 GEN_THREEVEC_TEST(sabdl_2d_2s_2s, "sabdl v2.2d, v11.2s, v29.2s", 2, 11, 29)
2689 GEN_THREEVEC_TEST(sabdl2_2d_4s_4s, "sabdl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
2690 GEN_THREEVEC_TEST(sabdl_4s_4h_4h, "sabdl v2.4s, v11.4h, v29.4h", 2, 11, 29)
2691 GEN_THREEVEC_TEST(sabdl2_4s_8h_8h, "sabdl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
2692 GEN_THREEVEC_TEST(sabdl_8h_8b_8b, "sabdl v2.8h, v11.8b, v29.8b", 2, 11, 29)
2693 GEN_THREEVEC_TEST(sabdl2_8h_16b_16b,
2694 "sabdl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
2695 GEN_THREEVEC_TEST(uabdl_2d_2s_2s, "uabdl v2.2d, v11.2s, v29.2s", 2, 11, 29)
2696 GEN_THREEVEC_TEST(uabdl2_2d_4s_4s, "uabdl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
2697 GEN_THREEVEC_TEST(uabdl_4s_4h_4h, "uabdl v2.4s, v11.4h, v29.4h", 2, 11, 29)
2698 GEN_THREEVEC_TEST(uabdl2_4s_8h_8h, "uabdl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
2699 GEN_THREEVEC_TEST(uabdl_8h_8b_8b, "uabdl v2.8h, v11.8b, v29.8b", 2, 11, 29)
2700 GEN_THREEVEC_TEST(uabdl2_8h_16b_16b,
2701 "uabdl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
2702
2703 GEN_TWOVEC_TEST(sadalp_4h_8b, "sadalp v3.4h, v19.8b", 3, 19)
2704 GEN_TWOVEC_TEST(sadalp_8h_16b, "sadalp v3.8h, v19.16b", 3, 19)
2705 GEN_TWOVEC_TEST(sadalp_2s_4h, "sadalp v3.2s, v19.4h", 3, 19)
2706 GEN_TWOVEC_TEST(sadalp_4s_8h, "sadalp v3.4s, v19.8h", 3, 19)
2707 GEN_TWOVEC_TEST(sadalp_1d_2s, "sadalp v3.1d, v19.2s", 3, 19)
2708 GEN_TWOVEC_TEST(sadalp_2d_4s, "sadalp v3.2d, v19.4s", 3, 19)
2709 GEN_TWOVEC_TEST(uadalp_4h_8b, "uadalp v3.4h, v19.8b", 3, 19)
2710 GEN_TWOVEC_TEST(uadalp_8h_16b, "uadalp v3.8h, v19.16b", 3, 19)
2711 GEN_TWOVEC_TEST(uadalp_2s_4h, "uadalp v3.2s, v19.4h", 3, 19)
2712 GEN_TWOVEC_TEST(uadalp_4s_8h, "uadalp v3.4s, v19.8h", 3, 19)
2713 GEN_TWOVEC_TEST(uadalp_1d_2s, "uadalp v3.1d, v19.2s", 3, 19)
2714 GEN_TWOVEC_TEST(uadalp_2d_4s, "uadalp v3.2d, v19.4s", 3, 19)
2715
2716 GEN_THREEVEC_TEST(saddl_2d_2s_2s, "saddl v2.2d, v11.2s, v29.2s", 2, 11, 29)
2717 GEN_THREEVEC_TEST(saddl2_2d_4s_4s, "saddl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
2718 GEN_THREEVEC_TEST(saddl_4s_4h_4h, "saddl v2.4s, v11.4h, v29.4h", 2, 11, 29)
2719 GEN_THREEVEC_TEST(saddl2_4s_8h_8h, "saddl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
2720 GEN_THREEVEC_TEST(saddl_8h_8b_8b, "saddl v2.8h, v11.8b, v29.8b", 2, 11, 29)
2721 GEN_THREEVEC_TEST(saddl2_8h_16b_16b,
2722 "saddl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
2723 GEN_THREEVEC_TEST(uaddl_2d_2s_2s, "uaddl v2.2d, v11.2s, v29.2s", 2, 11, 29)
2724 GEN_THREEVEC_TEST(uaddl2_2d_4s_4s, "uaddl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
2725 GEN_THREEVEC_TEST(uaddl_4s_4h_4h, "uaddl v2.4s, v11.4h, v29.4h", 2, 11, 29)
2726 GEN_THREEVEC_TEST(uaddl2_4s_8h_8h, "uaddl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
2727 GEN_THREEVEC_TEST(uaddl_8h_8b_8b, "uaddl v2.8h, v11.8b, v29.8b", 2, 11, 29)
2728 GEN_THREEVEC_TEST(uaddl2_8h_16b_16b,
2729 "uaddl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
2730 GEN_THREEVEC_TEST(ssubl_2d_2s_2s, "ssubl v2.2d, v11.2s, v29.2s", 2, 11, 29)
2731 GEN_THREEVEC_TEST(ssubl2_2d_4s_4s, "ssubl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
2732 GEN_THREEVEC_TEST(ssubl_4s_4h_4h, "ssubl v2.4s, v11.4h, v29.4h", 2, 11, 29)
2733 GEN_THREEVEC_TEST(ssubl2_4s_8h_8h, "ssubl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
2734 GEN_THREEVEC_TEST(ssubl_8h_8b_8b, "ssubl v2.8h, v11.8b, v29.8b", 2, 11, 29)
2735 GEN_THREEVEC_TEST(ssubl2_8h_16b_16b,
2736 "ssubl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
2737 GEN_THREEVEC_TEST(usubl_2d_2s_2s, "usubl v2.2d, v11.2s, v29.2s", 2, 11, 29)
2738 GEN_THREEVEC_TEST(usubl2_2d_4s_4s, "usubl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
2739 GEN_THREEVEC_TEST(usubl_4s_4h_4h, "usubl v2.4s, v11.4h, v29.4h", 2, 11, 29)
2740 GEN_THREEVEC_TEST(usubl2_4s_8h_8h, "usubl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
2741 GEN_THREEVEC_TEST(usubl_8h_8b_8b, "usubl v2.8h, v11.8b, v29.8b", 2, 11, 29)
2742 GEN_THREEVEC_TEST(usubl2_8h_16b_16b,
2743 "usubl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
2744
2745 GEN_TWOVEC_TEST(saddlp_4h_8b, "saddlp v3.4h, v19.8b", 3, 19)
2746 GEN_TWOVEC_TEST(saddlp_8h_16b, "saddlp v3.8h, v19.16b", 3, 19)
2747 GEN_TWOVEC_TEST(saddlp_2s_4h, "saddlp v3.2s, v19.4h", 3, 19)
2748 GEN_TWOVEC_TEST(saddlp_4s_8h, "saddlp v3.4s, v19.8h", 3, 19)
2749 GEN_TWOVEC_TEST(saddlp_1d_2s, "saddlp v3.1d, v19.2s", 3, 19)
2750 GEN_TWOVEC_TEST(saddlp_2d_4s, "saddlp v3.2d, v19.4s", 3, 19)
2751 GEN_TWOVEC_TEST(uaddlp_4h_8b, "uaddlp v3.4h, v19.8b", 3, 19)
2752 GEN_TWOVEC_TEST(uaddlp_8h_16b, "uaddlp v3.8h, v19.16b", 3, 19)
2753 GEN_TWOVEC_TEST(uaddlp_2s_4h, "uaddlp v3.2s, v19.4h", 3, 19)
2754 GEN_TWOVEC_TEST(uaddlp_4s_8h, "uaddlp v3.4s, v19.8h", 3, 19)
2755 GEN_TWOVEC_TEST(uaddlp_1d_2s, "uaddlp v3.1d, v19.2s", 3, 19)
2756 GEN_TWOVEC_TEST(uaddlp_2d_4s, "uaddlp v3.2d, v19.4s", 3, 19)
2757
2758 GEN_TWOVEC_TEST(saddlv_h_16b, "saddlv h3, v19.16b", 3, 19)
2759 GEN_TWOVEC_TEST(saddlv_h_8b, "saddlv h3, v19.8b", 3, 19)
2760 GEN_TWOVEC_TEST(saddlv_s_8h, "saddlv s3, v19.8h", 3, 19)
2761 GEN_TWOVEC_TEST(saddlv_s_4h, "saddlv s3, v19.4h", 3, 19)
2762 GEN_TWOVEC_TEST(saddlv_d_4s, "saddlv d3, v19.4s", 3, 19)
2763 GEN_TWOVEC_TEST(uaddlv_h_16b, "uaddlv h3, v19.16b", 3, 19)
2764 GEN_TWOVEC_TEST(uaddlv_h_8b, "uaddlv h3, v19.8b", 3, 19)
2765 GEN_TWOVEC_TEST(uaddlv_s_8h, "uaddlv s3, v19.8h", 3, 19)
2766 GEN_TWOVEC_TEST(uaddlv_s_4h, "uaddlv s3, v19.4h", 3, 19)
2767 GEN_TWOVEC_TEST(uaddlv_d_4s, "uaddlv d3, v19.4s", 3, 19)
2768
2769 GEN_THREEVEC_TEST(saddw2_8h_8h_16b, "saddw2 v5.8h, v13.8h, v31.16b", 5, 13, 31)
2770 GEN_THREEVEC_TEST(saddw_8h_8h_8b, "saddw v5.8h, v13.8h, v31.8b", 5, 13, 31)
2771 GEN_THREEVEC_TEST(saddw2_4s_4s_8h, "saddw2 v5.4s, v13.4s, v31.8h", 5, 13, 31)
2772 GEN_THREEVEC_TEST(saddw_4s_4s_4h, "saddw v5.4s, v13.4s, v31.4h", 5, 13, 31)
2773 GEN_THREEVEC_TEST(saddw2_2d_2d_4s, "saddw2 v5.2d, v13.2d, v31.4s", 5, 13, 31)
2774 GEN_THREEVEC_TEST(saddw_2d_2d_2s, "saddw v5.2d, v13.2d, v31.2s", 5, 13, 31)
2775 GEN_THREEVEC_TEST(uaddw2_8h_8h_16b, "uaddw2 v5.8h, v13.8h, v31.16b", 5, 13, 31)
2776 GEN_THREEVEC_TEST(uaddw_8h_8h_8b, "uaddw v5.8h, v13.8h, v31.8b", 5, 13, 31)
2777 GEN_THREEVEC_TEST(uaddw2_4s_4s_8h, "uaddw2 v5.4s, v13.4s, v31.8h", 5, 13, 31)
2778 GEN_THREEVEC_TEST(uaddw_4s_4s_4h, "uaddw v5.4s, v13.4s, v31.4h", 5, 13, 31)
2779 GEN_THREEVEC_TEST(uaddw2_2d_2d_4s, "uaddw2 v5.2d, v13.2d, v31.4s", 5, 13, 31)
2780 GEN_THREEVEC_TEST(uaddw_2d_2d_2s, "uaddw v5.2d, v13.2d, v31.2s", 5, 13, 31)
2781 GEN_THREEVEC_TEST(ssubw2_8h_8h_16b, "ssubw2 v5.8h, v13.8h, v31.16b", 5, 13, 31)
2782 GEN_THREEVEC_TEST(ssubw_8h_8h_8b, "ssubw v5.8h, v13.8h, v31.8b", 5, 13, 31)
2783 GEN_THREEVEC_TEST(ssubw2_4s_4s_8h, "ssubw2 v5.4s, v13.4s, v31.8h", 5, 13, 31)
2784 GEN_THREEVEC_TEST(ssubw_4s_4s_4h, "ssubw v5.4s, v13.4s, v31.4h", 5, 13, 31)
2785 GEN_THREEVEC_TEST(ssubw2_2d_2d_4s, "ssubw2 v5.2d, v13.2d, v31.4s", 5, 13, 31)
2786 GEN_THREEVEC_TEST(ssubw_2d_2d_2s, "ssubw v5.2d, v13.2d, v31.2s", 5, 13, 31)
2787 GEN_THREEVEC_TEST(usubw2_8h_8h_16b, "usubw2 v5.8h, v13.8h, v31.16b", 5, 13, 31)
2788 GEN_THREEVEC_TEST(usubw_8h_8h_8b, "usubw v5.8h, v13.8h, v31.8b", 5, 13, 31)
2789 GEN_THREEVEC_TEST(usubw2_4s_4s_8h, "usubw2 v5.4s, v13.4s, v31.8h", 5, 13, 31)
2790 GEN_THREEVEC_TEST(usubw_4s_4s_4h, "usubw v5.4s, v13.4s, v31.4h", 5, 13, 31)
2791 GEN_THREEVEC_TEST(usubw2_2d_2d_4s, "usubw2 v5.2d, v13.2d, v31.4s", 5, 13, 31)
2792 GEN_THREEVEC_TEST(usubw_2d_2d_2s, "usubw v5.2d, v13.2d, v31.2s", 5, 13, 31)
2793
2794 GEN_THREEVEC_TEST(shadd_4s_4s_4s, "shadd v2.4s, v11.4s, v29.4s", 2, 11, 29)
2795 GEN_THREEVEC_TEST(shadd_2s_2s_2s, "shadd v2.2s, v11.2s, v29.2s", 2, 11, 29)
2796 GEN_THREEVEC_TEST(shadd_8h_8h_8h, "shadd v2.8h, v11.8h, v29.8h", 2, 11, 29)
2797 GEN_THREEVEC_TEST(shadd_4h_4h_4h, "shadd v2.4h, v11.4h, v29.4h", 2, 11, 29)
2798 GEN_THREEVEC_TEST(shadd_16b_16b_16b,"shadd v2.16b, v11.16b, v29.16b", 2, 11, 29)
2799 GEN_THREEVEC_TEST(shadd_8b_8b_8b, "shadd v2.8b, v11.8b, v29.8b", 2, 11, 29)
2800 GEN_THREEVEC_TEST(uhadd_4s_4s_4s, "uhadd v2.4s, v11.4s, v29.4s", 2, 11, 29)
2801 GEN_THREEVEC_TEST(uhadd_2s_2s_2s, "uhadd v2.2s, v11.2s, v29.2s", 2, 11, 29)
2802 GEN_THREEVEC_TEST(uhadd_8h_8h_8h, "uhadd v2.8h, v11.8h, v29.8h", 2, 11, 29)
2803 GEN_THREEVEC_TEST(uhadd_4h_4h_4h, "uhadd v2.4h, v11.4h, v29.4h", 2, 11, 29)
2804 GEN_THREEVEC_TEST(uhadd_16b_16b_16b,"uhadd v2.16b, v11.16b, v29.16b", 2, 11, 29)
2805 GEN_THREEVEC_TEST(uhadd_8b_8b_8b, "uhadd v2.8b, v11.8b, v29.8b", 2, 11, 29)
2806 GEN_THREEVEC_TEST(shsub_4s_4s_4s, "shsub v2.4s, v11.4s, v29.4s", 2, 11, 29)
2807 GEN_THREEVEC_TEST(shsub_2s_2s_2s, "shsub v2.2s, v11.2s, v29.2s", 2, 11, 29)
2808 GEN_THREEVEC_TEST(shsub_8h_8h_8h, "shsub v2.8h, v11.8h, v29.8h", 2, 11, 29)
2809 GEN_THREEVEC_TEST(shsub_4h_4h_4h, "shsub v2.4h, v11.4h, v29.4h", 2, 11, 29)
2810 GEN_THREEVEC_TEST(shsub_16b_16b_16b,"shsub v2.16b, v11.16b, v29.16b", 2, 11, 29)
2811 GEN_THREEVEC_TEST(shsub_8b_8b_8b, "shsub v2.8b, v11.8b, v29.8b", 2, 11, 29)
2812 GEN_THREEVEC_TEST(uhsub_4s_4s_4s, "uhsub v2.4s, v11.4s, v29.4s", 2, 11, 29)
2813 GEN_THREEVEC_TEST(uhsub_2s_2s_2s, "uhsub v2.2s, v11.2s, v29.2s", 2, 11, 29)
2814 GEN_THREEVEC_TEST(uhsub_8h_8h_8h, "uhsub v2.8h, v11.8h, v29.8h", 2, 11, 29)
2815 GEN_THREEVEC_TEST(uhsub_4h_4h_4h, "uhsub v2.4h, v11.4h, v29.4h", 2, 11, 29)
2816 GEN_THREEVEC_TEST(uhsub_16b_16b_16b,"uhsub v2.16b, v11.16b, v29.16b", 2, 11, 29)
2817 GEN_THREEVEC_TEST(uhsub_8b_8b_8b, "uhsub v2.8b, v11.8b, v29.8b", 2, 11, 29)
2818
2819 GEN_TWOVEC_TEST(shll_8h_8b_8, "shll v3.8h, v24.8b, #8", 3, 24)
2820 GEN_TWOVEC_TEST(shll2_8h_16b_8, "shll2 v3.8h, v24.16b, #8", 3, 24)
2821 GEN_TWOVEC_TEST(shll_4s_4h_16, "shll v3.4s, v24.4h, #16", 3, 24)
2822 GEN_TWOVEC_TEST(shll2_4s_8h_16, "shll2 v3.4s, v24.8h, #16", 3, 24)
2823 GEN_TWOVEC_TEST(shll_2d_2s_32, "shll v3.2d, v24.2s, #32", 3, 24)
2824 GEN_TWOVEC_TEST(shll2_2d_4s_32, "shll2 v3.2d, v24.4s, #32", 3, 24)
2825
2826 GEN_TWOVEC_TEST(shrn_2s_2d_1, "shrn v4.2s, v29.2d, #1", 4, 29)
2827 GEN_TWOVEC_TEST(shrn_2s_2d_32, "shrn v4.2s, v29.2d, #32", 4, 29)
2828 GEN_TWOVEC_TEST(shrn2_4s_2d_1, "shrn2 v4.4s, v29.2d, #1", 4, 29)
2829 GEN_TWOVEC_TEST(shrn2_4s_2d_32, "shrn2 v4.4s, v29.2d, #32", 4, 29)
2830 GEN_TWOVEC_TEST(shrn_4h_4s_1, "shrn v4.4h, v29.4s, #1", 4, 29)
2831 GEN_TWOVEC_TEST(shrn_4h_4s_16, "shrn v4.4h, v29.4s, #16", 4, 29)
2832 GEN_TWOVEC_TEST(shrn2_8h_4s_1, "shrn2 v4.8h, v29.4s, #1", 4, 29)
2833 GEN_TWOVEC_TEST(shrn2_8h_4s_16, "shrn2 v4.8h, v29.4s, #16", 4, 29)
2834 GEN_TWOVEC_TEST(shrn_8b_8h_1, "shrn v4.8b, v29.8h, #1", 4, 29)
2835 GEN_TWOVEC_TEST(shrn_8b_8h_8, "shrn v4.8b, v29.8h, #8", 4, 29)
2836 GEN_TWOVEC_TEST(shrn2_16b_8h_1, "shrn2 v4.16b, v29.8h, #1", 4, 29)
2837 GEN_TWOVEC_TEST(shrn2_16b_8h_8, "shrn2 v4.16b, v29.8h, #8", 4, 29)
2838 GEN_TWOVEC_TEST(rshrn_2s_2d_1, "rshrn v4.2s, v29.2d, #1", 4, 29)
2839 GEN_TWOVEC_TEST(rshrn_2s_2d_32, "rshrn v4.2s, v29.2d, #32", 4, 29)
2840 GEN_TWOVEC_TEST(rshrn2_4s_2d_1, "rshrn2 v4.4s, v29.2d, #1", 4, 29)
2841 GEN_TWOVEC_TEST(rshrn2_4s_2d_32, "rshrn2 v4.4s, v29.2d, #32", 4, 29)
2842 GEN_TWOVEC_TEST(rshrn_4h_4s_1, "rshrn v4.4h, v29.4s, #1", 4, 29)
2843 GEN_TWOVEC_TEST(rshrn_4h_4s_16, "rshrn v4.4h, v29.4s, #16", 4, 29)
2844 GEN_TWOVEC_TEST(rshrn2_8h_4s_1, "rshrn2 v4.8h, v29.4s, #1", 4, 29)
2845 GEN_TWOVEC_TEST(rshrn2_8h_4s_16, "rshrn2 v4.8h, v29.4s, #16", 4, 29)
2846 GEN_TWOVEC_TEST(rshrn_8b_8h_1, "rshrn v4.8b, v29.8h, #1", 4, 29)
2847 GEN_TWOVEC_TEST(rshrn_8b_8h_8, "rshrn v4.8b, v29.8h, #8", 4, 29)
2848 GEN_TWOVEC_TEST(rshrn2_16b_8h_1, "rshrn2 v4.16b, v29.8h, #1", 4, 29)
2849 GEN_TWOVEC_TEST(rshrn2_16b_8h_8, "rshrn2 v4.16b, v29.8h, #8", 4, 29)
2850
2851 GEN_TWOVEC_TEST(sli_d_d_0, "sli d5, d28, #0", 5, 28)
2852 GEN_TWOVEC_TEST(sli_d_d_32, "sli d5, d28, #32", 5, 28)
2853 GEN_TWOVEC_TEST(sli_d_d_63, "sli d5, d28, #63", 5, 28)
2854 GEN_TWOVEC_TEST(sri_d_d_1, "sri d5, d28, #1", 5, 28)
2855 GEN_TWOVEC_TEST(sri_d_d_33, "sri d5, d28, #33", 5, 28)
2856 GEN_TWOVEC_TEST(sri_d_d_64, "sri d5, d28, #64", 5, 28)
2857
2858 GEN_TWOVEC_TEST(sli_2d_2d_0, "sli v6.2d, v27.2d, #0", 6, 27)
2859 GEN_TWOVEC_TEST(sli_2d_2d_32, "sli v6.2d, v27.2d, #32", 6, 27)
2860 GEN_TWOVEC_TEST(sli_2d_2d_63, "sli v6.2d, v27.2d, #63", 6, 27)
2861 GEN_TWOVEC_TEST(sli_4s_4s_0, "sli v6.4s, v27.4s, #0", 6, 27)
2862 GEN_TWOVEC_TEST(sli_4s_4s_16, "sli v6.4s, v27.4s, #16", 6, 27)
2863 GEN_TWOVEC_TEST(sli_4s_4s_31, "sli v6.4s, v27.4s, #31", 6, 27)
2864 GEN_TWOVEC_TEST(sli_2s_2s_0, "sli v6.2s, v27.2s, #0", 6, 27)
2865 GEN_TWOVEC_TEST(sli_2s_2s_16, "sli v6.2s, v27.2s, #16", 6, 27)
2866 GEN_TWOVEC_TEST(sli_2s_2s_31, "sli v6.2s, v27.2s, #31", 6, 27)
2867 GEN_TWOVEC_TEST(sli_8h_8h_0, "sli v6.8h, v27.8h, #0", 6, 27)
2868 GEN_TWOVEC_TEST(sli_8h_8h_8, "sli v6.8h, v27.8h, #8", 6, 27)
2869 GEN_TWOVEC_TEST(sli_8h_8h_15, "sli v6.8h, v27.8h, #15", 6, 27)
2870 GEN_TWOVEC_TEST(sli_4h_4h_0, "sli v6.4h, v27.4h, #0", 6, 27)
2871 GEN_TWOVEC_TEST(sli_4h_4h_8, "sli v6.4h, v27.4h, #8", 6, 27)
2872 GEN_TWOVEC_TEST(sli_4h_4h_15, "sli v6.4h, v27.4h, #15", 6, 27)
2873 GEN_TWOVEC_TEST(sli_16b_16b_0, "sli v6.16b, v27.16b, #0", 6, 27)
2874 GEN_TWOVEC_TEST(sli_16b_16b_3, "sli v6.16b, v27.16b, #3", 6, 27)
2875 GEN_TWOVEC_TEST(sli_16b_16b_7, "sli v6.16b, v27.16b, #7", 6, 27)
2876 GEN_TWOVEC_TEST(sli_8b_8b_0, "sli v6.8b, v27.8b, #0", 6, 27)
2877 GEN_TWOVEC_TEST(sli_8b_8b_3, "sli v6.8b, v27.8b, #3", 6, 27)
2878 GEN_TWOVEC_TEST(sli_8b_8b_7, "sli v6.8b, v27.8b, #7", 6, 27)
2879 GEN_TWOVEC_TEST(sri_2d_2d_1, "sri v6.2d, v27.2d, #1", 6, 27)
2880 GEN_TWOVEC_TEST(sri_2d_2d_33, "sri v6.2d, v27.2d, #33", 6, 27)
2881 GEN_TWOVEC_TEST(sri_2d_2d_64, "sri v6.2d, v27.2d, #64", 6, 27)
2882 GEN_TWOVEC_TEST(sri_4s_4s_1, "sri v6.4s, v27.4s, #1", 6, 27)
2883 GEN_TWOVEC_TEST(sri_4s_4s_17, "sri v6.4s, v27.4s, #17", 6, 27)
2884 GEN_TWOVEC_TEST(sri_4s_4s_32, "sri v6.4s, v27.4s, #32", 6, 27)
2885 GEN_TWOVEC_TEST(sri_2s_2s_1, "sri v6.2s, v27.2s, #1", 6, 27)
2886 GEN_TWOVEC_TEST(sri_2s_2s_17, "sri v6.2s, v27.2s, #17", 6, 27)
2887 GEN_TWOVEC_TEST(sri_2s_2s_32, "sri v6.2s, v27.2s, #32", 6, 27)
2888 GEN_TWOVEC_TEST(sri_8h_8h_1, "sri v6.8h, v27.8h, #1", 6, 27)
2889 GEN_TWOVEC_TEST(sri_8h_8h_8, "sri v6.8h, v27.8h, #8", 6, 27)
2890 GEN_TWOVEC_TEST(sri_8h_8h_16, "sri v6.8h, v27.8h, #16", 6, 27)
2891 GEN_TWOVEC_TEST(sri_4h_4h_1, "sri v6.4h, v27.4h, #1", 6, 27)
2892 GEN_TWOVEC_TEST(sri_4h_4h_8, "sri v6.4h, v27.4h, #8", 6, 27)
2893 GEN_TWOVEC_TEST(sri_4h_4h_16, "sri v6.4h, v27.4h, #16", 6, 27)
2894 GEN_TWOVEC_TEST(sri_16b_16b_1, "sri v6.16b, v27.16b, #1", 6, 27)
2895 GEN_TWOVEC_TEST(sri_16b_16b_4, "sri v6.16b, v27.16b, #4", 6, 27)
2896 GEN_TWOVEC_TEST(sri_16b_16b_8, "sri v6.16b, v27.16b, #8", 6, 27)
2897 GEN_TWOVEC_TEST(sri_8b_8b_1, "sri v6.8b, v27.8b, #1", 6, 27)
2898 GEN_TWOVEC_TEST(sri_8b_8b_4, "sri v6.8b, v27.8b, #4", 6, 27)
2899 GEN_TWOVEC_TEST(sri_8b_8b_8, "sri v6.8b, v27.8b, #8", 6, 27)
2900
2901 GEN_BINARY_TEST(smax, 4s, 4s, 4s)
2902 GEN_BINARY_TEST(smax, 2s, 2s, 2s)
2903 GEN_BINARY_TEST(smax, 8h, 8h, 8h)
2904 GEN_BINARY_TEST(smax, 4h, 4h, 4h)
2905 GEN_BINARY_TEST(smax, 16b, 16b, 16b)
2906 GEN_BINARY_TEST(smax, 8b, 8b, 8b)
2907 GEN_BINARY_TEST(umax, 4s, 4s, 4s)
2908 GEN_BINARY_TEST(umax, 2s, 2s, 2s)
2909 GEN_BINARY_TEST(umax, 8h, 8h, 8h)
2910 GEN_BINARY_TEST(umax, 4h, 4h, 4h)
2911 GEN_BINARY_TEST(umax, 16b, 16b, 16b)
2912 GEN_BINARY_TEST(umax, 8b, 8b, 8b)
2913 GEN_BINARY_TEST(smin, 4s, 4s, 4s)
2914 GEN_BINARY_TEST(smin, 2s, 2s, 2s)
2915 GEN_BINARY_TEST(smin, 8h, 8h, 8h)
2916 GEN_BINARY_TEST(smin, 4h, 4h, 4h)
2917 GEN_BINARY_TEST(smin, 16b, 16b, 16b)
2918 GEN_BINARY_TEST(smin, 8b, 8b, 8b)
2919 GEN_BINARY_TEST(umin, 4s, 4s, 4s)
2920 GEN_BINARY_TEST(umin, 2s, 2s, 2s)
2921 GEN_BINARY_TEST(umin, 8h, 8h, 8h)
2922 GEN_BINARY_TEST(umin, 4h, 4h, 4h)
2923 GEN_BINARY_TEST(umin, 16b, 16b, 16b)
2924 GEN_BINARY_TEST(umin, 8b, 8b, 8b)
2925
2926 GEN_BINARY_TEST(smaxp, 4s, 4s, 4s)
2927 GEN_BINARY_TEST(smaxp, 2s, 2s, 2s)
2928 GEN_BINARY_TEST(smaxp, 8h, 8h, 8h)
2929 GEN_BINARY_TEST(smaxp, 4h, 4h, 4h)
2930 GEN_BINARY_TEST(smaxp, 16b, 16b, 16b)
2931 GEN_BINARY_TEST(smaxp, 8b, 8b, 8b)
2932 GEN_BINARY_TEST(umaxp, 4s, 4s, 4s)
2933 GEN_BINARY_TEST(umaxp, 2s, 2s, 2s)
2934 GEN_BINARY_TEST(umaxp, 8h, 8h, 8h)
2935 GEN_BINARY_TEST(umaxp, 4h, 4h, 4h)
2936 GEN_BINARY_TEST(umaxp, 16b, 16b, 16b)
2937 GEN_BINARY_TEST(umaxp, 8b, 8b, 8b)
2938 GEN_BINARY_TEST(sminp, 4s, 4s, 4s)
2939 GEN_BINARY_TEST(sminp, 2s, 2s, 2s)
2940 GEN_BINARY_TEST(sminp, 8h, 8h, 8h)
2941 GEN_BINARY_TEST(sminp, 4h, 4h, 4h)
2942 GEN_BINARY_TEST(sminp, 16b, 16b, 16b)
2943 GEN_BINARY_TEST(sminp, 8b, 8b, 8b)
2944 GEN_BINARY_TEST(uminp, 4s, 4s, 4s)
2945 GEN_BINARY_TEST(uminp, 2s, 2s, 2s)
2946 GEN_BINARY_TEST(uminp, 8h, 8h, 8h)
2947 GEN_BINARY_TEST(uminp, 4h, 4h, 4h)
2948 GEN_BINARY_TEST(uminp, 16b, 16b, 16b)
2949 GEN_BINARY_TEST(uminp, 8b, 8b, 8b)
2950
2951 // test_SMAXV is a handwritten function
2952 // test_UMAXV is a handwritten function
2953 // test_SMINV is a handwritten function
2954 // test_UMINV is a handwritten function
2955
2956 GEN_THREEVEC_TEST(smlal_2d_2s_s0, "smlal v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
2957 GEN_THREEVEC_TEST(smlal_2d_2s_s3, "smlal v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
2958 GEN_THREEVEC_TEST(smlal2_2d_4s_s1, "smlal2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3)
2959 GEN_THREEVEC_TEST(smlal2_2d_4s_s2, "smlal2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3)
2960 GEN_THREEVEC_TEST(smlal_4s_4h_h0, "smlal v29.4s, v20.4h, v3.h[0]", 29, 20, 3)
2961 GEN_THREEVEC_TEST(smlal_4s_4h_h7, "smlal v29.4s, v20.4h, v3.h[7]", 29, 20, 3)
2962 GEN_THREEVEC_TEST(smlal2_4s_8h_h1, "smlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
2963 GEN_THREEVEC_TEST(smlal2_4s_8h_h4, "smlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
2964 GEN_THREEVEC_TEST(umlal_2d_2s_s0, "umlal v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
2965 GEN_THREEVEC_TEST(umlal_2d_2s_s3, "umlal v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
2966 GEN_THREEVEC_TEST(umlal2_2d_4s_s1, "umlal2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3)
2967 GEN_THREEVEC_TEST(umlal2_2d_4s_s2, "umlal2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3)
2968 GEN_THREEVEC_TEST(umlal_4s_4h_h0, "umlal v29.4s, v20.4h, v3.h[0]", 29, 20, 3)
2969 GEN_THREEVEC_TEST(umlal_4s_4h_h7, "umlal v29.4s, v20.4h, v3.h[7]", 29, 20, 3)
2970 GEN_THREEVEC_TEST(umlal2_4s_8h_h1, "umlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
2971 GEN_THREEVEC_TEST(umlal2_4s_8h_h4, "umlal2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
2972 GEN_THREEVEC_TEST(smlsl_2d_2s_s0, "smlsl v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
2973 GEN_THREEVEC_TEST(smlsl_2d_2s_s3, "smlsl v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
2974 GEN_THREEVEC_TEST(smlsl2_2d_4s_s1, "smlsl2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3)
2975 GEN_THREEVEC_TEST(smlsl2_2d_4s_s2, "smlsl2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3)
2976 GEN_THREEVEC_TEST(smlsl_4s_4h_h0, "smlsl v29.4s, v20.4h, v3.h[0]", 29, 20, 3)
2977 GEN_THREEVEC_TEST(smlsl_4s_4h_h7, "smlsl v29.4s, v20.4h, v3.h[7]", 29, 20, 3)
2978 GEN_THREEVEC_TEST(smlsl2_4s_8h_h1, "smlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
2979 GEN_THREEVEC_TEST(smlsl2_4s_8h_h4, "smlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
2980 GEN_THREEVEC_TEST(umlsl_2d_2s_s0, "umlsl v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
2981 GEN_THREEVEC_TEST(umlsl_2d_2s_s3, "umlsl v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
2982 GEN_THREEVEC_TEST(umlsl2_2d_4s_s1, "umlsl2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3)
2983 GEN_THREEVEC_TEST(umlsl2_2d_4s_s2, "umlsl2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3)
2984 GEN_THREEVEC_TEST(umlsl_4s_4h_h0, "umlsl v29.4s, v20.4h, v3.h[0]", 29, 20, 3)
2985 GEN_THREEVEC_TEST(umlsl_4s_4h_h7, "umlsl v29.4s, v20.4h, v3.h[7]", 29, 20, 3)
2986 GEN_THREEVEC_TEST(umlsl2_4s_8h_h1, "umlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
2987 GEN_THREEVEC_TEST(umlsl2_4s_8h_h4, "umlsl2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
2988 GEN_THREEVEC_TEST(smull_2d_2s_s0, "smull v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
2989 GEN_THREEVEC_TEST(smull_2d_2s_s3, "smull v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
2990 GEN_THREEVEC_TEST(smull2_2d_4s_s1, "smull2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3)
2991 GEN_THREEVEC_TEST(smull2_2d_4s_s2, "smull2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3)
2992 GEN_THREEVEC_TEST(smull_4s_4h_h0, "smull v29.4s, v20.4h, v3.h[0]", 29, 20, 3)
2993 GEN_THREEVEC_TEST(smull_4s_4h_h7, "smull v29.4s, v20.4h, v3.h[7]", 29, 20, 3)
2994 GEN_THREEVEC_TEST(smull2_4s_8h_h1, "smull2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
2995 GEN_THREEVEC_TEST(smull2_4s_8h_h4, "smull2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
2996 GEN_THREEVEC_TEST(umull_2d_2s_s0, "umull v29.2d, v20.2s, v3.s[0]", 29, 20, 3)
2997 GEN_THREEVEC_TEST(umull_2d_2s_s3, "umull v29.2d, v20.2s, v3.s[3]", 29, 20, 3)
2998 GEN_THREEVEC_TEST(umull2_2d_4s_s1, "umull2 v29.2d, v20.4s, v3.s[1]", 29, 20, 3)
2999 GEN_THREEVEC_TEST(umull2_2d_4s_s2, "umull2 v29.2d, v20.4s, v3.s[2]", 29, 20, 3)
3000 GEN_THREEVEC_TEST(umull_4s_4h_h0, "umull v29.4s, v20.4h, v3.h[0]", 29, 20, 3)
3001 GEN_THREEVEC_TEST(umull_4s_4h_h7, "umull v29.4s, v20.4h, v3.h[7]", 29, 20, 3)
3002 GEN_THREEVEC_TEST(umull2_4s_8h_h1, "umull2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
3003 GEN_THREEVEC_TEST(umull2_4s_8h_h4, "umull2 v29.4s, v20.8h, v3.h[1]", 29, 20, 3)
3004
3005 GEN_THREEVEC_TEST(smlal_2d_2s_2s, "smlal v2.2d, v11.2s, v29.2s", 2, 11, 29)
3006 GEN_THREEVEC_TEST(smlal2_2d_4s_4s, "smlal2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
3007 GEN_THREEVEC_TEST(smlal_4s_4h_4h, "smlal v2.4s, v11.4h, v29.4h", 2, 11, 29)
3008 GEN_THREEVEC_TEST(smlal2_4s_8h_8h, "smlal2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
3009 GEN_THREEVEC_TEST(smlal_8h_8b_8b, "smlal v2.8h, v11.8b, v29.8b", 2, 11, 29)
3010 GEN_THREEVEC_TEST(smlal2_8h_16b_16b,
3011 "smlal2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
3012 GEN_THREEVEC_TEST(umlal_2d_2s_2s, "umlal v2.2d, v11.2s, v29.2s", 2, 11, 29)
3013 GEN_THREEVEC_TEST(umlal2_2d_4s_4s, "umlal2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
3014 GEN_THREEVEC_TEST(umlal_4s_4h_4h, "umlal v2.4s, v11.4h, v29.4h", 2, 11, 29)
3015 GEN_THREEVEC_TEST(umlal2_4s_8h_8h, "umlal2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
3016 GEN_THREEVEC_TEST(umlal_8h_8b_8b, "umlal v2.8h, v11.8b, v29.8b", 2, 11, 29)
3017 GEN_THREEVEC_TEST(umlal2_8h_16b_16b,
3018 "umlal2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
3019 GEN_THREEVEC_TEST(smlsl_2d_2s_2s, "smlsl v2.2d, v11.2s, v29.2s", 2, 11, 29)
3020 GEN_THREEVEC_TEST(smlsl2_2d_4s_4s, "smlsl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
3021 GEN_THREEVEC_TEST(smlsl_4s_4h_4h, "smlsl v2.4s, v11.4h, v29.4h", 2, 11, 29)
3022 GEN_THREEVEC_TEST(smlsl2_4s_8h_8h, "smlsl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
3023 GEN_THREEVEC_TEST(smlsl_8h_8b_8b, "smlsl v2.8h, v11.8b, v29.8b", 2, 11, 29)
3024 GEN_THREEVEC_TEST(smlsl2_8h_16b_16b,
3025 "smlsl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
3026 GEN_THREEVEC_TEST(umlsl_2d_2s_2s, "umlsl v2.2d, v11.2s, v29.2s", 2, 11, 29)
3027 GEN_THREEVEC_TEST(umlsl2_2d_4s_4s, "umlsl2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
3028 GEN_THREEVEC_TEST(umlsl_4s_4h_4h, "umlsl v2.4s, v11.4h, v29.4h", 2, 11, 29)
3029 GEN_THREEVEC_TEST(umlsl2_4s_8h_8h, "umlsl2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
3030 GEN_THREEVEC_TEST(umlsl_8h_8b_8b, "umlsl v2.8h, v11.8b, v29.8b", 2, 11, 29)
3031 GEN_THREEVEC_TEST(umlsl2_8h_16b_16b,
3032 "umlsl2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
3033 GEN_THREEVEC_TEST(smull_2d_2s_2s, "smull v2.2d, v11.2s, v29.2s", 2, 11, 29)
3034 GEN_THREEVEC_TEST(smull2_2d_4s_4s, "smull2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
3035 GEN_THREEVEC_TEST(smull_4s_4h_4h, "smull v2.4s, v11.4h, v29.4h", 2, 11, 29)
3036 GEN_THREEVEC_TEST(smull2_4s_8h_8h, "smull2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
3037 GEN_THREEVEC_TEST(smull_8h_8b_8b, "smull v2.8h, v11.8b, v29.8b", 2, 11, 29)
3038 GEN_THREEVEC_TEST(smull2_8h_16b_16b,
3039 "smull2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
3040 GEN_THREEVEC_TEST(umull_2d_2s_2s, "umull v2.2d, v11.2s, v29.2s", 2, 11, 29)
3041 GEN_THREEVEC_TEST(umull2_2d_4s_4s, "umull2 v2.2d, v11.4s, v29.4s", 2, 11, 29)
3042 GEN_THREEVEC_TEST(umull_4s_4h_4h, "umull v2.4s, v11.4h, v29.4h", 2, 11, 29)
3043 GEN_THREEVEC_TEST(umull2_4s_8h_8h, "umull2 v2.4s, v11.8h, v29.8h", 2, 11, 29)
3044 GEN_THREEVEC_TEST(umull_8h_8b_8b, "umull v2.8h, v11.8b, v29.8b", 2, 11, 29)
3045 GEN_THREEVEC_TEST(umull2_8h_16b_16b,
3046 "umull2 v2.8h, v11.16b, v29.16b", 2, 11, 29)
3047
3048 GEN_ONEINT_ONEVEC_TEST(umov_x_d0, "umov x9, v10.d[0]", 9, 10)
3049 GEN_ONEINT_ONEVEC_TEST(umov_x_d1, "umov x9, v10.d[1]", 9, 10)
3050 GEN_ONEINT_ONEVEC_TEST(umov_w_s0, "umov w9, v10.s[0]", 9, 10)
3051 GEN_ONEINT_ONEVEC_TEST(umov_w_s3, "umov w9, v10.s[3]", 9, 10)
3052 GEN_ONEINT_ONEVEC_TEST(umov_w_h0, "umov w9, v10.h[0]", 9, 10)
3053 GEN_ONEINT_ONEVEC_TEST(umov_w_h7, "umov w9, v10.h[7]", 9, 10)
3054 GEN_ONEINT_ONEVEC_TEST(umov_w_b0, "umov w9, v10.b[0]", 9, 10)
3055 GEN_ONEINT_ONEVEC_TEST(umov_w_b15, "umov w9, v10.b[15]", 9, 10)
3056 GEN_ONEINT_ONEVEC_TEST(smov_x_s0, "smov x9, v10.s[0]", 9, 10)
3057 GEN_ONEINT_ONEVEC_TEST(smov_x_s3, "smov x9, v10.s[3]", 9, 10)
3058 GEN_ONEINT_ONEVEC_TEST(smov_x_h0, "smov x9, v10.h[0]", 9, 10)
3059 GEN_ONEINT_ONEVEC_TEST(smov_x_h7, "smov x9, v10.h[7]", 9, 10)
3060 GEN_ONEINT_ONEVEC_TEST(smov_w_h0, "smov w9, v10.h[0]", 9, 10)
3061 GEN_ONEINT_ONEVEC_TEST(smov_w_h7, "smov w9, v10.h[7]", 9, 10)
3062 GEN_ONEINT_ONEVEC_TEST(smov_x_b0, "smov x9, v10.b[0]", 9, 10)
3063 GEN_ONEINT_ONEVEC_TEST(smov_x_b15, "smov x9, v10.b[15]", 9, 10)
3064 GEN_ONEINT_ONEVEC_TEST(smov_w_b0, "smov w9, v10.b[0]", 9, 10)
3065 GEN_ONEINT_ONEVEC_TEST(smov_w_b15, "smov w9, v10.b[15]", 9, 10)
3066
3067 GEN_TWOVEC_TEST(sqabs_d_d, "sqabs d7, d30", 7, 30)
3068 GEN_TWOVEC_TEST(sqabs_s_s, "sqabs s7, s30", 7, 30)
3069 GEN_TWOVEC_TEST(sqabs_h_h, "sqabs h7, h30", 7, 30)
3070 GEN_TWOVEC_TEST(sqabs_b_b, "sqabs b7, b30", 7, 30)
3071 GEN_TWOVEC_TEST(sqneg_d_d, "sqneg d7, d30", 7, 30)
3072 GEN_TWOVEC_TEST(sqneg_s_s, "sqneg s7, s30", 7, 30)
3073 GEN_TWOVEC_TEST(sqneg_h_h, "sqneg h7, h30", 7, 30)
3074 GEN_TWOVEC_TEST(sqneg_b_b, "sqneg b7, b30", 7, 30)
3075
3076 GEN_UNARY_TEST(sqabs, 2d, 2d)
3077 GEN_UNARY_TEST(sqabs, 4s, 4s)
3078 GEN_UNARY_TEST(sqabs, 2s, 2s)
3079 GEN_UNARY_TEST(sqabs, 8h, 8h)
3080 GEN_UNARY_TEST(sqabs, 4h, 4h)
3081 GEN_UNARY_TEST(sqabs, 16b, 16b)
3082 GEN_UNARY_TEST(sqabs, 8b, 8b)
3083 GEN_UNARY_TEST(sqneg, 2d, 2d)
3084 GEN_UNARY_TEST(sqneg, 4s, 4s)
3085 GEN_UNARY_TEST(sqneg, 2s, 2s)
3086 GEN_UNARY_TEST(sqneg, 8h, 8h)
3087 GEN_UNARY_TEST(sqneg, 4h, 4h)
3088 GEN_UNARY_TEST(sqneg, 16b, 16b)
3089 GEN_UNARY_TEST(sqneg, 8b, 8b)
3090
3091 GEN_THREEVEC_TEST(sqadd_d_d_d, "sqadd d1, d2, d4", 1, 2, 4)
3092 GEN_THREEVEC_TEST(sqadd_s_s_s, "sqadd s1, s2, s4", 1, 2, 4)
3093 GEN_THREEVEC_TEST(sqadd_h_h_h, "sqadd h1, h2, h4", 1, 2, 4)
3094 GEN_THREEVEC_TEST(sqadd_b_b_b, "sqadd b1, b2, b4", 1, 2, 4)
3095 GEN_THREEVEC_TEST(uqadd_d_d_d, "uqadd d1, d2, d4", 1, 2, 4)
3096 GEN_THREEVEC_TEST(uqadd_s_s_s, "uqadd s1, s2, s4", 1, 2, 4)
3097 GEN_THREEVEC_TEST(uqadd_h_h_h, "uqadd h1, h2, h4", 1, 2, 4)
3098 GEN_THREEVEC_TEST(uqadd_b_b_b, "uqadd b1, b2, b4", 1, 2, 4)
3099 GEN_THREEVEC_TEST(sqsub_d_d_d, "sqsub d1, d2, d4", 1, 2, 4)
3100 GEN_THREEVEC_TEST(sqsub_s_s_s, "sqsub s1, s2, s4", 1, 2, 4)
3101 GEN_THREEVEC_TEST(sqsub_h_h_h, "sqsub h1, h2, h4", 1, 2, 4)
3102 GEN_THREEVEC_TEST(sqsub_b_b_b, "sqsub b1, b2, b4", 1, 2, 4)
3103 GEN_THREEVEC_TEST(uqsub_d_d_d, "uqsub d1, d2, d4", 1, 2, 4)
3104 GEN_THREEVEC_TEST(uqsub_s_s_s, "uqsub s1, s2, s4", 1, 2, 4)
3105 GEN_THREEVEC_TEST(uqsub_h_h_h, "uqsub h1, h2, h4", 1, 2, 4)
3106 GEN_THREEVEC_TEST(uqsub_b_b_b, "uqsub b1, b2, b4", 1, 2, 4)
3107
3108 GEN_THREEVEC_TEST(sqadd_2d_2d_2d, "sqadd v1.2d, v2.2d, v4.2d", 1, 2, 4)
3109 GEN_THREEVEC_TEST(sqadd_4s_4s_4s, "sqadd v1.4s, v2.4s, v4.4s", 1, 2, 4)
3110 GEN_THREEVEC_TEST(sqadd_2s_2s_2s, "sqadd v1.2s, v2.2s, v4.2s", 1, 2, 4)
3111 GEN_THREEVEC_TEST(sqadd_8h_8h_8h, "sqadd v1.8h, v2.8h, v4.8h", 1, 2, 4)
3112 GEN_THREEVEC_TEST(sqadd_4h_4h_4h, "sqadd v1.4h, v2.4h, v4.4h", 1, 2, 4)
3113 GEN_THREEVEC_TEST(sqadd_16b_16b_16b, "sqadd v1.16b, v2.16b, v4.16b", 1, 2, 4)
3114 GEN_THREEVEC_TEST(sqadd_8b_8b_8b, "sqadd v1.8b, v2.8b, v4.8b", 1, 2, 4)
3115 GEN_THREEVEC_TEST(uqadd_2d_2d_2d, "uqadd v1.2d, v2.2d, v4.2d", 1, 2, 4)
3116 GEN_THREEVEC_TEST(uqadd_4s_4s_4s, "uqadd v1.4s, v2.4s, v4.4s", 1, 2, 4)
3117 GEN_THREEVEC_TEST(uqadd_2s_2s_2s, "uqadd v1.2s, v2.2s, v4.2s", 1, 2, 4)
3118 GEN_THREEVEC_TEST(uqadd_8h_8h_8h, "uqadd v1.8h, v2.8h, v4.8h", 1, 2, 4)
3119 GEN_THREEVEC_TEST(uqadd_4h_4h_4h, "uqadd v1.4h, v2.4h, v4.4h", 1, 2, 4)
3120 GEN_THREEVEC_TEST(uqadd_16b_16b_16b, "uqadd v1.16b, v2.16b, v4.16b", 1, 2, 4)
3121 GEN_THREEVEC_TEST(uqadd_8b_8b_8b, "uqadd v1.8b, v2.8b, v4.8b", 1, 2, 4)
3122 GEN_THREEVEC_TEST(sqsub_2d_2d_2d, "sqsub v1.2d, v2.2d, v4.2d", 1, 2, 4)
3123 GEN_THREEVEC_TEST(sqsub_4s_4s_4s, "sqsub v1.4s, v2.4s, v4.4s", 1, 2, 4)
3124 GEN_THREEVEC_TEST(sqsub_2s_2s_2s, "sqsub v1.2s, v2.2s, v4.2s", 1, 2, 4)
3125 GEN_THREEVEC_TEST(sqsub_8h_8h_8h, "sqsub v1.8h, v2.8h, v4.8h", 1, 2, 4)
3126 GEN_THREEVEC_TEST(sqsub_4h_4h_4h, "sqsub v1.4h, v2.4h, v4.4h", 1, 2, 4)
3127 GEN_THREEVEC_TEST(sqsub_16b_16b_16b, "sqsub v1.16b, v2.16b, v4.16b", 1, 2, 4)
3128 GEN_THREEVEC_TEST(sqsub_8b_8b_8b, "sqsub v1.8b, v2.8b, v4.8b", 1, 2, 4)
3129 GEN_THREEVEC_TEST(uqsub_2d_2d_2d, "uqsub v1.2d, v2.2d, v4.2d", 1, 2, 4)
3130 GEN_THREEVEC_TEST(uqsub_4s_4s_4s, "uqsub v1.4s, v2.4s, v4.4s", 1, 2, 4)
3131 GEN_THREEVEC_TEST(uqsub_2s_2s_2s, "uqsub v1.2s, v2.2s, v4.2s", 1, 2, 4)
3132 GEN_THREEVEC_TEST(uqsub_8h_8h_8h, "uqsub v1.8h, v2.8h, v4.8h", 1, 2, 4)
3133 GEN_THREEVEC_TEST(uqsub_4h_4h_4h, "uqsub v1.4h, v2.4h, v4.4h", 1, 2, 4)
3134 GEN_THREEVEC_TEST(uqsub_16b_16b_16b, "uqsub v1.16b, v2.16b, v4.16b", 1, 2, 4)
3135 GEN_THREEVEC_TEST(uqsub_8b_8b_8b, "uqsub v1.8b, v2.8b, v4.8b", 1, 2, 4)
3136
3137 GEN_THREEVEC_TEST(sqdmlal_d_s_s0, "sqdmlal d31, s30, v29.s[0]", 31,30,29)
3138 GEN_THREEVEC_TEST(sqdmlal_d_s_s3, "sqdmlal d31, s30, v29.s[3]", 31,30,29)
3139 GEN_THREEVEC_TEST(sqdmlal_s_h_h1, "sqdmlal s31, h30, v13.h[1]", 31,30,13)
3140 GEN_THREEVEC_TEST(sqdmlal_s_h_h5, "sqdmlal s31, h30, v13.h[5]", 31,30,13)
3141 GEN_THREEVEC_TEST(sqdmlsl_d_s_s0, "sqdmlsl d31, s30, v29.s[0]", 31,30,29)
3142 GEN_THREEVEC_TEST(sqdmlsl_d_s_s3, "sqdmlsl d31, s30, v29.s[3]", 31,30,29)
3143 GEN_THREEVEC_TEST(sqdmlsl_s_h_h1, "sqdmlsl s31, h30, v13.h[1]", 31,30,13)
3144 GEN_THREEVEC_TEST(sqdmlsl_s_h_h5, "sqdmlsl s31, h30, v13.h[5]", 31,30,13)
3145 GEN_THREEVEC_TEST(sqdmull_d_s_s0, "sqdmull d31, s30, v29.s[0]", 31,30,29)
3146 GEN_THREEVEC_TEST(sqdmull_d_s_s3, "sqdmull d31, s30, v29.s[3]", 31,30,29)
3147 GEN_THREEVEC_TEST(sqdmull_s_h_h1, "sqdmull s31, h30, v13.h[1]", 31,30,13)
3148 GEN_THREEVEC_TEST(sqdmull_s_h_h5, "sqdmull s31, h30, v13.h[5]", 31,30,13)
3149
3150 GEN_THREEVEC_TEST(sqdmlal_2d_2s_s0, "sqdmlal v29.2d, v20.2s, v3.s[0]",29,20,3)
3151 GEN_THREEVEC_TEST(sqdmlal_2d_2s_s3, "sqdmlal v29.2d, v20.2s, v3.s[3]",29,20,3)
3152 GEN_THREEVEC_TEST(sqdmlal2_2d_4s_s1,"sqdmlal2 v29.2d, v20.4s, v3.s[1]",29,20,3)
3153 GEN_THREEVEC_TEST(sqdmlal2_2d_4s_s2,"sqdmlal2 v29.2d, v20.4s, v3.s[2]",29,20,3)
3154 GEN_THREEVEC_TEST(sqdmlal_4s_4h_h0, "sqdmlal v29.4s, v20.4h, v3.h[0]",29,20,3)
3155 GEN_THREEVEC_TEST(sqdmlal_4s_4h_h7, "sqdmlal v29.4s, v20.4h, v3.h[7]",29,20,3)
3156 GEN_THREEVEC_TEST(sqdmlal2_4s_8h_h1,"sqdmlal2 v29.4s, v20.8h, v3.h[1]",29,20,3)
3157 GEN_THREEVEC_TEST(sqdmlal2_4s_8h_h4,"sqdmlal2 v29.4s, v20.8h, v3.h[1]",29,20,3)
3158 GEN_THREEVEC_TEST(sqdmlsl_2d_2s_s0, "sqdmlsl v29.2d, v20.2s, v3.s[0]",29,20,3)
3159 GEN_THREEVEC_TEST(sqdmlsl_2d_2s_s3, "sqdmlsl v29.2d, v20.2s, v3.s[3]",29,20,3)
3160 GEN_THREEVEC_TEST(sqdmlsl2_2d_4s_s1,"sqdmlsl2 v29.2d, v20.4s, v3.s[1]",29,20,3)
3161 GEN_THREEVEC_TEST(sqdmlsl2_2d_4s_s2,"sqdmlsl2 v29.2d, v20.4s, v3.s[2]",29,20,3)
3162 GEN_THREEVEC_TEST(sqdmlsl_4s_4h_h0, "sqdmlsl v29.4s, v20.4h, v3.h[0]",29,20,3)
3163 GEN_THREEVEC_TEST(sqdmlsl_4s_4h_h7, "sqdmlsl v29.4s, v20.4h, v3.h[7]",29,20,3)
3164 GEN_THREEVEC_TEST(sqdmlsl2_4s_8h_h1,"sqdmlsl2 v29.4s, v20.8h, v3.h[1]",29,20,3)
3165 GEN_THREEVEC_TEST(sqdmlsl2_4s_8h_h4,"sqdmlsl2 v29.4s, v20.8h, v3.h[1]",29,20,3)
3166 GEN_THREEVEC_TEST(sqdmull_2d_2s_s0, "sqdmull v29.2d, v20.2s, v3.s[0]",29,20,3)
3167 GEN_THREEVEC_TEST(sqdmull_2d_2s_s3, "sqdmull v29.2d, v20.2s, v3.s[3]",29,20,3)
3168 GEN_THREEVEC_TEST(sqdmull2_2d_4s_s1,"sqdmull2 v29.2d, v20.4s, v3.s[1]",29,20,3)
3169 GEN_THREEVEC_TEST(sqdmull2_2d_4s_s2,"sqdmull2 v29.2d, v20.4s, v3.s[2]",29,20,3)
3170 GEN_THREEVEC_TEST(sqdmull_4s_4h_h0, "sqdmull v29.4s, v20.4h, v3.h[0]",29,20,3)
3171 GEN_THREEVEC_TEST(sqdmull_4s_4h_h7, "sqdmull v29.4s, v20.4h, v3.h[7]",29,20,3)
3172 GEN_THREEVEC_TEST(sqdmull2_4s_8h_h1,"sqdmull2 v29.4s, v20.8h, v3.h[1]",29,20,3)
3173 GEN_THREEVEC_TEST(sqdmull2_4s_8h_h4,"sqdmull2 v29.4s, v20.8h, v3.h[1]",29,20,3)
3174
3175 GEN_THREEVEC_TEST(sqdmlal_d_s_s, "sqdmlal d0, s8, s16", 0, 8, 16)
3176 GEN_THREEVEC_TEST(sqdmlal_s_h_h, "sqdmlal s0, h8, h16", 0, 8, 16)
3177 GEN_THREEVEC_TEST(sqdmlsl_d_s_s, "sqdmlsl d0, s8, s16", 0, 8, 16)
3178 GEN_THREEVEC_TEST(sqdmlsl_s_h_h, "sqdmlsl s0, h8, h16", 0, 8, 16)
3179 GEN_THREEVEC_TEST(sqdmull_d_s_s, "sqdmull d0, s8, s16", 0, 8, 16)
3180 GEN_THREEVEC_TEST(sqdmull_s_h_h, "sqdmull s0, h8, h16", 0, 8, 16)
3181
3182 GEN_THREEVEC_TEST(sqdmlal_2d_2s_2s, "sqdmlal v2.2d, v11.2s, v29.2s", 2,11,29)
3183 GEN_THREEVEC_TEST(sqdmlal2_2d_4s_4s, "sqdmlal2 v2.2d, v11.4s, v29.4s", 2,11,29)
3184 GEN_THREEVEC_TEST(sqdmlal_4s_4h_4h, "sqdmlal v2.4s, v11.4h, v29.4h", 2,11,29)
3185 GEN_THREEVEC_TEST(sqdmlal2_4s_8h_8h, "sqdmlal2 v2.4s, v11.8h, v29.8h", 2,11,29)
3186 GEN_THREEVEC_TEST(sqdmlsl_2d_2s_2s, "sqdmlsl v2.2d, v11.2s, v29.2s", 2,11,29)
3187 GEN_THREEVEC_TEST(sqdmlsl2_2d_4s_4s, "sqdmlsl2 v2.2d, v11.4s, v29.4s", 2,11,29)
3188 GEN_THREEVEC_TEST(sqdmlsl_4s_4h_4h, "sqdmlsl v2.4s, v11.4h, v29.4h", 2,11,29)
3189 GEN_THREEVEC_TEST(sqdmlsl2_4s_8h_8h, "sqdmlsl2 v2.4s, v11.8h, v29.8h", 2,11,29)
3190 GEN_THREEVEC_TEST(sqdmull_2d_2s_2s, "sqdmull v2.2d, v11.2s, v29.2s", 2,11,29)
3191 GEN_THREEVEC_TEST(sqdmull2_2d_4s_4s, "sqdmull2 v2.2d, v11.4s, v29.4s", 2,11,29)
3192 GEN_THREEVEC_TEST(sqdmull_4s_4h_4h, "sqdmull v2.4s, v11.4h, v29.4h", 2,11,29)
3193 GEN_THREEVEC_TEST(sqdmull2_4s_8h_8h, "sqdmull2 v2.4s, v11.8h, v29.8h", 2,11,29)
3194
3195 GEN_THREEVEC_TEST(sqdmulh_s_s_s1, "sqdmulh s0, s1, v2.s[1]", 0,1,2)
3196 GEN_THREEVEC_TEST(sqdmulh_s_s_s3, "sqdmulh s0, s1, v2.s[3]", 0,1,2)
3197 GEN_THREEVEC_TEST(sqdmulh_h_h_h2, "sqdmulh h0, h1, v2.h[2]", 0,1,2)
3198 GEN_THREEVEC_TEST(sqdmulh_h_h_h7, "sqdmulh h0, h1, v2.h[7]", 0,1,2)
3199 GEN_THREEVEC_TEST(sqrdmulh_s_s_s1, "sqrdmulh s0, s1, v2.s[1]", 0,1,2)
3200 GEN_THREEVEC_TEST(sqrdmulh_s_s_s3, "sqrdmulh s0, s1, v2.s[3]", 0,1,2)
3201 GEN_THREEVEC_TEST(sqrdmulh_h_h_h2, "sqrdmulh h0, h1, v2.h[2]", 0,1,2)
3202 GEN_THREEVEC_TEST(sqrdmulh_h_h_h7, "sqrdmulh h0, h1, v2.h[7]", 0,1,2)
3203
3204 GEN_THREEVEC_TEST(sqdmulh_4s_4s_s1, "sqdmulh v0.4s, v1.4s, v2.s[1]", 0,1,2)
3205 GEN_THREEVEC_TEST(sqdmulh_4s_4s_s3, "sqdmulh v0.4s, v1.4s, v2.s[3]", 0,1,2)
3206 GEN_THREEVEC_TEST(sqdmulh_2s_2s_s1, "sqdmulh v0.2s, v1.2s, v2.s[1]", 0,1,2)
3207 GEN_THREEVEC_TEST(sqdmulh_2s_2s_s3, "sqdmulh v0.2s, v1.2s, v2.s[3]", 0,1,2)
3208 GEN_THREEVEC_TEST(sqdmulh_8h_8h_h2, "sqdmulh v0.8h, v1.8h, v2.h[2]", 0,1,2)
3209 GEN_THREEVEC_TEST(sqdmulh_8h_8h_h7, "sqdmulh v0.8h, v1.8h, v2.h[7]", 0,1,2)
3210 GEN_THREEVEC_TEST(sqdmulh_4h_4h_h2, "sqdmulh v0.4h, v1.4h, v2.h[2]", 0,1,2)
3211 GEN_THREEVEC_TEST(sqdmulh_4h_4h_h7, "sqdmulh v0.4h, v1.4h, v2.h[7]", 0,1,2)
3212 GEN_THREEVEC_TEST(sqrdmulh_4s_4s_s1, "sqrdmulh v0.4s, v1.4s, v2.s[1]", 0,1,2)
3213 GEN_THREEVEC_TEST(sqrdmulh_4s_4s_s3, "sqrdmulh v0.4s, v1.4s, v2.s[3]", 0,1,2)
3214 GEN_THREEVEC_TEST(sqrdmulh_2s_2s_s1, "sqrdmulh v0.2s, v1.2s, v2.s[1]", 0,1,2)
3215 GEN_THREEVEC_TEST(sqrdmulh_2s_2s_s3, "sqrdmulh v0.2s, v1.2s, v2.s[3]", 0,1,2)
3216 GEN_THREEVEC_TEST(sqrdmulh_8h_8h_h2, "sqrdmulh v0.8h, v1.8h, v2.h[2]", 0,1,2)
3217 GEN_THREEVEC_TEST(sqrdmulh_8h_8h_h7, "sqrdmulh v0.8h, v1.8h, v2.h[7]", 0,1,2)
3218 GEN_THREEVEC_TEST(sqrdmulh_4h_4h_h2, "sqrdmulh v0.4h, v1.4h, v2.h[2]", 0,1,2)
3219 GEN_THREEVEC_TEST(sqrdmulh_4h_4h_h7, "sqrdmulh v0.4h, v1.4h, v2.h[7]", 0,1,2)
3220
3221 GEN_THREEVEC_TEST(sqdmulh_s_s_s, "sqdmulh s1, s2, s4", 1, 2, 4)
3222 GEN_THREEVEC_TEST(sqdmulh_h_h_h, "sqdmulh h1, h2, h4", 1, 2, 4)
3223 GEN_THREEVEC_TEST(sqrdmulh_s_s_s, "sqrdmulh s1, s2, s4", 1, 2, 4)
3224 GEN_THREEVEC_TEST(sqrdmulh_h_h_h, "sqrdmulh h1, h2, h4", 1, 2, 4)
3225
3226 GEN_THREEVEC_TEST(sqdmulh_4s_4s_4s, "sqdmulh v1.4s, v2.4s, v4.4s", 1, 2, 4)
3227 GEN_THREEVEC_TEST(sqdmulh_2s_2s_2s, "sqdmulh v1.2s, v2.2s, v4.2s", 1, 2, 4)
3228 GEN_THREEVEC_TEST(sqdmulh_8h_8h_8h, "sqdmulh v1.8h, v2.8h, v4.8h", 1, 2, 4)
3229 GEN_THREEVEC_TEST(sqdmulh_4h_4h_4h, "sqdmulh v1.4h, v2.4h, v4.4h", 1, 2, 4)
3230 GEN_THREEVEC_TEST(sqrdmulh_4s_4s_4s, "sqrdmulh v1.4s, v2.4s, v4.4s", 1, 2, 4)
3231 GEN_THREEVEC_TEST(sqrdmulh_2s_2s_2s, "sqrdmulh v1.2s, v2.2s, v4.2s", 1, 2, 4)
3232 GEN_THREEVEC_TEST(sqrdmulh_8h_8h_8h, "sqrdmulh v1.8h, v2.8h, v4.8h", 1, 2, 4)
3233 GEN_THREEVEC_TEST(sqrdmulh_4h_4h_4h, "sqrdmulh v1.4h, v2.4h, v4.4h", 1, 2, 4)
3234
3235 GEN_THREEVEC_TEST(sqshl_d_d_d, "sqshl d1, d2, d4", 1, 2, 4)
3236 GEN_THREEVEC_TEST(sqshl_s_s_s, "sqshl s1, s2, s4", 1, 2, 4)
3237 GEN_THREEVEC_TEST(sqshl_h_h_h, "sqshl h1, h2, h4", 1, 2, 4)
3238 GEN_THREEVEC_TEST(sqshl_b_b_b, "sqshl b1, b2, b4", 1, 2, 4)
3239 GEN_THREEVEC_TEST(uqshl_d_d_d, "uqshl d1, d2, d4", 1, 2, 4)
3240 GEN_THREEVEC_TEST(uqshl_s_s_s, "uqshl s1, s2, s4", 1, 2, 4)
3241 GEN_THREEVEC_TEST(uqshl_h_h_h, "uqshl h1, h2, h4", 1, 2, 4)
3242 GEN_THREEVEC_TEST(uqshl_b_b_b, "uqshl b1, b2, b4", 1, 2, 4)
3243 GEN_THREEVEC_TEST(sqrshl_d_d_d, "sqrshl d1, d2, d4", 1, 2, 4)
3244 GEN_THREEVEC_TEST(sqrshl_s_s_s, "sqrshl s1, s2, s4", 1, 2, 4)
3245 GEN_THREEVEC_TEST(sqrshl_h_h_h, "sqrshl h1, h2, h4", 1, 2, 4)
3246 GEN_THREEVEC_TEST(sqrshl_b_b_b, "sqrshl b1, b2, b4", 1, 2, 4)
3247 GEN_THREEVEC_TEST(uqrshl_d_d_d, "uqrshl d1, d2, d4", 1, 2, 4)
3248 GEN_THREEVEC_TEST(uqrshl_s_s_s, "uqrshl s1, s2, s4", 1, 2, 4)
3249 GEN_THREEVEC_TEST(uqrshl_h_h_h, "uqrshl h1, h2, h4", 1, 2, 4)
3250 GEN_THREEVEC_TEST(uqrshl_b_b_b, "uqrshl b1, b2, b4", 1, 2, 4)
3251
3252 GEN_THREEVEC_TEST(sqshl_2d_2d_2d, "sqshl v1.2d, v2.2d, v4.2d", 1, 2, 4)
3253 GEN_THREEVEC_TEST(sqshl_4s_4s_4s, "sqshl v1.4s, v2.4s, v4.4s", 1, 2, 4)
3254 GEN_THREEVEC_TEST(sqshl_2s_2s_2s, "sqshl v1.2s, v2.2s, v4.2s", 1, 2, 4)
3255 GEN_THREEVEC_TEST(sqshl_8h_8h_8h, "sqshl v1.8h, v2.8h, v4.8h", 1, 2, 4)
3256 GEN_THREEVEC_TEST(sqshl_4h_4h_4h, "sqshl v1.4h, v2.4h, v4.4h", 1, 2, 4)
3257 GEN_THREEVEC_TEST(sqshl_16b_16b_16b, "sqshl v1.16b, v2.16b, v4.16b", 1, 2, 4)
3258 GEN_THREEVEC_TEST(sqshl_8b_8b_8b, "sqshl v1.8b, v2.8b, v4.8b", 1, 2, 4)
3259 GEN_THREEVEC_TEST(uqshl_2d_2d_2d, "uqshl v1.2d, v2.2d, v4.2d", 1, 2, 4)
3260 GEN_THREEVEC_TEST(uqshl_4s_4s_4s, "uqshl v1.4s, v2.4s, v4.4s", 1, 2, 4)
3261 GEN_THREEVEC_TEST(uqshl_2s_2s_2s, "uqshl v1.2s, v2.2s, v4.2s", 1, 2, 4)
3262 GEN_THREEVEC_TEST(uqshl_8h_8h_8h, "uqshl v1.8h, v2.8h, v4.8h", 1, 2, 4)
3263 GEN_THREEVEC_TEST(uqshl_4h_4h_4h, "uqshl v1.4h, v2.4h, v4.4h", 1, 2, 4)
3264 GEN_THREEVEC_TEST(uqshl_16b_16b_16b, "uqshl v1.16b, v2.16b, v4.16b", 1, 2, 4)
3265 GEN_THREEVEC_TEST(uqshl_8b_8b_8b, "uqshl v1.8b, v2.8b, v4.8b", 1, 2, 4)
3266 GEN_THREEVEC_TEST(sqrshl_2d_2d_2d, "sqrshl v1.2d, v2.2d, v4.2d", 1, 2, 4)
3267 GEN_THREEVEC_TEST(sqrshl_4s_4s_4s, "sqrshl v1.4s, v2.4s, v4.4s", 1, 2, 4)
3268 GEN_THREEVEC_TEST(sqrshl_2s_2s_2s, "sqrshl v1.2s, v2.2s, v4.2s", 1, 2, 4)
3269 GEN_THREEVEC_TEST(sqrshl_8h_8h_8h, "sqrshl v1.8h, v2.8h, v4.8h", 1, 2, 4)
3270 GEN_THREEVEC_TEST(sqrshl_4h_4h_4h, "sqrshl v1.4h, v2.4h, v4.4h", 1, 2, 4)
3271 GEN_THREEVEC_TEST(sqrshl_16b_16b_16b, "sqrshl v1.16b, v2.16b, v4.16b", 1, 2, 4)
3272 GEN_THREEVEC_TEST(sqrshl_8b_8b_8b, "sqrshl v1.8b, v2.8b, v4.8b", 1, 2, 4)
3273 GEN_THREEVEC_TEST(uqrshl_2d_2d_2d, "uqrshl v1.2d, v2.2d, v4.2d", 1, 2, 4)
3274 GEN_THREEVEC_TEST(uqrshl_4s_4s_4s, "uqrshl v1.4s, v2.4s, v4.4s", 1, 2, 4)
3275 GEN_THREEVEC_TEST(uqrshl_2s_2s_2s, "uqrshl v1.2s, v2.2s, v4.2s", 1, 2, 4)
3276 GEN_THREEVEC_TEST(uqrshl_8h_8h_8h, "uqrshl v1.8h, v2.8h, v4.8h", 1, 2, 4)
3277 GEN_THREEVEC_TEST(uqrshl_4h_4h_4h, "uqrshl v1.4h, v2.4h, v4.4h", 1, 2, 4)
3278 GEN_THREEVEC_TEST(uqrshl_16b_16b_16b, "uqrshl v1.16b, v2.16b, v4.16b", 1, 2, 4)
3279 GEN_THREEVEC_TEST(uqrshl_8b_8b_8b, "uqrshl v1.8b, v2.8b, v4.8b", 1, 2, 4)
3280
3281 GEN_TWOVEC_TEST(sqrshrn_s_d_1, "sqrshrn s2, d5, #1", 2, 5)
3282 GEN_TWOVEC_TEST(sqrshrn_s_d_17, "sqrshrn s2, d5, #17", 2, 5)
3283 GEN_TWOVEC_TEST(sqrshrn_s_d_32, "sqrshrn s2, d5, #32", 2, 5)
3284 GEN_TWOVEC_TEST(sqrshrn_h_s_1, "sqrshrn h2, s5, #1", 2, 5)
3285 GEN_TWOVEC_TEST(sqrshrn_h_s_9, "sqrshrn h2, s5, #9", 2, 5)
3286 GEN_TWOVEC_TEST(sqrshrn_h_s_16, "sqrshrn h2, s5, #16", 2, 5)
3287 GEN_TWOVEC_TEST(sqrshrn_b_h_1, "sqrshrn b2, h5, #1", 2, 5)
3288 GEN_TWOVEC_TEST(sqrshrn_b_h_4, "sqrshrn b2, h5, #4", 2, 5)
3289 GEN_TWOVEC_TEST(sqrshrn_b_h_8, "sqrshrn b2, h5, #8", 2, 5)
3290 GEN_TWOVEC_TEST(uqrshrn_s_d_1, "uqrshrn s2, d5, #1", 2, 5)
3291 GEN_TWOVEC_TEST(uqrshrn_s_d_17, "uqrshrn s2, d5, #17", 2, 5)
3292 GEN_TWOVEC_TEST(uqrshrn_s_d_32, "uqrshrn s2, d5, #32", 2, 5)
3293 GEN_TWOVEC_TEST(uqrshrn_h_s_1, "uqrshrn h2, s5, #1", 2, 5)
3294 GEN_TWOVEC_TEST(uqrshrn_h_s_9, "uqrshrn h2, s5, #9", 2, 5)
3295 GEN_TWOVEC_TEST(uqrshrn_h_s_16, "uqrshrn h2, s5, #16", 2, 5)
3296 GEN_TWOVEC_TEST(uqrshrn_b_h_1, "uqrshrn b2, h5, #1", 2, 5)
3297 GEN_TWOVEC_TEST(uqrshrn_b_h_4, "uqrshrn b2, h5, #4", 2, 5)
3298 GEN_TWOVEC_TEST(uqrshrn_b_h_8, "uqrshrn b2, h5, #8", 2, 5)
3299 GEN_TWOVEC_TEST(sqshrn_s_d_1, "sqshrn s2, d5, #1", 2, 5)
3300 GEN_TWOVEC_TEST(sqshrn_s_d_17, "sqshrn s2, d5, #17", 2, 5)
3301 GEN_TWOVEC_TEST(sqshrn_s_d_32, "sqshrn s2, d5, #32", 2, 5)
3302 GEN_TWOVEC_TEST(sqshrn_h_s_1, "sqshrn h2, s5, #1", 2, 5)
3303 GEN_TWOVEC_TEST(sqshrn_h_s_9, "sqshrn h2, s5, #9", 2, 5)
3304 GEN_TWOVEC_TEST(sqshrn_h_s_16, "sqshrn h2, s5, #16", 2, 5)
3305 GEN_TWOVEC_TEST(sqshrn_b_h_1, "sqshrn b2, h5, #1", 2, 5)
3306 GEN_TWOVEC_TEST(sqshrn_b_h_4, "sqshrn b2, h5, #4", 2, 5)
3307 GEN_TWOVEC_TEST(sqshrn_b_h_8, "sqshrn b2, h5, #8", 2, 5)
3308 GEN_TWOVEC_TEST(uqshrn_s_d_1, "uqshrn s2, d5, #1", 2, 5)
3309 GEN_TWOVEC_TEST(uqshrn_s_d_17, "uqshrn s2, d5, #17", 2, 5)
3310 GEN_TWOVEC_TEST(uqshrn_s_d_32, "uqshrn s2, d5, #32", 2, 5)
3311 GEN_TWOVEC_TEST(uqshrn_h_s_1, "uqshrn h2, s5, #1", 2, 5)
3312 GEN_TWOVEC_TEST(uqshrn_h_s_9, "uqshrn h2, s5, #9", 2, 5)
3313 GEN_TWOVEC_TEST(uqshrn_h_s_16, "uqshrn h2, s5, #16", 2, 5)
3314 GEN_TWOVEC_TEST(uqshrn_b_h_1, "uqshrn b2, h5, #1", 2, 5)
3315 GEN_TWOVEC_TEST(uqshrn_b_h_4, "uqshrn b2, h5, #4", 2, 5)
3316 GEN_TWOVEC_TEST(uqshrn_b_h_8, "uqshrn b2, h5, #8", 2, 5)
3317 GEN_TWOVEC_TEST(sqrshrun_s_d_1, "sqrshrun s2, d5, #1", 2, 5)
3318 GEN_TWOVEC_TEST(sqrshrun_s_d_17, "sqrshrun s2, d5, #17", 2, 5)
3319 GEN_TWOVEC_TEST(sqrshrun_s_d_32, "sqrshrun s2, d5, #32", 2, 5)
3320 GEN_TWOVEC_TEST(sqrshrun_h_s_1, "sqrshrun h2, s5, #1", 2, 5)
3321 GEN_TWOVEC_TEST(sqrshrun_h_s_9, "sqrshrun h2, s5, #9", 2, 5)
3322 GEN_TWOVEC_TEST(sqrshrun_h_s_16, "sqrshrun h2, s5, #16", 2, 5)
3323 GEN_TWOVEC_TEST(sqrshrun_b_h_1, "sqrshrun b2, h5, #1", 2, 5)
3324 GEN_TWOVEC_TEST(sqrshrun_b_h_4, "sqrshrun b2, h5, #4", 2, 5)
3325 GEN_TWOVEC_TEST(sqrshrun_b_h_8, "sqrshrun b2, h5, #8", 2, 5)
3326 GEN_TWOVEC_TEST(sqshrun_s_d_1, "sqshrun s2, d5, #1", 2, 5)
3327 GEN_TWOVEC_TEST(sqshrun_s_d_17, "sqshrun s2, d5, #17", 2, 5)
3328 GEN_TWOVEC_TEST(sqshrun_s_d_32, "sqshrun s2, d5, #32", 2, 5)
3329 GEN_TWOVEC_TEST(sqshrun_h_s_1, "sqshrun h2, s5, #1", 2, 5)
3330 GEN_TWOVEC_TEST(sqshrun_h_s_9, "sqshrun h2, s5, #9", 2, 5)
3331 GEN_TWOVEC_TEST(sqshrun_h_s_16, "sqshrun h2, s5, #16", 2, 5)
3332 GEN_TWOVEC_TEST(sqshrun_b_h_1, "sqshrun b2, h5, #1", 2, 5)
3333 GEN_TWOVEC_TEST(sqshrun_b_h_4, "sqshrun b2, h5, #4", 2, 5)
3334 GEN_TWOVEC_TEST(sqshrun_b_h_8, "sqshrun b2, h5, #8", 2, 5)
3335
3336 GEN_TWOVEC_TEST(sqrshrn_2s_2d_1, "sqrshrn v4.2s, v29.2d, #1", 4, 29)
3337 GEN_TWOVEC_TEST(sqrshrn_2s_2d_17, "sqrshrn v4.2s, v29.2d, #17", 4, 29)
3338 GEN_TWOVEC_TEST(sqrshrn_2s_2d_32, "sqrshrn v4.2s, v29.2d, #32", 4, 29)
3339 GEN_TWOVEC_TEST(sqrshrn2_4s_2d_1, "sqrshrn2 v4.4s, v29.2d, #1", 4, 29)
3340 GEN_TWOVEC_TEST(sqrshrn2_4s_2d_17, "sqrshrn2 v4.4s, v29.2d, #17", 4, 29)
3341 GEN_TWOVEC_TEST(sqrshrn2_4s_2d_32, "sqrshrn2 v4.4s, v29.2d, #32", 4, 29)
3342 GEN_TWOVEC_TEST(sqrshrn_4h_4s_1, "sqrshrn v4.4h, v29.4s, #1", 4, 29)
3343 GEN_TWOVEC_TEST(sqrshrn_4h_4s_9, "sqrshrn v4.4h, v29.4s, #9", 4, 29)
3344 GEN_TWOVEC_TEST(sqrshrn_4h_4s_16, "sqrshrn v4.4h, v29.4s, #16", 4, 29)
3345 GEN_TWOVEC_TEST(sqrshrn2_8h_4s_1, "sqrshrn2 v4.8h, v29.4s, #1", 4, 29)
3346 GEN_TWOVEC_TEST(sqrshrn2_8h_4s_9, "sqrshrn2 v4.8h, v29.4s, #9", 4, 29)
3347 GEN_TWOVEC_TEST(sqrshrn2_8h_4s_16, "sqrshrn2 v4.8h, v29.4s, #16", 4, 29)
3348 GEN_TWOVEC_TEST(sqrshrn_8b_8h_1, "sqrshrn v4.8b, v29.8h, #1", 4, 29)
3349 GEN_TWOVEC_TEST(sqrshrn_8b_8h_4, "sqrshrn v4.8b, v29.8h, #4", 4, 29)
3350 GEN_TWOVEC_TEST(sqrshrn_8b_8h_8, "sqrshrn v4.8b, v29.8h, #8", 4, 29)
3351 GEN_TWOVEC_TEST(sqrshrn2_16b_8h_1, "sqrshrn2 v4.16b, v29.8h, #1", 4, 29)
3352 GEN_TWOVEC_TEST(sqrshrn2_16b_8h_4, "sqrshrn2 v4.16b, v29.8h, #4", 4, 29)
3353 GEN_TWOVEC_TEST(sqrshrn2_16b_8h_8, "sqrshrn2 v4.16b, v29.8h, #8", 4, 29)
3354 GEN_TWOVEC_TEST(uqrshrn_2s_2d_1, "uqrshrn v4.2s, v29.2d, #1", 4, 29)
3355 GEN_TWOVEC_TEST(uqrshrn_2s_2d_17, "uqrshrn v4.2s, v29.2d, #17", 4, 29)
3356 GEN_TWOVEC_TEST(uqrshrn_2s_2d_32, "uqrshrn v4.2s, v29.2d, #32", 4, 29)
3357 GEN_TWOVEC_TEST(uqrshrn2_4s_2d_1, "uqrshrn2 v4.4s, v29.2d, #1", 4, 29)
3358 GEN_TWOVEC_TEST(uqrshrn2_4s_2d_17, "uqrshrn2 v4.4s, v29.2d, #17", 4, 29)
3359 GEN_TWOVEC_TEST(uqrshrn2_4s_2d_32, "uqrshrn2 v4.4s, v29.2d, #32", 4, 29)
3360 GEN_TWOVEC_TEST(uqrshrn_4h_4s_1, "uqrshrn v4.4h, v29.4s, #1", 4, 29)
3361 GEN_TWOVEC_TEST(uqrshrn_4h_4s_9, "uqrshrn v4.4h, v29.4s, #9", 4, 29)
3362 GEN_TWOVEC_TEST(uqrshrn_4h_4s_16, "uqrshrn v4.4h, v29.4s, #16", 4, 29)
3363 GEN_TWOVEC_TEST(uqrshrn2_8h_4s_1, "uqrshrn2 v4.8h, v29.4s, #1", 4, 29)
3364 GEN_TWOVEC_TEST(uqrshrn2_8h_4s_9, "uqrshrn2 v4.8h, v29.4s, #9", 4, 29)
3365 GEN_TWOVEC_TEST(uqrshrn2_8h_4s_16, "uqrshrn2 v4.8h, v29.4s, #16", 4, 29)
3366 GEN_TWOVEC_TEST(uqrshrn_8b_8h_1, "uqrshrn v4.8b, v29.8h, #1", 4, 29)
3367 GEN_TWOVEC_TEST(uqrshrn_8b_8h_4, "uqrshrn v4.8b, v29.8h, #4", 4, 29)
3368 GEN_TWOVEC_TEST(uqrshrn_8b_8h_8, "uqrshrn v4.8b, v29.8h, #8", 4, 29)
3369 GEN_TWOVEC_TEST(uqrshrn2_16b_8h_1, "uqrshrn2 v4.16b, v29.8h, #1", 4, 29)
3370 GEN_TWOVEC_TEST(uqrshrn2_16b_8h_4, "uqrshrn2 v4.16b, v29.8h, #4", 4, 29)
3371 GEN_TWOVEC_TEST(uqrshrn2_16b_8h_8, "uqrshrn2 v4.16b, v29.8h, #8", 4, 29)
3372 GEN_TWOVEC_TEST(sqshrn_2s_2d_1, "sqshrn v4.2s, v29.2d, #1", 4, 29)
3373 GEN_TWOVEC_TEST(sqshrn_2s_2d_17, "sqshrn v4.2s, v29.2d, #17", 4, 29)
3374 GEN_TWOVEC_TEST(sqshrn_2s_2d_32, "sqshrn v4.2s, v29.2d, #32", 4, 29)
3375 GEN_TWOVEC_TEST(sqshrn2_4s_2d_1, "sqshrn2 v4.4s, v29.2d, #1", 4, 29)
3376 GEN_TWOVEC_TEST(sqshrn2_4s_2d_17, "sqshrn2 v4.4s, v29.2d, #17", 4, 29)
3377 GEN_TWOVEC_TEST(sqshrn2_4s_2d_32, "sqshrn2 v4.4s, v29.2d, #32", 4, 29)
3378 GEN_TWOVEC_TEST(sqshrn_4h_4s_1, "sqshrn v4.4h, v29.4s, #1", 4, 29)
3379 GEN_TWOVEC_TEST(sqshrn_4h_4s_9, "sqshrn v4.4h, v29.4s, #9", 4, 29)
3380 GEN_TWOVEC_TEST(sqshrn_4h_4s_16, "sqshrn v4.4h, v29.4s, #16", 4, 29)
3381 GEN_TWOVEC_TEST(sqshrn2_8h_4s_1, "sqshrn2 v4.8h, v29.4s, #1", 4, 29)
3382 GEN_TWOVEC_TEST(sqshrn2_8h_4s_9, "sqshrn2 v4.8h, v29.4s, #9", 4, 29)
3383 GEN_TWOVEC_TEST(sqshrn2_8h_4s_16, "sqshrn2 v4.8h, v29.4s, #16", 4, 29)
3384 GEN_TWOVEC_TEST(sqshrn_8b_8h_1, "sqshrn v4.8b, v29.8h, #1", 4, 29)
3385 GEN_TWOVEC_TEST(sqshrn_8b_8h_4, "sqshrn v4.8b, v29.8h, #4", 4, 29)
3386 GEN_TWOVEC_TEST(sqshrn_8b_8h_8, "sqshrn v4.8b, v29.8h, #8", 4, 29)
3387 GEN_TWOVEC_TEST(sqshrn2_16b_8h_1, "sqshrn2 v4.16b, v29.8h, #1", 4, 29)
3388 GEN_TWOVEC_TEST(sqshrn2_16b_8h_4, "sqshrn2 v4.16b, v29.8h, #4", 4, 29)
3389 GEN_TWOVEC_TEST(sqshrn2_16b_8h_8, "sqshrn2 v4.16b, v29.8h, #8", 4, 29)
3390 GEN_TWOVEC_TEST(uqshrn_2s_2d_1, "uqshrn v4.2s, v29.2d, #1", 4, 29)
3391 GEN_TWOVEC_TEST(uqshrn_2s_2d_17, "uqshrn v4.2s, v29.2d, #17", 4, 29)
3392 GEN_TWOVEC_TEST(uqshrn_2s_2d_32, "uqshrn v4.2s, v29.2d, #32", 4, 29)
3393 GEN_TWOVEC_TEST(uqshrn2_4s_2d_1, "uqshrn2 v4.4s, v29.2d, #1", 4, 29)
3394 GEN_TWOVEC_TEST(uqshrn2_4s_2d_17, "uqshrn2 v4.4s, v29.2d, #17", 4, 29)
3395 GEN_TWOVEC_TEST(uqshrn2_4s_2d_32, "uqshrn2 v4.4s, v29.2d, #32", 4, 29)
3396 GEN_TWOVEC_TEST(uqshrn_4h_4s_1, "uqshrn v4.4h, v29.4s, #1", 4, 29)
3397 GEN_TWOVEC_TEST(uqshrn_4h_4s_9, "uqshrn v4.4h, v29.4s, #9", 4, 29)
3398 GEN_TWOVEC_TEST(uqshrn_4h_4s_16, "uqshrn v4.4h, v29.4s, #16", 4, 29)
3399 GEN_TWOVEC_TEST(uqshrn2_8h_4s_1, "uqshrn2 v4.8h, v29.4s, #1", 4, 29)
3400 GEN_TWOVEC_TEST(uqshrn2_8h_4s_9, "uqshrn2 v4.8h, v29.4s, #9", 4, 29)
3401 GEN_TWOVEC_TEST(uqshrn2_8h_4s_16, "uqshrn2 v4.8h, v29.4s, #16", 4, 29)
3402 GEN_TWOVEC_TEST(uqshrn_8b_8h_1, "uqshrn v4.8b, v29.8h, #1", 4, 29)
3403 GEN_TWOVEC_TEST(uqshrn_8b_8h_4, "uqshrn v4.8b, v29.8h, #4", 4, 29)
3404 GEN_TWOVEC_TEST(uqshrn_8b_8h_8, "uqshrn v4.8b, v29.8h, #8", 4, 29)
3405 GEN_TWOVEC_TEST(uqshrn2_16b_8h_1, "uqshrn2 v4.16b, v29.8h, #1", 4, 29)
3406 GEN_TWOVEC_TEST(uqshrn2_16b_8h_4, "uqshrn2 v4.16b, v29.8h, #4", 4, 29)
3407 GEN_TWOVEC_TEST(uqshrn2_16b_8h_8, "uqshrn2 v4.16b, v29.8h, #8", 4, 29)
3408 GEN_TWOVEC_TEST(sqrshrun_2s_2d_1, "sqrshrun v4.2s, v29.2d, #1", 4, 29)
3409 GEN_TWOVEC_TEST(sqrshrun_2s_2d_17, "sqrshrun v4.2s, v29.2d, #17", 4, 29)
3410 GEN_TWOVEC_TEST(sqrshrun_2s_2d_32, "sqrshrun v4.2s, v29.2d, #32", 4, 29)
3411 GEN_TWOVEC_TEST(sqrshrun2_4s_2d_1, "sqrshrun2 v4.4s, v29.2d, #1", 4, 29)
3412 GEN_TWOVEC_TEST(sqrshrun2_4s_2d_17, "sqrshrun2 v4.4s, v29.2d, #17", 4, 29)
3413 GEN_TWOVEC_TEST(sqrshrun2_4s_2d_32, "sqrshrun2 v4.4s, v29.2d, #32", 4, 29)
3414 GEN_TWOVEC_TEST(sqrshrun_4h_4s_1, "sqrshrun v4.4h, v29.4s, #1", 4, 29)
3415 GEN_TWOVEC_TEST(sqrshrun_4h_4s_9, "sqrshrun v4.4h, v29.4s, #9", 4, 29)
3416 GEN_TWOVEC_TEST(sqrshrun_4h_4s_16, "sqrshrun v4.4h, v29.4s, #16", 4, 29)
3417 GEN_TWOVEC_TEST(sqrshrun2_8h_4s_1, "sqrshrun2 v4.8h, v29.4s, #1", 4, 29)
3418 GEN_TWOVEC_TEST(sqrshrun2_8h_4s_9, "sqrshrun2 v4.8h, v29.4s, #9", 4, 29)
3419 GEN_TWOVEC_TEST(sqrshrun2_8h_4s_16, "sqrshrun2 v4.8h, v29.4s, #16", 4, 29)
3420 GEN_TWOVEC_TEST(sqrshrun_8b_8h_1, "sqrshrun v4.8b, v29.8h, #1", 4, 29)
3421 GEN_TWOVEC_TEST(sqrshrun_8b_8h_4, "sqrshrun v4.8b, v29.8h, #4", 4, 29)
3422 GEN_TWOVEC_TEST(sqrshrun_8b_8h_8, "sqrshrun v4.8b, v29.8h, #8", 4, 29)
3423 GEN_TWOVEC_TEST(sqrshrun2_16b_8h_1, "sqrshrun2 v4.16b, v29.8h, #1", 4, 29)
3424 GEN_TWOVEC_TEST(sqrshrun2_16b_8h_4, "sqrshrun2 v4.16b, v29.8h, #4", 4, 29)
3425 GEN_TWOVEC_TEST(sqrshrun2_16b_8h_8, "sqrshrun2 v4.16b, v29.8h, #8", 4, 29)
3426 GEN_TWOVEC_TEST(sqshrun_2s_2d_1, "sqshrun v4.2s, v29.2d, #1", 4, 29)
3427 GEN_TWOVEC_TEST(sqshrun_2s_2d_17, "sqshrun v4.2s, v29.2d, #17", 4, 29)
3428 GEN_TWOVEC_TEST(sqshrun_2s_2d_32, "sqshrun v4.2s, v29.2d, #32", 4, 29)
3429 GEN_TWOVEC_TEST(sqshrun2_4s_2d_1, "sqshrun2 v4.4s, v29.2d, #1", 4, 29)
3430 GEN_TWOVEC_TEST(sqshrun2_4s_2d_17, "sqshrun2 v4.4s, v29.2d, #17", 4, 29)
3431 GEN_TWOVEC_TEST(sqshrun2_4s_2d_32, "sqshrun2 v4.4s, v29.2d, #32", 4, 29)
3432 GEN_TWOVEC_TEST(sqshrun_4h_4s_1, "sqshrun v4.4h, v29.4s, #1", 4, 29)
3433 GEN_TWOVEC_TEST(sqshrun_4h_4s_9, "sqshrun v4.4h, v29.4s, #9", 4, 29)
3434 GEN_TWOVEC_TEST(sqshrun_4h_4s_16, "sqshrun v4.4h, v29.4s, #16", 4, 29)
3435 GEN_TWOVEC_TEST(sqshrun2_8h_4s_1, "sqshrun2 v4.8h, v29.4s, #1", 4, 29)
3436 GEN_TWOVEC_TEST(sqshrun2_8h_4s_9, "sqshrun2 v4.8h, v29.4s, #9", 4, 29)
3437 GEN_TWOVEC_TEST(sqshrun2_8h_4s_16, "sqshrun2 v4.8h, v29.4s, #16", 4, 29)
3438 GEN_TWOVEC_TEST(sqshrun_8b_8h_1, "sqshrun v4.8b, v29.8h, #1", 4, 29)
3439 GEN_TWOVEC_TEST(sqshrun_8b_8h_4, "sqshrun v4.8b, v29.8h, #4", 4, 29)
3440 GEN_TWOVEC_TEST(sqshrun_8b_8h_8, "sqshrun v4.8b, v29.8h, #8", 4, 29)
3441 GEN_TWOVEC_TEST(sqshrun2_16b_8h_1, "sqshrun2 v4.16b, v29.8h, #1", 4, 29)
3442 GEN_TWOVEC_TEST(sqshrun2_16b_8h_4, "sqshrun2 v4.16b, v29.8h, #4", 4, 29)
3443 GEN_TWOVEC_TEST(sqshrun2_16b_8h_8, "sqshrun2 v4.16b, v29.8h, #8", 4, 29)
3444
3445 GEN_TWOVEC_TEST(sqshl_d_d_0, "sqshl d5, d28, #0", 5, 28)
3446 GEN_TWOVEC_TEST(sqshl_d_d_32, "sqshl d5, d28, #32", 5, 28)
3447 GEN_TWOVEC_TEST(sqshl_d_d_63, "sqshl d5, d28, #63", 5, 28)
3448 GEN_TWOVEC_TEST(sqshl_s_s_0, "sqshl s5, s28, #0", 5, 28)
3449 GEN_TWOVEC_TEST(sqshl_s_s_16, "sqshl s5, s28, #16", 5, 28)
3450 GEN_TWOVEC_TEST(sqshl_s_s_31, "sqshl s5, s28, #31", 5, 28)
3451 GEN_TWOVEC_TEST(sqshl_h_h_0, "sqshl h5, h28, #0", 5, 28)
3452 GEN_TWOVEC_TEST(sqshl_h_h_8, "sqshl h5, h28, #8", 5, 28)
3453 GEN_TWOVEC_TEST(sqshl_h_h_15, "sqshl h5, h28, #15", 5, 28)
3454 GEN_TWOVEC_TEST(sqshl_b_b_0, "sqshl b5, b28, #0", 5, 28)
3455 GEN_TWOVEC_TEST(sqshl_b_b_1, "sqshl b5, b28, #1", 5, 28)
3456 GEN_TWOVEC_TEST(sqshl_b_b_4, "sqshl b5, b28, #4", 5, 28)
3457 GEN_TWOVEC_TEST(sqshl_b_b_6, "sqshl b5, b28, #6", 5, 28)
3458 GEN_TWOVEC_TEST(sqshl_b_b_7, "sqshl b5, b28, #7", 5, 28)
3459 GEN_TWOVEC_TEST(uqshl_d_d_0, "uqshl d5, d28, #0", 5, 28)
3460 GEN_TWOVEC_TEST(uqshl_d_d_32, "uqshl d5, d28, #32", 5, 28)
3461 GEN_TWOVEC_TEST(uqshl_d_d_63, "uqshl d5, d28, #63", 5, 28)
3462 GEN_TWOVEC_TEST(uqshl_s_s_0, "uqshl s5, s28, #0", 5, 28)
3463 GEN_TWOVEC_TEST(uqshl_s_s_16, "uqshl s5, s28, #16", 5, 28)
3464 GEN_TWOVEC_TEST(uqshl_s_s_31, "uqshl s5, s28, #31", 5, 28)
3465 GEN_TWOVEC_TEST(uqshl_h_h_0, "uqshl h5, h28, #0", 5, 28)
3466 GEN_TWOVEC_TEST(uqshl_h_h_8, "uqshl h5, h28, #8", 5, 28)
3467 GEN_TWOVEC_TEST(uqshl_h_h_15, "uqshl h5, h28, #15", 5, 28)
3468 GEN_TWOVEC_TEST(uqshl_b_b_0, "uqshl b5, b28, #0", 5, 28)
3469 GEN_TWOVEC_TEST(uqshl_b_b_1, "uqshl b5, b28, #1", 5, 28)
3470 GEN_TWOVEC_TEST(uqshl_b_b_4, "uqshl b5, b28, #4", 5, 28)
3471 GEN_TWOVEC_TEST(uqshl_b_b_6, "uqshl b5, b28, #6", 5, 28)
3472 GEN_TWOVEC_TEST(uqshl_b_b_7, "uqshl b5, b28, #7", 5, 28)
3473 GEN_TWOVEC_TEST(sqshlu_d_d_0, "sqshlu d5, d28, #0", 5, 28)
3474 GEN_TWOVEC_TEST(sqshlu_d_d_32, "sqshlu d5, d28, #32", 5, 28)
3475 GEN_TWOVEC_TEST(sqshlu_d_d_63, "sqshlu d5, d28, #63", 5, 28)
3476 GEN_TWOVEC_TEST(sqshlu_s_s_0, "sqshlu s5, s28, #0", 5, 28)
3477 GEN_TWOVEC_TEST(sqshlu_s_s_16, "sqshlu s5, s28, #16", 5, 28)
3478 GEN_TWOVEC_TEST(sqshlu_s_s_31, "sqshlu s5, s28, #31", 5, 28)
3479 GEN_TWOVEC_TEST(sqshlu_h_h_0, "sqshlu h5, h28, #0", 5, 28)
3480 GEN_TWOVEC_TEST(sqshlu_h_h_8, "sqshlu h5, h28, #8", 5, 28)
3481 GEN_TWOVEC_TEST(sqshlu_h_h_15, "sqshlu h5, h28, #15", 5, 28)
3482 GEN_TWOVEC_TEST(sqshlu_b_b_0, "sqshlu b5, b28, #0", 5, 28)
3483 GEN_TWOVEC_TEST(sqshlu_b_b_1, "sqshlu b5, b28, #1", 5, 28)
3484 GEN_TWOVEC_TEST(sqshlu_b_b_2, "sqshlu b5, b28, #2", 5, 28)
3485 GEN_TWOVEC_TEST(sqshlu_b_b_3, "sqshlu b5, b28, #3", 5, 28)
3486 GEN_TWOVEC_TEST(sqshlu_b_b_4, "sqshlu b5, b28, #4", 5, 28)
3487 GEN_TWOVEC_TEST(sqshlu_b_b_5, "sqshlu b5, b28, #5", 5, 28)
3488 GEN_TWOVEC_TEST(sqshlu_b_b_6, "sqshlu b5, b28, #6", 5, 28)
3489 GEN_TWOVEC_TEST(sqshlu_b_b_7, "sqshlu b5, b28, #7", 5, 28)
3490
3491 GEN_TWOVEC_TEST(sqshl_2d_2d_0, "sqshl v6.2d, v27.2d, #0", 6, 27)
3492 GEN_TWOVEC_TEST(sqshl_2d_2d_32, "sqshl v6.2d, v27.2d, #32", 6, 27)
3493 GEN_TWOVEC_TEST(sqshl_2d_2d_63, "sqshl v6.2d, v27.2d, #63", 6, 27)
3494 GEN_TWOVEC_TEST(sqshl_4s_4s_0, "sqshl v6.4s, v27.4s, #0", 6, 27)
3495 GEN_TWOVEC_TEST(sqshl_4s_4s_16, "sqshl v6.4s, v27.4s, #16", 6, 27)
3496 GEN_TWOVEC_TEST(sqshl_4s_4s_31, "sqshl v6.4s, v27.4s, #31", 6, 27)
3497 GEN_TWOVEC_TEST(sqshl_2s_2s_0, "sqshl v6.2s, v27.2s, #0", 6, 27)
3498 GEN_TWOVEC_TEST(sqshl_2s_2s_16, "sqshl v6.2s, v27.2s, #16", 6, 27)
3499 GEN_TWOVEC_TEST(sqshl_2s_2s_31, "sqshl v6.2s, v27.2s, #31", 6, 27)
3500 GEN_TWOVEC_TEST(sqshl_8h_8h_0, "sqshl v6.8h, v27.8h, #0", 6, 27)
3501 GEN_TWOVEC_TEST(sqshl_8h_8h_8, "sqshl v6.8h, v27.8h, #8", 6, 27)
3502 GEN_TWOVEC_TEST(sqshl_8h_8h_15, "sqshl v6.8h, v27.8h, #15", 6, 27)
3503 GEN_TWOVEC_TEST(sqshl_4h_4h_0, "sqshl v6.4h, v27.4h, #0", 6, 27)
3504 GEN_TWOVEC_TEST(sqshl_4h_4h_8, "sqshl v6.4h, v27.4h, #8", 6, 27)
3505 GEN_TWOVEC_TEST(sqshl_4h_4h_15, "sqshl v6.4h, v27.4h, #15", 6, 27)
3506 GEN_TWOVEC_TEST(sqshl_16b_16b_0, "sqshl v6.16b, v27.16b, #0", 6, 27)
3507 GEN_TWOVEC_TEST(sqshl_16b_16b_3, "sqshl v6.16b, v27.16b, #3", 6, 27)
3508 GEN_TWOVEC_TEST(sqshl_16b_16b_7, "sqshl v6.16b, v27.16b, #7", 6, 27)
3509 GEN_TWOVEC_TEST(sqshl_8b_8b_0, "sqshl v6.8b, v27.8b, #0", 6, 27)
3510 GEN_TWOVEC_TEST(sqshl_8b_8b_3, "sqshl v6.8b, v27.8b, #3", 6, 27)
3511 GEN_TWOVEC_TEST(sqshl_8b_8b_7, "sqshl v6.8b, v27.8b, #7", 6, 27)
3512 GEN_TWOVEC_TEST(uqshl_2d_2d_0, "uqshl v6.2d, v27.2d, #0", 6, 27)
3513 GEN_TWOVEC_TEST(uqshl_2d_2d_32, "uqshl v6.2d, v27.2d, #32", 6, 27)
3514 GEN_TWOVEC_TEST(uqshl_2d_2d_63, "uqshl v6.2d, v27.2d, #63", 6, 27)
3515 GEN_TWOVEC_TEST(uqshl_4s_4s_0, "uqshl v6.4s, v27.4s, #0", 6, 27)
3516 GEN_TWOVEC_TEST(uqshl_4s_4s_16, "uqshl v6.4s, v27.4s, #16", 6, 27)
3517 GEN_TWOVEC_TEST(uqshl_4s_4s_31, "uqshl v6.4s, v27.4s, #31", 6, 27)
3518 GEN_TWOVEC_TEST(uqshl_2s_2s_0, "uqshl v6.2s, v27.2s, #0", 6, 27)
3519 GEN_TWOVEC_TEST(uqshl_2s_2s_16, "uqshl v6.2s, v27.2s, #16", 6, 27)
3520 GEN_TWOVEC_TEST(uqshl_2s_2s_31, "uqshl v6.2s, v27.2s, #31", 6, 27)
3521 GEN_TWOVEC_TEST(uqshl_8h_8h_0, "uqshl v6.8h, v27.8h, #0", 6, 27)
3522 GEN_TWOVEC_TEST(uqshl_8h_8h_8, "uqshl v6.8h, v27.8h, #8", 6, 27)
3523 GEN_TWOVEC_TEST(uqshl_8h_8h_15, "uqshl v6.8h, v27.8h, #15", 6, 27)
3524 GEN_TWOVEC_TEST(uqshl_4h_4h_0, "uqshl v6.4h, v27.4h, #0", 6, 27)
3525 GEN_TWOVEC_TEST(uqshl_4h_4h_8, "uqshl v6.4h, v27.4h, #8", 6, 27)
3526 GEN_TWOVEC_TEST(uqshl_4h_4h_15, "uqshl v6.4h, v27.4h, #15", 6, 27)
3527 GEN_TWOVEC_TEST(uqshl_16b_16b_0, "uqshl v6.16b, v27.16b, #0", 6, 27)
3528 GEN_TWOVEC_TEST(uqshl_16b_16b_3, "uqshl v6.16b, v27.16b, #3", 6, 27)
3529 GEN_TWOVEC_TEST(uqshl_16b_16b_7, "uqshl v6.16b, v27.16b, #7", 6, 27)
3530 GEN_TWOVEC_TEST(uqshl_8b_8b_0, "uqshl v6.8b, v27.8b, #0", 6, 27)
3531 GEN_TWOVEC_TEST(uqshl_8b_8b_3, "uqshl v6.8b, v27.8b, #3", 6, 27)
3532 GEN_TWOVEC_TEST(uqshl_8b_8b_7, "uqshl v6.8b, v27.8b, #7", 6, 27)
3533 GEN_TWOVEC_TEST(sqshlu_2d_2d_0, "sqshlu v6.2d, v27.2d, #0", 6, 27)
3534 GEN_TWOVEC_TEST(sqshlu_2d_2d_32, "sqshlu v6.2d, v27.2d, #32", 6, 27)
3535 GEN_TWOVEC_TEST(sqshlu_2d_2d_63, "sqshlu v6.2d, v27.2d, #63", 6, 27)
3536 GEN_TWOVEC_TEST(sqshlu_4s_4s_0, "sqshlu v6.4s, v27.4s, #0", 6, 27)
3537 GEN_TWOVEC_TEST(sqshlu_4s_4s_16, "sqshlu v6.4s, v27.4s, #16", 6, 27)
3538 GEN_TWOVEC_TEST(sqshlu_4s_4s_31, "sqshlu v6.4s, v27.4s, #31", 6, 27)
3539 GEN_TWOVEC_TEST(sqshlu_2s_2s_0, "sqshlu v6.2s, v27.2s, #0", 6, 27)
3540 GEN_TWOVEC_TEST(sqshlu_2s_2s_16, "sqshlu v6.2s, v27.2s, #16", 6, 27)
3541 GEN_TWOVEC_TEST(sqshlu_2s_2s_31, "sqshlu v6.2s, v27.2s, #31", 6, 27)
3542 GEN_TWOVEC_TEST(sqshlu_8h_8h_0, "sqshlu v6.8h, v27.8h, #0", 6, 27)
3543 GEN_TWOVEC_TEST(sqshlu_8h_8h_8, "sqshlu v6.8h, v27.8h, #8", 6, 27)
3544 GEN_TWOVEC_TEST(sqshlu_8h_8h_15, "sqshlu v6.8h, v27.8h, #15", 6, 27)
3545 GEN_TWOVEC_TEST(sqshlu_4h_4h_0, "sqshlu v6.4h, v27.4h, #0", 6, 27)
3546 GEN_TWOVEC_TEST(sqshlu_4h_4h_8, "sqshlu v6.4h, v27.4h, #8", 6, 27)
3547 GEN_TWOVEC_TEST(sqshlu_4h_4h_15, "sqshlu v6.4h, v27.4h, #15", 6, 27)
3548 GEN_TWOVEC_TEST(sqshlu_16b_16b_0, "sqshlu v6.16b, v27.16b, #0", 6, 27)
3549 GEN_TWOVEC_TEST(sqshlu_16b_16b_3, "sqshlu v6.16b, v27.16b, #3", 6, 27)
3550 GEN_TWOVEC_TEST(sqshlu_16b_16b_7, "sqshlu v6.16b, v27.16b, #7", 6, 27)
3551 GEN_TWOVEC_TEST(sqshlu_8b_8b_0, "sqshlu v6.8b, v27.8b, #0", 6, 27)
3552 GEN_TWOVEC_TEST(sqshlu_8b_8b_3, "sqshlu v6.8b, v27.8b, #3", 6, 27)
3553 GEN_TWOVEC_TEST(sqshlu_8b_8b_7, "sqshlu v6.8b, v27.8b, #7", 6, 27)
3554
3555 GEN_TWOVEC_TEST(sqxtn_s_d, "sqxtn s31, d0", 31, 0)
3556 GEN_TWOVEC_TEST(sqxtn_h_s, "sqxtn h31, s0", 31, 0)
3557 GEN_TWOVEC_TEST(sqxtn_b_h, "sqxtn b31, h0", 31, 0)
3558 GEN_TWOVEC_TEST(uqxtn_s_d, "uqxtn s31, d0", 31, 0)
3559 GEN_TWOVEC_TEST(uqxtn_h_s, "uqxtn h31, s0", 31, 0)
3560 GEN_TWOVEC_TEST(uqxtn_b_h, "uqxtn b31, h0", 31, 0)
3561 GEN_TWOVEC_TEST(sqxtun_s_d, "sqxtun s31, d0", 31, 0)
3562 GEN_TWOVEC_TEST(sqxtun_h_s, "sqxtun h31, s0", 31, 0)
3563 GEN_TWOVEC_TEST(sqxtun_b_h, "sqxtun b31, h0", 31, 0)
3564
3565 GEN_UNARY_TEST(sqxtn, 2s, 2d)
3566 GEN_UNARY_TEST(sqxtn2, 4s, 2d)
3567 GEN_UNARY_TEST(sqxtn, 4h, 4s)
3568 GEN_UNARY_TEST(sqxtn2, 8h, 4s)
3569 GEN_UNARY_TEST(sqxtn, 8b, 8h)
3570 GEN_UNARY_TEST(sqxtn2, 16b, 8h)
3571 GEN_UNARY_TEST(uqxtn, 2s, 2d)
3572 GEN_UNARY_TEST(uqxtn2, 4s, 2d)
3573 GEN_UNARY_TEST(uqxtn, 4h, 4s)
3574 GEN_UNARY_TEST(uqxtn2, 8h, 4s)
3575 GEN_UNARY_TEST(uqxtn, 8b, 8h)
3576 GEN_UNARY_TEST(uqxtn2, 16b, 8h)
3577 GEN_UNARY_TEST(sqxtun, 2s, 2d)
3578 GEN_UNARY_TEST(sqxtun2, 4s, 2d)
3579 GEN_UNARY_TEST(sqxtun, 4h, 4s)
3580 GEN_UNARY_TEST(sqxtun2, 8h, 4s)
3581 GEN_UNARY_TEST(sqxtun, 8b, 8h)
3582 GEN_UNARY_TEST(sqxtun2, 16b, 8h)
3583
3584 GEN_THREEVEC_TEST(srhadd_4s_4s_4s,"srhadd v2.4s, v11.4s, v29.4s", 2, 11, 29)
3585 GEN_THREEVEC_TEST(srhadd_2s_2s_2s,"srhadd v2.2s, v11.2s, v29.2s", 2, 11, 29)
3586 GEN_THREEVEC_TEST(srhadd_8h_8h_8h,"srhadd v2.8h, v11.8h, v29.8h", 2, 11, 29)
3587 GEN_THREEVEC_TEST(srhadd_4h_4h_4h,"srhadd v2.4h, v11.4h, v29.4h", 2, 11, 29)
3588 GEN_THREEVEC_TEST(srhadd_16b_16b_16b,
3589 "srhadd v2.16b, v11.16b, v29.16b", 2, 11, 29)
3590 GEN_THREEVEC_TEST(srhadd_8b_8b_8b,"srhadd v2.8b, v11.8b, v29.8b", 2, 11, 29)
3591 GEN_THREEVEC_TEST(urhadd_4s_4s_4s,"urhadd v2.4s, v11.4s, v29.4s", 2, 11, 29)
3592 GEN_THREEVEC_TEST(urhadd_2s_2s_2s,"urhadd v2.2s, v11.2s, v29.2s", 2, 11, 29)
3593 GEN_THREEVEC_TEST(urhadd_8h_8h_8h,"urhadd v2.8h, v11.8h, v29.8h", 2, 11, 29)
3594 GEN_THREEVEC_TEST(urhadd_4h_4h_4h,"urhadd v2.4h, v11.4h, v29.4h", 2, 11, 29)
3595 GEN_THREEVEC_TEST(urhadd_16b_16b_16b,
3596 "urhadd v2.16b, v11.16b, v29.16b", 2, 11, 29)
3597 GEN_THREEVEC_TEST(urhadd_8b_8b_8b,"urhadd v2.8b, v11.8b, v29.8b", 2, 11, 29)
3598
3599 GEN_THREEVEC_TEST(sshl_d_d_d, "sshl d29, d28, d27", 29, 28, 27)
3600 GEN_THREEVEC_TEST(ushl_d_d_d, "ushl d29, d28, d27", 29, 28, 27)
3601
3602 GEN_THREEVEC_TEST(sshl_2d_2d_2d, "sshl v29.2d, v28.2d, v27.2d", 29,28,27)
3603 GEN_THREEVEC_TEST(sshl_4s_4s_4s, "sshl v29.4s, v28.4s, v27.4s", 29,28,27)
3604 GEN_THREEVEC_TEST(sshl_2s_2s_2s, "sshl v29.2s, v28.2s, v27.2s", 29,28,27)
3605 GEN_THREEVEC_TEST(sshl_8h_8h_8h, "sshl v29.8h, v28.8h, v27.8h", 29,28,27)
3606 GEN_THREEVEC_TEST(sshl_4h_4h_4h, "sshl v29.4h, v28.4h, v27.4h", 29,28,27)
3607 GEN_THREEVEC_TEST(sshl_16b_16b_16b, "sshl v29.16b, v28.16b, v27.16b", 29,28,27)
3608 GEN_THREEVEC_TEST(sshl_8b_8b_8b, "sshl v29.8b, v28.8b, v27.8b", 29,28,27)
3609 GEN_THREEVEC_TEST(ushl_2d_2d_2d, "ushl v29.2d, v28.2d, v27.2d", 29,28,27)
3610 GEN_THREEVEC_TEST(ushl_4s_4s_4s, "ushl v29.4s, v28.4s, v27.4s", 29,28,27)
3611 GEN_THREEVEC_TEST(ushl_2s_2s_2s, "ushl v29.2s, v28.2s, v27.2s", 29,28,27)
3612 GEN_THREEVEC_TEST(ushl_8h_8h_8h, "ushl v29.8h, v28.8h, v27.8h", 29,28,27)
3613 GEN_THREEVEC_TEST(ushl_4h_4h_4h, "ushl v29.4h, v28.4h, v27.4h", 29,28,27)
3614 GEN_THREEVEC_TEST(ushl_16b_16b_16b, "ushl v29.16b, v28.16b, v27.16b", 29,28,27)
3615 GEN_THREEVEC_TEST(ushl_8b_8b_8b, "ushl v29.8b, v28.8b, v27.8b", 29,28,27)
3616
3617 GEN_TWOVEC_TEST(shl_d_d_0, "shl d5, d28, #0", 5, 28)
3618 GEN_TWOVEC_TEST(shl_d_d_32, "shl d5, d28, #32", 5, 28)
3619 GEN_TWOVEC_TEST(shl_d_d_63, "shl d5, d28, #63", 5, 28)
3620 GEN_TWOVEC_TEST(sshr_d_d_1, "sshr d5, d28, #1", 5, 28)
3621 GEN_TWOVEC_TEST(sshr_d_d_32, "sshr d5, d28, #32", 5, 28)
3622 GEN_TWOVEC_TEST(sshr_d_d_64, "sshr d5, d28, #64", 5, 28)
3623 GEN_TWOVEC_TEST(ushr_d_d_1, "ushr d5, d28, #1", 5, 28)
3624 GEN_TWOVEC_TEST(ushr_d_d_32, "ushr d5, d28, #32", 5, 28)
3625 GEN_TWOVEC_TEST(ushr_d_d_64, "ushr d5, d28, #64", 5, 28)
3626
3627 GEN_SHIFT_TEST(shl, 2d, 2d, 0)
3628 GEN_SHIFT_TEST(shl, 2d, 2d, 13)
3629 GEN_SHIFT_TEST(shl, 2d, 2d, 63)
3630 GEN_SHIFT_TEST(shl, 4s, 4s, 0)
3631 GEN_SHIFT_TEST(shl, 4s, 4s, 13)
3632 GEN_SHIFT_TEST(shl, 4s, 4s, 31)
3633 GEN_SHIFT_TEST(shl, 2s, 2s, 0)
3634 GEN_SHIFT_TEST(shl, 2s, 2s, 13)
3635 GEN_SHIFT_TEST(shl, 2s, 2s, 31)
3636 GEN_SHIFT_TEST(shl, 8h, 8h, 0)
3637 GEN_SHIFT_TEST(shl, 8h, 8h, 13)
3638 GEN_SHIFT_TEST(shl, 8h, 8h, 15)
3639 GEN_SHIFT_TEST(shl, 4h, 4h, 0)
3640 GEN_SHIFT_TEST(shl, 4h, 4h, 13)
3641 GEN_SHIFT_TEST(shl, 4h, 4h, 15)
3642 GEN_SHIFT_TEST(shl, 16b, 16b, 0)
3643 GEN_SHIFT_TEST(shl, 16b, 16b, 7)
3644 GEN_SHIFT_TEST(shl, 8b, 8b, 0)
3645 GEN_SHIFT_TEST(shl, 8b, 8b, 7)
3646 GEN_SHIFT_TEST(sshr, 2d, 2d, 1)
3647 GEN_SHIFT_TEST(sshr, 2d, 2d, 13)
3648 GEN_SHIFT_TEST(sshr, 2d, 2d, 64)
3649 GEN_SHIFT_TEST(sshr, 4s, 4s, 1)
3650 GEN_SHIFT_TEST(sshr, 4s, 4s, 13)
3651 GEN_SHIFT_TEST(sshr, 4s, 4s, 32)
3652 GEN_SHIFT_TEST(sshr, 2s, 2s, 1)
3653 GEN_SHIFT_TEST(sshr, 2s, 2s, 13)
3654 GEN_SHIFT_TEST(sshr, 2s, 2s, 32)
3655 GEN_SHIFT_TEST(sshr, 8h, 8h, 1)
3656 GEN_SHIFT_TEST(sshr, 8h, 8h, 13)
3657 GEN_SHIFT_TEST(sshr, 8h, 8h, 16)
3658 GEN_SHIFT_TEST(sshr, 4h, 4h, 1)
3659 GEN_SHIFT_TEST(sshr, 4h, 4h, 13)
3660 GEN_SHIFT_TEST(sshr, 4h, 4h, 16)
3661 GEN_SHIFT_TEST(sshr, 16b, 16b, 1)
3662 GEN_SHIFT_TEST(sshr, 16b, 16b, 8)
3663 GEN_SHIFT_TEST(sshr, 8b, 8b, 1)
3664 GEN_SHIFT_TEST(sshr, 8b, 8b, 8)
3665 GEN_SHIFT_TEST(ushr, 2d, 2d, 1)
3666 GEN_SHIFT_TEST(ushr, 2d, 2d, 13)
3667 GEN_SHIFT_TEST(ushr, 2d, 2d, 64)
3668 GEN_SHIFT_TEST(ushr, 4s, 4s, 1)
3669 GEN_SHIFT_TEST(ushr, 4s, 4s, 13)
3670 GEN_SHIFT_TEST(ushr, 4s, 4s, 32)
3671 GEN_SHIFT_TEST(ushr, 2s, 2s, 1)
3672 GEN_SHIFT_TEST(ushr, 2s, 2s, 13)
3673 GEN_SHIFT_TEST(ushr, 2s, 2s, 32)
3674 GEN_SHIFT_TEST(ushr, 8h, 8h, 1)
3675 GEN_SHIFT_TEST(ushr, 8h, 8h, 13)
3676 GEN_SHIFT_TEST(ushr, 8h, 8h, 16)
3677 GEN_SHIFT_TEST(ushr, 4h, 4h, 1)
3678 GEN_SHIFT_TEST(ushr, 4h, 4h, 13)
3679 GEN_SHIFT_TEST(ushr, 4h, 4h, 16)
3680 GEN_SHIFT_TEST(ushr, 16b, 16b, 1)
3681 GEN_SHIFT_TEST(ushr, 16b, 16b, 8)
3682 GEN_SHIFT_TEST(ushr, 8b, 8b, 1)
3683 GEN_SHIFT_TEST(ushr, 8b, 8b, 8)
3684
3685 GEN_TWOVEC_TEST(ssra_d_d_1, "ssra d5, d28, #1", 5, 28)
3686 GEN_TWOVEC_TEST(ssra_d_d_32, "ssra d5, d28, #32", 5, 28)
3687 GEN_TWOVEC_TEST(ssra_d_d_64, "ssra d5, d28, #64", 5, 28)
3688 GEN_TWOVEC_TEST(usra_d_d_1, "usra d5, d28, #1", 5, 28)
3689 GEN_TWOVEC_TEST(usra_d_d_32, "usra d5, d28, #32", 5, 28)
3690 GEN_TWOVEC_TEST(usra_d_d_64, "usra d5, d28, #64", 5, 28)
3691
3692 GEN_TWOVEC_TEST(ssra_2d_2d_1, "ssra v6.2d, v27.2d, #1", 6, 27)
3693 GEN_TWOVEC_TEST(ssra_2d_2d_32, "ssra v6.2d, v27.2d, #32", 6, 27)
3694 GEN_TWOVEC_TEST(ssra_2d_2d_64, "ssra v6.2d, v27.2d, #64", 6, 27)
3695 GEN_TWOVEC_TEST(ssra_4s_4s_1, "ssra v6.4s, v27.4s, #1", 6, 27)
3696 GEN_TWOVEC_TEST(ssra_4s_4s_16, "ssra v6.4s, v27.4s, #16", 6, 27)
3697 GEN_TWOVEC_TEST(ssra_4s_4s_32, "ssra v6.4s, v27.4s, #32", 6, 27)
3698 GEN_TWOVEC_TEST(ssra_2s_2s_1, "ssra v6.2s, v27.2s, #1", 6, 27)
3699 GEN_TWOVEC_TEST(ssra_2s_2s_16, "ssra v6.2s, v27.2s, #16", 6, 27)
3700 GEN_TWOVEC_TEST(ssra_2s_2s_32, "ssra v6.2s, v27.2s, #32", 6, 27)
3701 GEN_TWOVEC_TEST(ssra_8h_8h_1, "ssra v6.8h, v27.8h, #1", 6, 27)
3702 GEN_TWOVEC_TEST(ssra_8h_8h_8, "ssra v6.8h, v27.8h, #8", 6, 27)
3703 GEN_TWOVEC_TEST(ssra_8h_8h_16, "ssra v6.8h, v27.8h, #16", 6, 27)
3704 GEN_TWOVEC_TEST(ssra_4h_4h_1, "ssra v6.4h, v27.4h, #1", 6, 27)
3705 GEN_TWOVEC_TEST(ssra_4h_4h_8, "ssra v6.4h, v27.4h, #8", 6, 27)
3706 GEN_TWOVEC_TEST(ssra_4h_4h_16, "ssra v6.4h, v27.4h, #16", 6, 27)
3707 GEN_TWOVEC_TEST(ssra_16b_16b_1, "ssra v6.16b, v27.16b, #1", 6, 27)
3708 GEN_TWOVEC_TEST(ssra_16b_16b_3, "ssra v6.16b, v27.16b, #3", 6, 27)
3709 GEN_TWOVEC_TEST(ssra_16b_16b_8, "ssra v6.16b, v27.16b, #8", 6, 27)
3710 GEN_TWOVEC_TEST(ssra_8b_8b_1, "ssra v6.8b, v27.8b, #1", 6, 27)
3711 GEN_TWOVEC_TEST(ssra_8b_8b_3, "ssra v6.8b, v27.8b, #3", 6, 27)
3712 GEN_TWOVEC_TEST(ssra_8b_8b_8, "ssra v6.8b, v27.8b, #8", 6, 27)
3713 GEN_TWOVEC_TEST(usra_2d_2d_1, "usra v6.2d, v27.2d, #1", 6, 27)
3714 GEN_TWOVEC_TEST(usra_2d_2d_32, "usra v6.2d, v27.2d, #32", 6, 27)
3715 GEN_TWOVEC_TEST(usra_2d_2d_64, "usra v6.2d, v27.2d, #64", 6, 27)
3716 GEN_TWOVEC_TEST(usra_4s_4s_1, "usra v6.4s, v27.4s, #1", 6, 27)
3717 GEN_TWOVEC_TEST(usra_4s_4s_16, "usra v6.4s, v27.4s, #16", 6, 27)
3718 GEN_TWOVEC_TEST(usra_4s_4s_32, "usra v6.4s, v27.4s, #32", 6, 27)
3719 GEN_TWOVEC_TEST(usra_2s_2s_1, "usra v6.2s, v27.2s, #1", 6, 27)
3720 GEN_TWOVEC_TEST(usra_2s_2s_16, "usra v6.2s, v27.2s, #16", 6, 27)
3721 GEN_TWOVEC_TEST(usra_2s_2s_32, "usra v6.2s, v27.2s, #32", 6, 27)
3722 GEN_TWOVEC_TEST(usra_8h_8h_1, "usra v6.8h, v27.8h, #1", 6, 27)
3723 GEN_TWOVEC_TEST(usra_8h_8h_8, "usra v6.8h, v27.8h, #8", 6, 27)
3724 GEN_TWOVEC_TEST(usra_8h_8h_16, "usra v6.8h, v27.8h, #16", 6, 27)
3725 GEN_TWOVEC_TEST(usra_4h_4h_1, "usra v6.4h, v27.4h, #1", 6, 27)
3726 GEN_TWOVEC_TEST(usra_4h_4h_8, "usra v6.4h, v27.4h, #8", 6, 27)
3727 GEN_TWOVEC_TEST(usra_4h_4h_16, "usra v6.4h, v27.4h, #16", 6, 27)
3728 GEN_TWOVEC_TEST(usra_16b_16b_1, "usra v6.16b, v27.16b, #1", 6, 27)
3729 GEN_TWOVEC_TEST(usra_16b_16b_3, "usra v6.16b, v27.16b, #3", 6, 27)
3730 GEN_TWOVEC_TEST(usra_16b_16b_8, "usra v6.16b, v27.16b, #8", 6, 27)
3731 GEN_TWOVEC_TEST(usra_8b_8b_1, "usra v6.8b, v27.8b, #1", 6, 27)
3732 GEN_TWOVEC_TEST(usra_8b_8b_3, "usra v6.8b, v27.8b, #3", 6, 27)
3733 GEN_TWOVEC_TEST(usra_8b_8b_8, "usra v6.8b, v27.8b, #8", 6, 27)
3734
3735 GEN_THREEVEC_TEST(srshl_d_d_d, "srshl d29, d28, d27", 29, 28, 27)
3736 GEN_THREEVEC_TEST(urshl_d_d_d, "urshl d29, d28, d27", 29, 28, 27)
3737
3738 GEN_THREEVEC_TEST(srshl_2d_2d_2d, "srshl v29.2d, v28.2d, v27.2d", 29,28,27)
3739 GEN_THREEVEC_TEST(srshl_4s_4s_4s, "srshl v29.4s, v28.4s, v27.4s", 29,28,27)
3740 GEN_THREEVEC_TEST(srshl_2s_2s_2s, "srshl v29.2s, v28.2s, v27.2s", 29,28,27)
3741 GEN_THREEVEC_TEST(srshl_8h_8h_8h, "srshl v29.8h, v28.8h, v27.8h", 29,28,27)
3742 GEN_THREEVEC_TEST(srshl_4h_4h_4h, "srshl v29.4h, v28.4h, v27.4h", 29,28,27)
3743 GEN_THREEVEC_TEST(srshl_16b_16b_16b,"srshl v29.16b, v28.16b, v27.16b", 29,28,27)
3744 GEN_THREEVEC_TEST(srshl_8b_8b_8b, "srshl v29.8b, v28.8b, v27.8b", 29,28,27)
3745 GEN_THREEVEC_TEST(urshl_2d_2d_2d, "urshl v29.2d, v28.2d, v27.2d", 29,28,27)
3746 GEN_THREEVEC_TEST(urshl_4s_4s_4s, "urshl v29.4s, v28.4s, v27.4s", 29,28,27)
3747 GEN_THREEVEC_TEST(urshl_2s_2s_2s, "urshl v29.2s, v28.2s, v27.2s", 29,28,27)
3748 GEN_THREEVEC_TEST(urshl_8h_8h_8h, "urshl v29.8h, v28.8h, v27.8h", 29,28,27)
3749 GEN_THREEVEC_TEST(urshl_4h_4h_4h, "urshl v29.4h, v28.4h, v27.4h", 29,28,27)
3750 GEN_THREEVEC_TEST(urshl_16b_16b_16b,"urshl v29.16b, v28.16b, v27.16b", 29,28,27)
3751 GEN_THREEVEC_TEST(urshl_8b_8b_8b, "urshl v29.8b, v28.8b, v27.8b", 29,28,27)
3752
3753 GEN_TWOVEC_TEST(srshr_d_d_1, "srshr d5, d28, #1", 5, 28)
3754 GEN_TWOVEC_TEST(srshr_d_d_32, "srshr d5, d28, #32", 5, 28)
3755 GEN_TWOVEC_TEST(srshr_d_d_64, "srshr d5, d28, #64", 5, 28)
3756 GEN_TWOVEC_TEST(urshr_d_d_1, "urshr d5, d28, #1", 5, 28)
3757 GEN_TWOVEC_TEST(urshr_d_d_32, "urshr d5, d28, #32", 5, 28)
3758 GEN_TWOVEC_TEST(urshr_d_d_64, "urshr d5, d28, #64", 5, 28)
3759
3760 GEN_TWOVEC_TEST(srshr_2d_2d_1, "srshr v6.2d, v27.2d, #1", 6, 27)
3761 GEN_TWOVEC_TEST(srshr_2d_2d_32, "srshr v6.2d, v27.2d, #32", 6, 27)
3762 GEN_TWOVEC_TEST(srshr_2d_2d_64, "srshr v6.2d, v27.2d, #64", 6, 27)
3763 GEN_TWOVEC_TEST(srshr_4s_4s_1, "srshr v6.4s, v27.4s, #1", 6, 27)
3764 GEN_TWOVEC_TEST(srshr_4s_4s_16, "srshr v6.4s, v27.4s, #16", 6, 27)
3765 GEN_TWOVEC_TEST(srshr_4s_4s_32, "srshr v6.4s, v27.4s, #32", 6, 27)
3766 GEN_TWOVEC_TEST(srshr_2s_2s_1, "srshr v6.2s, v27.2s, #1", 6, 27)
3767 GEN_TWOVEC_TEST(srshr_2s_2s_16, "srshr v6.2s, v27.2s, #16", 6, 27)
3768 GEN_TWOVEC_TEST(srshr_2s_2s_32, "srshr v6.2s, v27.2s, #32", 6, 27)
3769 GEN_TWOVEC_TEST(srshr_8h_8h_1, "srshr v6.8h, v27.8h, #1", 6, 27)
3770 GEN_TWOVEC_TEST(srshr_8h_8h_8, "srshr v6.8h, v27.8h, #8", 6, 27)
3771 GEN_TWOVEC_TEST(srshr_8h_8h_16, "srshr v6.8h, v27.8h, #16", 6, 27)
3772 GEN_TWOVEC_TEST(srshr_4h_4h_1, "srshr v6.4h, v27.4h, #1", 6, 27)
3773 GEN_TWOVEC_TEST(srshr_4h_4h_8, "srshr v6.4h, v27.4h, #8", 6, 27)
3774 GEN_TWOVEC_TEST(srshr_4h_4h_16, "srshr v6.4h, v27.4h, #16", 6, 27)
3775 GEN_TWOVEC_TEST(srshr_16b_16b_1, "srshr v6.16b, v27.16b, #1", 6, 27)
3776 GEN_TWOVEC_TEST(srshr_16b_16b_3, "srshr v6.16b, v27.16b, #3", 6, 27)
3777 GEN_TWOVEC_TEST(srshr_16b_16b_8, "srshr v6.16b, v27.16b, #8", 6, 27)
3778 GEN_TWOVEC_TEST(srshr_8b_8b_1, "srshr v6.8b, v27.8b, #1", 6, 27)
3779 GEN_TWOVEC_TEST(srshr_8b_8b_3, "srshr v6.8b, v27.8b, #3", 6, 27)
3780 GEN_TWOVEC_TEST(srshr_8b_8b_8, "srshr v6.8b, v27.8b, #8", 6, 27)
3781 GEN_TWOVEC_TEST(urshr_2d_2d_1, "urshr v6.2d, v27.2d, #1", 6, 27)
3782 GEN_TWOVEC_TEST(urshr_2d_2d_32, "urshr v6.2d, v27.2d, #32", 6, 27)
3783 GEN_TWOVEC_TEST(urshr_2d_2d_64, "urshr v6.2d, v27.2d, #64", 6, 27)
3784 GEN_TWOVEC_TEST(urshr_4s_4s_1, "urshr v6.4s, v27.4s, #1", 6, 27)
3785 GEN_TWOVEC_TEST(urshr_4s_4s_16, "urshr v6.4s, v27.4s, #16", 6, 27)
3786 GEN_TWOVEC_TEST(urshr_4s_4s_32, "urshr v6.4s, v27.4s, #32", 6, 27)
3787 GEN_TWOVEC_TEST(urshr_2s_2s_1, "urshr v6.2s, v27.2s, #1", 6, 27)
3788 GEN_TWOVEC_TEST(urshr_2s_2s_16, "urshr v6.2s, v27.2s, #16", 6, 27)
3789 GEN_TWOVEC_TEST(urshr_2s_2s_32, "urshr v6.2s, v27.2s, #32", 6, 27)
3790 GEN_TWOVEC_TEST(urshr_8h_8h_1, "urshr v6.8h, v27.8h, #1", 6, 27)
3791 GEN_TWOVEC_TEST(urshr_8h_8h_8, "urshr v6.8h, v27.8h, #8", 6, 27)
3792 GEN_TWOVEC_TEST(urshr_8h_8h_16, "urshr v6.8h, v27.8h, #16", 6, 27)
3793 GEN_TWOVEC_TEST(urshr_4h_4h_1, "urshr v6.4h, v27.4h, #1", 6, 27)
3794 GEN_TWOVEC_TEST(urshr_4h_4h_8, "urshr v6.4h, v27.4h, #8", 6, 27)
3795 GEN_TWOVEC_TEST(urshr_4h_4h_16, "urshr v6.4h, v27.4h, #16", 6, 27)
3796 GEN_TWOVEC_TEST(urshr_16b_16b_1, "urshr v6.16b, v27.16b, #1", 6, 27)
3797 GEN_TWOVEC_TEST(urshr_16b_16b_3, "urshr v6.16b, v27.16b, #3", 6, 27)
3798 GEN_TWOVEC_TEST(urshr_16b_16b_8, "urshr v6.16b, v27.16b, #8", 6, 27)
3799 GEN_TWOVEC_TEST(urshr_8b_8b_1, "urshr v6.8b, v27.8b, #1", 6, 27)
3800 GEN_TWOVEC_TEST(urshr_8b_8b_3, "urshr v6.8b, v27.8b, #3", 6, 27)
3801 GEN_TWOVEC_TEST(urshr_8b_8b_8, "urshr v6.8b, v27.8b, #8", 6, 27)
3802
3803 GEN_TWOVEC_TEST(srsra_d_d_1, "srsra d5, d28, #1", 5, 28)
3804 GEN_TWOVEC_TEST(srsra_d_d_32, "srsra d5, d28, #32", 5, 28)
3805 GEN_TWOVEC_TEST(srsra_d_d_64, "srsra d5, d28, #64", 5, 28)
3806 GEN_TWOVEC_TEST(ursra_d_d_1, "ursra d5, d28, #1", 5, 28)
3807 GEN_TWOVEC_TEST(ursra_d_d_32, "ursra d5, d28, #32", 5, 28)
3808 GEN_TWOVEC_TEST(ursra_d_d_64, "ursra d5, d28, #64", 5, 28)
3809
3810 GEN_TWOVEC_TEST(srsra_2d_2d_1, "srsra v6.2d, v27.2d, #1", 6, 27)
3811 GEN_TWOVEC_TEST(srsra_2d_2d_32, "srsra v6.2d, v27.2d, #32", 6, 27)
3812 GEN_TWOVEC_TEST(srsra_2d_2d_64, "srsra v6.2d, v27.2d, #64", 6, 27)
3813 GEN_TWOVEC_TEST(srsra_4s_4s_1, "srsra v6.4s, v27.4s, #1", 6, 27)
3814 GEN_TWOVEC_TEST(srsra_4s_4s_16, "srsra v6.4s, v27.4s, #16", 6, 27)
3815 GEN_TWOVEC_TEST(srsra_4s_4s_32, "srsra v6.4s, v27.4s, #32", 6, 27)
3816 GEN_TWOVEC_TEST(srsra_2s_2s_1, "srsra v6.2s, v27.2s, #1", 6, 27)
3817 GEN_TWOVEC_TEST(srsra_2s_2s_16, "srsra v6.2s, v27.2s, #16", 6, 27)
3818 GEN_TWOVEC_TEST(srsra_2s_2s_32, "srsra v6.2s, v27.2s, #32", 6, 27)
3819 GEN_TWOVEC_TEST(srsra_8h_8h_1, "srsra v6.8h, v27.8h, #1", 6, 27)
3820 GEN_TWOVEC_TEST(srsra_8h_8h_8, "srsra v6.8h, v27.8h, #8", 6, 27)
3821 GEN_TWOVEC_TEST(srsra_8h_8h_16, "srsra v6.8h, v27.8h, #16", 6, 27)
3822 GEN_TWOVEC_TEST(srsra_4h_4h_1, "srsra v6.4h, v27.4h, #1", 6, 27)
3823 GEN_TWOVEC_TEST(srsra_4h_4h_8, "srsra v6.4h, v27.4h, #8", 6, 27)
3824 GEN_TWOVEC_TEST(srsra_4h_4h_16, "srsra v6.4h, v27.4h, #16", 6, 27)
3825 GEN_TWOVEC_TEST(srsra_16b_16b_1, "srsra v6.16b, v27.16b, #1", 6, 27)
3826 GEN_TWOVEC_TEST(srsra_16b_16b_3, "srsra v6.16b, v27.16b, #3", 6, 27)
3827 GEN_TWOVEC_TEST(srsra_16b_16b_8, "srsra v6.16b, v27.16b, #8", 6, 27)
3828 GEN_TWOVEC_TEST(srsra_8b_8b_1, "srsra v6.8b, v27.8b, #1", 6, 27)
3829 GEN_TWOVEC_TEST(srsra_8b_8b_3, "srsra v6.8b, v27.8b, #3", 6, 27)
3830 GEN_TWOVEC_TEST(srsra_8b_8b_8, "srsra v6.8b, v27.8b, #8", 6, 27)
3831 GEN_TWOVEC_TEST(ursra_2d_2d_1, "ursra v6.2d, v27.2d, #1", 6, 27)
3832 GEN_TWOVEC_TEST(ursra_2d_2d_32, "ursra v6.2d, v27.2d, #32", 6, 27)
3833 GEN_TWOVEC_TEST(ursra_2d_2d_64, "ursra v6.2d, v27.2d, #64", 6, 27)
3834 GEN_TWOVEC_TEST(ursra_4s_4s_1, "ursra v6.4s, v27.4s, #1", 6, 27)
3835 GEN_TWOVEC_TEST(ursra_4s_4s_16, "ursra v6.4s, v27.4s, #16", 6, 27)
3836 GEN_TWOVEC_TEST(ursra_4s_4s_32, "ursra v6.4s, v27.4s, #32", 6, 27)
3837 GEN_TWOVEC_TEST(ursra_2s_2s_1, "ursra v6.2s, v27.2s, #1", 6, 27)
3838 GEN_TWOVEC_TEST(ursra_2s_2s_16, "ursra v6.2s, v27.2s, #16", 6, 27)
3839 GEN_TWOVEC_TEST(ursra_2s_2s_32, "ursra v6.2s, v27.2s, #32", 6, 27)
3840 GEN_TWOVEC_TEST(ursra_8h_8h_1, "ursra v6.8h, v27.8h, #1", 6, 27)
3841 GEN_TWOVEC_TEST(ursra_8h_8h_8, "ursra v6.8h, v27.8h, #8", 6, 27)
3842 GEN_TWOVEC_TEST(ursra_8h_8h_16, "ursra v6.8h, v27.8h, #16", 6, 27)
3843 GEN_TWOVEC_TEST(ursra_4h_4h_1, "ursra v6.4h, v27.4h, #1", 6, 27)
3844 GEN_TWOVEC_TEST(ursra_4h_4h_8, "ursra v6.4h, v27.4h, #8", 6, 27)
3845 GEN_TWOVEC_TEST(ursra_4h_4h_16, "ursra v6.4h, v27.4h, #16", 6, 27)
3846 GEN_TWOVEC_TEST(ursra_16b_16b_1, "ursra v6.16b, v27.16b, #1", 6, 27)
3847 GEN_TWOVEC_TEST(ursra_16b_16b_3, "ursra v6.16b, v27.16b, #3", 6, 27)
3848 GEN_TWOVEC_TEST(ursra_16b_16b_8, "ursra v6.16b, v27.16b, #8", 6, 27)
3849 GEN_TWOVEC_TEST(ursra_8b_8b_1, "ursra v6.8b, v27.8b, #1", 6, 27)
3850 GEN_TWOVEC_TEST(ursra_8b_8b_3, "ursra v6.8b, v27.8b, #3", 6, 27)
3851 GEN_TWOVEC_TEST(ursra_8b_8b_8, "ursra v6.8b, v27.8b, #8", 6, 27)
3852
3853 GEN_SHIFT_TEST(sshll, 2d, 2s, 0)
3854 GEN_SHIFT_TEST(sshll, 2d, 2s, 15)
3855 GEN_SHIFT_TEST(sshll, 2d, 2s, 31)
3856 GEN_SHIFT_TEST(sshll2, 2d, 4s, 0)
3857 GEN_SHIFT_TEST(sshll2, 2d, 4s, 15)
3858 GEN_SHIFT_TEST(sshll2, 2d, 4s, 31)
3859 GEN_SHIFT_TEST(sshll, 4s, 4h, 0)
3860 GEN_SHIFT_TEST(sshll, 4s, 4h, 7)
3861 GEN_SHIFT_TEST(sshll, 4s, 4h, 15)
3862 GEN_SHIFT_TEST(sshll2, 4s, 8h, 0)
3863 GEN_SHIFT_TEST(sshll2, 4s, 8h, 7)
3864 GEN_SHIFT_TEST(sshll2, 4s, 8h, 15)
3865 GEN_SHIFT_TEST(sshll, 8h, 8b, 0)
3866 GEN_SHIFT_TEST(sshll, 8h, 8b, 3)
3867 GEN_SHIFT_TEST(sshll, 8h, 8b, 7)
3868 GEN_SHIFT_TEST(sshll2, 8h, 16b, 0)
3869 GEN_SHIFT_TEST(sshll2, 8h, 16b, 3)
3870 GEN_SHIFT_TEST(sshll2, 8h, 16b, 7)
3871 GEN_SHIFT_TEST(ushll, 2d, 2s, 0)
3872 GEN_SHIFT_TEST(ushll, 2d, 2s, 15)
3873 GEN_SHIFT_TEST(ushll, 2d, 2s, 31)
3874 GEN_SHIFT_TEST(ushll2, 2d, 4s, 0)
3875 GEN_SHIFT_TEST(ushll2, 2d, 4s, 15)
3876 GEN_SHIFT_TEST(ushll2, 2d, 4s, 31)
3877 GEN_SHIFT_TEST(ushll, 4s, 4h, 0)
3878 GEN_SHIFT_TEST(ushll, 4s, 4h, 7)
3879 GEN_SHIFT_TEST(ushll, 4s, 4h, 15)
3880 GEN_SHIFT_TEST(ushll2, 4s, 8h, 0)
3881 GEN_SHIFT_TEST(ushll2, 4s, 8h, 7)
3882 GEN_SHIFT_TEST(ushll2, 4s, 8h, 15)
3883 GEN_SHIFT_TEST(ushll, 8h, 8b, 0)
3884 GEN_SHIFT_TEST(ushll, 8h, 8b, 3)
3885 GEN_SHIFT_TEST(ushll, 8h, 8b, 7)
3886 GEN_SHIFT_TEST(ushll2, 8h, 16b, 0)
3887 GEN_SHIFT_TEST(ushll2, 8h, 16b, 3)
3888 GEN_SHIFT_TEST(ushll2, 8h, 16b, 7)
3889
3890 GEN_TWOVEC_TEST(suqadd_d_d, "suqadd d22, d23", 22, 23)
3891 GEN_TWOVEC_TEST(suqadd_s_s, "suqadd s22, s23", 22, 23)
3892 GEN_TWOVEC_TEST(suqadd_h_h, "suqadd h22, h23", 22, 23)
3893 GEN_TWOVEC_TEST(suqadd_b_b, "suqadd b22, b23", 22, 23)
3894 GEN_TWOVEC_TEST(usqadd_d_d, "usqadd d22, d23", 22, 23)
3895 GEN_TWOVEC_TEST(usqadd_s_s, "usqadd s22, s23", 22, 23)
3896 GEN_TWOVEC_TEST(usqadd_h_h, "usqadd h22, h23", 22, 23)
3897 GEN_TWOVEC_TEST(usqadd_b_b, "usqadd b22, b23", 22, 23)
3898
3899 GEN_TWOVEC_TEST(suqadd_2d_2d, "suqadd v6.2d, v27.2d", 6, 27)
3900 GEN_TWOVEC_TEST(suqadd_4s_4s, "suqadd v6.4s, v27.4s", 6, 27)
3901 GEN_TWOVEC_TEST(suqadd_2s_2s, "suqadd v6.2s, v27.2s", 6, 27)
3902 GEN_TWOVEC_TEST(suqadd_8h_8h, "suqadd v6.8h, v27.8h", 6, 27)
3903 GEN_TWOVEC_TEST(suqadd_4h_4h, "suqadd v6.4h, v27.4h", 6, 27)
3904 GEN_TWOVEC_TEST(suqadd_16b_16b, "suqadd v6.16b, v27.16b", 6, 27)
3905 GEN_TWOVEC_TEST(suqadd_8b_8b, "suqadd v6.8b, v27.8b", 6, 27)
3906 GEN_TWOVEC_TEST(usqadd_2d_2d, "usqadd v6.2d, v27.2d", 6, 27)
3907 GEN_TWOVEC_TEST(usqadd_4s_4s, "usqadd v6.4s, v27.4s", 6, 27)
3908 GEN_TWOVEC_TEST(usqadd_2s_2s, "usqadd v6.2s, v27.2s", 6, 27)
3909 GEN_TWOVEC_TEST(usqadd_8h_8h, "usqadd v6.8h, v27.8h", 6, 27)
3910 GEN_TWOVEC_TEST(usqadd_4h_4h, "usqadd v6.4h, v27.4h", 6, 27)
3911 GEN_TWOVEC_TEST(usqadd_16b_16b, "usqadd v6.16b, v27.16b", 6, 27)
3912 GEN_TWOVEC_TEST(usqadd_8b_8b, "usqadd v6.8b, v27.8b", 6, 27)
3913
3914 // Uses v15 as the first table entry
3915 GEN_THREEVEC_TEST(
3916 tbl_16b_1reg, "tbl v21.16b, {v15.16b}, v23.16b", 21, 15, 23)
3917 // and v15 ^ v21 as the second table entry
3918 GEN_THREEVEC_TEST(
3919 tbl_16b_2reg, "eor v16.16b, v15.16b, v21.16b ; "
3920 "tbl v21.16b, {v15.16b, v16.16b}, v23.16b", 21, 15, 23)
3921 // and v15 ^ v23 as the third table entry
3922 GEN_THREEVEC_TEST(
3923 tbl_16b_3reg, "eor v16.16b, v15.16b, v21.16b ; "
3924 "eor v17.16b, v15.16b, v23.16b ; "
3925 "tbl v21.16b, {v15.16b, v16.16b, v17.16b}, v23.16b",
3926 21, 15, 23)
3927 // and v21 ^ v23 as the fourth table entry
3928 GEN_THREEVEC_TEST(
3929 tbl_16b_4reg, "eor v16.16b, v15.16b, v21.16b ; "
3930 "eor v17.16b, v15.16b, v23.16b ; "
3931 "eor v18.16b, v21.16b, v23.16b ; "
3932 "tbl v21.16b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.16b",
3933 21, 15, 23)
3934 // Same register scheme for tbl .8b, tbx .16b, tbx.8b
3935 GEN_THREEVEC_TEST(
3936 tbl_8b_1reg, "tbl v21.8b, {v15.16b}, v23.8b", 21, 15, 23)
3937 GEN_THREEVEC_TEST(
3938 tbl_8b_2reg, "eor v16.16b, v15.16b, v21.16b ; "
3939 "tbl v21.8b, {v15.16b, v16.16b}, v23.8b", 21, 15, 23)
3940 GEN_THREEVEC_TEST(
3941 tbl_8b_3reg, "eor v16.16b, v15.16b, v21.16b ; "
3942 "eor v17.16b, v15.16b, v23.16b ; "
3943 "tbl v21.8b, {v15.16b, v16.16b, v17.16b}, v23.8b",
3944 21, 15, 23)
3945 GEN_THREEVEC_TEST(
3946 tbl_8b_4reg, "eor v16.16b, v15.16b, v21.16b ; "
3947 "eor v17.16b, v15.16b, v23.16b ; "
3948 "eor v18.16b, v21.16b, v23.16b ; "
3949 "tbl v21.8b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.8b",
3950 21, 15, 23)
3951
3952 GEN_THREEVEC_TEST(
3953 tbx_16b_1reg, "tbx v21.16b, {v15.16b}, v23.16b", 21, 15, 23)
3954 GEN_THREEVEC_TEST(
3955 tbx_16b_2reg, "eor v16.16b, v15.16b, v21.16b ; "
3956 "tbx v21.16b, {v15.16b, v16.16b}, v23.16b", 21, 15, 23)
3957 GEN_THREEVEC_TEST(
3958 tbx_16b_3reg, "eor v16.16b, v15.16b, v21.16b ; "
3959 "eor v17.16b, v15.16b, v23.16b ; "
3960 "tbx v21.16b, {v15.16b, v16.16b, v17.16b}, v23.16b",
3961 21, 15, 23)
3962 GEN_THREEVEC_TEST(
3963 tbx_16b_4reg, "eor v16.16b, v15.16b, v21.16b ; "
3964 "eor v17.16b, v15.16b, v23.16b ; "
3965 "eor v18.16b, v21.16b, v23.16b ; "
3966 "tbx v21.16b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.16b",
3967 21, 15, 23)
3968 // Same register scheme for tbx .8b, tbx .16b, tbx.8b
3969 GEN_THREEVEC_TEST(
3970 tbx_8b_1reg, "tbx v21.8b, {v15.16b}, v23.8b", 21, 15, 23)
3971 GEN_THREEVEC_TEST(
3972 tbx_8b_2reg, "eor v16.16b, v15.16b, v21.16b ; "
3973 "tbx v21.8b, {v15.16b, v16.16b}, v23.8b", 21, 15, 23)
3974 GEN_THREEVEC_TEST(
3975 tbx_8b_3reg, "eor v16.16b, v15.16b, v21.16b ; "
3976 "eor v17.16b, v15.16b, v23.16b ; "
3977 "tbx v21.8b, {v15.16b, v16.16b, v17.16b}, v23.8b",
3978 21, 15, 23)
3979 GEN_THREEVEC_TEST(
3980 tbx_8b_4reg, "eor v16.16b, v15.16b, v21.16b ; "
3981 "eor v17.16b, v15.16b, v23.16b ; "
3982 "eor v18.16b, v21.16b, v23.16b ; "
3983 "tbx v21.8b, {v15.16b, v16.16b, v17.16b, v18.16b}, v23.8b",
3984 21, 15, 23)
3985
3986 GEN_THREEVEC_TEST(trn1_2d_2d_2d, "trn1 v1.2d, v2.2d, v4.2d", 1, 2, 4)
3987 GEN_THREEVEC_TEST(trn1_4s_4s_4s, "trn1 v1.4s, v2.4s, v4.4s", 1, 2, 4)
3988 GEN_THREEVEC_TEST(trn1_2s_2s_2s, "trn1 v1.2s, v2.2s, v4.2s", 1, 2, 4)
3989 GEN_THREEVEC_TEST(trn1_8h_8h_8h, "trn1 v1.8h, v2.8h, v4.8h", 1, 2, 4)
3990 GEN_THREEVEC_TEST(trn1_4h_4h_4h, "trn1 v1.4h, v2.4h, v4.4h", 1, 2, 4)
3991 GEN_THREEVEC_TEST(trn1_16b_16b_16b, "trn1 v1.16b, v2.16b, v4.16b", 1, 2, 4)
3992 GEN_THREEVEC_TEST(trn1_8b_8b_8b, "trn1 v1.8b, v2.8b, v4.8b", 1, 2, 4)
3993 GEN_THREEVEC_TEST(trn2_2d_2d_2d, "trn2 v1.2d, v2.2d, v4.2d", 1, 2, 4)
3994 GEN_THREEVEC_TEST(trn2_4s_4s_4s, "trn2 v1.4s, v2.4s, v4.4s", 1, 2, 4)
3995 GEN_THREEVEC_TEST(trn2_2s_2s_2s, "trn2 v1.2s, v2.2s, v4.2s", 1, 2, 4)
3996 GEN_THREEVEC_TEST(trn2_8h_8h_8h, "trn2 v1.8h, v2.8h, v4.8h", 1, 2, 4)
3997 GEN_THREEVEC_TEST(trn2_4h_4h_4h, "trn2 v1.4h, v2.4h, v4.4h", 1, 2, 4)
3998 GEN_THREEVEC_TEST(trn2_16b_16b_16b, "trn2 v1.16b, v2.16b, v4.16b", 1, 2, 4)
3999 GEN_THREEVEC_TEST(trn2_8b_8b_8b, "trn2 v1.8b, v2.8b, v4.8b", 1, 2, 4)
4000
4001 GEN_TWOVEC_TEST(urecpe_4s_4s, "urecpe v6.4s, v27.4s", 6, 27)
4002 GEN_TWOVEC_TEST(urecpe_2s_2s, "urecpe v6.2s, v27.2s", 6, 27)
4003 GEN_TWOVEC_TEST(ursqrte_4s_4s, "ursqrte v6.4s, v27.4s", 6, 27)
4004 GEN_TWOVEC_TEST(ursqrte_2s_2s, "ursqrte v6.2s, v27.2s", 6, 27)
4005
4006 GEN_THREEVEC_TEST(uzp1_2d_2d_2d, "uzp1 v1.2d, v2.2d, v4.2d", 1, 2, 4)
4007 GEN_THREEVEC_TEST(uzp1_4s_4s_4s, "uzp1 v1.4s, v2.4s, v4.4s", 1, 2, 4)
4008 GEN_THREEVEC_TEST(uzp1_2s_2s_2s, "uzp1 v1.2s, v2.2s, v4.2s", 1, 2, 4)
4009 GEN_THREEVEC_TEST(uzp1_8h_8h_8h, "uzp1 v1.8h, v2.8h, v4.8h", 1, 2, 4)
4010 GEN_THREEVEC_TEST(uzp1_4h_4h_4h, "uzp1 v1.4h, v2.4h, v4.4h", 1, 2, 4)
4011 GEN_THREEVEC_TEST(uzp1_16b_16b_16b, "uzp1 v1.16b, v2.16b, v4.16b", 1, 2, 4)
4012 GEN_THREEVEC_TEST(uzp1_8b_8b_8b, "uzp1 v1.8b, v2.8b, v4.8b", 1, 2, 4)
4013 GEN_THREEVEC_TEST(uzp2_2d_2d_2d, "uzp2 v1.2d, v2.2d, v4.2d", 1, 2, 4)
4014 GEN_THREEVEC_TEST(uzp2_4s_4s_4s, "uzp2 v1.4s, v2.4s, v4.4s", 1, 2, 4)
4015 GEN_THREEVEC_TEST(uzp2_2s_2s_2s, "uzp2 v1.2s, v2.2s, v4.2s", 1, 2, 4)
4016 GEN_THREEVEC_TEST(uzp2_8h_8h_8h, "uzp2 v1.8h, v2.8h, v4.8h", 1, 2, 4)
4017 GEN_THREEVEC_TEST(uzp2_4h_4h_4h, "uzp2 v1.4h, v2.4h, v4.4h", 1, 2, 4)
4018 GEN_THREEVEC_TEST(uzp2_16b_16b_16b, "uzp2 v1.16b, v2.16b, v4.16b", 1, 2, 4)
4019 GEN_THREEVEC_TEST(uzp2_8b_8b_8b, "uzp2 v1.8b, v2.8b, v4.8b", 1, 2, 4)
4020 GEN_THREEVEC_TEST(zip1_2d_2d_2d, "zip1 v1.2d, v2.2d, v4.2d", 1, 2, 4)
4021 GEN_THREEVEC_TEST(zip1_4s_4s_4s, "zip1 v1.4s, v2.4s, v4.4s", 1, 2, 4)
4022 GEN_THREEVEC_TEST(zip1_2s_2s_2s, "zip1 v1.2s, v2.2s, v4.2s", 1, 2, 4)
4023 GEN_THREEVEC_TEST(zip1_8h_8h_8h, "zip1 v1.8h, v2.8h, v4.8h", 1, 2, 4)
4024 GEN_THREEVEC_TEST(zip1_4h_4h_4h, "zip1 v1.4h, v2.4h, v4.4h", 1, 2, 4)
4025 GEN_THREEVEC_TEST(zip1_16b_16b_16b, "zip1 v1.16b, v2.16b, v4.16b", 1, 2, 4)
4026 GEN_THREEVEC_TEST(zip1_8b_8b_8b, "zip1 v1.8b, v2.8b, v4.8b", 1, 2, 4)
4027 GEN_THREEVEC_TEST(zip2_2d_2d_2d, "zip2 v1.2d, v2.2d, v4.2d", 1, 2, 4)
4028 GEN_THREEVEC_TEST(zip2_4s_4s_4s, "zip2 v1.4s, v2.4s, v4.4s", 1, 2, 4)
4029 GEN_THREEVEC_TEST(zip2_2s_2s_2s, "zip2 v1.2s, v2.2s, v4.2s", 1, 2, 4)
4030 GEN_THREEVEC_TEST(zip2_8h_8h_8h, "zip2 v1.8h, v2.8h, v4.8h", 1, 2, 4)
4031 GEN_THREEVEC_TEST(zip2_4h_4h_4h, "zip2 v1.4h, v2.4h, v4.4h", 1, 2, 4)
4032 GEN_THREEVEC_TEST(zip2_16b_16b_16b, "zip2 v1.16b, v2.16b, v4.16b", 1, 2, 4)
4033 GEN_THREEVEC_TEST(zip2_8b_8b_8b, "zip2 v1.8b, v2.8b, v4.8b", 1, 2, 4)
4034
4035 GEN_UNARY_TEST(xtn, 2s, 2d)
4036 GEN_UNARY_TEST(xtn2, 4s, 2d)
4037 GEN_UNARY_TEST(xtn, 4h, 4s)
4038 GEN_UNARY_TEST(xtn2, 8h, 4s)
4039 GEN_UNARY_TEST(xtn, 8b, 8h)
4040 GEN_UNARY_TEST(xtn2, 16b, 8h)
4041
4042 // ======================== MEM ========================
4043
4044 // All the SIMD and FP memory tests are in none/tests/arm64/memory.c.
4045
4046 // ======================== CRYPTO ========================
4047
4048 GEN_TWOVEC_TEST(aesd_16b_16b, "aesd v6.16b, v27.16b", 6, 27)
4049 GEN_TWOVEC_TEST(aese_16b_16b, "aese v6.16b, v27.16b", 6, 27)
4050 GEN_TWOVEC_TEST(aesimc_16b_16b, "aesimc v6.16b, v27.16b", 6, 27)
4051 GEN_TWOVEC_TEST(aesmc_16b_16b, "aesmc v6.16b, v27.16b", 6, 27)
4052
4053 GEN_THREEVEC_TEST(sha1c_q_s_4s, "sha1c q29, s28, v27.4s", 29,28,27)
4054 GEN_TWOVEC_TEST(sha1h_s_s, "sha1h s6, s27", 6, 27)
4055 GEN_THREEVEC_TEST(sha1m_q_s_4s, "sha1m q29, s28, v27.4s", 29,28,27)
4056 GEN_THREEVEC_TEST(sha1p_q_s_4s, "sha1p q29, s28, v27.4s", 29,28,27)
4057 GEN_THREEVEC_TEST(sha1su0_4s_4s_4s, "sha1su0 v29.4s, v28.4s, v27.4s", 29,28,27)
4058 GEN_TWOVEC_TEST(sha1su1_4s_4s, "sha1su1 v6.4s, v27.4s", 6, 27)
4059
4060 GEN_THREEVEC_TEST(sha256h2_q_q_4s, "sha256h2 q29, q28, v27.4s", 29,28,27)
4061 GEN_THREEVEC_TEST(sha256h_q_q_4s, "sha256h q29, q28, v27.4s", 29,28,27)
4062 GEN_TWOVEC_TEST(sha256su0_4s_4s, "sha256su0 v6.4s, v27.4s", 6, 27)
4063 GEN_THREEVEC_TEST(sha256su1_4s_4s_4s, "sha256su1 v29.4s, v28.4s, v27.4s",
4064 29,28,27)
4065
4066
4067 /* ---------------------------------------------------------------- */
4068 /* -- main() -- */
4069 /* ---------------------------------------------------------------- */
4070
4071 int main ( void )
4072 {
4073 assert(sizeof(V128) == 16);
4074
4075 // ======================== FP ========================
4076
4077 // fabs d,s
4078 // fabs 2d,4s,2s
4079 if (1) test_fabs_d_d(TyDF);
4080 if (1) test_fabs_s_s(TySF);
4081 if (1) test_fabs_2d_2d(TyDF);
4082 if (1) test_fabs_4s_4s(TySF);
4083 if (1) test_fabs_2s_2s(TyDF);
4084
4085 // fneg d,s
4086 // fneg 2d,4s,2s
4087 if (1) test_fneg_d_d(TyDF);
4088 if (1) test_fneg_s_s(TySF);
4089 if (1) test_fneg_2d_2d(TySF);
4090 if (1) test_fneg_4s_4s(TyDF);
4091 if (1) test_fneg_2s_2s(TySF);
4092
4093 // fsqrt d,s
4094 // fsqrt 2d,4s,2s
4095 if (1) test_fsqrt_d_d(TyDF);
4096 if (1) test_fsqrt_s_s(TySF);
4097 if (1) test_fsqrt_2d_2d(TySF);
4098 if (1) test_fsqrt_4s_4s(TyDF);
4099 if (1) test_fsqrt_2s_2s(TySF);
4100
4101 // fadd d,s
4102 // fsub d,s
4103 if (1) test_fadd_d_d_d(TyDF);
4104 if (1) test_fadd_s_s_s(TySF);
4105 if (1) test_fsub_d_d_d(TyDF);
4106 if (1) test_fsub_s_s_s(TySF);
4107
4108 // fadd 2d,4s,2s
4109 // fsub 2d,4s,2s
4110 if (1) test_fadd_2d_2d_2d(TyDF);
4111 if (1) test_fadd_4s_4s_4s(TySF);
4112 if (1) test_fadd_2s_2s_2s(TySF);
4113 if (1) test_fsub_2d_2d_2d(TyDF);
4114 if (1) test_fsub_4s_4s_4s(TySF);
4115 if (1) test_fsub_2s_2s_2s(TySF);
4116
4117 // fabd d,s
4118 // fabd 2d,4s,2s
4119 if (1) test_fabd_d_d_d(TyDF);
4120 if (1) test_fabd_s_s_s(TySF);
4121 if (1) test_fabd_2d_2d_2d(TyDF);
4122 if (1) test_fabd_4s_4s_4s(TySF);
4123 if (1) test_fabd_2s_2s_2s(TySF);
4124
4125 // faddp d,s (floating add pair)
4126 // faddp 2d,4s,2s
4127 if (1) test_faddp_d_2d(TyDF);
4128 if (1) test_faddp_s_2s(TySF);
4129 if (1) test_faddp_2d_2d_2d(TySF);
4130 if (1) test_faddp_4s_4s_4s(TyDF);
4131 if (1) test_faddp_2s_2s_2s(TySF);
4132
4133 // fccmp d,s (floating point conditional quiet compare)
4134 // fccmpe d,s (floating point conditional signaling compare)
4135 if (1) DO50( test_FCCMP_D_D_0xF_EQ() );
4136 if (1) DO50( test_FCCMP_D_D_0xF_NE() );
4137 if (1) DO50( test_FCCMP_D_D_0x0_EQ() );
4138 if (1) DO50( test_FCCMP_D_D_0x0_NE() );
4139 if (1) DO50( test_FCCMP_S_S_0xF_EQ() );
4140 if (1) DO50( test_FCCMP_S_S_0xF_NE() );
4141 if (1) DO50( test_FCCMP_S_S_0x0_EQ() );
4142 if (1) DO50( test_FCCMP_S_S_0x0_NE() );
4143 if (1) DO50( test_FCCMPE_D_D_0xF_EQ() );
4144 if (1) DO50( test_FCCMPE_D_D_0xF_NE() );
4145 if (1) DO50( test_FCCMPE_D_D_0x0_EQ() );
4146 if (1) DO50( test_FCCMPE_D_D_0x0_NE() );
4147 if (1) DO50( test_FCCMPE_S_S_0xF_EQ() );
4148 if (1) DO50( test_FCCMPE_S_S_0xF_NE() );
4149 if (1) DO50( test_FCCMPE_S_S_0x0_EQ() );
4150 if (1) DO50( test_FCCMPE_S_S_0x0_NE() );
4151
4152 // fcmeq d,s
4153 // fcmge d,s
4154 // fcmgt d,s
4155 // facgt d,s (floating abs compare GE)
4156 // facge d,s (floating abs compare GE)
4157 if (1) DO50( test_FCMEQ_D_D_D() );
4158 if (1) DO50( test_FCMEQ_S_S_S() );
4159 if (1) DO50( test_FCMGE_D_D_D() );
4160 if (1) DO50( test_FCMGE_S_S_S() );
4161 if (1) DO50( test_FCMGT_D_D_D() );
4162 if (1) DO50( test_FCMGT_S_S_S() );
4163 if (1) DO50( test_FACGT_D_D_D() );
4164 if (1) DO50( test_FACGT_S_S_S() );
4165 if (1) DO50( test_FACGE_D_D_D() );
4166 if (1) DO50( test_FACGE_S_S_S() );
4167
4168 // fcmeq 2d,4s,2s
4169 // fcmge 2d,4s,2s
4170 // fcmgt 2d,4s,2s
4171 // facge 2d,4s,2s
4172 // facgt 2d,4s,2s
4173 if (1) test_fcmeq_2d_2d_2d(TyDF);
4174 if (1) test_fcmeq_4s_4s_4s(TySF);
4175 if (1) test_fcmeq_2s_2s_2s(TySF);
4176 if (1) test_fcmge_2d_2d_2d(TyDF);
4177 if (1) test_fcmge_4s_4s_4s(TySF);
4178 if (1) test_fcmge_2s_2s_2s(TySF);
4179 if (1) test_fcmgt_2d_2d_2d(TyDF);
4180 if (1) test_fcmgt_4s_4s_4s(TySF);
4181 if (1) test_fcmgt_2s_2s_2s(TySF);
4182 if (1) test_facge_2d_2d_2d(TyDF);
4183 if (1) test_facge_4s_4s_4s(TySF);
4184 if (1) test_facge_2s_2s_2s(TySF);
4185 if (1) test_facgt_2d_2d_2d(TyDF);
4186 if (1) test_facgt_4s_4s_4s(TySF);
4187 if (1) test_facgt_2s_2s_2s(TySF);
4188
4189 // fcmeq_z d,s
4190 // fcmge_z d,s
4191 // fcmgt_z d,s
4192 // fcmle_z d,s
4193 // fcmlt_z d,s
4194 if (1) DO50( test_FCMEQ_D_D_Z() );
4195 if (1) DO50( test_FCMEQ_S_S_Z() );
4196 if (1) DO50( test_FCMGE_D_D_Z() );
4197 if (1) DO50( test_FCMGE_S_S_Z() );
4198 if (1) DO50( test_FCMGT_D_D_Z() );
4199 if (1) DO50( test_FCMGT_S_S_Z() );
4200 if (1) DO50( test_FCMLE_D_D_Z() );
4201 if (1) DO50( test_FCMLE_S_S_Z() );
4202 if (1) DO50( test_FCMLT_D_D_Z() );
4203 if (1) DO50( test_FCMLT_S_S_Z() );
4204
4205 // fcmeq_z 2d,4s,2s
4206 // fcmge_z 2d,4s,2s
4207 // fcmgt_z 2d,4s,2s
4208 // fcmle_z 2d,4s,2s
4209 // fcmlt_z 2d,4s,2s
4210 if (1) test_fcmeq_z_2d_2d(TyDF);
4211 if (1) test_fcmeq_z_4s_4s(TySF);
4212 if (1) test_fcmeq_z_2s_2s(TySF);
4213 if (1) test_fcmge_z_2d_2d(TyDF);
4214 if (1) test_fcmge_z_4s_4s(TySF);
4215 if (1) test_fcmge_z_2s_2s(TySF);
4216 if (1) test_fcmgt_z_2d_2d(TyDF);
4217 if (1) test_fcmgt_z_4s_4s(TySF);
4218 if (1) test_fcmgt_z_2s_2s(TySF);
4219 if (1) test_fcmle_z_2d_2d(TyDF);
4220 if (1) test_fcmle_z_4s_4s(TySF);
4221 if (1) test_fcmle_z_2s_2s(TySF);
4222 if (1) test_fcmlt_z_2d_2d(TyDF);
4223 if (1) test_fcmlt_z_4s_4s(TySF);
4224 if (1) test_fcmlt_z_2s_2s(TySF);
4225
4226 // fcmp_z d,s
4227 // fcmpe_z d,s
4228 // fcmp d,s (floating point quiet, set flags)
4229 // fcmpe d,s (floating point signaling, set flags)
4230 if (1) DO50( test_FCMP_D_Z() );
4231 if (1) DO50( test_FCMP_S_Z() );
4232 if (1) DO50( test_FCMPE_D_Z() );
4233 if (1) DO50( test_FCMPE_S_Z() );
4234 if (1) DO50( test_FCMP_D_D() );
4235 if (1) DO50( test_FCMP_S_S() );
4236 if (1) DO50( test_FCMPE_D_D() );
4237 if (1) DO50( test_FCMPE_S_S() );
4238
4239 // fcsel d,s (fp cond select)
4240 if (1) DO50( test_FCSEL_D_D_D_EQ() );
4241 if (1) DO50( test_FCSEL_D_D_D_NE() );
4242 if (1) DO50( test_FCSEL_S_S_S_EQ() );
4243 if (1) DO50( test_FCSEL_S_S_S_NE() );
4244
4245 // fdiv d,s
4246 // fdiv 2d,4s,2s
4247 if (1) test_fdiv_d_d_d(TyDF);
4248 if (1) test_fdiv_s_s_s(TySF);
4249 if (1) test_fdiv_2d_2d_2d(TyDF);
4250 if (1) test_fdiv_4s_4s_4s(TySF);
4251 if (1) test_fdiv_2s_2s_2s(TySF);
4252
4253 // fmadd d,s
4254 // fnmadd d,s
4255 // fmsub d,s
4256 // fnmsub d,s
4257 if (1) test_fmadd_d_d_d_d(TyDF);
4258 if (1) test_fmadd_s_s_s_s(TySF);
4259 if (1) test_fnmadd_d_d_d_d(TyDF);
4260 if (1) test_fnmadd_s_s_s_s(TySF);
4261 if (1) test_fmsub_d_d_d_d(TyDF);
4262 if (1) test_fmsub_s_s_s_s(TySF);
4263 if (1) test_fnmsub_d_d_d_d(TyDF);
4264 if (1) test_fnmsub_s_s_s_s(TySF);
4265
4266 // fnmul d,s
4267 if (1) test_fnmul_d_d_d(TyDF);
4268 if (1) test_fnmul_s_s_s(TySF);
4269
4270 // fmax d,s
4271 // fmin d,s
4272 // fmaxnm d,s ("max number")
4273 // fminnm d,s
4274 if (1) test_fmax_d_d_d(TyDF);
4275 if (1) test_fmax_s_s_s(TySF);
4276 if (1) test_fmin_d_d_d(TyDF);
4277 if (1) test_fmin_s_s_s(TySF);
4278 if (1) test_fmaxnm_d_d_d(TyDF);
4279 if (1) test_fmaxnm_s_s_s(TySF);
4280 if (1) test_fminnm_d_d_d(TyDF);
4281 if (1) test_fminnm_s_s_s(TySF);
4282
4283 // fmax 2d,4s,2s
4284 // fmin 2d,4s,2s
4285 // fmaxnm 2d,4s,2s
4286 // fminnm 2d,4s,2s
4287 if (1) test_fmax_2d_2d_2d(TyDF);
4288 if (1) test_fmax_4s_4s_4s(TySF);
4289 if (1) test_fmax_2s_2s_2s(TySF);
4290 if (1) test_fmin_2d_2d_2d(TyDF);
4291 if (1) test_fmin_4s_4s_4s(TySF);
4292 if (1) test_fmin_2s_2s_2s(TySF);
4293 if (1) test_fmaxnm_2d_2d_2d(TyDF);
4294 if (1) test_fmaxnm_4s_4s_4s(TySF);
4295 if (1) test_fmaxnm_2s_2s_2s(TySF);
4296 if (1) test_fminnm_2d_2d_2d(TyDF);
4297 if (1) test_fminnm_4s_4s_4s(TySF);
4298 if (1) test_fminnm_2s_2s_2s(TySF);
4299
4300 // fmaxnmp d_2d,s_2s ("max number pairwise")
4301 // fminnmp d_2d,s_2s
4302 if (1) test_fmaxnmp_d_2d(TyDF);
4303 if (1) test_fmaxnmp_s_2s(TySF);
4304 if (1) test_fminnmp_d_2d(TyDF);
4305 if (1) test_fminnmp_s_2s(TySF);
4306
4307 // fmaxnmp 2d,4s,2s
4308 // fminnmp 2d,4s,2s
4309 if (1) test_fmaxnmp_2d_2d_2d(TyDF);
4310 if (1) test_fmaxnmp_4s_4s_4s(TySF);
4311 if (1) test_fmaxnmp_2s_2s_2s(TySF);
4312 if (1) test_fminnmp_2d_2d_2d(TyDF);
4313 if (1) test_fminnmp_4s_4s_4s(TySF);
4314 if (1) test_fminnmp_2s_2s_2s(TySF);
4315
4316 // fmaxnmv s_4s (maxnum across vector)
4317 // fminnmv s_4s
4318 if (1) test_fmaxnmv_s_4s(TySF);
4319 if (1) test_fminnmv_s_4s(TySF);
4320
4321 // fmaxp d_2d,s_2s (max of a pair)
4322 // fminp d_2d,s_2s (max of a pair)
4323 if (1) test_fmaxp_d_2d(TyDF);
4324 if (1) test_fmaxp_s_2s(TySF);
4325 if (1) test_fminp_d_2d(TyDF);
4326 if (1) test_fminp_s_2s(TySF);
4327
4328 // fmaxp 2d,4s,2s (max pairwise)
4329 // fminp 2d,4s,2s
4330 if (1) test_fmaxp_2d_2d_2d(TyDF);
4331 if (1) test_fmaxp_4s_4s_4s(TySF);
4332 if (1) test_fmaxp_2s_2s_2s(TySF);
4333 if (1) test_fminp_2d_2d_2d(TyDF);
4334 if (1) test_fminp_4s_4s_4s(TySF);
4335 if (1) test_fminp_2s_2s_2s(TySF);
4336
4337 // fmaxv s_4s (max across vector)
4338 // fminv s_4s
4339 if (1) test_fmaxv_s_4s(TySF);
4340 if (1) test_fminv_s_4s(TySF);
4341
4342 // fmla 2d,4s,2s
4343 // fmls 2d,4s,2s
4344 if (1) test_fmla_2d_2d_2d(TyDF);
4345 if (1) test_fmla_4s_4s_4s(TySF);
4346 if (1) test_fmla_2s_2s_2s(TySF);
4347 if (1) test_fmls_2d_2d_2d(TyDF);
4348 if (1) test_fmls_4s_4s_4s(TySF);
4349 if (1) test_fmls_2s_2s_2s(TySF);
4350
4351 // fmla d_d_d[],s_s_s[] (by element)
4352 // fmls d_d_d[],s_s_s[] (by element)
4353 if (1) test_fmla_d_d_d0(TyDF);
4354 if (1) test_fmla_d_d_d1(TyDF);
4355 if (1) test_fmla_s_s_s0(TySF);
4356 if (1) test_fmla_s_s_s3(TySF);
4357 if (1) test_fmls_d_d_d0(TyDF);
4358 if (1) test_fmls_d_d_d1(TyDF);
4359 if (1) test_fmls_s_s_s0(TySF);
4360 if (1) test_fmls_s_s_s3(TySF);
4361
4362 // fmla 2d_2d_d[],4s_4s_s[],2s_2s_s[]
4363 // fmls 2d_2d_d[],4s_4s_s[],2s_2s_s[]
4364 if (1) test_fmla_2d_2d_d0(TyDF);
4365 if (1) test_fmla_2d_2d_d1(TyDF);
4366 if (1) test_fmla_4s_4s_s0(TySF);
4367 if (1) test_fmla_4s_4s_s3(TySF);
4368 if (1) test_fmla_2s_2s_s0(TySF);
4369 if (1) test_fmla_2s_2s_s3(TySF);
4370 if (1) test_fmls_2d_2d_d0(TyDF);
4371 if (1) test_fmls_2d_2d_d1(TyDF);
4372 if (1) test_fmls_4s_4s_s0(TySF);
4373 if (1) test_fmls_4s_4s_s3(TySF);
4374 if (1) test_fmls_2s_2s_s0(TySF);
4375 if (1) test_fmls_2s_2s_s3(TySF);
4376
4377 // fmov 2d,4s,2s #imm (part of the MOVI/MVNI/ORR/BIC imm group)
4378 if (1) test_fmov_2d_imm_01(TyD);
4379 if (1) test_fmov_2d_imm_02(TyD);
4380 if (1) test_fmov_2d_imm_03(TyD);
4381 if (1) test_fmov_4s_imm_01(TyS);
4382 if (1) test_fmov_4s_imm_02(TyS);
4383 if (1) test_fmov_4s_imm_03(TyS);
4384 if (1) test_fmov_2s_imm_01(TyS);
4385 if (1) test_fmov_2s_imm_02(TyS);
4386 if (1) test_fmov_2s_imm_03(TyS);
4387
4388 // fmov d_d,s_s
4389 if (1) test_fmov_d_d(TyDF);
4390 if (1) test_fmov_s_s(TySF);
4391
4392 // fmov s_w,w_s,d_x,d[1]_x,x_d,x_d[1]
4393 if (1) test_fmov_s_w(TyS);
4394 if (1) test_fmov_d_x(TyD);
4395 if (1) test_fmov_d1_x(TyD);
4396 if (1) test_fmov_w_s(TyS);
4397 if (1) test_fmov_x_d(TyD);
4398 if (1) test_fmov_x_d1(TyD);
4399
4400 // fmov d,s #imm
4401 if (1) test_fmov_d_imm_01(TyNONE);
4402 if (1) test_fmov_d_imm_02(TyNONE);
4403 if (1) test_fmov_d_imm_03(TyNONE);
4404 if (1) test_fmov_s_imm_01(TyNONE);
4405 if (1) test_fmov_s_imm_02(TyNONE);
4406 if (1) test_fmov_s_imm_03(TyNONE);
4407
4408 // fmul d_d_d[],s_s_s[]
4409 if (1) test_fmul_d_d_d0(TyDF);
4410 if (1) test_fmul_d_d_d1(TyDF);
4411 if (1) test_fmul_s_s_s0(TySF);
4412 if (1) test_fmul_s_s_s3(TySF);
4413
4414 // fmul 2d_2d_d[],4s_4s_s[],2s_2s_s[]
4415 if (1) test_fmul_2d_2d_d0(TyDF);
4416 if (1) test_fmul_2d_2d_d1(TyDF);
4417 if (1) test_fmul_4s_4s_s0(TySF);
4418 if (1) test_fmul_4s_4s_s3(TySF);
4419 if (1) test_fmul_2s_2s_s0(TySF);
4420 if (1) test_fmul_2s_2s_s3(TySF);
4421
4422 // fmul d,s
4423 // fmul 2d,4s,2s
4424 if (1) test_fmul_d_d_d(TyDF);
4425 if (1) test_fmul_s_s_s(TySF);
4426 if (1) test_fmul_2d_2d_2d(TyDF);
4427 if (1) test_fmul_4s_4s_4s(TySF);
4428 if (1) test_fmul_2s_2s_2s(TySF);
4429
4430 // fmulx d_d_d[],s_s_s[]
4431 // fmulx 2d_2d_d[],4s_4s_s[],2s_2s_s[]
4432 if (1) test_fmulx_d_d_d0(TyDF);
4433 if (1) test_fmulx_d_d_d1(TyDF);
4434 if (1) test_fmulx_s_s_s0(TySF);
4435 if (1) test_fmulx_s_s_s3(TySF);
4436 if (1) test_fmulx_2d_2d_d0(TyDF);
4437 if (1) test_fmulx_2d_2d_d1(TyDF);
4438 if (1) test_fmulx_4s_4s_s0(TySF);
4439 if (1) test_fmulx_4s_4s_s3(TySF);
4440 if (1) test_fmulx_2s_2s_s0(TySF);
4441 if (1) test_fmulx_2s_2s_s3(TySF);
4442
4443 // fmulx d,s
4444 // fmulx 2d,4s,2s
4445 if (1) test_fmulx_d_d_d(TyDF);
4446 if (1) test_fmulx_s_s_s(TySF);
4447 if (1) test_fmulx_2d_2d_2d(TyDF);
4448 if (1) test_fmulx_4s_4s_4s(TySF);
4449 if (1) test_fmulx_2s_2s_2s(TySF);
4450
4451 // frecpe d,s (recip estimate)
4452 // frecpe 2d,4s,2s
4453 if (1) test_frecpe_d_d(TyDF);
4454 if (1) test_frecpe_s_s(TySF);
4455 if (1) test_frecpe_2d_2d(TyDF);
4456 if (1) test_frecpe_4s_4s(TySF);
4457 if (1) test_frecpe_2s_2s(TySF);
4458
4459 // frecps d,s (recip step)
4460 // frecps 2d,4s,2s
4461 if (1) test_frecps_d_d_d(TyDF);
4462 if (1) test_frecps_s_s_s(TySF);
4463 if (1) test_frecps_2d_2d_2d(TyDF);
4464 if (1) test_frecps_4s_4s_4s(TySF);
4465 if (1) test_frecps_2s_2s_2s(TySF);
4466
4467 // frecpx d,s (recip exponent)
4468 if (1) test_frecpx_d_d(TyDF);
4469 if (1) test_frecpx_s_s(TySF);
4470
4471 // frinta d,s
4472 // frinti d,s
4473 // frintm d,s
4474 // frintn d,s
4475 // frintp d,s
4476 // frintx d,s
4477 // frintz d,s
4478 if (1) test_frinta_d_d(TyDF);
4479 if (1) test_frinta_s_s(TySF);
4480 if (1) test_frinti_d_d(TyDF);
4481 if (1) test_frinti_s_s(TySF);
4482 if (1) test_frintm_d_d(TyDF);
4483 if (1) test_frintm_s_s(TySF);
4484 if (1) test_frintn_d_d(TyDF);
4485 if (1) test_frintn_s_s(TySF);
4486 if (1) test_frintp_d_d(TyDF);
4487 if (1) test_frintp_s_s(TySF);
4488 if (1) test_frintx_d_d(TyDF);
4489 if (1) test_frintx_s_s(TySF);
4490 if (1) test_frintz_d_d(TyDF);
4491 if (1) test_frintz_s_s(TySF);
4492
4493 // frinta 2d,4s,2s (round to integral, nearest away)
4494 // frinti 2d,4s,2s (round to integral, per FPCR)
4495 // frintm 2d,4s,2s (round to integral, minus inf)
4496 // frintn 2d,4s,2s (round to integral, nearest, to even)
4497 // frintp 2d,4s,2s (round to integral, plus inf)
4498 // frintx 2d,4s,2s (round to integral exact, per FPCR)
4499 // frintz 2d,4s,2s (round to integral, zero)
4500 if (1) test_frinta_2d_2d(TyDF);
4501 if (1) test_frinta_4s_4s(TySF);
4502 if (1) test_frinta_2s_2s(TySF);
4503 if (1) test_frinti_2d_2d(TyDF);
4504 if (1) test_frinti_4s_4s(TySF);
4505 if (1) test_frinti_2s_2s(TySF);
4506 if (1) test_frintm_2d_2d(TyDF);
4507 if (1) test_frintm_4s_4s(TySF);
4508 if (1) test_frintm_2s_2s(TySF);
4509 if (1) test_frintn_2d_2d(TyDF);
4510 if (1) test_frintn_4s_4s(TySF);
4511 if (1) test_frintn_2s_2s(TySF);
4512 if (1) test_frintp_2d_2d(TyDF);
4513 if (1) test_frintp_4s_4s(TySF);
4514 if (1) test_frintp_2s_2s(TySF);
4515 if (1) test_frintx_2d_2d(TyDF);
4516 if (1) test_frintx_4s_4s(TySF);
4517 if (1) test_frintx_2s_2s(TySF);
4518 if (1) test_frintz_2d_2d(TyDF);
4519 if (1) test_frintz_4s_4s(TySF);
4520 if (1) test_frintz_2s_2s(TySF);
4521
4522 // frsqrte d,s (est)
4523 // frsqrte 2d,4s,2s
4524 if (1) test_frsqrte_d_d(TyDF);
4525 if (1) test_frsqrte_s_s(TySF);
4526 if (1) test_frsqrte_2d_2d(TyDF);
4527 if (1) test_frsqrte_4s_4s(TySF);
4528 if (1) test_frsqrte_2s_2s(TySF);
4529
4530 // frsqrts d,s (step)
4531 // frsqrts 2d,4s,2s
4532 if (1) test_frsqrts_d_d_d(TyDF);
4533 if (1) test_frsqrts_s_s_s(TySF);
4534 if (1) test_frsqrts_2d_2d_2d(TyDF);
4535 if (1) test_frsqrts_4s_4s_4s(TySF);
4536 if (1) test_frsqrts_2s_2s_2s(TySF);
4537
4538 // ======================== CONV ========================
4539
4540 // fcvt s_h,d_h,h_s,d_s,h_d,s_d (fp convert, scalar)
4541 if (1) test_fcvt_s_h(TyHF);
4542 if (1) test_fcvt_d_h(TyHF);
4543 if (1) test_fcvt_h_s(TySF);
4544 if (1) test_fcvt_d_s(TySF);
4545 if (1) test_fcvt_h_d(TyDF);
4546 if (1) test_fcvt_s_d(TyDF);
4547
4548 // fcvtl{2} 4s/4h, 4s/8h, 2d/2s, 2d/4s (float convert to longer form)
4549 if (1) test_fcvtl_4s_4h(TyHF);
4550 if (1) test_fcvtl_4s_8h(TyHF);
4551 if (1) test_fcvtl_2d_2s(TySF);
4552 if (1) test_fcvtl_2d_4s(TySF);
4553
4554 // fcvtn{2} 4h/4s, 8h/4s, 2s/2d, 4s/2d (float convert to narrower form)
4555 if (1) test_fcvtn_4h_4s(TySF);
4556 if (1) test_fcvtn_8h_4s(TySF);
4557 if (1) test_fcvtn_2s_2d(TyDF);
4558 if (1) test_fcvtn_4s_2d(TyDF);
4559
4560 // fcvtas d,s (fcvt to signed int, nearest, ties away)
4561 // fcvtau d,s (fcvt to unsigned int, nearest, ties away)
4562 // fcvtas 2d,4s,2s
4563 // fcvtau 2d,4s,2s
4564 // fcvtas w_s,x_s,w_d,x_d
4565 // fcvtau w_s,x_s,w_d,x_d
4566 if (1) test_fcvtas_d_d(TyDF);
4567 if (1) test_fcvtau_d_d(TyDF);
4568 if (1) test_fcvtas_s_s(TySF);
4569 if (1) test_fcvtau_s_s(TySF);
4570 if (1) test_fcvtas_2d_2d(TyDF);
4571 if (1) test_fcvtau_2d_2d(TyDF);
4572 if (1) test_fcvtas_4s_4s(TySF);
4573 if (1) test_fcvtau_4s_4s(TySF);
4574 if (1) test_fcvtas_2s_2s(TySF);
4575 if (1) test_fcvtau_2s_2s(TySF);
4576 if (1) test_fcvtas_w_s(TySF);
4577 if (1) test_fcvtau_w_s(TySF);
4578 if (1) test_fcvtas_x_s(TySF);
4579 if (1) test_fcvtau_x_s(TySF);
4580 if (1) test_fcvtas_w_d(TyDF);
4581 if (1) test_fcvtau_w_d(TyDF);
4582 if (1) test_fcvtas_x_d(TyDF);
4583 if (1) test_fcvtau_x_d(TyDF);
4584
4585 // fcvtms d,s (fcvt to signed int, minus inf)
4586 // fcvtmu d,s (fcvt to unsigned int, minus inf)
4587 // fcvtms 2d,4s,2s
4588 // fcvtmu 2d,4s,2s
4589 // fcvtms w_s,x_s,w_d,x_d
4590 // fcvtmu w_s,x_s,w_d,x_d
4591 if (1) test_fcvtms_d_d(TyDF);
4592 if (1) test_fcvtmu_d_d(TyDF);
4593 if (1) test_fcvtms_s_s(TySF);
4594 if (1) test_fcvtmu_s_s(TySF);
4595 if (1) test_fcvtms_2d_2d(TyDF);
4596 if (1) test_fcvtmu_2d_2d(TyDF);
4597 if (1) test_fcvtms_4s_4s(TySF);
4598 if (1) test_fcvtmu_4s_4s(TySF);
4599 if (1) test_fcvtms_2s_2s(TySF);
4600 if (1) test_fcvtmu_2s_2s(TySF);
4601 if (1) test_fcvtms_w_s(TySF);
4602 if (1) test_fcvtmu_w_s(TySF);
4603 if (1) test_fcvtms_x_s(TySF);
4604 if (1) test_fcvtmu_x_s(TySF);
4605 if (1) test_fcvtms_w_d(TyDF);
4606 if (1) test_fcvtmu_w_d(TyDF);
4607 if (1) test_fcvtms_x_d(TyDF);
4608 if (1) test_fcvtmu_x_d(TyDF);
4609
4610 // fcvtns d,s (fcvt to signed int, nearest)
4611 // fcvtnu d,s (fcvt to unsigned int, nearest)
4612 // fcvtns 2d,4s,2s
4613 // fcvtnu 2d,4s,2s
4614 // fcvtns w_s,x_s,w_d,x_d
4615 // fcvtnu w_s,x_s,w_d,x_d
4616 if (1) test_fcvtns_d_d(TyDF);
4617 if (1) test_fcvtnu_d_d(TyDF);
4618 if (1) test_fcvtns_s_s(TySF);
4619 if (1) test_fcvtnu_s_s(TySF);
4620 if (1) test_fcvtns_2d_2d(TyDF);
4621 if (1) test_fcvtnu_2d_2d(TyDF);
4622 if (1) test_fcvtns_4s_4s(TySF);
4623 if (1) test_fcvtnu_4s_4s(TySF);
4624 if (1) test_fcvtns_2s_2s(TySF);
4625 if (1) test_fcvtnu_2s_2s(TySF);
4626 if (1) test_fcvtns_w_s(TySF);
4627 if (1) test_fcvtnu_w_s(TySF);
4628 if (1) test_fcvtns_x_s(TySF);
4629 if (1) test_fcvtnu_x_s(TySF);
4630 if (1) test_fcvtns_w_d(TyDF);
4631 if (1) test_fcvtnu_w_d(TyDF);
4632 if (1) test_fcvtns_x_d(TyDF);
4633 if (1) test_fcvtnu_x_d(TyDF);
4634
4635 // fcvtps d,s (fcvt to signed int, plus inf)
4636 // fcvtpu d,s (fcvt to unsigned int, plus inf)
4637 // fcvtps 2d,4s,2s
4638 // fcvtpu 2d,4s,2s
4639 // fcvtps w_s,x_s,w_d,x_d
4640 // fcvtpu w_s,x_s,w_d,x_d
4641 if (1) test_fcvtps_d_d(TyDF);
4642 if (1) test_fcvtpu_d_d(TyDF);
4643 if (1) test_fcvtps_s_s(TySF);
4644 if (1) test_fcvtpu_s_s(TySF);
4645 if (1) test_fcvtps_2d_2d(TyDF);
4646 if (1) test_fcvtpu_2d_2d(TyDF);
4647 if (1) test_fcvtps_4s_4s(TySF);
4648 if (1) test_fcvtpu_4s_4s(TySF);
4649 if (1) test_fcvtps_2s_2s(TySF);
4650 if (1) test_fcvtpu_2s_2s(TySF);
4651 if (1) test_fcvtps_w_s(TySF);
4652 if (1) test_fcvtpu_w_s(TySF);
4653 if (1) test_fcvtps_x_s(TySF);
4654 if (1) test_fcvtpu_x_s(TySF);
4655 if (1) test_fcvtps_w_d(TyDF);
4656 if (1) test_fcvtpu_w_d(TyDF);
4657 if (1) test_fcvtps_x_d(TyDF);
4658 if (1) test_fcvtpu_x_d(TyDF);
4659
4660 // fcvtzs d,s (fcvt to signed integer, to zero)
4661 // fcvtzu d,s (fcvt to unsigned integer, to zero)
4662 // fcvtzs 2d,4s,2s
4663 // fcvtzu 2d,4s,2s
4664 // fcvtzs w_s,x_s,w_d,x_d
4665 // fcvtzu w_s,x_s,w_d,x_d
4666 if (1) test_fcvtzs_d_d(TyDF);
4667 if (1) test_fcvtzu_d_d(TyDF);
4668 if (1) test_fcvtzs_s_s(TySF);
4669 if (1) test_fcvtzu_s_s(TySF);
4670 if (1) test_fcvtzs_2d_2d(TyDF);
4671 if (1) test_fcvtzu_2d_2d(TyDF);
4672 if (1) test_fcvtzs_4s_4s(TySF);
4673 if (1) test_fcvtzu_4s_4s(TySF);
4674 if (1) test_fcvtzs_2s_2s(TySF);
4675 if (1) test_fcvtzu_2s_2s(TySF);
4676 if (1) test_fcvtzs_w_s(TySF);
4677 if (1) test_fcvtzu_w_s(TySF);
4678 if (1) test_fcvtzs_x_s(TySF);
4679 if (1) test_fcvtzu_x_s(TySF);
4680 if (1) test_fcvtzs_w_d(TyDF);
4681 if (1) test_fcvtzu_w_d(TyDF);
4682 if (1) test_fcvtzs_x_d(TyDF);
4683 if (1) test_fcvtzu_x_d(TyDF);
4684
4685 // fcvtzs d,s (fcvt to signed fixedpt, to zero) (w/ #fbits)
4686 // fcvtzu d,s (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
4687 // fcvtzs 2d,4s,2s (fcvt to signed fixedpt, to zero) (w/ #fbits)
4688 // fcvtzu 2d,4s,2s (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
4689 // fcvtzs w_s,x_s,w_d,x_d (fcvt to signed fixedpt, to zero) (w/ #fbits)
4690 // fcvtzu w_s,x_s,w_d,x_d (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
4691 if (1) test_fcvtzs_d_d_fbits1(TyDF);
4692 if (1) test_fcvtzs_d_d_fbits32(TyDF);
4693 if (1) test_fcvtzs_d_d_fbits64(TyDF);
4694 if (1) test_fcvtzu_d_d_fbits1(TyDF);
4695 if (1) test_fcvtzu_d_d_fbits32(TyDF);
4696 if (1) test_fcvtzu_d_d_fbits64(TyDF);
4697 if (1) test_fcvtzs_s_s_fbits1(TySF);
4698 if (1) test_fcvtzs_s_s_fbits16(TySF);
4699 if (1) test_fcvtzs_s_s_fbits32(TySF);
4700 if (1) test_fcvtzu_s_s_fbits1(TySF);
4701 if (1) test_fcvtzu_s_s_fbits16(TySF);
4702 if (1) test_fcvtzu_s_s_fbits32(TySF);
4703 if (1) test_fcvtzs_2d_2d_fbits1(TyDF);
4704 if (1) test_fcvtzs_2d_2d_fbits32(TyDF);
4705 if (1) test_fcvtzs_2d_2d_fbits64(TyDF);
4706 if (1) test_fcvtzu_2d_2d_fbits1(TyDF);
4707 if (1) test_fcvtzu_2d_2d_fbits32(TyDF);
4708 if (1) test_fcvtzu_2d_2d_fbits64(TyDF);
4709 if (1) test_fcvtzs_4s_4s_fbits1(TySF);
4710 if (1) test_fcvtzs_4s_4s_fbits16(TySF);
4711 if (1) test_fcvtzs_4s_4s_fbits32(TySF);
4712 if (1) test_fcvtzu_4s_4s_fbits1(TySF);
4713 if (1) test_fcvtzu_4s_4s_fbits16(TySF);
4714 if (1) test_fcvtzu_4s_4s_fbits32(TySF);
4715 if (1) test_fcvtzs_2s_2s_fbits1(TySF);
4716 if (1) test_fcvtzs_2s_2s_fbits16(TySF);
4717 if (1) test_fcvtzs_2s_2s_fbits32(TySF);
4718 if (1) test_fcvtzu_2s_2s_fbits1(TySF);
4719 if (1) test_fcvtzu_2s_2s_fbits16(TySF);
4720 if (1) test_fcvtzu_2s_2s_fbits32(TySF);
4721 if (1) test_fcvtzs_w_s_fbits1(TySF);
4722 if (1) test_fcvtzs_w_s_fbits16(TySF);
4723 if (1) test_fcvtzs_w_s_fbits32(TySF);
4724 if (1) test_fcvtzu_w_s_fbits1(TySF);
4725 if (1) test_fcvtzu_w_s_fbits16(TySF);
4726 if (1) test_fcvtzu_w_s_fbits32(TySF);
4727 if (1) test_fcvtzs_x_s_fbits1(TySF);
4728 if (1) test_fcvtzs_x_s_fbits32(TySF);
4729 if (1) test_fcvtzs_x_s_fbits64(TySF);
4730 if (1) test_fcvtzu_x_s_fbits1(TySF);
4731 if (1) test_fcvtzu_x_s_fbits32(TySF);
4732 if (1) test_fcvtzu_x_s_fbits64(TySF);
4733 if (1) test_fcvtzs_w_d_fbits1(TyDF);
4734 if (1) test_fcvtzs_w_d_fbits16(TyDF);
4735 if (1) test_fcvtzs_w_d_fbits32(TyDF);
4736 if (1) test_fcvtzu_w_d_fbits1(TyDF);
4737 if (1) test_fcvtzu_w_d_fbits16(TyDF);
4738 if (1) test_fcvtzu_w_d_fbits32(TyDF);
4739 if (1) test_fcvtzs_x_d_fbits1(TyDF);
4740 if (1) test_fcvtzs_x_d_fbits32(TyDF);
4741 if (1) test_fcvtzs_x_d_fbits64(TyDF);
4742 if (1) test_fcvtzu_x_d_fbits1(TyDF);
4743 if (1) test_fcvtzu_x_d_fbits32(TyDF);
4744 if (1) test_fcvtzu_x_d_fbits64(TyDF);
4745
4746 // fcvtxn s_d (fcvt to lower prec narrow, rounding to odd)
4747 // fcvtxn 2s_2d,4s_2d
4748 if (1) test_fcvtxn_s_d(TyDF);
4749 if (1) test_fcvtxn_2s_2d(TyDF);
4750 if (1) test_fcvtxn_4s_2d(TyDF);
4751
4752 // scvtf d,s _#fbits
4753 // ucvtf d,s _#fbits
4754 // scvtf 2d,4s,2s _#fbits
4755 // ucvtf 2d,4s,2s _#fbits
4756 if (1) test_scvtf_d_d_fbits1(TyD);
4757 if (1) test_scvtf_d_d_fbits32(TyD);
4758 if (1) test_scvtf_d_d_fbits64(TyD);
4759 if (1) test_ucvtf_d_d_fbits1(TyD);
4760 if (1) test_ucvtf_d_d_fbits32(TyD);
4761 if (1) test_ucvtf_d_d_fbits64(TyD);
4762 if (1) test_scvtf_s_s_fbits1(TyS);
4763 if (1) test_scvtf_s_s_fbits16(TyS);
4764 if (1) test_scvtf_s_s_fbits32(TyS);
4765 if (1) test_ucvtf_s_s_fbits1(TyS);
4766 if (1) test_ucvtf_s_s_fbits16(TyS);
4767 if (1) test_ucvtf_s_s_fbits32(TyS);
4768 if (1) test_scvtf_2d_2d_fbits1(TyD);
4769 if (1) test_scvtf_2d_2d_fbits32(TyD);
4770 if (1) test_scvtf_2d_2d_fbits64(TyD);
4771 if (1) test_ucvtf_2d_2d_fbits1(TyD);
4772 if (1) test_ucvtf_2d_2d_fbits32(TyD);
4773 if (1) test_ucvtf_2d_2d_fbits64(TyD);
4774 if (1) test_scvtf_4s_4s_fbits1(TyS);
4775 if (1) test_scvtf_4s_4s_fbits16(TyS);
4776 if (1) test_scvtf_4s_4s_fbits32(TyS);
4777 if (1) test_ucvtf_4s_4s_fbits1(TyS);
4778 if (1) test_ucvtf_4s_4s_fbits16(TyS);
4779 if (1) test_ucvtf_4s_4s_fbits32(TyS);
4780 if (1) test_scvtf_2s_2s_fbits1(TyS);
4781 if (1) test_scvtf_2s_2s_fbits16(TyS);
4782 if (1) test_scvtf_2s_2s_fbits32(TyS);
4783 if (1) test_ucvtf_2s_2s_fbits1(TyS);
4784 if (1) test_ucvtf_2s_2s_fbits16(TyS);
4785 if (1) test_ucvtf_2s_2s_fbits32(TyS);
4786
4787 // scvtf d,s
4788 // ucvtf d,s
4789 // scvtf 2d,4s,2s
4790 // ucvtf 2d,4s,2s
4791 if (1) test_scvtf_d_d(TyD);
4792 if (1) test_ucvtf_d_d(TyD);
4793 if (1) test_scvtf_s_s(TyS);
4794 if (1) test_ucvtf_s_s(TyS);
4795 if (1) test_scvtf_2d_2d(TyD);
4796 if (1) test_ucvtf_2d_2d(TyD);
4797 if (1) test_scvtf_4s_4s(TyS);
4798 if (1) test_ucvtf_4s_4s(TyS);
4799 if (1) test_scvtf_2s_2s(TyS);
4800 if (1) test_ucvtf_2s_2s(TyS);
4801
4802 // scvtf s_w, d_w, s_x, d_x, _#fbits
4803 // ucvtf s_w, d_w, s_x, d_x, _#fbits
4804 if (1) test_scvtf_s_w_fbits1(TyS);
4805 if (1) test_scvtf_s_w_fbits16(TyS);
4806 if (1) test_scvtf_s_w_fbits32(TyS);
4807 if (1) test_scvtf_d_w_fbits1(TyS);
4808 if (1) test_scvtf_d_w_fbits16(TyS);
4809 if (1) test_scvtf_d_w_fbits32(TyS);
4810 if (1) test_scvtf_s_x_fbits1(TyD);
4811 if (1) test_scvtf_s_x_fbits32(TyD);
4812 if (1) test_scvtf_s_x_fbits64(TyD);
4813 if (1) test_scvtf_d_x_fbits1(TyD);
4814 if (1) test_scvtf_d_x_fbits32(TyD);
4815 if (1) test_scvtf_d_x_fbits64(TyD);
4816 if (1) test_ucvtf_s_w_fbits1(TyS);
4817 if (1) test_ucvtf_s_w_fbits16(TyS);
4818 if (1) test_ucvtf_s_w_fbits32(TyS);
4819 if (1) test_ucvtf_d_w_fbits1(TyS);
4820 if (1) test_ucvtf_d_w_fbits16(TyS);
4821 if (1) test_ucvtf_d_w_fbits32(TyS);
4822 if (1) test_ucvtf_s_x_fbits1(TyD);
4823 if (1) test_ucvtf_s_x_fbits32(TyD);
4824 if (1) test_ucvtf_s_x_fbits64(TyD);
4825 if (1) test_ucvtf_d_x_fbits1(TyD);
4826 if (1) test_ucvtf_d_x_fbits32(TyD);
4827 if (1) test_ucvtf_d_x_fbits64(TyD);
4828
4829 // scvtf s_w, d_w, s_x, d_x
4830 // ucvtf s_w, d_w, s_x, d_x
4831 if (1) test_scvtf_s_w(TyS);
4832 if (1) test_scvtf_d_w(TyS);
4833 if (1) test_scvtf_s_x(TyD);
4834 if (1) test_scvtf_d_x(TyD);
4835 if (1) test_ucvtf_s_w(TyS);
4836 if (1) test_ucvtf_d_w(TyS);
4837 if (1) test_ucvtf_s_x(TyD);
4838 if (1) test_ucvtf_d_x(TyD);
4839
4840 // ======================== INT ========================
4841
4842 // abs d
4843 // neg d
4844 if (1) test_abs_d_d(TyD);
4845 if (1) test_neg_d_d(TyD);
4846
4847 // abs 2d,4s,2s,8h,4h,16b,8b
4848 // neg 2d,4s,2s,8h,4h,16b,8b
4849 if (1) test_abs_2d_2d(TyD);
4850 if (1) test_abs_4s_4s(TyS);
4851 if (1) test_abs_2s_2s(TyS);
4852 if (1) test_abs_8h_8h(TyH);
4853 if (1) test_abs_4h_4h(TyH);
4854 if (1) test_abs_16b_16b(TyB);
4855 if (1) test_abs_8b_8b(TyB);
4856 if (1) test_neg_2d_2d(TyD);
4857 if (1) test_neg_4s_4s(TyS);
4858 if (1) test_neg_2s_2s(TyS);
4859 if (1) test_neg_8h_8h(TyH);
4860 if (1) test_neg_4h_4h(TyH);
4861 if (1) test_neg_16b_16b(TyB);
4862 if (1) test_neg_8b_8b(TyB);
4863
4864 // add d
4865 // sub d
4866 if (1) test_add_d_d_d(TyD);
4867 if (1) test_sub_d_d_d(TyD);
4868
4869 // add 2d,4s,2s,8h,4h,16b,8b
4870 // sub 2d,4s,2s,8h,4h,16b,8b
4871 if (1) test_add_2d_2d_2d(TyD);
4872 if (1) test_add_4s_4s_4s(TyS);
4873 if (1) test_add_2s_2s_2s(TyS);
4874 if (1) test_add_8h_8h_8h(TyH);
4875 if (1) test_add_4h_4h_4h(TyH);
4876 if (1) test_add_16b_16b_16b(TyB);
4877 if (1) test_add_8b_8b_8b(TyB);
4878 if (1) test_sub_2d_2d_2d(TyD);
4879 if (1) test_sub_4s_4s_4s(TyS);
4880 if (1) test_sub_2s_2s_2s(TyS);
4881 if (1) test_sub_8h_8h_8h(TyH);
4882 if (1) test_sub_4h_4h_4h(TyH);
4883 if (1) test_sub_16b_16b_16b(TyB);
4884 if (1) test_sub_8b_8b_8b(TyB);
4885
4886 // addhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
4887 // subhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
4888 // raddhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
4889 // rsubhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
4890 if (1) test_addhn_2s_2d_2d(TyD);
4891 if (1) test_addhn2_4s_2d_2d(TyD);
4892 if (1) test_addhn_4h_4s_4s(TyS);
4893 if (1) test_addhn2_8h_4s_4s(TyS);
4894 if (1) test_addhn_8b_8h_8h(TyH);
4895 if (1) test_addhn2_16b_8h_8h(TyH);
4896 if (1) test_subhn_2s_2d_2d(TyD);
4897 if (1) test_subhn2_4s_2d_2d(TyD);
4898 if (1) test_subhn_4h_4s_4s(TyS);
4899 if (1) test_subhn2_8h_4s_4s(TyS);
4900 if (1) test_subhn_8b_8h_8h(TyH);
4901 if (1) test_subhn2_16b_8h_8h(TyH);
4902 if (1) test_raddhn_2s_2d_2d(TyD);
4903 if (1) test_raddhn2_4s_2d_2d(TyD);
4904 if (1) test_raddhn_4h_4s_4s(TyS);
4905 if (1) test_raddhn2_8h_4s_4s(TyS);
4906 if (1) test_raddhn_8b_8h_8h(TyH);
4907 if (1) test_raddhn2_16b_8h_8h(TyH);
4908 if (1) test_rsubhn_2s_2d_2d(TyD);
4909 if (1) test_rsubhn2_4s_2d_2d(TyD);
4910 if (1) test_rsubhn_4h_4s_4s(TyS);
4911 if (1) test_rsubhn2_8h_4s_4s(TyS);
4912 if (1) test_rsubhn_8b_8h_8h(TyH);
4913 if (1) test_rsubhn2_16b_8h_8h(TyH);
4914
4915 // addp d (add pairs, across)
4916 if (1) test_addp_d_2d(TyD);
4917
4918 // addp 2d,4s,2s,8h,4h,16b,8b
4919 if (1) test_addp_2d_2d_2d(TyD);
4920 if (1) test_addp_4s_4s_4s(TyS);
4921 if (1) test_addp_2s_2s_2s(TyS);
4922 if (1) test_addp_8h_8h_8h(TyH);
4923 if (1) test_addp_4h_4h_4h(TyH);
4924 if (1) test_addp_16b_16b_16b(TyB);
4925 if (1) test_addp_8b_8b_8b(TyB);
4926
4927 // addv 4s,8h,4h,16b,18b (reduce across vector)
4928 if (1) test_addv_s_4s(TyS);
4929 if (1) test_addv_h_8h(TyH);
4930 if (1) test_addv_h_4h(TyH);
4931 if (1) test_addv_b_16b(TyB);
4932 if (1) test_addv_b_8b(TyB);
4933
4934 // and 16b,8b
4935 // bic 16b,8b
4936 // orn 16b,8b
4937 // orr 16b,8b
4938 if (1) test_and_16b_16b_16b(TyB);
4939 if (1) test_and_8b_8b_8b(TyB);
4940 if (1) test_bic_16b_16b_16b(TyB);
4941 if (1) test_bic_8b_8b_8b(TyB);
4942 if (1) test_orr_16b_16b_16b(TyB);
4943 if (1) test_orr_8b_8b_8b(TyB);
4944 if (1) test_orn_16b_16b_16b(TyB);
4945 if (1) test_orn_8b_8b_8b(TyB);
4946
4947 // orr 8h,4h #imm8, LSL #0 or 8
4948 // orr 4s,2s #imm8, LSL #0, 8, 16 or 24
4949 // bic 8h,4h #imm8, LSL #0 or 8
4950 // bic 4s,2s #imm8, LSL #0, 8, 16 or 24
4951 // movi and mvni are very similar, a superset of these.
4952 // Cases are below.
4953 if (1) test_orr_8h_0x5A_lsl0(TyH);
4954 if (1) test_orr_8h_0xA5_lsl8(TyH);
4955 if (1) test_orr_4h_0x5A_lsl0(TyH);
4956 if (1) test_orr_4h_0xA5_lsl8(TyH);
4957 if (1) test_orr_4s_0x5A_lsl0(TyS);
4958 if (1) test_orr_4s_0x6B_lsl8(TyS);
4959 if (1) test_orr_4s_0x49_lsl16(TyS);
4960 if (1) test_orr_4s_0x3D_lsl24(TyS);
4961 if (1) test_orr_2s_0x5A_lsl0(TyS);
4962 if (1) test_orr_2s_0x6B_lsl8(TyS);
4963 if (1) test_orr_2s_0x49_lsl16(TyS);
4964 if (1) test_orr_2s_0x3D_lsl24(TyS);
4965 if (1) test_bic_8h_0x5A_lsl0(TyH);
4966 if (1) test_bic_8h_0xA5_lsl8(TyH);
4967 if (1) test_bic_4h_0x5A_lsl0(TyH);
4968 if (1) test_bic_4h_0xA5_lsl8(TyH);
4969 if (1) test_bic_4s_0x5A_lsl0(TyS);
4970 if (1) test_bic_4s_0x6B_lsl8(TyS);
4971 if (1) test_bic_4s_0x49_lsl16(TyS);
4972 if (1) test_bic_4s_0x3D_lsl24(TyS);
4973 if (1) test_bic_2s_0x5A_lsl0(TyS);
4974 if (1) test_bic_2s_0x6B_lsl8(TyS);
4975 if (1) test_bic_2s_0x49_lsl16(TyS);
4976 if (1) test_bic_2s_0x3D_lsl24(TyS);
4977
4978 // bif 16b,8b (vector) (bit insert if false)
4979 // bit 16b,8b (vector) (bit insert if true)
4980 // bsl 16b,8b (vector) (bit select)
4981 // eor 16b,8b (vector)
4982 if (1) test_bif_16b_16b_16b(TyB);
4983 if (1) test_bif_8b_8b_8b(TyB);
4984 if (1) test_bit_16b_16b_16b(TyB);
4985 if (1) test_bit_8b_8b_8b(TyB);
4986 if (1) test_bsl_16b_16b_16b(TyB);
4987 if (1) test_bsl_8b_8b_8b(TyB);
4988 if (1) test_eor_16b_16b_16b(TyB);
4989 if (1) test_eor_8b_8b_8b(TyB);
4990
4991 // cls 4s,2s,8h,4h,16b,8b (count leading sign bits)
4992 // clz 4s,2s,8h,4h,16b,8b (count leading zero bits)
4993 if (1) test_cls_4s_4s(TyS);
4994 if (1) test_cls_2s_2s(TyS);
4995 if (1) test_cls_8h_8h(TyH);
4996 if (1) test_cls_4h_4h(TyH);
4997 if (1) test_cls_16b_16b(TyB);
4998 if (1) test_cls_8b_8b(TyB);
4999 if (1) test_clz_4s_4s(TyS);
5000 if (1) test_clz_2s_2s(TyS);
5001 if (1) test_clz_8h_8h(TyH);
5002 if (1) test_clz_4h_4h(TyH);
5003 if (1) test_clz_16b_16b(TyB);
5004 if (1) test_clz_8b_8b(TyB);
5005
5006 // cmeq d
5007 // cmge d
5008 // cmgt d
5009 // cmhi d
5010 // cmhs d
5011 // cmtst d
5012 if (1) test_cmeq_d_d_d(TyD);
5013 if (1) test_cmge_d_d_d(TyD);
5014 if (1) test_cmgt_d_d_d(TyD);
5015 if (1) test_cmhi_d_d_d(TyD);
5016 if (1) test_cmhs_d_d_d(TyD);
5017 if (1) test_cmtst_d_d_d(TyD);
5018
5019 // cmeq 2d,4s,2s,8h,4h,16b,8b
5020 // cmge 2d,4s,2s,8h,4h,16b,8b
5021 // cmgt 2d,4s,2s,8h,4h,16b,8b
5022 // cmhi 2d,4s,2s,8h,4h,16b,8b
5023 // cmhs 2d,4s,2s,8h,4h,16b,8b
5024 // cmtst 2d,4s,2s,8h,4h,16b,8b
5025 if (1) test_cmeq_2d_2d_2d(TyD);
5026 if (1) test_cmeq_4s_4s_4s(TyS);
5027 if (1) test_cmeq_2s_2s_2s(TyS);
5028 if (1) test_cmeq_8h_8h_8h(TyH);
5029 if (1) test_cmeq_4h_4h_4h(TyH);
5030 if (1) test_cmeq_16b_16b_16b(TyB);
5031 if (1) test_cmeq_8b_8b_8b(TyB);
5032 if (1) test_cmge_2d_2d_2d(TyD);
5033 if (1) test_cmge_4s_4s_4s(TyS);
5034 if (1) test_cmge_2s_2s_2s(TyS);
5035 if (1) test_cmge_8h_8h_8h(TyH);
5036 if (1) test_cmge_4h_4h_4h(TyH);
5037 if (1) test_cmge_16b_16b_16b(TyB);
5038 if (1) test_cmge_8b_8b_8b(TyB);
5039 if (1) test_cmgt_2d_2d_2d(TyD);
5040 if (1) test_cmgt_4s_4s_4s(TyS);
5041 if (1) test_cmgt_2s_2s_2s(TyS);
5042 if (1) test_cmgt_8h_8h_8h(TyH);
5043 if (1) test_cmgt_4h_4h_4h(TyH);
5044 if (1) test_cmgt_16b_16b_16b(TyB);
5045 if (1) test_cmgt_8b_8b_8b(TyB);
5046 if (1) test_cmhi_2d_2d_2d(TyD);
5047 if (1) test_cmhi_4s_4s_4s(TyS);
5048 if (1) test_cmhi_2s_2s_2s(TyS);
5049 if (1) test_cmhi_8h_8h_8h(TyH);
5050 if (1) test_cmhi_4h_4h_4h(TyH);
5051 if (1) test_cmhi_16b_16b_16b(TyB);
5052 if (1) test_cmhi_8b_8b_8b(TyB);
5053 if (1) test_cmhs_2d_2d_2d(TyD);
5054 if (1) test_cmhs_4s_4s_4s(TyS);
5055 if (1) test_cmhs_2s_2s_2s(TyS);
5056 if (1) test_cmhs_8h_8h_8h(TyH);
5057 if (1) test_cmhs_4h_4h_4h(TyH);
5058 if (1) test_cmhs_16b_16b_16b(TyB);
5059 if (1) test_cmhs_8b_8b_8b(TyB);
5060 if (1) test_cmtst_2d_2d_2d(TyD);
5061 if (1) test_cmtst_4s_4s_4s(TyS);
5062 if (1) test_cmtst_2s_2s_2s(TyS);
5063 if (1) test_cmtst_8h_8h_8h(TyH);
5064 if (1) test_cmtst_4h_4h_4h(TyH);
5065 if (1) test_cmtst_16b_16b_16b(TyB);
5066 if (1) test_cmtst_8b_8b_8b(TyB);
5067
5068 // cmeq_z d
5069 // cmge_z d
5070 // cmgt_z d
5071 // cmle_z d
5072 // cmlt_z d
5073 if (1) test_cmeq_zero_d_d(TyD);
5074 if (1) test_cmge_zero_d_d(TyD);
5075 if (1) test_cmgt_zero_d_d(TyD);
5076 if (1) test_cmle_zero_d_d(TyD);
5077 if (1) test_cmlt_zero_d_d(TyD);
5078
5079 // cmeq_z 2d,4s,2s,8h,4h,16b,8b
5080 // cmge_z 2d,4s,2s,8h,4h,16b,8b
5081 // cmgt_z 2d,4s,2s,8h,4h,16b,8b
5082 // cmle_z 2d,4s,2s,8h,4h,16b,8b
5083 // cmlt_z 2d,4s,2s,8h,4h,16b,8b
5084 if (1) test_cmeq_zero_2d_2d(TyD);
5085 if (1) test_cmeq_zero_4s_4s(TyS);
5086 if (1) test_cmeq_zero_2s_2s(TyS);
5087 if (1) test_cmeq_zero_8h_8h(TyH);
5088 if (1) test_cmeq_zero_4h_4h(TyH);
5089 if (1) test_cmeq_zero_16b_16b(TyB);
5090 if (1) test_cmeq_zero_8b_8b(TyB);
5091 if (1) test_cmge_zero_2d_2d(TyD);
5092 if (1) test_cmge_zero_4s_4s(TyS);
5093 if (1) test_cmge_zero_2s_2s(TyS);
5094 if (1) test_cmge_zero_8h_8h(TyH);
5095 if (1) test_cmge_zero_4h_4h(TyH);
5096 if (1) test_cmge_zero_16b_16b(TyB);
5097 if (1) test_cmge_zero_8b_8b(TyB);
5098 if (1) test_cmgt_zero_2d_2d(TyD);
5099 if (1) test_cmgt_zero_4s_4s(TyS);
5100 if (1) test_cmgt_zero_2s_2s(TyS);
5101 if (1) test_cmgt_zero_8h_8h(TyH);
5102 if (1) test_cmgt_zero_4h_4h(TyH);
5103 if (1) test_cmgt_zero_16b_16b(TyB);
5104 if (1) test_cmgt_zero_8b_8b(TyB);
5105 if (1) test_cmle_zero_2d_2d(TyD);
5106 if (1) test_cmle_zero_4s_4s(TyS);
5107 if (1) test_cmle_zero_2s_2s(TyS);
5108 if (1) test_cmle_zero_8h_8h(TyH);
5109 if (1) test_cmle_zero_4h_4h(TyH);
5110 if (1) test_cmle_zero_16b_16b(TyB);
5111 if (1) test_cmle_zero_8b_8b(TyB);
5112 if (1) test_cmlt_zero_2d_2d(TyD);
5113 if (1) test_cmlt_zero_4s_4s(TyS);
5114 if (1) test_cmlt_zero_2s_2s(TyS);
5115 if (1) test_cmlt_zero_8h_8h(TyH);
5116 if (1) test_cmlt_zero_4h_4h(TyH);
5117 if (1) test_cmlt_zero_16b_16b(TyB);
5118 if (1) test_cmlt_zero_8b_8b(TyB);
5119
5120 // cnt 16b,8b (population count per byte)
5121 if (1) test_cnt_16b_16b(TyB);
5122 if (1) test_cnt_8b_8b(TyB);
5123
5124 // dup d,s,h,b (vec elem to scalar)
5125 if (1) test_dup_d_d0(TyD);
5126 if (1) test_dup_d_d1(TyD);
5127 if (1) test_dup_s_s0(TyS);
5128 if (1) test_dup_s_s3(TyS);
5129 if (1) test_dup_h_h0(TyH);
5130 if (1) test_dup_h_h6(TyH);
5131 if (1) test_dup_b_b0(TyB);
5132 if (1) test_dup_b_b13(TyB);
5133
5134 // dup 2d,4s,2s,8h,4h,16b,8b (vec elem to vector)
5135 if (1) test_dup_2d_d0(TyD);
5136 if (1) test_dup_2d_d1(TyD);
5137 if (1) test_dup_4s_s0(TyS);
5138 if (1) test_dup_4s_s3(TyS);
5139 if (1) test_dup_2s_s0(TyS);
5140 if (1) test_dup_2s_s2(TyS);
5141 if (1) test_dup_8h_h0(TyH);
5142 if (1) test_dup_8h_h6(TyH);
5143 if (1) test_dup_4h_h1(TyH);
5144 if (1) test_dup_4h_h5(TyH);
5145 if (1) test_dup_16b_b2(TyB);
5146 if (1) test_dup_16b_b12(TyB);
5147 if (1) test_dup_8b_b3(TyB);
5148 if (1) test_dup_8b_b13(TyB);
5149
5150 // dup 2d,4s,2s,8h,4h,16b,8b (general reg to vector)
5151 if (1) test_dup_2d_x(TyD);
5152 if (1) test_dup_4s_w(TyS);
5153 if (1) test_dup_2s_w(TyS);
5154 if (1) test_dup_8h_w(TyH);
5155 if (1) test_dup_4h_w(TyH);
5156 if (1) test_dup_16b_w(TyB);
5157 if (1) test_dup_8b_w(TyB);
5158
5159 // ext 16b,8b,#imm4 (concat 2 vectors, then slice)
5160 if (1) test_ext_16b_16b_16b_0x0(TyB);
5161 if (1) test_ext_16b_16b_16b_0x1(TyB);
5162 if (1) test_ext_16b_16b_16b_0x2(TyB);
5163 if (1) test_ext_16b_16b_16b_0x3(TyB);
5164 if (1) test_ext_16b_16b_16b_0x4(TyB);
5165 if (1) test_ext_16b_16b_16b_0x5(TyB);
5166 if (1) test_ext_16b_16b_16b_0x6(TyB);
5167 if (1) test_ext_16b_16b_16b_0x7(TyB);
5168 if (1) test_ext_16b_16b_16b_0x8(TyB);
5169 if (1) test_ext_16b_16b_16b_0x9(TyB);
5170 if (1) test_ext_16b_16b_16b_0xA(TyB);
5171 if (1) test_ext_16b_16b_16b_0xB(TyB);
5172 if (1) test_ext_16b_16b_16b_0xC(TyB);
5173 if (1) test_ext_16b_16b_16b_0xD(TyB);
5174 if (1) test_ext_16b_16b_16b_0xE(TyB);
5175 if (1) test_ext_16b_16b_16b_0xF(TyB);
5176 if (1) test_ext_8b_8b_8b_0x0(TyB);
5177 if (1) test_ext_8b_8b_8b_0x1(TyB);
5178 if (1) test_ext_8b_8b_8b_0x2(TyB);
5179 if (1) test_ext_8b_8b_8b_0x3(TyB);
5180 if (1) test_ext_8b_8b_8b_0x4(TyB);
5181 if (1) test_ext_8b_8b_8b_0x5(TyB);
5182 if (1) test_ext_8b_8b_8b_0x6(TyB);
5183 if (1) test_ext_8b_8b_8b_0x7(TyB);
5184
5185 // ins d[]_d[],s[]_s[],h[]_h[],b[]_b[]
5186 if (1) test_ins_d0_d0(TyD);
5187 if (1) test_ins_d0_d1(TyD);
5188 if (1) test_ins_d1_d0(TyD);
5189 if (1) test_ins_d1_d1(TyD);
5190 if (1) test_ins_s0_s2(TyS);
5191 if (1) test_ins_s3_s0(TyS);
5192 if (1) test_ins_s2_s1(TyS);
5193 if (1) test_ins_s1_s3(TyS);
5194 if (1) test_ins_h0_h6(TyH);
5195 if (1) test_ins_h7_h0(TyH);
5196 if (1) test_ins_h6_h1(TyH);
5197 if (1) test_ins_h1_h7(TyH);
5198 if (1) test_ins_b0_b14(TyB);
5199 if (1) test_ins_b15_b8(TyB);
5200 if (1) test_ins_b13_b9(TyB);
5201 if (1) test_ins_b5_b12(TyB);
5202
5203 // ins d[]_x, s[]_w, h[]_w, b[]_w
5204 if (1) test_INS_general();
5205
5206 // mla 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
5207 // mls 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
5208 // mul 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
5209 if (1) test_mla_4s_4s_s0(TyS);
5210 if (1) test_mla_4s_4s_s3(TyS);
5211 if (1) test_mla_2s_2s_s0(TyS);
5212 if (1) test_mla_2s_2s_s3(TyS);
5213 if (1) test_mla_8h_8h_h1(TyH);
5214 if (1) test_mla_8h_8h_h5(TyH);
5215 if (1) test_mla_4h_4h_h2(TyH);
5216 if (1) test_mla_4h_4h_h7(TyH);
5217 if (1) test_mls_4s_4s_s0(TyS);
5218 if (1) test_mls_4s_4s_s3(TyS);
5219 if (1) test_mls_2s_2s_s0(TyS);
5220 if (1) test_mls_2s_2s_s3(TyS);
5221 if (1) test_mls_8h_8h_h1(TyH);
5222 if (1) test_mls_8h_8h_h5(TyH);
5223 if (1) test_mls_4h_4h_h2(TyH);
5224 if (1) test_mls_4h_4h_h7(TyH);
5225 if (1) test_mul_4s_4s_s0(TyS);
5226 if (1) test_mul_4s_4s_s3(TyS);
5227 if (1) test_mul_2s_2s_s0(TyS);
5228 if (1) test_mul_2s_2s_s3(TyS);
5229 if (1) test_mul_8h_8h_h1(TyH);
5230 if (1) test_mul_8h_8h_h5(TyH);
5231 if (1) test_mul_4h_4h_h2(TyH);
5232 if (1) test_mul_4h_4h_h7(TyH);
5233
5234 // mla 4s,2s,8h,4h,16b,8b
5235 // mls 4s,2s,8h,4h,16b,8b
5236 // mul 4s,2s,8h,4h,16b,8b
5237 if (1) test_mla_4s_4s_4s(TyS);
5238 if (1) test_mla_2s_2s_2s(TyS);
5239 if (1) test_mla_8h_8h_8h(TyH);
5240 if (1) test_mla_4h_4h_4h(TyH);
5241 if (1) test_mla_16b_16b_16b(TyB);
5242 if (1) test_mla_8b_8b_8b(TyB);
5243 if (1) test_mls_4s_4s_4s(TyS);
5244 if (1) test_mls_2s_2s_2s(TyS);
5245 if (1) test_mls_8h_8h_8h(TyH);
5246 if (1) test_mls_4h_4h_4h(TyH);
5247 if (1) test_mls_16b_16b_16b(TyB);
5248 if (1) test_mls_8b_8b_8b(TyB);
5249 if (1) test_mul_4s_4s_4s(TyS);
5250 if (1) test_mul_2s_2s_2s(TyS);
5251 if (1) test_mul_8h_8h_8h(TyH);
5252 if (1) test_mul_4h_4h_4h(TyH);
5253 if (1) test_mul_16b_16b_16b(TyB);
5254 if (1) test_mul_8b_8b_8b(TyB);
5255
5256 // Some of these movi and mvni cases are similar to orr and bic
5257 // cases with immediates. Maybe they should be moved together.
5258 // movi 16b,8b #imm8, LSL #0
5259 if (1) test_movi_16b_0x9C_lsl0(TyB);
5260 if (1) test_movi_8b_0x8B_lsl0(TyB);
5261
5262 // movi 8h,4h #imm8, LSL #0 or 8
5263 // mvni 8h,4h #imm8, LSL #0 or 8
5264 if (1) test_movi_8h_0x5A_lsl0(TyH);
5265 if (1) test_movi_8h_0xA5_lsl8(TyH);
5266 if (1) test_movi_4h_0x5A_lsl0(TyH);
5267 if (1) test_movi_4h_0xA5_lsl8(TyH);
5268 if (1) test_mvni_8h_0x5A_lsl0(TyH);
5269 if (1) test_mvni_8h_0xA5_lsl8(TyH);
5270 if (1) test_mvni_4h_0x5A_lsl0(TyH);
5271 if (1) test_mvni_4h_0xA5_lsl8(TyH);
5272
5273 // movi 4s,2s #imm8, LSL #0, 8, 16, 24
5274 // mvni 4s,2s #imm8, LSL #0, 8, 16, 24
5275 if (1) test_movi_4s_0x5A_lsl0(TyS);
5276 if (1) test_movi_4s_0x6B_lsl8(TyS);
5277 if (1) test_movi_4s_0x49_lsl16(TyS);
5278 if (1) test_movi_4s_0x3D_lsl24(TyS);
5279 if (1) test_movi_2s_0x5A_lsl0(TyS);
5280 if (1) test_movi_2s_0x6B_lsl8(TyS);
5281 if (1) test_movi_2s_0x49_lsl16(TyS);
5282 if (1) test_movi_2s_0x3D_lsl24(TyS);
5283 if (1) test_mvni_4s_0x5A_lsl0(TyS);
5284 if (1) test_mvni_4s_0x6B_lsl8(TyS);
5285 if (1) test_mvni_4s_0x49_lsl16(TyS);
5286 if (1) test_mvni_4s_0x3D_lsl24(TyS);
5287 if (1) test_mvni_2s_0x5A_lsl0(TyS);
5288 if (1) test_mvni_2s_0x6B_lsl8(TyS);
5289 if (1) test_mvni_2s_0x49_lsl16(TyS);
5290 if (1) test_mvni_2s_0x3D_lsl24(TyS);
5291
5292 // movi 4s,2s #imm8, MSL #8 or 16
5293 // mvni 4s,2s #imm8, MSL #8 or 16
5294 if (1) test_movi_4s_0x6B_msl8(TyS);
5295 if (1) test_movi_4s_0x94_msl16(TyS);
5296 if (1) test_movi_2s_0x7A_msl8(TyS);
5297 if (1) test_movi_2s_0xA5_msl16(TyS);
5298 if (1) test_mvni_4s_0x6B_msl8(TyS);
5299 if (1) test_mvni_4s_0x94_msl16(TyS);
5300 if (1) test_mvni_2s_0x7A_msl8(TyS);
5301 if (1) test_mvni_2s_0xA5_msl16(TyS);
5302
5303 // movi d, #imm64
5304 // movi 2d, #imm64
5305 if (1) test_movi_d_0xA5(TyD);
5306 if (1) test_movi_2d_0xB4(TyD);
5307
5308 // not 16b,8b
5309 if (1) test_not_16b_16b(TyB);
5310 if (1) test_not_8b_8b(TyB);
5311
5312 // pmul 16b,8b
5313 if (1) test_pmul_16b_16b_16b(TyB);
5314 if (1) test_pmul_8b_8b_8b(TyB);
5315
5316 // pmull{2} 8h_8b_8b,8h_16b_16b
5317 // pmull{2} 1q_1d_1d,1q_2d_2d is in the crypto section below
5318 if (1) test_pmull_8h_8b_8b(TyB);
5319 if (1) test_pmull2_8h_16b_16b(TyB);
5320
5321 // rbit 16b,8b
5322 // rev16 16b,8b
5323 // rev32 16b,8b,8h,4h
5324 // rev64 16b,8b,8h,4h,4s,2s
5325 if (1) test_rbit_16b_16b(TyB);
5326 if (1) test_rbit_8b_8b(TyB);
5327 if (1) test_rev16_16b_16b(TyB);
5328 if (1) test_rev16_8b_8b(TyB);
5329 if (1) test_rev32_16b_16b(TyB);
5330 if (1) test_rev32_8b_8b(TyB);
5331 if (1) test_rev32_8h_8h(TyH);
5332 if (1) test_rev32_4h_4h(TyH);
5333 if (1) test_rev64_16b_16b(TyB);
5334 if (1) test_rev64_8b_8b(TyB);
5335 if (1) test_rev64_8h_8h(TyH);
5336 if (1) test_rev64_4h_4h(TyH);
5337 if (1) test_rev64_4s_4s(TyS);
5338 if (1) test_rev64_2s_2s(TyS);
5339
5340 // saba 16b,8b,8h,4h,4s,2s
5341 // uaba 16b,8b,8h,4h,4s,2s
5342 if (1) test_saba_4s_4s_4s(TyS);
5343 if (1) test_saba_2s_2s_2s(TyS);
5344 if (1) test_saba_8h_8h_8h(TyH);
5345 if (1) test_saba_4h_4h_4h(TyH);
5346 if (1) test_saba_16b_16b_16b(TyB);
5347 if (1) test_saba_8b_8b_8b(TyB);
5348 if (1) test_uaba_4s_4s_4s(TyS);
5349 if (1) test_uaba_2s_2s_2s(TyS);
5350 if (1) test_uaba_8h_8h_8h(TyH);
5351 if (1) test_uaba_4h_4h_4h(TyH);
5352 if (1) test_uaba_16b_16b_16b(TyB);
5353 if (1) test_uaba_8b_8b_8b(TyB);
5354
5355 // sabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5356 // uabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5357 if (1) test_sabal_2d_2s_2s(TyS);
5358 if (1) test_sabal2_2d_4s_4s(TyS);
5359 if (1) test_sabal_4s_4h_4h(TyH);
5360 if (1) test_sabal2_4s_8h_8h(TyH);
5361 if (1) test_sabal_8h_8b_8b(TyB);
5362 if (1) test_sabal2_8h_16b_16b(TyB);
5363 if (1) test_uabal_2d_2s_2s(TyS);
5364 if (1) test_uabal2_2d_4s_4s(TyS);
5365 if (1) test_uabal_4s_4h_4h(TyH);
5366 if (1) test_uabal2_4s_8h_8h(TyH);
5367 if (1) test_uabal_8h_8b_8b(TyB);
5368 if (1) test_uabal2_8h_16b_16b(TyB);
5369
5370 // sabd 16b,8b,8h,4h,4s,2s
5371 // uabd 16b,8b,8h,4h,4s,2s
5372 if (1) test_sabd_4s_4s_4s(TyS);
5373 if (1) test_sabd_2s_2s_2s(TyS);
5374 if (1) test_sabd_8h_8h_8h(TyH);
5375 if (1) test_sabd_4h_4h_4h(TyH);
5376 if (1) test_sabd_16b_16b_16b(TyB);
5377 if (1) test_sabd_8b_8b_8b(TyB);
5378 if (1) test_uabd_4s_4s_4s(TyS);
5379 if (1) test_uabd_2s_2s_2s(TyS);
5380 if (1) test_uabd_8h_8h_8h(TyH);
5381 if (1) test_uabd_4h_4h_4h(TyH);
5382 if (1) test_uabd_16b_16b_16b(TyB);
5383 if (1) test_uabd_8b_8b_8b(TyB);
5384
5385 // sabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5386 // uabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5387 if (1) test_sabdl_2d_2s_2s(TyS);
5388 if (1) test_sabdl2_2d_4s_4s(TyS);
5389 if (1) test_sabdl_4s_4h_4h(TyH);
5390 if (1) test_sabdl2_4s_8h_8h(TyH);
5391 if (1) test_sabdl_8h_8b_8b(TyB);
5392 if (1) test_sabdl2_8h_16b_16b(TyB);
5393 if (1) test_uabdl_2d_2s_2s(TyS);
5394 if (1) test_uabdl2_2d_4s_4s(TyS);
5395 if (1) test_uabdl_4s_4h_4h(TyH);
5396 if (1) test_uabdl2_4s_8h_8h(TyH);
5397 if (1) test_uabdl_8h_8b_8b(TyB);
5398 if (1) test_uabdl2_8h_16b_16b(TyB);
5399
5400 // sadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
5401 // uadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
5402 if (1) test_sadalp_1d_2s(TyS);
5403 if (1) test_sadalp_2d_4s(TyS);
5404 if (1) test_sadalp_2s_4h(TyH);
5405 if (1) test_sadalp_4s_8h(TyH);
5406 if (1) test_sadalp_4h_8b(TyB);
5407 if (1) test_sadalp_8h_16b(TyB);
5408 if (1) test_uadalp_1d_2s(TyS);
5409 if (1) test_uadalp_2d_4s(TyS);
5410 if (1) test_uadalp_2s_4h(TyH);
5411 if (1) test_uadalp_4s_8h(TyH);
5412 if (1) test_uadalp_4h_8b(TyB);
5413 if (1) test_uadalp_8h_16b(TyB);
5414
5415 // saddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5416 // uaddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5417 // ssubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5418 // usubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5419 if (1) test_saddl_2d_2s_2s(TyS);
5420 if (1) test_saddl2_2d_4s_4s(TyS);
5421 if (1) test_saddl_4s_4h_4h(TyH);
5422 if (1) test_saddl2_4s_8h_8h(TyH);
5423 if (1) test_saddl_8h_8b_8b(TyB);
5424 if (1) test_saddl2_8h_16b_16b(TyB);
5425 if (1) test_uaddl_2d_2s_2s(TyS);
5426 if (1) test_uaddl2_2d_4s_4s(TyS);
5427 if (1) test_uaddl_4s_4h_4h(TyH);
5428 if (1) test_uaddl2_4s_8h_8h(TyH);
5429 if (1) test_uaddl_8h_8b_8b(TyB);
5430 if (1) test_uaddl2_8h_16b_16b(TyB);
5431 if (1) test_ssubl_2d_2s_2s(TyS);
5432 if (1) test_ssubl2_2d_4s_4s(TyS);
5433 if (1) test_ssubl_4s_4h_4h(TyH);
5434 if (1) test_ssubl2_4s_8h_8h(TyH);
5435 if (1) test_ssubl_8h_8b_8b(TyB);
5436 if (1) test_ssubl2_8h_16b_16b(TyB);
5437 if (1) test_usubl_2d_2s_2s(TyS);
5438 if (1) test_usubl2_2d_4s_4s(TyS);
5439 if (1) test_usubl_4s_4h_4h(TyH);
5440 if (1) test_usubl2_4s_8h_8h(TyH);
5441 if (1) test_usubl_8h_8b_8b(TyB);
5442 if (1) test_usubl2_8h_16b_16b(TyB);
5443
5444 // saddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
5445 // uaddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
5446 if (1) test_saddlp_1d_2s(TyS);
5447 if (1) test_saddlp_2d_4s(TyS);
5448 if (1) test_saddlp_2s_4h(TyH);
5449 if (1) test_saddlp_4s_8h(TyH);
5450 if (1) test_saddlp_4h_8b(TyB);
5451 if (1) test_saddlp_8h_16b(TyB);
5452 if (1) test_uaddlp_1d_2s(TyS);
5453 if (1) test_uaddlp_2d_4s(TyS);
5454 if (1) test_uaddlp_2s_4h(TyH);
5455 if (1) test_uaddlp_4s_8h(TyH);
5456 if (1) test_uaddlp_4h_8b(TyB);
5457 if (1) test_uaddlp_8h_16b(TyB);
5458
5459 // saddlv h_16b/8b, s_8h/4h, d_4s
5460 // uaddlv h_16b/8b, s_8h/4h, d_4s
5461 if (1) test_saddlv_h_16b(TyB);
5462 if (1) test_saddlv_h_8b(TyB);
5463 if (1) test_saddlv_s_8h(TyH);
5464 if (1) test_saddlv_s_4h(TyH);
5465 if (1) test_saddlv_d_4s(TyH);
5466 if (1) test_uaddlv_h_16b(TyB);
5467 if (1) test_uaddlv_h_8b(TyB);
5468 if (1) test_uaddlv_s_8h(TyH);
5469 if (1) test_uaddlv_s_4h(TyH);
5470 if (1) test_uaddlv_d_4s(TyH);
5471
5472 // saddw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s
5473 // uaddw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s
5474 // ssubw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s
5475 // usubw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_4s/2s
5476 if (1) test_saddw2_8h_8h_16b(TyB);
5477 if (1) test_saddw_8h_8h_8b(TyB);
5478 if (1) test_saddw2_4s_4s_8h(TyH);
5479 if (1) test_saddw_4s_4s_4h(TyH);
5480 if (1) test_saddw2_2d_2d_4s(TyS);
5481 if (1) test_saddw_2d_2d_2s(TyS);
5482 if (1) test_uaddw2_8h_8h_16b(TyB);
5483 if (1) test_uaddw_8h_8h_8b(TyB);
5484 if (1) test_uaddw2_4s_4s_8h(TyH);
5485 if (1) test_uaddw_4s_4s_4h(TyH);
5486 if (1) test_uaddw2_2d_2d_4s(TyS);
5487 if (1) test_uaddw_2d_2d_2s(TyS);
5488 if (1) test_ssubw2_8h_8h_16b(TyB);
5489 if (1) test_ssubw_8h_8h_8b(TyB);
5490 if (1) test_ssubw2_4s_4s_8h(TyH);
5491 if (1) test_ssubw_4s_4s_4h(TyH);
5492 if (1) test_ssubw2_2d_2d_4s(TyS);
5493 if (1) test_ssubw_2d_2d_2s(TyS);
5494 if (1) test_usubw2_8h_8h_16b(TyB);
5495 if (1) test_usubw_8h_8h_8b(TyB);
5496 if (1) test_usubw2_4s_4s_8h(TyH);
5497 if (1) test_usubw_4s_4s_4h(TyH);
5498 if (1) test_usubw2_2d_2d_4s(TyS);
5499 if (1) test_usubw_2d_2d_2s(TyS);
5500
5501 // shadd 16b,8b,8h,4h,4s,2s
5502 // uhadd 16b,8b,8h,4h,4s,2s
5503 // shsub 16b,8b,8h,4h,4s,2s
5504 // uhsub 16b,8b,8h,4h,4s,2s
5505 if (1) test_shadd_4s_4s_4s(TyS);
5506 if (1) test_shadd_2s_2s_2s(TyS);
5507 if (1) test_shadd_8h_8h_8h(TyH);
5508 if (1) test_shadd_4h_4h_4h(TyH);
5509 if (1) test_shadd_16b_16b_16b(TyB);
5510 if (1) test_shadd_8b_8b_8b(TyB);
5511 if (1) test_uhadd_4s_4s_4s(TyS);
5512 if (1) test_uhadd_2s_2s_2s(TyS);
5513 if (1) test_uhadd_8h_8h_8h(TyH);
5514 if (1) test_uhadd_4h_4h_4h(TyH);
5515 if (1) test_uhadd_16b_16b_16b(TyB);
5516 if (1) test_uhadd_8b_8b_8b(TyB);
5517 if (1) test_shsub_4s_4s_4s(TyS);
5518 if (1) test_shsub_2s_2s_2s(TyS);
5519 if (1) test_shsub_8h_8h_8h(TyH);
5520 if (1) test_shsub_4h_4h_4h(TyH);
5521 if (1) test_shsub_16b_16b_16b(TyB);
5522 if (1) test_shsub_8b_8b_8b(TyB);
5523 if (1) test_uhsub_4s_4s_4s(TyS);
5524 if (1) test_uhsub_2s_2s_2s(TyS);
5525 if (1) test_uhsub_8h_8h_8h(TyH);
5526 if (1) test_uhsub_4h_4h_4h(TyH);
5527 if (1) test_uhsub_16b_16b_16b(TyB);
5528 if (1) test_uhsub_8b_8b_8b(TyB);
5529
5530 // shll{2} 8h_8b/16b_#8, 4s_4h/8h_#16, 2d_2s/4s_#32
5531 if (1) test_shll_8h_8b_8(TyB);
5532 if (1) test_shll2_8h_16b_8(TyB);
5533 if (1) test_shll_4s_4h_16(TyH);
5534 if (1) test_shll2_4s_8h_16(TyH);
5535 if (1) test_shll_2d_2s_32(TyS);
5536 if (1) test_shll2_2d_4s_32(TyS);
5537
5538 // shrn{2} 2s/4s_2d, 8h/4h_4s, 8b/16b_8h, #imm in 1 .. elem_bits
5539 // rshrn{2} 2s/4s_2d, 8h/4h_4s, 8b/16b_8h, #imm in 1 .. elem_bits
5540 if (1) test_shrn_2s_2d_1(TyD);
5541 if (1) test_shrn_2s_2d_32(TyD);
5542 if (1) test_shrn2_4s_2d_1(TyD);
5543 if (1) test_shrn2_4s_2d_32(TyD);
5544 if (1) test_shrn_4h_4s_1(TyS);
5545 if (1) test_shrn_4h_4s_16(TyS);
5546 if (1) test_shrn2_8h_4s_1(TyS);
5547 if (1) test_shrn2_8h_4s_16(TyS);
5548 if (1) test_shrn_8b_8h_1(TyH);
5549 if (1) test_shrn_8b_8h_8(TyH);
5550 if (1) test_shrn2_16b_8h_1(TyH);
5551 if (1) test_shrn2_16b_8h_8(TyH);
5552 if (1) test_rshrn_2s_2d_1(TyD);
5553 if (1) test_rshrn_2s_2d_32(TyD);
5554 if (1) test_rshrn2_4s_2d_1(TyD);
5555 if (1) test_rshrn2_4s_2d_32(TyD);
5556 if (1) test_rshrn_4h_4s_1(TyS);
5557 if (1) test_rshrn_4h_4s_16(TyS);
5558 if (1) test_rshrn2_8h_4s_1(TyS);
5559 if (1) test_rshrn2_8h_4s_16(TyS);
5560 if (1) test_rshrn_8b_8h_1(TyH);
5561 if (1) test_rshrn_8b_8h_8(TyH);
5562 if (1) test_rshrn2_16b_8h_1(TyH);
5563 if (1) test_rshrn2_16b_8h_8(TyH);
5564
5565 // sli d_#imm
5566 // sri d_#imm
5567 if (1) test_sli_d_d_0(TyD);
5568 if (1) test_sli_d_d_32(TyD);
5569 if (1) test_sli_d_d_63(TyD);
5570 if (1) test_sri_d_d_1(TyD);
5571 if (1) test_sri_d_d_33(TyD);
5572 if (1) test_sri_d_d_64(TyD);
5573
5574 // sli 2d,4s,2s,8h,4h,16b,8b _#imm
5575 // sri 2d,4s,2s,8h,4h,16b,8b _#imm
5576 if (1) test_sli_2d_2d_0(TyD);
5577 if (1) test_sli_2d_2d_32(TyD);
5578 if (1) test_sli_2d_2d_63(TyD);
5579 if (1) test_sli_4s_4s_0(TyS);
5580 if (1) test_sli_4s_4s_16(TyS);
5581 if (1) test_sli_4s_4s_31(TyS);
5582 if (1) test_sli_2s_2s_0(TyS);
5583 if (1) test_sli_2s_2s_16(TyS);
5584 if (1) test_sli_2s_2s_31(TyS);
5585 if (1) test_sli_8h_8h_0(TyH);
5586 if (1) test_sli_8h_8h_8(TyH);
5587 if (1) test_sli_8h_8h_15(TyH);
5588 if (1) test_sli_4h_4h_0(TyH);
5589 if (1) test_sli_4h_4h_8(TyH);
5590 if (1) test_sli_4h_4h_15(TyH);
5591 if (1) test_sli_16b_16b_0(TyB);
5592 if (1) test_sli_16b_16b_3(TyB);
5593 if (1) test_sli_16b_16b_7(TyB);
5594 if (1) test_sli_8b_8b_0(TyB);
5595 if (1) test_sli_8b_8b_3(TyB);
5596 if (1) test_sli_8b_8b_7(TyB);
5597 if (1) test_sri_2d_2d_1(TyD);
5598 if (1) test_sri_2d_2d_33(TyD);
5599 if (1) test_sri_2d_2d_64(TyD);
5600 if (1) test_sri_4s_4s_1(TyS);
5601 if (1) test_sri_4s_4s_17(TyS);
5602 if (1) test_sri_4s_4s_32(TyS);
5603 if (1) test_sri_2s_2s_1(TyS);
5604 if (1) test_sri_2s_2s_17(TyS);
5605 if (1) test_sri_2s_2s_32(TyS);
5606 if (1) test_sri_8h_8h_1(TyH);
5607 if (1) test_sri_8h_8h_8(TyH);
5608 if (1) test_sri_8h_8h_16(TyH);
5609 if (1) test_sri_4h_4h_1(TyH);
5610 if (1) test_sri_4h_4h_8(TyH);
5611 if (1) test_sri_4h_4h_16(TyH);
5612 if (1) test_sri_16b_16b_1(TyB);
5613 if (1) test_sri_16b_16b_4(TyB);
5614 if (1) test_sri_16b_16b_8(TyB);
5615 if (1) test_sri_8b_8b_1(TyB);
5616 if (1) test_sri_8b_8b_4(TyB);
5617 if (1) test_sri_8b_8b_8(TyB);
5618
5619 // smax 4s,2s,8h,4h,16b,8b
5620 // umax 4s,2s,8h,4h,16b,8b
5621 // smin 4s,2s,8h,4h,16b,8b
5622 // umin 4s,2s,8h,4h,16b,8b
5623 if (1) test_smax_4s_4s_4s(TyS);
5624 if (1) test_smax_2s_2s_2s(TyS);
5625 if (1) test_smax_8h_8h_8h(TyH);
5626 if (1) test_smax_4h_4h_4h(TyH);
5627 if (1) test_smax_16b_16b_16b(TyB);
5628 if (1) test_smax_8b_8b_8b(TyB);
5629 if (1) test_umax_4s_4s_4s(TyS);
5630 if (1) test_umax_2s_2s_2s(TyS);
5631 if (1) test_umax_8h_8h_8h(TyH);
5632 if (1) test_umax_4h_4h_4h(TyH);
5633 if (1) test_umax_16b_16b_16b(TyB);
5634 if (1) test_umax_8b_8b_8b(TyB);
5635 if (1) test_smin_4s_4s_4s(TyS);
5636 if (1) test_smin_2s_2s_2s(TyS);
5637 if (1) test_smin_8h_8h_8h(TyH);
5638 if (1) test_smin_4h_4h_4h(TyH);
5639 if (1) test_smin_16b_16b_16b(TyB);
5640 if (1) test_smin_8b_8b_8b(TyB);
5641 if (1) test_umin_4s_4s_4s(TyS);
5642 if (1) test_umin_2s_2s_2s(TyS);
5643 if (1) test_umin_8h_8h_8h(TyH);
5644 if (1) test_umin_4h_4h_4h(TyH);
5645 if (1) test_umin_16b_16b_16b(TyB);
5646 if (1) test_umin_8b_8b_8b(TyB);
5647
5648 // smaxp 4s,2s,8h,4h,16b,8b
5649 // umaxp 4s,2s,8h,4h,16b,8b
5650 // sminp 4s,2s,8h,4h,16b,8b
5651 // uminp 4s,2s,8h,4h,16b,8b
5652 if (1) test_smaxp_4s_4s_4s(TyS);
5653 if (1) test_smaxp_2s_2s_2s(TyS);
5654 if (1) test_smaxp_8h_8h_8h(TyH);
5655 if (1) test_smaxp_4h_4h_4h(TyH);
5656 if (1) test_smaxp_16b_16b_16b(TyB);
5657 if (1) test_smaxp_8b_8b_8b(TyB);
5658 if (1) test_umaxp_4s_4s_4s(TyS);
5659 if (1) test_umaxp_2s_2s_2s(TyS);
5660 if (1) test_umaxp_8h_8h_8h(TyH);
5661 if (1) test_umaxp_4h_4h_4h(TyH);
5662 if (1) test_umaxp_16b_16b_16b(TyB);
5663 if (1) test_umaxp_8b_8b_8b(TyB);
5664 if (1) test_sminp_4s_4s_4s(TyS);
5665 if (1) test_sminp_2s_2s_2s(TyS);
5666 if (1) test_sminp_8h_8h_8h(TyH);
5667 if (1) test_sminp_4h_4h_4h(TyH);
5668 if (1) test_sminp_16b_16b_16b(TyB);
5669 if (1) test_sminp_8b_8b_8b(TyB);
5670 if (1) test_uminp_4s_4s_4s(TyS);
5671 if (1) test_uminp_2s_2s_2s(TyS);
5672 if (1) test_uminp_8h_8h_8h(TyH);
5673 if (1) test_uminp_4h_4h_4h(TyH);
5674 if (1) test_uminp_16b_16b_16b(TyB);
5675 if (1) test_uminp_8b_8b_8b(TyB);
5676
5677 // smaxv s_4s,h_8h,h_4h,b_16b,b_8b
5678 // umaxv s_4s,h_8h,h_4h,b_16b,b_8b
5679 // sminv s_4s,h_8h,h_4h,b_16b,b_8b
5680 // uminv s_4s,h_8h,h_4h,b_16b,b_8b
5681 if (1) test_SMAXV();
5682 if (1) test_UMAXV();
5683 if (1) test_SMINV();
5684 if (1) test_UMINV();
5685
5686 // smlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
5687 // umlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
5688 // smlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
5689 // umlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
5690 // smull{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
5691 // umull{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
5692 if (1) test_smlal_2d_2s_s0(TyS);
5693 if (1) test_smlal_2d_2s_s3(TyS);
5694 if (1) test_smlal2_2d_4s_s1(TyS);
5695 if (1) test_smlal2_2d_4s_s2(TyS);
5696 if (1) test_smlal_4s_4h_h0(TyH);
5697 if (1) test_smlal_4s_4h_h7(TyH);
5698 if (1) test_smlal2_4s_8h_h1(TyH);
5699 if (1) test_smlal2_4s_8h_h4(TyH);
5700 if (1) test_umlal_2d_2s_s0(TyS);
5701 if (1) test_umlal_2d_2s_s3(TyS);
5702 if (1) test_umlal2_2d_4s_s1(TyS);
5703 if (1) test_umlal2_2d_4s_s2(TyS);
5704 if (1) test_umlal_4s_4h_h0(TyH);
5705 if (1) test_umlal_4s_4h_h7(TyH);
5706 if (1) test_umlal2_4s_8h_h1(TyH);
5707 if (1) test_umlal2_4s_8h_h4(TyH);
5708 if (1) test_smlsl_2d_2s_s0(TyS);
5709 if (1) test_smlsl_2d_2s_s3(TyS);
5710 if (1) test_smlsl2_2d_4s_s1(TyS);
5711 if (1) test_smlsl2_2d_4s_s2(TyS);
5712 if (1) test_smlsl_4s_4h_h0(TyH);
5713 if (1) test_smlsl_4s_4h_h7(TyH);
5714 if (1) test_smlsl2_4s_8h_h1(TyH);
5715 if (1) test_smlsl2_4s_8h_h4(TyH);
5716 if (1) test_umlsl_2d_2s_s0(TyS);
5717 if (1) test_umlsl_2d_2s_s3(TyS);
5718 if (1) test_umlsl2_2d_4s_s1(TyS);
5719 if (1) test_umlsl2_2d_4s_s2(TyS);
5720 if (1) test_umlsl_4s_4h_h0(TyH);
5721 if (1) test_umlsl_4s_4h_h7(TyH);
5722 if (1) test_umlsl2_4s_8h_h1(TyH);
5723 if (1) test_umlsl2_4s_8h_h4(TyH);
5724 if (1) test_smull_2d_2s_s0(TyS);
5725 if (1) test_smull_2d_2s_s3(TyS);
5726 if (1) test_smull2_2d_4s_s1(TyS);
5727 if (1) test_smull2_2d_4s_s2(TyS);
5728 if (1) test_smull_4s_4h_h0(TyH);
5729 if (1) test_smull_4s_4h_h7(TyH);
5730 if (1) test_smull2_4s_8h_h1(TyH);
5731 if (1) test_smull2_4s_8h_h4(TyH);
5732 if (1) test_umull_2d_2s_s0(TyS);
5733 if (1) test_umull_2d_2s_s3(TyS);
5734 if (1) test_umull2_2d_4s_s1(TyS);
5735 if (1) test_umull2_2d_4s_s2(TyS);
5736 if (1) test_umull_4s_4h_h0(TyH);
5737 if (1) test_umull_4s_4h_h7(TyH);
5738 if (1) test_umull2_4s_8h_h1(TyH);
5739 if (1) test_umull2_4s_8h_h4(TyH);
5740
5741 // smlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5742 // umlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5743 // smlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5744 // umlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5745 // smull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5746 // umull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
5747 if (1) test_smlal_2d_2s_2s(TyS);
5748 if (1) test_smlal2_2d_4s_4s(TyS);
5749 if (1) test_smlal_4s_4h_4h(TyH);
5750 if (1) test_smlal2_4s_8h_8h(TyH);
5751 if (1) test_smlal_8h_8b_8b(TyB);
5752 if (1) test_smlal2_8h_16b_16b(TyB);
5753 if (1) test_umlal_2d_2s_2s(TyS);
5754 if (1) test_umlal2_2d_4s_4s(TyS);
5755 if (1) test_umlal_4s_4h_4h(TyH);
5756 if (1) test_umlal2_4s_8h_8h(TyH);
5757 if (1) test_umlal_8h_8b_8b(TyB);
5758 if (1) test_umlal2_8h_16b_16b(TyB);
5759 if (1) test_smlsl_2d_2s_2s(TyS);
5760 if (1) test_smlsl2_2d_4s_4s(TyS);
5761 if (1) test_smlsl_4s_4h_4h(TyH);
5762 if (1) test_smlsl2_4s_8h_8h(TyH);
5763 if (1) test_smlsl_8h_8b_8b(TyB);
5764 if (1) test_smlsl2_8h_16b_16b(TyB);
5765 if (1) test_umlsl_2d_2s_2s(TyS);
5766 if (1) test_umlsl2_2d_4s_4s(TyS);
5767 if (1) test_umlsl_4s_4h_4h(TyH);
5768 if (1) test_umlsl2_4s_8h_8h(TyH);
5769 if (1) test_umlsl_8h_8b_8b(TyB);
5770 if (1) test_umlsl2_8h_16b_16b(TyB);
5771 if (1) test_smull_2d_2s_2s(TyS);
5772 if (1) test_smull2_2d_4s_4s(TyS);
5773 if (1) test_smull_4s_4h_4h(TyH);
5774 if (1) test_smull2_4s_8h_8h(TyH);
5775 if (1) test_smull_8h_8b_8b(TyB);
5776 if (1) test_smull2_8h_16b_16b(TyB);
5777 if (1) test_umull_2d_2s_2s(TyS);
5778 if (1) test_umull2_2d_4s_4s(TyS);
5779 if (1) test_umull_4s_4h_4h(TyH);
5780 if (1) test_umull2_4s_8h_8h(TyH);
5781 if (1) test_umull_8h_8b_8b(TyB);
5782 if (1) test_umull2_8h_16b_16b(TyB);
5783
5784 // smov w_b[], w_h[], x_b[], x_h[], x_s[]
5785 // umov w_b[], w_h[], w_s[], x_d[]
5786 if (1) test_umov_x_d0(TyD);
5787 if (1) test_umov_x_d1(TyD);
5788 if (1) test_umov_w_s0(TyS);
5789 if (1) test_umov_w_s3(TyS);
5790 if (1) test_umov_w_h0(TyH);
5791 if (1) test_umov_w_h7(TyH);
5792 if (1) test_umov_w_b0(TyB);
5793 if (1) test_umov_w_b15(TyB);
5794 if (1) test_smov_x_s0(TyS);
5795 if (1) test_smov_x_s3(TyS);
5796 if (1) test_smov_x_h0(TyH);
5797 if (1) test_smov_x_h7(TyH);
5798 if (1) test_smov_w_h0(TyH);
5799 if (1) test_smov_w_h7(TyH);
5800 if (1) test_smov_x_b0(TyB);
5801 if (1) test_smov_x_b15(TyB);
5802 if (1) test_smov_w_b0(TyB);
5803 if (1) test_smov_w_b15(TyB);
5804
5805 // sqabs d,s,h,b
5806 // sqneg d,s,h,b
5807 if (1) test_sqabs_d_d(TyD);
5808 if (1) test_sqabs_s_s(TyS);
5809 if (1) test_sqabs_h_h(TyH);
5810 if (1) test_sqabs_b_b(TyB);
5811 if (1) test_sqneg_d_d(TyD);
5812 if (1) test_sqneg_s_s(TyS);
5813 if (1) test_sqneg_h_h(TyH);
5814 if (1) test_sqneg_b_b(TyB);
5815
5816 // sqabs 2d,4s,2s,8h,4h,16b,8b
5817 // sqneg 2d,4s,2s,8h,4h,16b,8b
5818 if (1) test_sqabs_2d_2d(TyD);
5819 if (1) test_sqabs_4s_4s(TyS);
5820 if (1) test_sqabs_2s_2s(TyS);
5821 if (1) test_sqabs_8h_8h(TyH);
5822 if (1) test_sqabs_4h_4h(TyH);
5823 if (1) test_sqabs_16b_16b(TyB);
5824 if (1) test_sqabs_8b_8b(TyB);
5825 if (1) test_sqneg_2d_2d(TyD);
5826 if (1) test_sqneg_4s_4s(TyS);
5827 if (1) test_sqneg_2s_2s(TyS);
5828 if (1) test_sqneg_8h_8h(TyH);
5829 if (1) test_sqneg_4h_4h(TyH);
5830 if (1) test_sqneg_16b_16b(TyB);
5831 if (1) test_sqneg_8b_8b(TyB);
5832
5833 // sqadd d,s,h,b
5834 // uqadd d,s,h,b
5835 // sqsub d,s,h,b
5836 // uqsub d,s,h,b
5837 if (1) test_sqadd_d_d_d(TyD);
5838 if (1) test_sqadd_s_s_s(TyS);
5839 if (1) test_sqadd_h_h_h(TyH);
5840 if (1) test_sqadd_b_b_b(TyB);
5841 if (1) test_uqadd_d_d_d(TyD);
5842 if (1) test_uqadd_s_s_s(TyS);
5843 if (1) test_uqadd_h_h_h(TyH);
5844 if (1) test_uqadd_b_b_b(TyB);
5845 if (1) test_sqsub_d_d_d(TyD);
5846 if (1) test_sqsub_s_s_s(TyS);
5847 if (1) test_sqsub_h_h_h(TyH);
5848 if (1) test_sqsub_b_b_b(TyB);
5849 if (1) test_uqsub_d_d_d(TyD);
5850 if (1) test_uqsub_s_s_s(TyS);
5851 if (1) test_uqsub_h_h_h(TyH);
5852 if (1) test_uqsub_b_b_b(TyB);
5853
5854 // sqadd 2d,4s,2s,8h,4h,16b,8b
5855 // uqadd 2d,4s,2s,8h,4h,16b,8b
5856 // sqsub 2d,4s,2s,8h,4h,16b,8b
5857 // uqsub 2d,4s,2s,8h,4h,16b,8b
5858 if (1) test_sqadd_2d_2d_2d(TyD);
5859 if (1) test_sqadd_4s_4s_4s(TyS);
5860 if (1) test_sqadd_2s_2s_2s(TyS);
5861 if (1) test_sqadd_8h_8h_8h(TyH);
5862 if (1) test_sqadd_4h_4h_4h(TyH);
5863 if (1) test_sqadd_16b_16b_16b(TyB);
5864 if (1) test_sqadd_8b_8b_8b(TyB);
5865 if (1) test_uqadd_2d_2d_2d(TyD);
5866 if (1) test_uqadd_4s_4s_4s(TyS);
5867 if (1) test_uqadd_2s_2s_2s(TyS);
5868 if (1) test_uqadd_8h_8h_8h(TyH);
5869 if (1) test_uqadd_4h_4h_4h(TyH);
5870 if (1) test_uqadd_16b_16b_16b(TyB);
5871 if (1) test_uqadd_8b_8b_8b(TyB);
5872 if (1) test_sqsub_2d_2d_2d(TyD);
5873 if (1) test_sqsub_4s_4s_4s(TyS);
5874 if (1) test_sqsub_2s_2s_2s(TyS);
5875 if (1) test_sqsub_8h_8h_8h(TyH);
5876 if (1) test_sqsub_4h_4h_4h(TyH);
5877 if (1) test_sqsub_16b_16b_16b(TyB);
5878 if (1) test_sqsub_8b_8b_8b(TyB);
5879 if (1) test_uqsub_2d_2d_2d(TyD);
5880 if (1) test_uqsub_4s_4s_4s(TyS);
5881 if (1) test_uqsub_2s_2s_2s(TyS);
5882 if (1) test_uqsub_8h_8h_8h(TyH);
5883 if (1) test_uqsub_4h_4h_4h(TyH);
5884 if (1) test_uqsub_16b_16b_16b(TyB);
5885 if (1) test_uqsub_8b_8b_8b(TyB);
5886
5887 // sqdmlal d_s_s[], s_h_h[]
5888 // sqdmlsl d_s_s[], s_h_h[]
5889 // sqdmull d_s_s[], s_h_h[]
5890 if (1) test_sqdmlal_d_s_s0(TyS);
5891 if (1) test_sqdmlal_d_s_s3(TyS);
5892 if (1) test_sqdmlal_s_h_h1(TyH);
5893 if (1) test_sqdmlal_s_h_h5(TyH);
5894 if (1) test_sqdmlsl_d_s_s0(TyS);
5895 if (1) test_sqdmlsl_d_s_s3(TyS);
5896 if (1) test_sqdmlsl_s_h_h1(TyH);
5897 if (1) test_sqdmlsl_s_h_h5(TyH);
5898 if (1) test_sqdmull_d_s_s0(TyS);
5899 if (1) test_sqdmull_d_s_s3(TyS);
5900 if (1) test_sqdmull_s_h_h1(TyH);
5901 if (1) test_sqdmull_s_h_h5(TyH);
5902
5903 // sqdmlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
5904 // sqdmlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
5905 // sqdmull{2} 2d_2s/4s_s[], 4s_4h/2h_h[]
5906 if (1) test_sqdmlal_2d_2s_s0(TyS);
5907 if (1) test_sqdmlal_2d_2s_s3(TyS);
5908 if (1) test_sqdmlal2_2d_4s_s1(TyS);
5909 if (1) test_sqdmlal2_2d_4s_s2(TyS);
5910 if (1) test_sqdmlal_4s_4h_h0(TyH);
5911 if (1) test_sqdmlal_4s_4h_h7(TyH);
5912 if (1) test_sqdmlal2_4s_8h_h1(TyH);
5913 if (1) test_sqdmlal2_4s_8h_h4(TyH);
5914 if (1) test_sqdmlsl_2d_2s_s0(TyS);
5915 if (1) test_sqdmlsl_2d_2s_s3(TyS);
5916 if (1) test_sqdmlsl2_2d_4s_s1(TyS);
5917 if (1) test_sqdmlsl2_2d_4s_s2(TyS);
5918 if (1) test_sqdmlsl_4s_4h_h0(TyH);
5919 if (1) test_sqdmlsl_4s_4h_h7(TyH);
5920 if (1) test_sqdmlsl2_4s_8h_h1(TyH);
5921 if (1) test_sqdmlsl2_4s_8h_h4(TyH);
5922 if (1) test_sqdmull_2d_2s_s0(TyS);
5923 if (1) test_sqdmull_2d_2s_s3(TyS);
5924 if (1) test_sqdmull2_2d_4s_s1(TyS);
5925 if (1) test_sqdmull2_2d_4s_s2(TyS);
5926 if (1) test_sqdmull_4s_4h_h0(TyH);
5927 if (1) test_sqdmull_4s_4h_h7(TyH);
5928 if (1) test_sqdmull2_4s_8h_h1(TyH);
5929 if (1) test_sqdmull2_4s_8h_h4(TyH);
5930
5931 // sqdmlal d_s_s, s_h_h
5932 // sqdmlsl d_s_s, s_h_h
5933 // sqdmull d_s_s, s_h_h
5934 if (1) test_sqdmlal_d_s_s(TyS);
5935 if (1) test_sqdmlal_s_h_h(TyH);
5936 if (1) test_sqdmlsl_d_s_s(TyS);
5937 if (1) test_sqdmlsl_s_h_h(TyH);
5938 if (1) test_sqdmull_d_s_s(TyS);
5939 if (1) test_sqdmull_s_h_h(TyH);
5940
5941 // sqdmlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h)
5942 // sqdmlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h)
5943 // sqdmull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h)
5944 if (1) test_sqdmlal_2d_2s_2s(TyS);
5945 if (1) test_sqdmlal2_2d_4s_4s(TyS);
5946 if (1) test_sqdmlal_4s_4h_4h(TyH);
5947 if (1) test_sqdmlal2_4s_8h_8h(TyH);
5948 if (1) test_sqdmlsl_2d_2s_2s(TyS);
5949 if (1) test_sqdmlsl2_2d_4s_4s(TyS);
5950 if (1) test_sqdmlsl_4s_4h_4h(TyH);
5951 if (1) test_sqdmlsl2_4s_8h_8h(TyH);
5952 if (1) test_sqdmull_2d_2s_2s(TyS);
5953 if (1) test_sqdmull2_2d_4s_4s(TyS);
5954 if (1) test_sqdmull_4s_4h_4h(TyH);
5955 if (1) test_sqdmull2_4s_8h_8h(TyH);
5956
5957 // sqdmulh s_s_s[], h_h_h[]
5958 // sqrdmulh s_s_s[], h_h_h[]
5959 if (1) test_sqdmulh_s_s_s1(TyS);
5960 if (1) test_sqdmulh_s_s_s3(TyS);
5961 if (1) test_sqdmulh_h_h_h2(TyH);
5962 if (1) test_sqdmulh_h_h_h7(TyH);
5963 if (1) test_sqrdmulh_s_s_s1(TyS);
5964 if (1) test_sqrdmulh_s_s_s3(TyS);
5965 if (1) test_sqrdmulh_h_h_h2(TyH);
5966 if (1) test_sqrdmulh_h_h_h7(TyH);
5967
5968 // sqdmulh 4s_4s_s[], 2s_2s_s[], 8h_8h_h[], 4h_4h_h[]
5969 // sqrdmulh 4s_4s_s[], 2s_2s_s[], 8h_8h_h[], 4h_4h_h[]
5970 if (1) test_sqdmulh_4s_4s_s1(TyS);
5971 if (1) test_sqdmulh_4s_4s_s3(TyS);
5972 if (1) test_sqdmulh_2s_2s_s1(TyS);
5973 if (1) test_sqdmulh_2s_2s_s3(TyS);
5974 if (1) test_sqdmulh_8h_8h_h2(TyH);
5975 if (1) test_sqdmulh_8h_8h_h7(TyH);
5976 if (1) test_sqdmulh_4h_4h_h2(TyH);
5977 if (1) test_sqdmulh_4h_4h_h7(TyH);
5978 if (1) test_sqrdmulh_4s_4s_s1(TyS);
5979 if (1) test_sqrdmulh_4s_4s_s3(TyS);
5980 if (1) test_sqrdmulh_2s_2s_s1(TyS);
5981 if (1) test_sqrdmulh_2s_2s_s3(TyS);
5982 if (1) test_sqrdmulh_8h_8h_h2(TyH);
5983 if (1) test_sqrdmulh_8h_8h_h7(TyH);
5984 if (1) test_sqrdmulh_4h_4h_h2(TyH);
5985 if (1) test_sqrdmulh_4h_4h_h7(TyH);
5986
5987 // sqdmulh h,s
5988 // sqrdmulh h,s
5989 if (1) test_sqdmulh_s_s_s(TyS);
5990 if (1) test_sqdmulh_h_h_h(TyH);
5991 if (1) test_sqrdmulh_s_s_s(TyS);
5992 if (1) test_sqrdmulh_h_h_h(TyH);
5993
5994 // sqdmulh 4s,2s,8h,4h
5995 // sqrdmulh 4s,2s,8h,4h
5996 if (1) test_sqdmulh_4s_4s_4s(TyS);
5997 if (1) test_sqdmulh_2s_2s_2s(TyS);
5998 if (1) test_sqdmulh_8h_8h_8h(TyH);
5999 if (1) test_sqdmulh_4h_4h_4h(TyH);
6000 if (1) test_sqrdmulh_4s_4s_4s(TyS);
6001 if (1) test_sqrdmulh_2s_2s_2s(TyS);
6002 if (1) test_sqrdmulh_8h_8h_8h(TyH);
6003 if (1) test_sqrdmulh_4h_4h_4h(TyH);
6004
6005 // sqshl (reg) d,s,h,b
6006 // uqshl (reg) d,s,h,b
6007 // sqrshl (reg) d,s,h,b
6008 // uqrshl (reg) d,s,h,b
6009 if (1) test_sqshl_d_d_d(TyD);
6010 if (1) test_sqshl_s_s_s(TyS);
6011 if (1) test_sqshl_h_h_h(TyH);
6012 if (1) test_sqshl_b_b_b(TyB);
6013 if (1) test_uqshl_d_d_d(TyD);
6014 if (1) test_uqshl_s_s_s(TyS);
6015 if (1) test_uqshl_h_h_h(TyH);
6016 if (1) test_uqshl_b_b_b(TyB);
6017 if (1) test_sqrshl_d_d_d(TyD);
6018 if (1) test_sqrshl_s_s_s(TyS);
6019 if (1) test_sqrshl_h_h_h(TyH);
6020 if (1) test_sqrshl_b_b_b(TyB);
6021 if (1) test_uqrshl_d_d_d(TyD);
6022 if (1) test_uqrshl_s_s_s(TyS);
6023 if (1) test_uqrshl_h_h_h(TyH);
6024 if (1) test_uqrshl_b_b_b(TyB);
6025
6026 // sqshl (reg) 2d,4s,2s,8h,4h,16b,8b
6027 // uqshl (reg) 2d,4s,2s,8h,4h,16b,8b
6028 // sqrshl (reg) 2d,4s,2s,8h,4h,16b,8b
6029 // uqrshl (reg) 2d,4s,2s,8h,4h,16b,8b
6030 if (1) test_sqshl_2d_2d_2d(TyD);
6031 if (1) test_sqshl_4s_4s_4s(TyS);
6032 if (1) test_sqshl_2s_2s_2s(TyS);
6033 if (1) test_sqshl_8h_8h_8h(TyH);
6034 if (1) test_sqshl_4h_4h_4h(TyH);
6035 if (1) test_sqshl_16b_16b_16b(TyB);
6036 if (1) test_sqshl_8b_8b_8b(TyB);
6037 if (1) test_uqshl_2d_2d_2d(TyD);
6038 if (1) test_uqshl_4s_4s_4s(TyS);
6039 if (1) test_uqshl_2s_2s_2s(TyS);
6040 if (1) test_uqshl_8h_8h_8h(TyH);
6041 if (1) test_uqshl_4h_4h_4h(TyH);
6042 if (1) test_uqshl_16b_16b_16b(TyB);
6043 if (1) test_uqshl_8b_8b_8b(TyB);
6044 if (1) test_sqrshl_2d_2d_2d(TyD);
6045 if (1) test_sqrshl_4s_4s_4s(TyS);
6046 if (1) test_sqrshl_2s_2s_2s(TyS);
6047 if (1) test_sqrshl_8h_8h_8h(TyH);
6048 if (1) test_sqrshl_4h_4h_4h(TyH);
6049 if (1) test_sqrshl_16b_16b_16b(TyB);
6050 if (1) test_sqrshl_8b_8b_8b(TyB);
6051 if (1) test_uqrshl_2d_2d_2d(TyD);
6052 if (1) test_uqrshl_4s_4s_4s(TyS);
6053 if (1) test_uqrshl_2s_2s_2s(TyS);
6054 if (1) test_uqrshl_8h_8h_8h(TyH);
6055 if (1) test_uqrshl_4h_4h_4h(TyH);
6056 if (1) test_uqrshl_16b_16b_16b(TyB);
6057 if (1) test_uqrshl_8b_8b_8b(TyB);
6058
6059 // sqrshrn s_d, h_s, b_h #imm
6060 // uqrshrn s_d, h_s, b_h #imm
6061 // sqshrn s_d, h_s, b_h #imm
6062 // uqshrn s_d, h_s, b_h #imm
6063 // sqrshrun s_d, h_s, b_h #imm
6064 // sqshrun s_d, h_s, b_h #imm
6065 if (1) test_sqrshrn_s_d_1(TyD);
6066 if (1) test_sqrshrn_s_d_17(TyD);
6067 if (1) test_sqrshrn_s_d_32(TyD);
6068 if (1) test_sqrshrn_h_s_1(TyS);
6069 if (1) test_sqrshrn_h_s_9(TyS);
6070 if (1) test_sqrshrn_h_s_16(TyS);
6071 if (1) test_sqrshrn_b_h_1(TyH);
6072 if (1) test_sqrshrn_b_h_4(TyH);
6073 if (1) test_sqrshrn_b_h_8(TyH);
6074 if (1) test_uqrshrn_s_d_1(TyD);
6075 if (1) test_uqrshrn_s_d_17(TyD);
6076 if (1) test_uqrshrn_s_d_32(TyD);
6077 if (1) test_uqrshrn_h_s_1(TyS);
6078 if (1) test_uqrshrn_h_s_9(TyS);
6079 if (1) test_uqrshrn_h_s_16(TyS);
6080 if (1) test_uqrshrn_b_h_1(TyH);
6081 if (1) test_uqrshrn_b_h_4(TyH);
6082 if (1) test_uqrshrn_b_h_8(TyH);
6083 if (1) test_sqshrn_s_d_1(TyD);
6084 if (1) test_sqshrn_s_d_17(TyD);
6085 if (1) test_sqshrn_s_d_32(TyD);
6086 if (1) test_sqshrn_h_s_1(TyS);
6087 if (1) test_sqshrn_h_s_9(TyS);
6088 if (1) test_sqshrn_h_s_16(TyS);
6089 if (1) test_sqshrn_b_h_1(TyH);
6090 if (1) test_sqshrn_b_h_4(TyH);
6091 if (1) test_sqshrn_b_h_8(TyH);
6092 if (1) test_uqshrn_s_d_1(TyD);
6093 if (1) test_uqshrn_s_d_17(TyD);
6094 if (1) test_uqshrn_s_d_32(TyD);
6095 if (1) test_uqshrn_h_s_1(TyS);
6096 if (1) test_uqshrn_h_s_9(TyS);
6097 if (1) test_uqshrn_h_s_16(TyS);
6098 if (1) test_uqshrn_b_h_1(TyH);
6099 if (1) test_uqshrn_b_h_4(TyH);
6100 if (1) test_uqshrn_b_h_8(TyH);
6101 if (1) test_sqrshrun_s_d_1(TyD);
6102 if (1) test_sqrshrun_s_d_17(TyD);
6103 if (1) test_sqrshrun_s_d_32(TyD);
6104 if (1) test_sqrshrun_h_s_1(TyS);
6105 if (1) test_sqrshrun_h_s_9(TyS);
6106 if (1) test_sqrshrun_h_s_16(TyS);
6107 if (1) test_sqrshrun_b_h_1(TyH);
6108 if (1) test_sqrshrun_b_h_4(TyH);
6109 if (1) test_sqrshrun_b_h_8(TyH);
6110 if (1) test_sqshrun_s_d_1(TyD);
6111 if (1) test_sqshrun_s_d_17(TyD);
6112 if (1) test_sqshrun_s_d_32(TyD);
6113 if (1) test_sqshrun_h_s_1(TyS);
6114 if (1) test_sqshrun_h_s_9(TyS);
6115 if (1) test_sqshrun_h_s_16(TyS);
6116 if (1) test_sqshrun_b_h_1(TyH);
6117 if (1) test_sqshrun_b_h_4(TyH);
6118 if (1) test_sqshrun_b_h_8(TyH);
6119
6120 // sqrshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
6121 // uqrshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
6122 // sqshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
6123 // uqshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
6124 // sqrshrun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
6125 // sqshrun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
6126 if (1) test_sqrshrn_2s_2d_1(TyD);
6127 if (1) test_sqrshrn_2s_2d_17(TyD);
6128 if (1) test_sqrshrn_2s_2d_32(TyD);
6129 if (1) test_sqrshrn2_4s_2d_1(TyD);
6130 if (1) test_sqrshrn2_4s_2d_17(TyD);
6131 if (1) test_sqrshrn2_4s_2d_32(TyD);
6132 if (1) test_sqrshrn_4h_4s_1(TyS);
6133 if (1) test_sqrshrn_4h_4s_9(TyS);
6134 if (1) test_sqrshrn_4h_4s_16(TyS);
6135 if (1) test_sqrshrn2_8h_4s_1(TyS);
6136 if (1) test_sqrshrn2_8h_4s_9(TyS);
6137 if (1) test_sqrshrn2_8h_4s_16(TyS);
6138 if (1) test_sqrshrn_8b_8h_1(TyH);
6139 if (1) test_sqrshrn_8b_8h_4(TyH);
6140 if (1) test_sqrshrn_8b_8h_8(TyH);
6141 if (1) test_sqrshrn2_16b_8h_1(TyH);
6142 if (1) test_sqrshrn2_16b_8h_4(TyH);
6143 if (1) test_sqrshrn2_16b_8h_8(TyH);
6144 if (1) test_uqrshrn_2s_2d_1(TyD);
6145 if (1) test_uqrshrn_2s_2d_17(TyD);
6146 if (1) test_uqrshrn_2s_2d_32(TyD);
6147 if (1) test_uqrshrn2_4s_2d_1(TyD);
6148 if (1) test_uqrshrn2_4s_2d_17(TyD);
6149 if (1) test_uqrshrn2_4s_2d_32(TyD);
6150 if (1) test_uqrshrn_4h_4s_1(TyS);
6151 if (1) test_uqrshrn_4h_4s_9(TyS);
6152 if (1) test_uqrshrn_4h_4s_16(TyS);
6153 if (1) test_uqrshrn2_8h_4s_1(TyS);
6154 if (1) test_uqrshrn2_8h_4s_9(TyS);
6155 if (1) test_uqrshrn2_8h_4s_16(TyS);
6156 if (1) test_uqrshrn_8b_8h_1(TyH);
6157 if (1) test_uqrshrn_8b_8h_4(TyH);
6158 if (1) test_uqrshrn_8b_8h_8(TyH);
6159 if (1) test_uqrshrn2_16b_8h_1(TyH);
6160 if (1) test_uqrshrn2_16b_8h_4(TyH);
6161 if (1) test_uqrshrn2_16b_8h_8(TyH);
6162 if (1) test_sqshrn_2s_2d_1(TyD);
6163 if (1) test_sqshrn_2s_2d_17(TyD);
6164 if (1) test_sqshrn_2s_2d_32(TyD);
6165 if (1) test_sqshrn2_4s_2d_1(TyD);
6166 if (1) test_sqshrn2_4s_2d_17(TyD);
6167 if (1) test_sqshrn2_4s_2d_32(TyD);
6168 if (1) test_sqshrn_4h_4s_1(TyS);
6169 if (1) test_sqshrn_4h_4s_9(TyS);
6170 if (1) test_sqshrn_4h_4s_16(TyS);
6171 if (1) test_sqshrn2_8h_4s_1(TyS);
6172 if (1) test_sqshrn2_8h_4s_9(TyS);
6173 if (1) test_sqshrn2_8h_4s_16(TyS);
6174 if (1) test_sqshrn_8b_8h_1(TyH);
6175 if (1) test_sqshrn_8b_8h_4(TyH);
6176 if (1) test_sqshrn_8b_8h_8(TyH);
6177 if (1) test_sqshrn2_16b_8h_1(TyH);
6178 if (1) test_sqshrn2_16b_8h_4(TyH);
6179 if (1) test_sqshrn2_16b_8h_8(TyH);
6180 if (1) test_uqshrn_2s_2d_1(TyD);
6181 if (1) test_uqshrn_2s_2d_17(TyD);
6182 if (1) test_uqshrn_2s_2d_32(TyD);
6183 if (1) test_uqshrn2_4s_2d_1(TyD);
6184 if (1) test_uqshrn2_4s_2d_17(TyD);
6185 if (1) test_uqshrn2_4s_2d_32(TyD);
6186 if (1) test_uqshrn_4h_4s_1(TyS);
6187 if (1) test_uqshrn_4h_4s_9(TyS);
6188 if (1) test_uqshrn_4h_4s_16(TyS);
6189 if (1) test_uqshrn2_8h_4s_1(TyS);
6190 if (1) test_uqshrn2_8h_4s_9(TyS);
6191 if (1) test_uqshrn2_8h_4s_16(TyS);
6192 if (1) test_uqshrn_8b_8h_1(TyH);
6193 if (1) test_uqshrn_8b_8h_4(TyH);
6194 if (1) test_uqshrn_8b_8h_8(TyH);
6195 if (1) test_uqshrn2_16b_8h_1(TyH);
6196 if (1) test_uqshrn2_16b_8h_4(TyH);
6197 if (1) test_uqshrn2_16b_8h_8(TyH);
6198 if (1) test_sqrshrun_2s_2d_1(TyD);
6199 if (1) test_sqrshrun_2s_2d_17(TyD);
6200 if (1) test_sqrshrun_2s_2d_32(TyD);
6201 if (1) test_sqrshrun2_4s_2d_1(TyD);
6202 if (1) test_sqrshrun2_4s_2d_17(TyD);
6203 if (1) test_sqrshrun2_4s_2d_32(TyD);
6204 if (1) test_sqrshrun_4h_4s_1(TyS);
6205 if (1) test_sqrshrun_4h_4s_9(TyS);
6206 if (1) test_sqrshrun_4h_4s_16(TyS);
6207 if (1) test_sqrshrun2_8h_4s_1(TyS);
6208 if (1) test_sqrshrun2_8h_4s_9(TyS);
6209 if (1) test_sqrshrun2_8h_4s_16(TyS);
6210 if (1) test_sqrshrun_8b_8h_1(TyH);
6211 if (1) test_sqrshrun_8b_8h_4(TyH);
6212 if (1) test_sqrshrun_8b_8h_8(TyH);
6213 if (1) test_sqrshrun2_16b_8h_1(TyH);
6214 if (1) test_sqrshrun2_16b_8h_4(TyH);
6215 if (1) test_sqrshrun2_16b_8h_8(TyH);
6216 if (1) test_sqshrun_2s_2d_1(TyD);
6217 if (1) test_sqshrun_2s_2d_17(TyD);
6218 if (1) test_sqshrun_2s_2d_32(TyD);
6219 if (1) test_sqshrun2_4s_2d_1(TyD);
6220 if (1) test_sqshrun2_4s_2d_17(TyD);
6221 if (1) test_sqshrun2_4s_2d_32(TyD);
6222 if (1) test_sqshrun_4h_4s_1(TyS);
6223 if (1) test_sqshrun_4h_4s_9(TyS);
6224 if (1) test_sqshrun_4h_4s_16(TyS);
6225 if (1) test_sqshrun2_8h_4s_1(TyS);
6226 if (1) test_sqshrun2_8h_4s_9(TyS);
6227 if (1) test_sqshrun2_8h_4s_16(TyS);
6228 if (1) test_sqshrun_8b_8h_1(TyH);
6229 if (1) test_sqshrun_8b_8h_4(TyH);
6230 if (1) test_sqshrun_8b_8h_8(TyH);
6231 if (1) test_sqshrun2_16b_8h_1(TyH);
6232 if (1) test_sqshrun2_16b_8h_4(TyH);
6233 if (1) test_sqshrun2_16b_8h_8(TyH);
6234
6235 // sqshl (imm) d,s,h,b _#imm
6236 // uqshl (imm) d,s,h,b _#imm
6237 // sqshlu (imm) d,s,h,b _#imm
6238 if (1) test_sqshl_d_d_0(TyD);
6239 if (1) test_sqshl_d_d_32(TyD);
6240 if (1) test_sqshl_d_d_63(TyD);
6241 if (1) test_sqshl_s_s_0(TyS);
6242 if (1) test_sqshl_s_s_16(TyS);
6243 if (1) test_sqshl_s_s_31(TyS);
6244 if (1) test_sqshl_h_h_0(TyH);
6245 if (1) test_sqshl_h_h_8(TyH);
6246 if (1) test_sqshl_h_h_15(TyH);
6247 if (1) test_sqshl_b_b_0(TyB);
6248 if (1) test_sqshl_b_b_1(TyB);
6249 if (1) test_sqshl_b_b_4(TyB);
6250 if (1) test_sqshl_b_b_6(TyB);
6251 if (1) test_sqshl_b_b_7(TyB);
6252 if (1) test_uqshl_d_d_0(TyD);
6253 if (1) test_uqshl_d_d_32(TyD);
6254 if (1) test_uqshl_d_d_63(TyD);
6255 if (1) test_uqshl_s_s_0(TyS);
6256 if (1) test_uqshl_s_s_16(TyS);
6257 if (1) test_uqshl_s_s_31(TyS);
6258 if (1) test_uqshl_h_h_0(TyH);
6259 if (1) test_uqshl_h_h_8(TyH);
6260 if (1) test_uqshl_h_h_15(TyH);
6261 if (1) test_uqshl_b_b_0(TyB);
6262 if (1) test_uqshl_b_b_1(TyB);
6263 if (1) test_uqshl_b_b_4(TyB);
6264 if (1) test_uqshl_b_b_6(TyB);
6265 if (1) test_uqshl_b_b_7(TyB);
6266 if (1) test_sqshlu_d_d_0(TyD);
6267 if (1) test_sqshlu_d_d_32(TyD);
6268 if (1) test_sqshlu_d_d_63(TyD);
6269 if (1) test_sqshlu_s_s_0(TyS);
6270 if (1) test_sqshlu_s_s_16(TyS);
6271 if (1) test_sqshlu_s_s_31(TyS);
6272 if (1) test_sqshlu_h_h_0(TyH);
6273 if (1) test_sqshlu_h_h_8(TyH);
6274 if (1) test_sqshlu_h_h_15(TyH);
6275 if (1) test_sqshlu_b_b_0(TyB);
6276 if (1) test_sqshlu_b_b_1(TyB);
6277 if (1) test_sqshlu_b_b_2(TyB);
6278 if (1) test_sqshlu_b_b_3(TyB);
6279 if (1) test_sqshlu_b_b_4(TyB);
6280 if (1) test_sqshlu_b_b_5(TyB);
6281 if (1) test_sqshlu_b_b_6(TyB);
6282 if (1) test_sqshlu_b_b_7(TyB);
6283
6284 // sqshl (imm) 2d,4s,2s,8h,4h,16b,8b _#imm
6285 // uqshl (imm) 2d,4s,2s,8h,4h,16b,8b _#imm
6286 // sqshlu (imm) 2d,4s,2s,8h,4h,16b,8b _#imm
6287 if (1) test_sqshl_2d_2d_0(TyD);
6288 if (1) test_sqshl_2d_2d_32(TyD);
6289 if (1) test_sqshl_2d_2d_63(TyD);
6290 if (1) test_sqshl_4s_4s_0(TyS);
6291 if (1) test_sqshl_4s_4s_16(TyS);
6292 if (1) test_sqshl_4s_4s_31(TyS);
6293 if (1) test_sqshl_2s_2s_0(TyS);
6294 if (1) test_sqshl_2s_2s_16(TyS);
6295 if (1) test_sqshl_2s_2s_31(TyS);
6296 if (1) test_sqshl_8h_8h_0(TyH);
6297 if (1) test_sqshl_8h_8h_8(TyH);
6298 if (1) test_sqshl_8h_8h_15(TyH);
6299 if (1) test_sqshl_4h_4h_0(TyH);
6300 if (1) test_sqshl_4h_4h_8(TyH);
6301 if (1) test_sqshl_4h_4h_15(TyH);
6302 if (1) test_sqshl_16b_16b_0(TyB);
6303 if (1) test_sqshl_16b_16b_3(TyB);
6304 if (1) test_sqshl_16b_16b_7(TyB);
6305 if (1) test_sqshl_8b_8b_0(TyB);
6306 if (1) test_sqshl_8b_8b_3(TyB);
6307 if (1) test_sqshl_8b_8b_7(TyB);
6308 if (1) test_uqshl_2d_2d_0(TyD);
6309 if (1) test_uqshl_2d_2d_32(TyD);
6310 if (1) test_uqshl_2d_2d_63(TyD);
6311 if (1) test_uqshl_4s_4s_0(TyS);
6312 if (1) test_uqshl_4s_4s_16(TyS);
6313 if (1) test_uqshl_4s_4s_31(TyS);
6314 if (1) test_uqshl_2s_2s_0(TyS);
6315 if (1) test_uqshl_2s_2s_16(TyS);
6316 if (1) test_uqshl_2s_2s_31(TyS);
6317 if (1) test_uqshl_8h_8h_0(TyH);
6318 if (1) test_uqshl_8h_8h_8(TyH);
6319 if (1) test_uqshl_8h_8h_15(TyH);
6320 if (1) test_uqshl_4h_4h_0(TyH);
6321 if (1) test_uqshl_4h_4h_8(TyH);
6322 if (1) test_uqshl_4h_4h_15(TyH);
6323 if (1) test_uqshl_16b_16b_0(TyB);
6324 if (1) test_uqshl_16b_16b_3(TyB);
6325 if (1) test_uqshl_16b_16b_7(TyB);
6326 if (1) test_uqshl_8b_8b_0(TyB);
6327 if (1) test_uqshl_8b_8b_3(TyB);
6328 if (1) test_uqshl_8b_8b_7(TyB);
6329 if (1) test_sqshlu_2d_2d_0(TyD);
6330 if (1) test_sqshlu_2d_2d_32(TyD);
6331 if (1) test_sqshlu_2d_2d_63(TyD);
6332 if (1) test_sqshlu_4s_4s_0(TyS);
6333 if (1) test_sqshlu_4s_4s_16(TyS);
6334 if (1) test_sqshlu_4s_4s_31(TyS);
6335 if (1) test_sqshlu_2s_2s_0(TyS);
6336 if (1) test_sqshlu_2s_2s_16(TyS);
6337 if (1) test_sqshlu_2s_2s_31(TyS);
6338 if (1) test_sqshlu_8h_8h_0(TyH);
6339 if (1) test_sqshlu_8h_8h_8(TyH);
6340 if (1) test_sqshlu_8h_8h_15(TyH);
6341 if (1) test_sqshlu_4h_4h_0(TyH);
6342 if (1) test_sqshlu_4h_4h_8(TyH);
6343 if (1) test_sqshlu_4h_4h_15(TyH);
6344 if (1) test_sqshlu_16b_16b_0(TyB);
6345 if (1) test_sqshlu_16b_16b_3(TyB);
6346 if (1) test_sqshlu_16b_16b_7(TyB);
6347 if (1) test_sqshlu_8b_8b_0(TyB);
6348 if (1) test_sqshlu_8b_8b_3(TyB);
6349 if (1) test_sqshlu_8b_8b_7(TyB);
6350
6351 // sqxtn s_d,h_s,b_h
6352 // uqxtn s_d,h_s,b_h
6353 // sqxtun s_d,h_s,b_h
6354 if (1) test_sqxtn_s_d(TyD);
6355 if (1) test_sqxtn_h_s(TyS);
6356 if (1) test_sqxtn_b_h(TyH);
6357 if (1) test_uqxtn_s_d(TyD);
6358 if (1) test_uqxtn_h_s(TyS);
6359 if (1) test_uqxtn_b_h(TyH);
6360 if (1) test_sqxtun_s_d(TyD);
6361 if (1) test_sqxtun_h_s(TyS);
6362 if (1) test_sqxtun_b_h(TyH);
6363
6364 // sqxtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
6365 // uqxtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
6366 // sqxtun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
6367 if (1) test_sqxtn_2s_2d(TyD);
6368 if (1) test_sqxtn2_4s_2d(TyD);
6369 if (1) test_sqxtn_4h_4s(TyS);
6370 if (1) test_sqxtn2_8h_4s(TyS);
6371 if (1) test_sqxtn_8b_8h(TyH);
6372 if (1) test_sqxtn2_16b_8h(TyH);
6373 if (1) test_uqxtn_2s_2d(TyD);
6374 if (1) test_uqxtn2_4s_2d(TyD);
6375 if (1) test_uqxtn_4h_4s(TyS);
6376 if (1) test_uqxtn2_8h_4s(TyS);
6377 if (1) test_uqxtn_8b_8h(TyH);
6378 if (1) test_uqxtn2_16b_8h(TyH);
6379 if (1) test_sqxtun_2s_2d(TyD);
6380 if (1) test_sqxtun2_4s_2d(TyD);
6381 if (1) test_sqxtun_4h_4s(TyS);
6382 if (1) test_sqxtun2_8h_4s(TyS);
6383 if (1) test_sqxtun_8b_8h(TyH);
6384 if (1) test_sqxtun2_16b_8h(TyH);
6385
6386 // srhadd 4s,2s,8h,4h,16b,8b
6387 // urhadd 4s,2s,8h,4h,16b,8b
6388 if (1) test_srhadd_4s_4s_4s(TyS);
6389 if (1) test_srhadd_2s_2s_2s(TyS);
6390 if (1) test_srhadd_8h_8h_8h(TyH);
6391 if (1) test_srhadd_4h_4h_4h(TyH);
6392 if (1) test_srhadd_16b_16b_16b(TyB);
6393 if (1) test_srhadd_8b_8b_8b(TyB);
6394 if (1) test_urhadd_4s_4s_4s(TyS);
6395 if (1) test_urhadd_2s_2s_2s(TyS);
6396 if (1) test_urhadd_8h_8h_8h(TyH);
6397 if (1) test_urhadd_4h_4h_4h(TyH);
6398 if (1) test_urhadd_16b_16b_16b(TyB);
6399 if (1) test_urhadd_8b_8b_8b(TyB);
6400
6401 // sshl (reg) d
6402 // ushl (reg) d
6403 if (1) test_sshl_d_d_d(TyD);
6404 if (1) test_ushl_d_d_d(TyD);
6405
6406 // sshl (reg) 2d,4s,2s,8h,4h,16b,8b
6407 // ushl (reg) 2d,4s,2s,8h,4h,16b,8b
6408 if (1) test_sshl_2d_2d_2d(TyD);
6409 if (1) test_sshl_4s_4s_4s(TyS);
6410 if (1) test_sshl_2s_2s_2s(TyS);
6411 if (1) test_sshl_8h_8h_8h(TyH);
6412 if (1) test_sshl_4h_4h_4h(TyH);
6413 if (1) test_sshl_16b_16b_16b(TyB);
6414 if (1) test_sshl_8b_8b_8b(TyB);
6415 if (1) test_ushl_2d_2d_2d(TyD);
6416 if (1) test_ushl_4s_4s_4s(TyS);
6417 if (1) test_ushl_2s_2s_2s(TyS);
6418 if (1) test_ushl_8h_8h_8h(TyH);
6419 if (1) test_ushl_4h_4h_4h(TyH);
6420 if (1) test_ushl_16b_16b_16b(TyB);
6421 if (1) test_ushl_8b_8b_8b(TyB);
6422
6423 // shl (imm) d
6424 // sshr (imm) d
6425 // ushr (imm) d
6426 if (1) test_shl_d_d_0(TyD);
6427 if (1) test_shl_d_d_32(TyD);
6428 if (1) test_shl_d_d_63(TyD);
6429 if (1) test_sshr_d_d_1(TyD);
6430 if (1) test_sshr_d_d_32(TyD);
6431 if (1) test_sshr_d_d_64(TyD);
6432 if (1) test_ushr_d_d_1(TyD);
6433 if (1) test_ushr_d_d_32(TyD);
6434 if (1) test_ushr_d_d_64(TyD);
6435
6436 // shl (imm) 16b,8b,8h,4h,4s,2s,2d
6437 // sshr (imm) 2d,4s,2s,8h,4h,16b,8b
6438 // ushr (imm) 2d,4s,2s,8h,4h,16b,8b
6439 if (1) test_shl_2d_2d_0(TyD);
6440 if (1) test_shl_2d_2d_13(TyD);
6441 if (1) test_shl_2d_2d_63(TyD);
6442 if (1) test_shl_4s_4s_0(TyS);
6443 if (1) test_shl_4s_4s_13(TyS);
6444 if (1) test_shl_4s_4s_31(TyS);
6445 if (1) test_shl_2s_2s_0(TyS);
6446 if (1) test_shl_2s_2s_13(TyS);
6447 if (1) test_shl_2s_2s_31(TyS);
6448 if (1) test_shl_8h_8h_0(TyH);
6449 if (1) test_shl_8h_8h_13(TyH);
6450 if (1) test_shl_8h_8h_15(TyH);
6451 if (1) test_shl_4h_4h_0(TyH);
6452 if (1) test_shl_4h_4h_13(TyH);
6453 if (1) test_shl_4h_4h_15(TyH);
6454 if (1) test_shl_16b_16b_0(TyB);
6455 if (1) test_shl_16b_16b_7(TyB);
6456 if (1) test_shl_8b_8b_0(TyB);
6457 if (1) test_shl_8b_8b_7(TyB);
6458 if (1) test_sshr_2d_2d_1(TyD);
6459 if (1) test_sshr_2d_2d_13(TyD);
6460 if (1) test_sshr_2d_2d_64(TyD);
6461 if (1) test_sshr_4s_4s_1(TyS);
6462 if (1) test_sshr_4s_4s_13(TyS);
6463 if (1) test_sshr_4s_4s_32(TyS);
6464 if (1) test_sshr_2s_2s_1(TyS);
6465 if (1) test_sshr_2s_2s_13(TyS);
6466 if (1) test_sshr_2s_2s_32(TyS);
6467 if (1) test_sshr_8h_8h_1(TyH);
6468 if (1) test_sshr_8h_8h_13(TyH);
6469 if (1) test_sshr_8h_8h_16(TyH);
6470 if (1) test_sshr_4h_4h_1(TyH);
6471 if (1) test_sshr_4h_4h_13(TyH);
6472 if (1) test_sshr_4h_4h_16(TyH);
6473 if (1) test_sshr_16b_16b_1(TyB);
6474 if (1) test_sshr_16b_16b_8(TyB);
6475 if (1) test_sshr_8b_8b_1(TyB);
6476 if (1) test_sshr_8b_8b_8(TyB);
6477 if (1) test_ushr_2d_2d_1(TyD);
6478 if (1) test_ushr_2d_2d_13(TyD);
6479 if (1) test_ushr_2d_2d_64(TyD);
6480 if (1) test_ushr_4s_4s_1(TyS);
6481 if (1) test_ushr_4s_4s_13(TyS);
6482 if (1) test_ushr_4s_4s_32(TyS);
6483 if (1) test_ushr_2s_2s_1(TyS);
6484 if (1) test_ushr_2s_2s_13(TyS);
6485 if (1) test_ushr_2s_2s_32(TyS);
6486 if (1) test_ushr_8h_8h_1(TyH);
6487 if (1) test_ushr_8h_8h_13(TyH);
6488 if (1) test_ushr_8h_8h_16(TyH);
6489 if (1) test_ushr_4h_4h_1(TyH);
6490 if (1) test_ushr_4h_4h_13(TyH);
6491 if (1) test_ushr_4h_4h_16(TyH);
6492 if (1) test_ushr_16b_16b_1(TyB);
6493 if (1) test_ushr_16b_16b_8(TyB);
6494 if (1) test_ushr_8b_8b_1(TyB);
6495 if (1) test_ushr_8b_8b_8(TyB);
6496
6497 // ssra (imm) d
6498 // usra (imm) d
6499 if (1) test_ssra_d_d_1(TyD);
6500 if (1) test_ssra_d_d_32(TyD);
6501 if (1) test_ssra_d_d_64(TyD);
6502 if (1) test_usra_d_d_1(TyD);
6503 if (1) test_usra_d_d_32(TyD);
6504 if (1) test_usra_d_d_64(TyD);
6505
6506 // ssra (imm) 2d,4s,2s,8h,4h,16b,8b
6507 // usra (imm) 2d,4s,2s,8h,4h,16b,8b
6508 if (1) test_ssra_2d_2d_1(TyD);
6509 if (1) test_ssra_2d_2d_32(TyD);
6510 if (1) test_ssra_2d_2d_64(TyD);
6511 if (1) test_ssra_4s_4s_1(TyS);
6512 if (1) test_ssra_4s_4s_16(TyS);
6513 if (1) test_ssra_4s_4s_32(TyS);
6514 if (1) test_ssra_2s_2s_1(TyS);
6515 if (1) test_ssra_2s_2s_16(TyS);
6516 if (1) test_ssra_2s_2s_32(TyS);
6517 if (1) test_ssra_8h_8h_1(TyH);
6518 if (1) test_ssra_8h_8h_8(TyH);
6519 if (1) test_ssra_8h_8h_16(TyH);
6520 if (1) test_ssra_4h_4h_1(TyH);
6521 if (1) test_ssra_4h_4h_8(TyH);
6522 if (1) test_ssra_4h_4h_16(TyH);
6523 if (1) test_ssra_16b_16b_1(TyB);
6524 if (1) test_ssra_16b_16b_3(TyB);
6525 if (1) test_ssra_16b_16b_8(TyB);
6526 if (1) test_ssra_8b_8b_1(TyB);
6527 if (1) test_ssra_8b_8b_3(TyB);
6528 if (1) test_ssra_8b_8b_8(TyB);
6529 if (1) test_usra_2d_2d_1(TyD);
6530 if (1) test_usra_2d_2d_32(TyD);
6531 if (1) test_usra_2d_2d_64(TyD);
6532 if (1) test_usra_4s_4s_1(TyS);
6533 if (1) test_usra_4s_4s_16(TyS);
6534 if (1) test_usra_4s_4s_32(TyS);
6535 if (1) test_usra_2s_2s_1(TyS);
6536 if (1) test_usra_2s_2s_16(TyS);
6537 if (1) test_usra_2s_2s_32(TyS);
6538 if (1) test_usra_8h_8h_1(TyH);
6539 if (1) test_usra_8h_8h_8(TyH);
6540 if (1) test_usra_8h_8h_16(TyH);
6541 if (1) test_usra_4h_4h_1(TyH);
6542 if (1) test_usra_4h_4h_8(TyH);
6543 if (1) test_usra_4h_4h_16(TyH);
6544 if (1) test_usra_16b_16b_1(TyB);
6545 if (1) test_usra_16b_16b_3(TyB);
6546 if (1) test_usra_16b_16b_8(TyB);
6547 if (1) test_usra_8b_8b_1(TyB);
6548 if (1) test_usra_8b_8b_3(TyB);
6549 if (1) test_usra_8b_8b_8(TyB);
6550
6551 // srshl (reg) d
6552 // urshl (reg) d
6553 if (1) test_srshl_d_d_d(TyD);
6554 if (1) test_urshl_d_d_d(TyD);
6555
6556 // srshl (reg) 2d,4s,2s,8h,4h,16b,8b
6557 // urshl (reg) 2d,4s,2s,8h,4h,16b,8b
6558 if (1) test_srshl_2d_2d_2d(TyD);
6559 if (1) test_srshl_4s_4s_4s(TyS);
6560 if (1) test_srshl_2s_2s_2s(TyS);
6561 if (1) test_srshl_8h_8h_8h(TyH);
6562 if (1) test_srshl_4h_4h_4h(TyH);
6563 if (1) test_srshl_16b_16b_16b(TyB);
6564 if (1) test_srshl_8b_8b_8b(TyB);
6565 if (1) test_urshl_2d_2d_2d(TyD);
6566 if (1) test_urshl_4s_4s_4s(TyS);
6567 if (1) test_urshl_2s_2s_2s(TyS);
6568 if (1) test_urshl_8h_8h_8h(TyH);
6569 if (1) test_urshl_4h_4h_4h(TyH);
6570 if (1) test_urshl_16b_16b_16b(TyB);
6571 if (1) test_urshl_8b_8b_8b(TyB);
6572
6573 // srshr (imm) d
6574 // urshr (imm) d
6575 if (1) test_srshr_d_d_1(TyD);
6576 if (1) test_srshr_d_d_32(TyD);
6577 if (1) test_srshr_d_d_64(TyD);
6578 if (1) test_urshr_d_d_1(TyD);
6579 if (1) test_urshr_d_d_32(TyD);
6580 if (1) test_urshr_d_d_64(TyD);
6581
6582 // srshr (imm) 2d,4s,2s,8h,4h,16b,8b
6583 // urshr (imm) 2d,4s,2s,8h,4h,16b,8b
6584 if (1) test_srshr_2d_2d_1(TyD);
6585 if (1) test_srshr_2d_2d_32(TyD);
6586 if (1) test_srshr_2d_2d_64(TyD);
6587 if (1) test_srshr_4s_4s_1(TyS);
6588 if (1) test_srshr_4s_4s_16(TyS);
6589 if (1) test_srshr_4s_4s_32(TyS);
6590 if (1) test_srshr_2s_2s_1(TyS);
6591 if (1) test_srshr_2s_2s_16(TyS);
6592 if (1) test_srshr_2s_2s_32(TyS);
6593 if (1) test_srshr_8h_8h_1(TyH);
6594 if (1) test_srshr_8h_8h_8(TyH);
6595 if (1) test_srshr_8h_8h_16(TyH);
6596 if (1) test_srshr_4h_4h_1(TyH);
6597 if (1) test_srshr_4h_4h_8(TyH);
6598 if (1) test_srshr_4h_4h_16(TyH);
6599 if (1) test_srshr_16b_16b_1(TyB);
6600 if (1) test_srshr_16b_16b_3(TyB);
6601 if (1) test_srshr_16b_16b_8(TyB);
6602 if (1) test_srshr_8b_8b_1(TyB);
6603 if (1) test_srshr_8b_8b_3(TyB);
6604 if (1) test_srshr_8b_8b_8(TyB);
6605 if (1) test_urshr_2d_2d_1(TyD);
6606 if (1) test_urshr_2d_2d_32(TyD);
6607 if (1) test_urshr_2d_2d_64(TyD);
6608 if (1) test_urshr_4s_4s_1(TyS);
6609 if (1) test_urshr_4s_4s_16(TyS);
6610 if (1) test_urshr_4s_4s_32(TyS);
6611 if (1) test_urshr_2s_2s_1(TyS);
6612 if (1) test_urshr_2s_2s_16(TyS);
6613 if (1) test_urshr_2s_2s_32(TyS);
6614 if (1) test_urshr_8h_8h_1(TyH);
6615 if (1) test_urshr_8h_8h_8(TyH);
6616 if (1) test_urshr_8h_8h_16(TyH);
6617 if (1) test_urshr_4h_4h_1(TyH);
6618 if (1) test_urshr_4h_4h_8(TyH);
6619 if (1) test_urshr_4h_4h_16(TyH);
6620 if (1) test_urshr_16b_16b_1(TyB);
6621 if (1) test_urshr_16b_16b_3(TyB);
6622 if (1) test_urshr_16b_16b_8(TyB);
6623 if (1) test_urshr_8b_8b_1(TyB);
6624 if (1) test_urshr_8b_8b_3(TyB);
6625 if (1) test_urshr_8b_8b_8(TyB);
6626
6627 // srsra (imm) d
6628 // ursra (imm) d
6629 if (1) test_srsra_d_d_1(TyD);
6630 if (1) test_srsra_d_d_32(TyD);
6631 if (1) test_srsra_d_d_64(TyD);
6632 if (1) test_ursra_d_d_1(TyD);
6633 if (1) test_ursra_d_d_32(TyD);
6634 if (1) test_ursra_d_d_64(TyD);
6635
6636 // srsra (imm) 2d,4s,2s,8h,4h,16b,8b
6637 // ursra (imm) 2d,4s,2s,8h,4h,16b,8b
6638 if (1) test_srsra_2d_2d_1(TyD);
6639 if (1) test_srsra_2d_2d_32(TyD);
6640 if (1) test_srsra_2d_2d_64(TyD);
6641 if (1) test_srsra_4s_4s_1(TyS);
6642 if (1) test_srsra_4s_4s_16(TyS);
6643 if (1) test_srsra_4s_4s_32(TyS);
6644 if (1) test_srsra_2s_2s_1(TyS);
6645 if (1) test_srsra_2s_2s_16(TyS);
6646 if (1) test_srsra_2s_2s_32(TyS);
6647 if (1) test_srsra_8h_8h_1(TyH);
6648 if (1) test_srsra_8h_8h_8(TyH);
6649 if (1) test_srsra_8h_8h_16(TyH);
6650 if (1) test_srsra_4h_4h_1(TyH);
6651 if (1) test_srsra_4h_4h_8(TyH);
6652 if (1) test_srsra_4h_4h_16(TyH);
6653 if (1) test_srsra_16b_16b_1(TyB);
6654 if (1) test_srsra_16b_16b_3(TyB);
6655 if (1) test_srsra_16b_16b_8(TyB);
6656 if (1) test_srsra_8b_8b_1(TyB);
6657 if (1) test_srsra_8b_8b_3(TyB);
6658 if (1) test_srsra_8b_8b_8(TyB);
6659 if (1) test_ursra_2d_2d_1(TyD);
6660 if (1) test_ursra_2d_2d_32(TyD);
6661 if (1) test_ursra_2d_2d_64(TyD);
6662 if (1) test_ursra_4s_4s_1(TyS);
6663 if (1) test_ursra_4s_4s_16(TyS);
6664 if (1) test_ursra_4s_4s_32(TyS);
6665 if (1) test_ursra_2s_2s_1(TyS);
6666 if (1) test_ursra_2s_2s_16(TyS);
6667 if (1) test_ursra_2s_2s_32(TyS);
6668 if (1) test_ursra_8h_8h_1(TyH);
6669 if (1) test_ursra_8h_8h_8(TyH);
6670 if (1) test_ursra_8h_8h_16(TyH);
6671 if (1) test_ursra_4h_4h_1(TyH);
6672 if (1) test_ursra_4h_4h_8(TyH);
6673 if (1) test_ursra_4h_4h_16(TyH);
6674 if (1) test_ursra_16b_16b_1(TyB);
6675 if (1) test_ursra_16b_16b_3(TyB);
6676 if (1) test_ursra_16b_16b_8(TyB);
6677 if (1) test_ursra_8b_8b_1(TyB);
6678 if (1) test_ursra_8b_8b_3(TyB);
6679 if (1) test_ursra_8b_8b_8(TyB);
6680
6681 // sshll{2} (imm) 2d_2s/4s, 4s_4h/8h, 8h_8b/16b
6682 // ushll{2} (imm) 2d_2s/4s, 4s_4h/8h, 8h_8b/16b
6683 if (1) test_sshll_2d_2s_0(TyS);
6684 if (1) test_sshll_2d_2s_15(TyS);
6685 if (1) test_sshll_2d_2s_31(TyS);
6686 if (1) test_sshll2_2d_4s_0(TyS);
6687 if (1) test_sshll2_2d_4s_15(TyS);
6688 if (1) test_sshll2_2d_4s_31(TyS);
6689 if (1) test_sshll_4s_4h_0(TyH);
6690 if (1) test_sshll_4s_4h_7(TyH);
6691 if (1) test_sshll_4s_4h_15(TyH);
6692 if (1) test_sshll2_4s_8h_0(TyH);
6693 if (1) test_sshll2_4s_8h_7(TyH);
6694 if (1) test_sshll2_4s_8h_15(TyH);
6695 if (1) test_sshll_8h_8b_0(TyB);
6696 if (1) test_sshll_8h_8b_3(TyB);
6697 if (1) test_sshll_8h_8b_7(TyB);
6698 if (1) test_sshll2_8h_16b_0(TyB);
6699 if (1) test_sshll2_8h_16b_3(TyB);
6700 if (1) test_sshll2_8h_16b_7(TyB);
6701 if (1) test_ushll_2d_2s_0(TyS);
6702 if (1) test_ushll_2d_2s_15(TyS);
6703 if (1) test_ushll_2d_2s_31(TyS);
6704 if (1) test_ushll2_2d_4s_0(TyS);
6705 if (1) test_ushll2_2d_4s_15(TyS);
6706 if (1) test_ushll2_2d_4s_31(TyS);
6707 if (1) test_ushll_4s_4h_0(TyH);
6708 if (1) test_ushll_4s_4h_7(TyH);
6709 if (1) test_ushll_4s_4h_15(TyH);
6710 if (1) test_ushll2_4s_8h_0(TyH);
6711 if (1) test_ushll2_4s_8h_7(TyH);
6712 if (1) test_ushll2_4s_8h_15(TyH);
6713 if (1) test_ushll_8h_8b_0(TyB);
6714 if (1) test_ushll_8h_8b_3(TyB);
6715 if (1) test_ushll_8h_8b_7(TyB);
6716 if (1) test_ushll2_8h_16b_0(TyB);
6717 if (1) test_ushll2_8h_16b_3(TyB);
6718 if (1) test_ushll2_8h_16b_7(TyB);
6719
6720 // suqadd d,s,h,b
6721 // usqadd d,s,h,b
6722 if (1) test_suqadd_d_d(TyD);
6723 if (1) test_suqadd_s_s(TyS);
6724 if (1) test_suqadd_h_h(TyH);
6725 if (1) test_suqadd_b_b(TyB);
6726 if (1) test_usqadd_d_d(TyD);
6727 if (1) test_usqadd_s_s(TyS);
6728 if (1) test_usqadd_h_h(TyH);
6729 if (1) test_usqadd_b_b(TyB);
6730
6731 // suqadd 2d,4s,2s,8h,4h,16b,8b
6732 // usqadd 2d,4s,2s,8h,4h,16b,8b
6733 if (1) test_suqadd_2d_2d(TyD);
6734 if (1) test_suqadd_4s_4s(TyS);
6735 if (1) test_suqadd_2s_2s(TyS);
6736 if (1) test_suqadd_8h_8h(TyH);
6737 if (1) test_suqadd_4h_4h(TyH);
6738 if (1) test_suqadd_16b_16b(TyB);
6739 if (1) test_suqadd_8b_8b(TyB);
6740 if (1) test_usqadd_2d_2d(TyD);
6741 if (1) test_usqadd_4s_4s(TyS);
6742 if (1) test_usqadd_2s_2s(TyS);
6743 if (1) test_usqadd_8h_8h(TyH);
6744 if (1) test_usqadd_4h_4h(TyH);
6745 if (1) test_usqadd_16b_16b(TyB);
6746 if (1) test_usqadd_8b_8b(TyB);
6747
6748 // tbl 8b_{16b}_8b, 16b_{16b}_16b
6749 // tbl 8b_{16b,16b}_8b, 16b_{16b,16b}_16b
6750 // tbl 8b_{16b,16b,16b}_8b, 16b_{16b,16b,16b}_16b
6751 // tbl 8b_{16b,16b,16b,16b}_8b, 16b_{16b,16b,16b,16b}_16b
6752 if (1) test_tbl_16b_1reg(TyB);
6753 if (1) test_tbl_16b_2reg(TyB);
6754 if (1) test_tbl_16b_3reg(TyB);
6755 if (1) test_tbl_16b_4reg(TyB);
6756 if (1) test_tbl_8b_1reg(TyB);
6757 if (1) test_tbl_8b_2reg(TyB);
6758 if (1) test_tbl_8b_3reg(TyB);
6759 if (1) test_tbl_8b_4reg(TyB);
6760
6761 // tbx 8b_{16b}_8b, 16b_{16b}_16b
6762 // tbx 8b_{16b,16b}_8b, 16b_{16b,16b}_16b
6763 // tbx 8b_{16b,16b,16b}_8b, 16b_{16b,16b,16b}_16b
6764 // tbx 8b_{16b,16b,16b,16b}_8b, 16b_{16b,16b,16b,16b}_16b
6765 if (1) test_tbx_16b_1reg(TyB);
6766 if (1) test_tbx_16b_2reg(TyB);
6767 if (1) test_tbx_16b_3reg(TyB);
6768 if (1) test_tbx_16b_4reg(TyB);
6769 if (1) test_tbx_8b_1reg(TyB);
6770 if (1) test_tbx_8b_2reg(TyB);
6771 if (1) test_tbx_8b_3reg(TyB);
6772 if (1) test_tbx_8b_4reg(TyB);
6773
6774 // trn1 2d,4s,2s,8h,4h,16b,8b
6775 // trn2 2d,4s,2s,8h,4h,16b,8b
6776 if (1) test_trn1_2d_2d_2d(TyD);
6777 if (1) test_trn1_4s_4s_4s(TyS);
6778 if (1) test_trn1_2s_2s_2s(TyS);
6779 if (1) test_trn1_8h_8h_8h(TyH);
6780 if (1) test_trn1_4h_4h_4h(TyH);
6781 if (1) test_trn1_16b_16b_16b(TyB);
6782 if (1) test_trn1_8b_8b_8b(TyB);
6783 if (1) test_trn2_2d_2d_2d(TyD);
6784 if (1) test_trn2_4s_4s_4s(TyS);
6785 if (1) test_trn2_2s_2s_2s(TyS);
6786 if (1) test_trn2_8h_8h_8h(TyH);
6787 if (1) test_trn2_4h_4h_4h(TyH);
6788 if (1) test_trn2_16b_16b_16b(TyB);
6789 if (1) test_trn2_8b_8b_8b(TyB);
6790
6791 // urecpe 4s,2s
6792 // ursqrte 4s,2s
6793 if (1) test_urecpe_4s_4s(TyS);
6794 if (1) test_urecpe_2s_2s(TyS);
6795 if (1) test_ursqrte_4s_4s(TyS);
6796 if (1) test_ursqrte_2s_2s(TyS);
6797
6798 // uzp1 2d,4s,2s,8h,4h,16b,8b
6799 // uzp2 2d,4s,2s,8h,4h,16b,8b
6800 // zip1 2d,4s,2s,8h,4h,16b,8b
6801 // zip2 2d,4s,2s,8h,4h,16b,8b
6802 if (1) test_uzp1_2d_2d_2d(TyD);
6803 if (1) test_uzp1_4s_4s_4s(TyS);
6804 if (1) test_uzp1_2s_2s_2s(TyS);
6805 if (1) test_uzp1_8h_8h_8h(TyH);
6806 if (1) test_uzp1_4h_4h_4h(TyH);
6807 if (1) test_uzp1_16b_16b_16b(TyB);
6808 if (1) test_uzp1_8b_8b_8b(TyB);
6809 if (1) test_uzp2_2d_2d_2d(TyD);
6810 if (1) test_uzp2_4s_4s_4s(TyS);
6811 if (1) test_uzp2_2s_2s_2s(TyS);
6812 if (1) test_uzp2_8h_8h_8h(TyH);
6813 if (1) test_uzp2_4h_4h_4h(TyH);
6814 if (1) test_uzp2_16b_16b_16b(TyB);
6815 if (1) test_uzp2_8b_8b_8b(TyB);
6816 if (1) test_zip1_2d_2d_2d(TyD);
6817 if (1) test_zip1_4s_4s_4s(TyS);
6818 if (1) test_zip1_2s_2s_2s(TyS);
6819 if (1) test_zip1_8h_8h_8h(TyH);
6820 if (1) test_zip1_4h_4h_4h(TyH);
6821 if (1) test_zip1_16b_16b_16b(TyB);
6822 if (1) test_zip1_8b_8b_8b(TyB);
6823 if (1) test_zip2_2d_2d_2d(TyD);
6824 if (1) test_zip2_4s_4s_4s(TyS);
6825 if (1) test_zip2_2s_2s_2s(TyS);
6826 if (1) test_zip2_8h_8h_8h(TyH);
6827 if (1) test_zip2_4h_4h_4h(TyH);
6828 if (1) test_zip2_16b_16b_16b(TyB);
6829 if (1) test_zip2_8b_8b_8b(TyB);
6830
6831 // xtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
6832 if (1) test_xtn_2s_2d(TyD);
6833 if (1) test_xtn2_4s_2d(TyD);
6834 if (1) test_xtn_4h_4s(TyS);
6835 if (1) test_xtn2_8h_4s(TyS);
6836 if (1) test_xtn_8b_8h(TyH);
6837 if (1) test_xtn2_16b_8h(TyH);
6838
6839 // ======================== MEM ========================
6840
6841 // All the SIMD and FP memory tests are in none/tests/arm64/memory.c.
6842
6843 // ld1 (multiple 1-element structures to 1/2/3/4 regs)
6844 // ld1 (single 1-element structure to one lane of 1 reg)
6845 // ld1r (single 1-element structure and rep to all lanes of 1 reg)
6846
6847 // ld2 (multiple 2-element structures to 2 regs)
6848 // ld2 (single 2-element structure to one lane of 2 regs)
6849 // ld2r (single 2-element structure and rep to all lanes of 2 regs)
6850
6851 // ld3 (multiple 3-element structures to 3 regs)
6852 // ld3 (single 3-element structure to one lane of 3 regs)
6853 // ld3r (single 3-element structure and rep to all lanes of 3 regs)
6854
6855 // ld4 (multiple 4-element structures to 4 regs)
6856 // ld4 (single 4-element structure to one lane of 4 regs)
6857 // ld4r (single 4-element structure and rep to all lanes of 4 regs)
6858
6859 // ldnp q_q_addr,d_d_addr,s_s_addr (load pair w/ non-temporal hint)
6860 // addr = reg + uimm7 * reg_size
6861
6862 // ldp q_q_addr,d_d_addr,s_s_addr (load pair)
6863 // addr = [Xn|SP],#imm or [Xn|SP,#imm]! or [Xn|SP,#imm]
6864
6865 // ldr q,d,s,h,b from addr
6866 // addr = [Xn|SP],#imm or [Xn|SP,#imm]! or [Xn|SP,#imm]
6867
6868 // ldr q,d,s from pc+#imm19
6869
6870 // ldr q,d,s,h,b from addr
6871 // addr = [Xn|SP, R <extend> <shift]
6872
6873 // ldur q,d,s,h,b from addr
6874 // addr = [Xn|SP,#imm] (unscaled offset)
6875
6876 // st1 (multiple 1-element structures from 1/2/3/4 regs)
6877 // st1 (single 1-element structure for 1 lane of 1 reg)
6878
6879 // st2 (multiple 2-element structures from 2 regs)
6880 // st2 (single 2-element structure from 1 lane of 2 regs)
6881
6882 // st3 (multiple 3-element structures from 3 regs)
6883 // st3 (single 3-element structure from 1 lane of 3 regs)
6884
6885 // st4 (multiple 4-element structures from 4 regs)
6886 // st4 (single 4-element structure from one lane of 4 regs)
6887
6888 // stnp q_q_addr, d_d_addr, s_s_addr
6889 // addr = [Xn|SP, #imm]
6890
6891 // stp q_q_addr, d_d_addr, s_s_addr
6892 // addr = [Xn|SP], #imm or [Xn|SP, #imm]! or [Xn|SP, #imm]
6893
6894 // str q,d,s,h,b_addr
6895 // addr = [Xn|SP], #simm or [Xn|SP, #simm]! or [Xn|SP, #pimm]
6896
6897 // str q,d,s,h,b_addr
6898 // addr = [Xn|SP, R <extend> <shift]
6899
6900 // stur q,d,s,h,b_addr
6901 // addr = [Xn|SP,#imm] (unscaled offset)
6902
6903 // ======================== CRYPTO ========================
6904
6905 // aesd 16b (aes single round decryption)
6906 // aese 16b (aes single round encryption)
6907 // aesimc 16b (aes inverse mix columns)
6908 // aesmc 16b (aes mix columns)
6909 if (1) DO50( test_aesd_16b_16b(TyNONE) );
6910 if (1) DO50( test_aese_16b_16b(TyNONE) );
6911 if (1) DO50( test_aesimc_16b_16b(TyNONE) );
6912 if (1) DO50( test_aesmc_16b_16b(TyNONE) );
6913
6914 // sha1c q_s_4s
6915 // sha1h s_s
6916 // sha1m q_s_4s
6917 // sha1p q_s_4s
6918 // sha1su0 4s_4s_4s
6919 // sha1su1 4s_4s
6920 if (1) DO50( test_sha1c_q_s_4s(TyNONE) );
6921 if (1) DO50( test_sha1h_s_s(TyNONE) );
6922 if (1) DO50( test_sha1m_q_s_4s(TyNONE) );
6923 if (1) DO50( test_sha1p_q_s_4s(TyNONE) );
6924 if (1) DO50( test_sha1su0_4s_4s_4s(TyNONE) );
6925 if (1) DO50( test_sha1su1_4s_4s(TyNONE) );
6926
6927 // sha256h2 q_q_4s
6928 // sha256h q_q_4s
6929 // sha256su0 4s_4s
6930 // sha256su1 4s_4s_4s
6931 if (1) DO50( test_sha256h2_q_q_4s(TyNONE) );
6932 if (1) DO50( test_sha256h_q_q_4s(TyNONE) );
6933 if (1) DO50( test_sha256su0_4s_4s(TyNONE) );
6934 if (1) DO50( test_sha256su1_4s_4s_4s(TyNONE) );
6935
6936 // pmull{2} 1q_1d_1d,1q_2d_2d
6937 if (1) test_pmull_1q_1d_1d(TyD);
6938 if (1) test_pmull2_1q_2d_2d(TyD);
6939
6940 return 0;
6941 }
6942
6943
6944 /* ---------------------------------------------------------------- */
6945 /* -- Alphabetical list of insns -- */
6946 /* ---------------------------------------------------------------- */
6947 /*
6948 abs d
6949 abs 2d,4s,2s,8h,4h,16b,8b
6950 add d
6951 add 2d,4s,2s,8h,4h,16b,8b
6952 addhn 2s.2d.2d, 4s.2d.2d, h_from_s and b_from_h (add and get high half)
6953 addp d (add pairs, across)
6954 addp 2d,4s,2s,8h,4h,16b,8b
6955 addv 4s,8h,4h,16b,18b (reduce across vector)
6956 aesd 16b (aes single round decryption)
6957 aese 16b (aes single round encryption)
6958 aesimc 16b (aes inverse mix columns)
6959 aesmc 16b (aes mix columns)
6960 and 16b,8b
6961
6962 bic 4s,2s,8h,4h (vector, imm)
6963 also movi, mvni, orr
6964
6965 bic 16b,8b (vector,reg) (bit clear)
6966 bif 16b,8b (vector) (bit insert if false)
6967 bit 16b,8b (vector) (bit insert if true)
6968 bsl 16b,8b (vector) (bit select)
6969
6970 cls 4s,2s,8h,4h,16b,8b (count leading sign bits)
6971 clz 4s,2s,8h,4h,16b,8b (count leading zero bits)
6972
6973 cmeq d
6974 cmeq 2d,4s,2s,8h,4h,16b,8b
6975 cmeq_z d
6976 cmeq_z 2d,4s,2s,8h,4h,16b,8b
6977
6978 cmge d
6979 cmge 2d,4s,2s,8h,4h,16b,8b
6980 cmge_z d
6981 cmge_z 2d,4s,2s,8h,4h,16b,8b
6982
6983 cmgt d
6984 cmgt 2d,4s,2s,8h,4h,16b,8b
6985 cmgt_z d
6986 cmgt_z 2d,4s,2s,8h,4h,16b,8b
6987
6988 cmhi d
6989 cmhi 2d,4s,2s,8h,4h,16b,8b
6990
6991 cmhs d
6992 cmhs 2d,4s,2s,8h,4h,16b,8b
6993
6994 cmle_z d
6995 cmle_z 2d,4s,2s,8h,4h,16b,8b
6996
6997 cmlt_z d
6998 cmlt_z 2d,4s,2s,8h,4h,16b,8b
6999
7000 cmtst d
7001 cmtst 2d,4s,2s,8h,4h,16b,8b
7002
7003 cnt 16b,8b (population count per byte)
7004
7005 dup d,s,h,b (vec elem to scalar)
7006 dup 2d,4s,2s,8h,4h,16b,8b (vec elem to vector)
7007 dup 2d,4s,2s,8h,4h,16b,8b (general reg to vector)
7008
7009 eor 16b,8b (vector)
7010 ext 16b,8b,#imm4 (concat 2 vectors, then slice)
7011
7012 fabd d,s
7013 fabd 2d,4s,2s
7014
7015 fabs d,s
7016 fabs 2d,4s,2s
7017
7018 facge s,d (floating abs compare GE)
7019 facge 2d,4s,2s
7020
7021 facgt s,d (floating abs compare GE)
7022 facgt 2d,4s,2s
7023
7024 fadd d,s
7025 fadd 2d,4s,2s
7026
7027 faddp d,s (floating add pair)
7028 faddp 2d,4s,2s
7029
7030 fccmp d,s (floating point conditional quiet compare)
7031 fccmpe d,s (floating point conditional signaling compare)
7032
7033 fcmeq d,s
7034 fcmeq 2d,4s,2s
7035 fcmeq_z d,s
7036 fcmeq_z 2d,4s,2s
7037
7038 fcmge d,s
7039 fcmge 2d,4s,2s
7040 fcmge_z d,s
7041 fcmge_z 2d,4s,2s
7042
7043 fcmgt d,s
7044 fcmgt 2d,4s,2s
7045 fcmgt_z d,s
7046 fcmgt_z 2d,4s,2s
7047
7048 fcmle_z d,s
7049 fcmle_z 2d,4s,2s
7050
7051 fcmlt_z d,s
7052 fcmlt_z 2d,4s,2s
7053
7054 fcmp d,s (floating point quiet, set flags)
7055 fcmp_z d,s
7056 fcmpe d,s (floating point signaling, set flags)
7057 fcmpe_z d,s
7058
7059 fcsel d,s (fp cond select)
7060
7061 fcvt s_h,d_h,h_s,d_s,h_d,s_d (fp convert, scalar)
7062
7063 fcvtas d,s (fcvt to signed int, nearest, ties away)
7064 fcvtas 2d,4s,2s
7065 fcvtas w_s,x_s,w_d,x_d
7066
7067 fcvtau d,s (fcvt to unsigned int, nearest, ties away)
7068 fcvtau 2d,4s,2s
7069 fcvtau w_s,x_s,w_d,x_d
7070
7071 fcvtl{2} 4s/4h, 4s/8h, 2d/2s, 2d/4s (float convert to longer form)
7072
7073 fcvtms d,s (fcvt to signed int, minus inf)
7074 fcvtms 2d,4s,2s
7075 fcvtms w_s,x_s,w_d,x_d
7076
7077 fcvtmu d,s (fcvt to unsigned int, minus inf)
7078 fcvtmu 2d,4s,2s
7079 fcvtmu w_s,x_s,w_d,x_d
7080
7081 fcvtn{2} 4h/4s, 8h/4s, 2s/2d, 4s/2d (float convert to narrower form)
7082
7083 fcvtns d,s (fcvt to signed int, nearest)
7084 fcvtns 2d,4s,2s
7085 fcvtns w_s,x_s,w_d,x_d
7086
7087 fcvtnu d,s (fcvt to unsigned int, nearest)
7088 fcvtnu 2d,4s,2s
7089 fcvtnu w_s,x_s,w_d,x_d
7090
7091 fcvtps d,s (fcvt to signed int, plus inf)
7092 fcvtps 2d,4s,2s
7093 fcvtps w_s,x_s,w_d,x_d
7094
7095 fcvtpu d,s (fcvt to unsigned int, plus inf)
7096 fcvtpu 2d,4s,2s
7097 fcvtpu w_s,x_s,w_d,x_d
7098
7099 fcvtxn s_d (fcvt to lower prec narrow, rounding to odd)
7100 fcvtxn 2s_2d,4s_2d
7101
7102 fcvtzs s,d (fcvt to signed fixedpt, to zero) (w/ #fbits)
7103 fcvtzs 2d,4s,2s
7104
7105 fcvtzs s,d (fcvt to signed integer, to zero)
7106 fcvtzs 2d,4s,2s
7107
7108 fcvtzs w_s,x_s,w_d,x_d (fcvt to signed fixedpt, to zero) (w/ #fbits)
7109
7110 fcvtzs w_s,x_s,w_d,x_d (fcvt to signed integer, to zero)
7111
7112 fcvtzu s,d (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
7113 fcvtzu 2d,4s,2s
7114
7115 fcvtzu s,d (fcvt to unsigned integer, to zero)
7116 fcvtzu 2d,4s,2s
7117
7118 fcvtzu w_s,x_s,w_d,x_d (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
7119
7120 fcvtzu w_s,x_s,w_d,x_d (fcvt to unsigned integer, to zero)
7121
7122 fdiv d,s
7123 fdiv 2d,4s,2s
7124
7125 fmadd d,s
7126 fnmadd d,s
7127 fnmsub d,s
7128 fnmul d,s
7129
7130 fmax d,s
7131 fmin d,s
7132
7133 fmax 2d,4s,2s
7134 fmin 2d,4s,2s
7135
7136 fmaxnm d,s ("max number")
7137 fminnm d,s
7138
7139 fmaxnm 2d,4s,2s
7140 fminnm 2d,4s,2s
7141
7142 fmaxnmp d_2d,s_2s ("max number pairwise")
7143 fminnmp d_2d,s_2s
7144
7145 fmaxnmp 2d,4s,2s
7146 fminnmp 2d,4s,2s
7147
7148 fmaxnmv s_4s (maxnum across vector)
7149 fminnmv s_4s
7150
7151 fmaxp d_2d,s_2s (max of a pair)
7152 fminp d_2d,s_2s (max of a pair)
7153
7154 fmaxp 2d,4s,2s (max pairwise)
7155 fminp 2d,4s,2s
7156
7157 fmaxv s_4s (max across vector)
7158 fminv s_4s
7159
7160 fmla d_d_d[],s_s_s[] (by element)
7161 fmla 2d_2d_d[],4s_4s_s[],2s_2s_s[]
7162
7163 fmla 2d,4s,2s
7164
7165 fmls d_d_d[],s_s_s[] (by element)
7166 fmls 2d_2d_d[],4s_4s_s[],2s_2s_s[]
7167
7168 fmls 2d,4s,2s
7169
7170 fmov 2d,4s,2s #imm (part of the MOVI/MVNI/ORR/BIC imm group)
7171
7172 fmov d_d,s_s
7173
7174 fmov s_w,w_s,d_x,d[1]_x,x_d,x_d[1]
7175
7176 fmov d,s #imm
7177
7178 fmsub d,s
7179
7180 fmul d_d_d[],s_s_s[]
7181 fmul 2d_2d_d[],4s_4s_s[],2s_2s_s[]
7182
7183 fmul 2d,4s,2s
7184 fmul d,s
7185
7186 fmulx d_d_d[],s_s_s[]
7187 fmulx 2d_2d_d[],4s_4s_s[],2s_2s_s[]
7188
7189 fmulx d,s
7190 fmulx 2d,4s,2s
7191
7192 fneg d,s
7193 fneg 2d,4s,2s
7194
7195 frecpe d,s (recip estimate)
7196 frecpe 2d,4s,2s
7197
7198 frecps d,s (recip step)
7199 frecps 2d,4s,2s
7200
7201 frecpx d,s (recip exponent)
7202
7203 frinta 2d,4s,2s (round to integral, nearest away)
7204 frinta d,s
7205
7206 frinti 2d,4s,2s (round to integral, per FPCR)
7207 frinti d,s
7208
7209 frintm 2d,4s,2s (round to integral, minus inf)
7210 frintm d,s
7211
7212 frintn 2d,4s,2s (round to integral, nearest, to even)
7213 frintn d,s
7214
7215 frintp 2d,4s,2s (round to integral, plus inf)
7216 frintp d,s
7217
7218 frintx 2d,4s,2s (round to integral exact, per FPCR)
7219 frintx d,s
7220
7221 frintz 2d,4s,2s (round to integral, zero)
7222 frintz d,s
7223
7224 frsqrte d,s (est)
7225 frsqrte 2d,4s,2s
7226
7227 frsqrts d,s (step)
7228 frsqrts 2d,4s,2s
7229
7230 fsqrt d,s
7231 fsqrt 2d,4s,2s
7232
7233 fsub d,s
7234 fsub 2d,4s,2s
7235
7236 ins d[]_d[],s[]_s[],h[]_h[],b[]_b[]
7237
7238 ins d[]_x, s[]_w, h[]_w, b[]_w
7239
7240 ld1 (multiple 1-element structures to 1/2/3/4 regs)
7241 ld1 (single 1-element structure to one lane of 1 reg)
7242 ld1r (single 1-element structure and rep to all lanes of 1 reg)
7243
7244 ld2 (multiple 2-element structures to 2 regs)
7245 ld2 (single 2-element structure to one lane of 2 regs)
7246 ld2r (single 2-element structure and rep to all lanes of 2 regs)
7247
7248 ld3 (multiple 3-element structures to 3 regs)
7249 ld3 (single 3-element structure to one lane of 3 regs)
7250 ld3r (single 3-element structure and rep to all lanes of 3 regs)
7251
7252 ld4 (multiple 4-element structures to 4 regs)
7253 ld4 (single 4-element structure to one lane of 4 regs)
7254 ld4r (single 4-element structure and rep to all lanes of 4 regs)
7255
7256 ldnp q_q_addr,d_d_addr,s_s_addr (load pair w/ non-temporal hint)
7257 addr = reg + uimm7 * reg_size
7258
7259 ldp q_q_addr,d_d_addr,s_s_addr (load pair)
7260 addr = [Xn|SP],#imm or [Xn|SP,#imm]! or [Xn|SP,#imm]
7261
7262 ldr q,d,s,h,b from addr
7263 addr = [Xn|SP],#imm or [Xn|SP,#imm]! or [Xn|SP,#imm]
7264
7265 ldr q,d,s from pc+#imm19
7266
7267 ldr q,d,s,h,b from addr
7268 addr = [Xn|SP, R <extend> <shift]
7269
7270 ldur q,d,s,h,b from addr
7271 addr = [Xn|SP,#imm] (unscaled offset)
7272
7273 mla 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
7274 mla 4s,2s,8h,4h,16b,8b
7275
7276 mls 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
7277 mls 4s,2s,8h,4h,16b,8b
7278
7279 movi 16b,8b #imm8, LSL #0
7280 movi 8h,4h #imm8, LSL #0 or 8
7281 movi 4s,2s #imm8, LSL #0, 8, 16, 24
7282 movi 4s,2s #imm8, MSL #8 or 16
7283 movi d, #imm64
7284 movi 2d, #imm64
7285
7286 mul 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
7287 mul 4s,2s,8h,4h,16b,8b
7288
7289 mvni 8h,4h #imm8, LSL #0 or 8
7290 mvni 4s,2s #imm8, LSL #0, 8, 16, 24
7291 mvni 4s,2s #imm8, MSL #8 or 16
7292
7293 neg d
7294 neg 2d,4s,2s,8h,4h,16b,8b
7295
7296 not 16b,8b
7297
7298 orn 16b,8b
7299
7300 orr 8h,4h #imm8, LSL #0 or 8
7301 orr 4s,2s #imm8, LSL #0, 8, 16 or 24
7302
7303 orr 16b,8b
7304
7305 pmul 16b,8b
7306
7307 pmull{2} 8h_8b_8b,8h_16b_16b,1q_1d_1d,1d_2d_2d
7308
7309 raddhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
7310
7311 rbit 16b,8b
7312 rev16 16b,8b
7313 rev32 16b,8b,8h,4h
7314 rev64 16b,8b,8h,4h,4s,2s
7315
7316 rshrn{2} 2s/4s_2d, 8h/4h_4s, 2s/4s_2d, #imm in 1 .. elem_bits
7317
7318 rsubhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
7319
7320 saba 16b,8b,8h,4h,4s,2s
7321 sabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7322
7323 sabd 16b,8b,8h,4h,4s,2s
7324 sabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7325
7326 sadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
7327
7328 saddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7329
7330 saddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
7331
7332 saddlv h_16b/8b, s_8h/4h, d_4s
7333
7334 saddw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_2s/4s
7335
7336 scvtf d,s _#fbits
7337 scvtf 2d,4s,2s _#fbits
7338
7339 scvtf d,s
7340 scvtf 2d,4s,2s
7341
7342 scvtf s_w, d_w, s_x, d_x, _#fbits
7343 scvtf s_w, d_w, s_x, d_x
7344
7345 sha1c q_s_4s
7346 sha1h s_s
7347 sha1m q_s_4s
7348 sha1p q_s_4s
7349 sha1su0 4s_4s_4s
7350 sha1su1 4s_4s
7351 sha256h2 q_q_4s
7352 sha256h q_q_4s
7353 sha256su0 4s_4s
7354 sha256su1 4s_4s_4s
7355
7356 shadd 16b,8b,8h,4h,4s,2s
7357
7358 shl d_#imm
7359 shl 16b,8b,8h,4h,4s,2s,2d _#imm
7360
7361 shll{2} 8h_8b/16b_#8, 4s_4h/8h_#16, 2d_2s/4s_#32
7362
7363 shrn{2} 2s/4s_2d, 8h/4h_4s, 2s/4s_2d, #imm in 1 .. elem_bits
7364
7365 shsub 16b,8b,8h,4h,4s,2s
7366
7367 sli d_#imm
7368 sli 2d,4s,2s,8h,4h,16b,8b _#imm
7369
7370 smax 4s,2s,8h,4h,16b,8b
7371
7372 smaxp 4s,2s,8h,4h,16b,8b
7373
7374 smaxv s_4s,h_8h,h_4h,b_16b,b_8b
7375
7376 smin 4s,2s,8h,4h,16b,8b
7377
7378 sminp 4s,2s,8h,4h,16b,8b
7379
7380 sminv s_4s,h_8h,h_4h,b_16b,b_8b
7381
7382 smlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
7383 smlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7384
7385 smlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
7386 smlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7387
7388 smov w_b[], w_h[], x_b[], x_h[], x_s[]
7389
7390 smull{2} 2d_2s/4s_s[]. 4s_4h/8h_h[]
7391 smull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7392
7393 sqabs d,s,h,b
7394 sqabs 2d,4s,2s,8h,4h,16b,8b
7395
7396 sqadd d,s,h,b
7397 sqadd 2d,4s,2s,8h,4h,16b,8b
7398
7399 sqdmlal d_s_s[], s_h_h[]
7400 sqdmlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
7401
7402 sqdmlal d_s_s, s_h_h
7403 sqdmlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h)
7404
7405 sqdmlsl d_s_s[], s_h_h[]
7406 sqdmlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
7407
7408 sqdmlsl d_s_s, s_h_h
7409 sqdmlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h)
7410
7411 sqdmulh s_s_s[], h_h_h[]
7412 sqdmulh 4s_4s_s[], 2s_2s_s[], 8h_8h_h[], 4h_4h_h[]
7413
7414 sqdmulh h,s
7415 sqdmulh 4s,2s,8h,4h
7416
7417 sqdmull d_s_s[], s_h_h[]
7418 sqdmull{2} 2d_2s/4s_s[], 4s_4h/2h_h[]
7419
7420 sqdmull d_s_s,s_h_h
7421 sqdmull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h)
7422
7423 sqneg d,s,h,b
7424 sqneg 2d,4s,2s,8h,4h,16b,8b
7425
7426 sqrdmulh s_s_s[], h_h_h[]
7427 sqrdmulh 4s_4s_s[], 2s_2s_s[], 8h_8h_h[], 4h_4h_h[]
7428
7429 sqrdmulh h,s
7430 sqrdmulh 4s,2s,8h,4h
7431
7432 sqrshl d,s,h,b
7433 sqrshl 2d,4s,2s,8h,4h,16b,8b
7434
7435 sqrshrn s_d, h_s, b_h #imm
7436 sqrshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
7437
7438 sqrshrun s_d, h_s, b_h #imm
7439 sqrshrun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
7440
7441 sqshl d,s,h,b _#imm
7442 sqshl 2d,4s,2s,8h,4h,16b,8b _#imm
7443
7444 sqshl d,s,h,b
7445 sqshl 2d,4s,2s,8h,4h,16b,8b
7446
7447 sqshlu d,s,h,b _#imm
7448 sqshlu 2d,4s,2s,8h,4h,16b,8b _#imm
7449
7450 sqshrn s_d, h_s, b_h #imm
7451 sqshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
7452
7453 sqshrun s_d, h_s, b_h #imm
7454 sqshrun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
7455
7456 sqsub d,s,h,b
7457 sqsub 2d,4s,2s,8h,4h,16b,8b
7458
7459 sqxtn s_d,h_s,b_h
7460 sqxtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
7461
7462 sqxtun s_d,h_s,b_h
7463 sqxtun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
7464
7465 srhadd 4s,2s,8h,4h,16b,8b
7466
7467 sri d_#imm
7468 sri 2d,4s,2s,8h,4h,16b,8b _#imm
7469
7470 srshl (reg) d
7471 srshl 2d,4s,2s,8h,4h,16b,8b
7472
7473 srshr (imm) d
7474 srshr 2d,4s,2s,8h,4h,16b,8b
7475
7476 srsra (imm) d
7477 srsra 2d,4s,2s,8h,4h,16b,8b
7478
7479 sshl (reg) d
7480 sshl 2d,4s,2s,8h,4h,16b,8b
7481
7482 sshll{2} (imm) 2d_2s/4s 4s_4h/8h, 8h_8b/16b
7483
7484 sshr (imm) d
7485 sshr 2d,4s,2s,8h,4h,16b,8b
7486
7487 ssra (imm) d
7488 ssra 2d,4s,2s,8h,4h,16b,8b
7489
7490 ssubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7491
7492 ssubw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_2s/4s
7493
7494 st1 (multiple 1-element structures from 1/2/3/4 regs)
7495 st1 (single 1-element structure for 1 lane of 1 reg)
7496
7497 st2 (multiple 2-element structures from 2 regs)
7498 st2 (single 2-element structure from 1 lane of 2 regs)
7499
7500 st3 (multiple 3-element structures from 3 regs)
7501 st3 (single 3-element structure from 1 lane of 3 regs)
7502
7503 st4 (multiple 4-element structures from 4 regs)
7504 st4 (single 4-element structure from one lane of 4 regs)
7505
7506 stnp q_q_addr, d_d_addr, s_s_addr
7507 addr = [Xn|SP, #imm]
7508
7509 stp q_q_addr, d_d_addr, s_s_addr
7510 addr = [Xn|SP], #imm or [Xn|SP, #imm]! or [Xn|SP, #imm]
7511
7512 str q,d,s,h,b_addr
7513 addr = [Xn|SP], #simm or [Xn|SP, #simm]! or [Xn|SP, #pimm]
7514
7515 str q,d,s,h,b_addr
7516 addr = [Xn|SP, R <extend> <shift]
7517
7518 stur q,d,s,h,b_addr
7519 addr = [Xn|SP,#imm] (unscaled offset)
7520
7521 sub d
7522 sub 2d,4s,2s,8h,4h,16b,8b
7523
7524 subhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
7525
7526 suqadd d,s,h,b
7527 suqadd 2d,4s,2s,8h,4h,16b,8b
7528
7529 tbl 8b_{16b}_8b, 16b_{16b}_16b
7530 tbl 8b_{16b,16b}_8b, 16b_{16b,16b}_16b
7531 tbl 8b_{16b,16b,16b}_8b, 16b_{16b,16b,16b}_16b
7532 tbl 8b_{16b,16b,16b,16b}_8b, 16b_{16b,16b,16b,16b}_16b
7533
7534 tbx 8b_{16b}_8b, 16b_{16b}_16b
7535 tbx 8b_{16b,16b}_8b, 16b_{16b,16b}_16b
7536 tbx 8b_{16b,16b,16b}_8b, 16b_{16b,16b,16b}_16b
7537 tbx 8b_{16b,16b,16b,16b}_8b, 16b_{16b,16b,16b,16b}_16b
7538
7539 trn1 2d,4s,2s,8h,4h,16b,8b
7540 trn2 2d,4s,2s,8h,4h,16b,8b
7541
7542 uaba 16b,8b,8h,4h,4s,2s
7543 uabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7544
7545 uabd 16b,8b,8h,4h,4s,2s
7546 uabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7547
7548 uadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
7549
7550 uaddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7551
7552 uaddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
7553
7554 uaddlv h_16b/8b, s_8h/4h, d_4s
7555
7556 uaddw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_2s/4s
7557
7558 ucvtf d,s _#fbits
7559 ucvtf 2d,4s,2s _#fbits
7560
7561 ucvtf d,s
7562 ucvtf 2d,4s,2s
7563
7564 ucvtf s_w, d_w, s_x, d_x, _#fbits
7565 ucvtf s_w, d_w, s_x, d_x
7566
7567 uhadd 16b,8b,8h,4h,4s,2s
7568
7569 uhsub 16b,8b,8h,4h,4s,2s
7570
7571 umax 4s,2s,8h,4h,16b,8b
7572
7573 umaxp 4s,2s,8h,4h,16b,8b
7574
7575 umaxv s_4s,h_8h,h_4h,b_16b,b_8b
7576
7577 umin 4s,2s,8h,4h,16b,8b
7578
7579 uminp 4s,2s,8h,4h,16b,8b
7580
7581 uminv s_4s,h_8h,h_4h,b_16b,b_8b
7582
7583 umlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
7584 umlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7585
7586 umlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
7587 umlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7588
7589 umov w_b[], w_h[], x_b[], x_h[], x_s[]
7590
7591 umull{2} 2d_2s/4s_s[]. 4s_4h/8h_h[]
7592 umull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7593
7594 uqadd d,s,h,b
7595 uqadd 2d,4s,2s,8h,4h,16b,8b
7596
7597 uqrshl d,s,h,b
7598 uqrshl 2d,4s,2s,8h,4h,16b,8b
7599
7600 uqrshrn s_d, h_s, b_h #imm
7601 uqrshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
7602
7603 uqshl d,s,h,b _#imm
7604 uqshl 2d,4s,2s,8h,4h,16b,8b _#imm
7605
7606 uqshl d,s,h,b
7607 uqshl 2d,4s,2s,8h,4h,16b,8b
7608
7609 uqshrn s_d, h_s, b_h #imm
7610 uqshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
7611
7612 uqsub d,s,h,b
7613 uqsub 2d,4s,2s,8h,4h,16b,8b
7614
7615 uqxtn s_d,h_s,b_h
7616 uqxtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
7617
7618 urecpe 4s,2s
7619
7620 urhadd 4s,2s,8h,4h,16b,8b
7621
7622 urshl (reg) d
7623 urshl 2d,4s,2s,8h,4h,16b,8b
7624
7625 urshr (imm) d
7626 urshr 2d,4s,2s,8h,4h,16b,8b
7627
7628 ursqrte 4s,2s
7629
7630 ursra (imm) d
7631 ursra 2d,4s,2s,8h,4h,16b,8b
7632
7633 ushl (reg) d
7634 ushl 2d,4s,2s,8h,4h,16b,8b
7635
7636 ushll{2} (imm) 2d_2s/4s 4s_4h/8h, 8h_8b/16b
7637
7638 ushr (imm) d
7639 ushr 2d,4s,2s,8h,4h,16b,8b
7640
7641 usqadd d,s,h,b
7642 usqadd 2d,4s,2s,8h,4h,16b,8b
7643
7644 usra (imm) d
7645 usra 2d,4s,2s,8h,4h,16b,8b
7646
7647 usubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
7648
7649 usubw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_2s/4s
7650
7651 uzp1 2d,4s,2s,8h,4h,16b,8b
7652 uzp2 2d,4s,2s,8h,4h,16b,8b
7653
7654 xtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
7655
7656 zip1 2d,4s,2s,8h,4h,16b,8b
7657 zip2 2d,4s,2s,8h,4h,16b,8b
7658 */
7659
7660
7661 /* ---------------------------------------------------------------- */
7662 /* -- List of insns, grouped somewhat by laneage configuration -- */
7663 /* ---------------------------------------------------------------- */
7664 /*
7665 ======================== FP ========================
7666
7667 fabs d,s
7668 fabs 2d,4s,2s
7669
7670 fneg d,s
7671 fneg 2d,4s,2s
7672
7673 fsqrt d,s
7674 fsqrt 2d,4s,2s
7675
7676 fadd d,s
7677 fsub d,s
7678
7679 fadd 2d,4s,2s
7680 fsub 2d,4s,2s
7681
7682 fabd d,s
7683 fabd 2d,4s,2s
7684
7685 faddp d,s (floating add pair)
7686 faddp 2d,4s,2s
7687
7688 fccmp d,s (floating point conditional quiet compare)
7689 fccmpe d,s (floating point conditional signaling compare)
7690
7691 fcmeq d,s
7692 fcmge d,s
7693 fcmgt d,s
7694 facgt d,s (floating abs compare GE)
7695 facge d,s (floating abs compare GE)
7696
7697 fcmeq 2d,4s,2s
7698 fcmge 2d,4s,2s
7699 fcmgt 2d,4s,2s
7700 facge 2d,4s,2s
7701 facgt 2d,4s,2s
7702
7703 fcmeq_z d,s
7704 fcmge_z d,s
7705 fcmgt_z d,s
7706 fcmle_z d,s
7707 fcmlt_z d,s
7708
7709 fcmeq_z 2d,4s,2s
7710 fcmge_z 2d,4s,2s
7711 fcmgt_z 2d,4s,2s
7712 fcmle_z 2d,4s,2s
7713 fcmlt_z 2d,4s,2s
7714
7715 fcmp_z d,s
7716 fcmpe_z d,s
7717 fcmp d,s (floating point quiet, set flags)
7718 fcmpe d,s (floating point signaling, set flags)
7719
7720 fcsel d,s (fp cond select)
7721
7722 fdiv d,s
7723 fdiv 2d,4s,2s
7724
7725 fmadd d,s
7726 fnmadd d,s
7727 fmsub d,s
7728 fnmsub d,s
7729
7730 fnmul d,s
7731
7732 fmax d,s
7733 fmin d,s
7734 fmaxnm d,s ("max number")
7735 fminnm d,s
7736
7737 fmax 2d,4s,2s
7738 fmin 2d,4s,2s
7739 fmaxnm 2d,4s,2s
7740 fminnm 2d,4s,2s
7741
7742 fmaxnmp d_2d,s_2s ("max number pairwise")
7743 fminnmp d_2d,s_2s
7744
7745 fmaxnmp 2d,4s,2s
7746 fminnmp 2d,4s,2s
7747
7748 fmaxnmv s_4s (maxnum across vector)
7749 fminnmv s_4s
7750
7751 fmaxp d_2d,s_2s (max of a pair)
7752 fminp d_2d,s_2s (max of a pair)
7753
7754 fmaxp 2d,4s,2s (max pairwise)
7755 fminp 2d,4s,2s
7756
7757 fmaxv s_4s (max across vector)
7758 fminv s_4s
7759
7760 fmla 2d,4s,2s
7761 fmls 2d,4s,2s
7762
7763 fmla d_d_d[],s_s_s[] (by element)
7764 fmls d_d_d[],s_s_s[] (by element)
7765
7766 fmla 2d_2d_d[],4s_4s_s[],2s_2s_s[]
7767 fmls 2d_2d_d[],4s_4s_s[],2s_2s_s[]
7768
7769 fmov 2d,4s,2s #imm (part of the MOVI/MVNI/ORR/BIC imm group)
7770
7771 fmov d_d,s_s
7772
7773 fmov s_w,w_s,d_x,d[1]_x,x_d,x_d[1]
7774
7775 fmov d,s #imm
7776
7777 fmul d_d_d[],s_s_s[]
7778 fmul 2d_2d_d[],4s_4s_s[],2s_2s_s[]
7779
7780 fmul 2d,4s,2s
7781 fmul d,s
7782
7783 fmulx d_d_d[],s_s_s[]
7784 fmulx 2d_2d_d[],4s_4s_s[],2s_2s_s[]
7785
7786 fmulx d,s
7787 fmulx 2d,4s,2s
7788
7789 frecpe d,s (recip estimate)
7790 frecpe 2d,4s,2s
7791
7792 frecps d,s (recip step)
7793 frecps 2d,4s,2s
7794
7795 frecpx d,s (recip exponent)
7796
7797 frinta d,s
7798 frinti d,s
7799 frintm d,s
7800 frintn d,s
7801 frintp d,s
7802 frintx d,s
7803 frintz d,s
7804
7805 frinta 2d,4s,2s (round to integral, nearest away)
7806 frinti 2d,4s,2s (round to integral, per FPCR)
7807 frintm 2d,4s,2s (round to integral, minus inf)
7808 frintn 2d,4s,2s (round to integral, nearest, to even)
7809 frintp 2d,4s,2s (round to integral, plus inf)
7810 frintx 2d,4s,2s (round to integral exact, per FPCR)
7811 frintz 2d,4s,2s (round to integral, zero)
7812
7813 frsqrte d,s (est)
7814 frsqrte 2d,4s,2s
7815
7816 frsqrts d,s (step)
7817 frsqrts 2d,4s,2s
7818
7819 ======================== CONV ========================
7820
7821 fcvt s_h,d_h,h_s,d_s,h_d,s_d (fp convert, scalar)
7822
7823 fcvtl{2} 4s/4h, 4s/8h, 2d/2s, 2d/4s (float convert to longer form)
7824
7825 fcvtn{2} 4h/4s, 8h/4s, 2s/2d, 4s/2d (float convert to narrower form)
7826
7827 fcvtas d,s (fcvt to signed int, nearest, ties away)
7828 fcvtau d,s (fcvt to unsigned int, nearest, ties away)
7829 fcvtas 2d,4s,2s
7830 fcvtau 2d,4s,2s
7831 fcvtas w_s,x_s,w_d,x_d
7832 fcvtau w_s,x_s,w_d,x_d
7833
7834 fcvtms d,s (fcvt to signed int, minus inf)
7835 fcvtmu d,s (fcvt to unsigned int, minus inf)
7836 fcvtms 2d,4s,2s
7837 fcvtmu 2d,4s,2s
7838 fcvtms w_s,x_s,w_d,x_d
7839 fcvtmu w_s,x_s,w_d,x_d
7840
7841 fcvtns d,s (fcvt to signed int, nearest)
7842 fcvtnu d,s (fcvt to unsigned int, nearest)
7843 fcvtns 2d,4s,2s
7844 fcvtnu 2d,4s,2s
7845 fcvtns w_s,x_s,w_d,x_d
7846 fcvtnu w_s,x_s,w_d,x_d
7847
7848 fcvtps d,s (fcvt to signed int, plus inf)
7849 fcvtpu d,s (fcvt to unsigned int, plus inf)
7850 fcvtps 2d,4s,2s
7851 fcvtpu 2d,4s,2s
7852 fcvtps w_s,x_s,w_d,x_d
7853 fcvtpu w_s,x_s,w_d,x_d
7854
7855 fcvtzs d,s (fcvt to signed integer, to zero)
7856 fcvtzu d,s (fcvt to unsigned integer, to zero)
7857 fcvtzs 2d,4s,2s
7858 fcvtzu 2d,4s,2s
7859 fcvtzs w_s,x_s,w_d,x_d
7860 fcvtzu w_s,x_s,w_d,x_d
7861
7862 fcvtzs d,s (fcvt to signed fixedpt, to zero) (w/ #fbits)
7863 fcvtzu d,s (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
7864 fcvtzs 2d,4s,2s
7865 fcvtzu 2d,4s,2s
7866 fcvtzs w_s,x_s,w_d,x_d (fcvt to signed fixedpt, to zero) (w/ #fbits)
7867 fcvtzu w_s,x_s,w_d,x_d (fcvt to unsigned fixedpt, to zero) (w/ #fbits)
7868
7869 fcvtxn s_d (fcvt to lower prec narrow, rounding to odd)
7870 fcvtxn 2s_2d,4s_2d
7871
7872 scvtf d,s _#fbits
7873 ucvtf d,s _#fbits
7874
7875 scvtf 2d,4s,2s _#fbits
7876 ucvtf 2d,4s,2s _#fbits
7877
7878 scvtf d,s
7879 ucvtf d,s
7880
7881 scvtf 2d,4s,2s
7882 ucvtf 2d,4s,2s
7883
7884 scvtf s_w, d_w, s_x, d_x, _#fbits
7885 ucvtf s_w, d_w, s_x, d_x, _#fbits
7886
7887 scvtf s_w, d_w, s_x, d_x
7888 ucvtf s_w, d_w, s_x, d_x
7889
7890 ======================== INT ========================
7891
7892 abs d
7893 neg d
7894
7895 abs 2d,4s,2s,8h,4h,16b,8b
7896 neg 2d,4s,2s,8h,4h,16b,8b
7897
7898 add d
7899 sub d
7900
7901 add 2d,4s,2s,8h,4h,16b,8b
7902 sub 2d,4s,2s,8h,4h,16b,8b
7903
7904 addhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
7905 subhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
7906 raddhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
7907 rsubhn{2} 2s/4s_2d_2d, 4h/8h_4s_4s, 8b/16b_8h_8h
7908
7909 addp d (add pairs, across)
7910 addp 2d,4s,2s,8h,4h,16b,8b
7911 addv 4s,8h,4h,16b,18b (reduce across vector)
7912
7913 and 16b,8b
7914
7915 orr 8h,4h #imm8, LSL #0 or 8
7916 orr 4s,2s #imm8, LSL #0, 8, 16 or 24
7917 bic 8h,4h #imm8, LSL #0 or 8
7918 bic 4s,2s #imm8, LSL #0, 8, 16 or 24
7919 also movi, mvni
7920
7921 bic 16b,8b (vector,reg) (bit clear)
7922 bif 16b,8b (vector) (bit insert if false)
7923 bit 16b,8b (vector) (bit insert if true)
7924 bsl 16b,8b (vector) (bit select)
7925
7926 cls 4s,2s,8h,4h,16b,8b (count leading sign bits)
7927 clz 4s,2s,8h,4h,16b,8b (count leading zero bits)
7928
7929 cmeq d
7930 cmge d
7931 cmgt d
7932 cmhi d
7933 cmhs d
7934 cmtst d
7935
7936 cmeq 2d,4s,2s,8h,4h,16b,8b
7937 cmge 2d,4s,2s,8h,4h,16b,8b
7938 cmgt 2d,4s,2s,8h,4h,16b,8b
7939 cmhi 2d,4s,2s,8h,4h,16b,8b
7940 cmhs 2d,4s,2s,8h,4h,16b,8b
7941 cmtst 2d,4s,2s,8h,4h,16b,8b
7942
7943 cmeq_z d
7944 cmge_z d
7945 cmgt_z d
7946 cmle_z d
7947 cmlt_z d
7948
7949 cmeq_z 2d,4s,2s,8h,4h,16b,8b
7950 cmge_z 2d,4s,2s,8h,4h,16b,8b
7951 cmgt_z 2d,4s,2s,8h,4h,16b,8b
7952 cmle_z 2d,4s,2s,8h,4h,16b,8b
7953 cmlt_z 2d,4s,2s,8h,4h,16b,8b
7954
7955 cnt 16b,8b (population count per byte)
7956
7957 dup d,s,h,b (vec elem to scalar)
7958 dup 2d,4s,2s,8h,4h,16b,8b (vec elem to vector)
7959 dup 2d,4s,2s,8h,4h,16b,8b (general reg to vector)
7960
7961 eor 16b,8b (vector)
7962 ext 16b,8b,#imm4 (concat 2 vectors, then slice)
7963
7964 ins d[]_d[],s[]_s[],h[]_h[],b[]_b[]
7965
7966 ins d[]_x, s[]_w, h[]_w, b[]_w
7967
7968 mla 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
7969 mla 4s,2s,8h,4h,16b,8b
7970
7971 mls 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
7972 mls 4s,2s,8h,4h,16b,8b
7973
7974 movi 16b,8b #imm8, LSL #0
7975 movi 8h,4h #imm8, LSL #0 or 8
7976 movi 4s,2s #imm8, LSL #0, 8, 16, 24
7977 movi 4s,2s #imm8, MSL #8 or 16
7978 movi d, #imm64
7979 movi 2d, #imm64
7980
7981 mul 4s_4s_s[],2s_2s_s[],8h_8h_h[],4h_4h_h[]
7982 mul 4s,2s,8h,4h,16b,8b
7983
7984 mvni 8h,4h #imm8, LSL #0 or 8
7985 mvni 4s,2s #imm8, LSL #0, 8, 16, 24
7986 mvni 4s,2s #imm8, MSL #8 or 16
7987
7988 not 16b,8b
7989
7990 orn 16b,8b
7991 orr 16b,8b
7992
7993 pmul 16b,8b
7994
7995 pmull{2} 8h_8b_8b,8h_16b_16b,1q_1d_1d,1d_2d_2d
7996
7997 rbit 16b,8b
7998 rev16 16b,8b
7999 rev32 16b,8b,8h,4h
8000 rev64 16b,8b,8h,4h,4s,2s
8001
8002 saba 16b,8b,8h,4h,4s,2s
8003 uaba 16b,8b,8h,4h,4s,2s
8004
8005 sabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8006 uabal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8007
8008 sabd 16b,8b,8h,4h,4s,2s
8009 uabd 16b,8b,8h,4h,4s,2s
8010
8011 sabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8012 uabdl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8013
8014 sadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
8015 uadalp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
8016
8017 saddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8018 uaddl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8019 ssubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8020 usubl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8021
8022 saddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
8023 uaddlp 4h_8b,8h_16b,2s_4h,4s_8h,1d_2s,2d_4s
8024
8025 saddlv h_16b/8b, s_8h/4h, d_4s
8026 uaddlv h_16b/8b, s_8h/4h, d_4s
8027
8028 saddw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_2s/4s
8029 uaddw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_2s/4s
8030 ssubw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_2s/4s
8031 usubw{2} 8h_8h_16b/8b, 4s_4s_8h/4h, 2d_2d_2s/4s
8032
8033 shadd 16b,8b,8h,4h,4s,2s
8034 uhadd 16b,8b,8h,4h,4s,2s
8035 shsub 16b,8b,8h,4h,4s,2s
8036 uhsub 16b,8b,8h,4h,4s,2s
8037
8038 shl d_#imm
8039 shl 16b,8b,8h,4h,4s,2s,2d _#imm
8040
8041 shll{2} 8h_8b/16b_#8, 4s_4h/8h_#16, 2d_2s/4s_#32
8042
8043 shrn{2} 2s/4s_2d, 8h/4h_4s, 2s/4s_2d, #imm in 1 .. elem_bits
8044 rshrn{2} 2s/4s_2d, 8h/4h_4s, 2s/4s_2d, #imm in 1 .. elem_bits
8045
8046 sli d_#imm
8047 sri d_#imm
8048
8049 sli 2d,4s,2s,8h,4h,16b,8b _#imm
8050 sri 2d,4s,2s,8h,4h,16b,8b _#imm
8051
8052 smax 4s,2s,8h,4h,16b,8b
8053 umax 4s,2s,8h,4h,16b,8b
8054 smin 4s,2s,8h,4h,16b,8b
8055 umin 4s,2s,8h,4h,16b,8b
8056
8057 smaxp 4s,2s,8h,4h,16b,8b
8058 umaxp 4s,2s,8h,4h,16b,8b
8059 sminp 4s,2s,8h,4h,16b,8b
8060 uminp 4s,2s,8h,4h,16b,8b
8061
8062 smaxv s_4s,h_8h,h_4h,b_16b,b_8b
8063 umaxv s_4s,h_8h,h_4h,b_16b,b_8b
8064 sminv s_4s,h_8h,h_4h,b_16b,b_8b
8065 uminv s_4s,h_8h,h_4h,b_16b,b_8b
8066
8067 smlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
8068 umlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
8069 smlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
8070 umlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
8071 smull{2} 2d_2s/4s_s[]. 4s_4h/8h_h[]
8072 umull{2} 2d_2s/4s_s[]. 4s_4h/8h_h[]
8073
8074 smlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8075 umlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8076 smlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8077 umlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8078 smull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8079 umull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h), 8h_(8b_8b)/(16b_16b)
8080
8081 smov w_b[], w_h[], x_b[], x_h[], x_s[]
8082 umov w_b[], w_h[], x_b[], x_h[], x_s[]
8083
8084 sqabs d,s,h,b
8085 sqneg d,s,h,b
8086
8087 sqabs 2d,4s,2s,8h,4h,16b,8b
8088 sqneg 2d,4s,2s,8h,4h,16b,8b
8089
8090 sqadd d,s,h,b
8091 uqadd d,s,h,b
8092 sqsub d,s,h,b
8093 uqsub d,s,h,b
8094
8095 sqadd 2d,4s,2s,8h,4h,16b,8b
8096 uqadd 2d,4s,2s,8h,4h,16b,8b
8097 sqsub 2d,4s,2s,8h,4h,16b,8b
8098 uqsub 2d,4s,2s,8h,4h,16b,8b
8099
8100 sqdmlal d_s_s[], s_h_h[]
8101 sqdmlsl d_s_s[], s_h_h[]
8102 sqdmull d_s_s[], s_h_h[]
8103
8104 sqdmlal{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
8105 sqdmlsl{2} 2d_2s/4s_s[], 4s_4h/8h_h[]
8106 sqdmull{2} 2d_2s/4s_s[], 4s_4h/2h_h[]
8107
8108 sqdmlal d_s_s, s_h_h
8109 sqdmlsl d_s_s, s_h_h
8110 sqdmull d_s_s, s_h_h
8111
8112 sqdmlal{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h)
8113 sqdmlsl{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h)
8114 sqdmull{2} 2d_(2s_2s)/(4s_4s), 4s_(4h_4h)/(8h_8h)
8115
8116 sqdmulh s_s_s[], h_h_h[]
8117 sqrdmulh s_s_s[], h_h_h[]
8118
8119 sqdmulh 4s_4s_s[], 2s_2s_s[], 8h_8h_h[], 4h_4h_h[]
8120 sqrdmulh 4s_4s_s[], 2s_2s_s[], 8h_8h_h[], 4h_4h_h[]
8121
8122 sqdmulh h,s
8123 sqrdmulh h,s
8124
8125 sqdmulh 4s,2s,8h,4h
8126 sqrdmulh 4s,2s,8h,4h
8127
8128 sqshl d,s,h,b
8129 uqshl d,s,h,b
8130 sqrshl d,s,h,b
8131 uqrshl d,s,h,b
8132
8133 sqshl 2d,4s,2s,8h,4h,16b,8b
8134 uqshl 2d,4s,2s,8h,4h,16b,8b
8135 sqrshl 2d,4s,2s,8h,4h,16b,8b
8136 uqrshl 2d,4s,2s,8h,4h,16b,8b
8137
8138 sqrshrn s_d, h_s, b_h #imm
8139 uqrshrn s_d, h_s, b_h #imm
8140 sqshrn s_d, h_s, b_h #imm
8141 uqshrn s_d, h_s, b_h #imm
8142
8143 sqrshrun s_d, h_s, b_h #imm
8144 sqshrun s_d, h_s, b_h #imm
8145
8146 sqrshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
8147 uqrshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
8148 sqshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
8149 uqshrn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
8150
8151 sqrshrun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
8152 sqshrun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h, #imm
8153
8154 sqshl d,s,h,b _#imm
8155 uqshl d,s,h,b _#imm
8156 sqshlu d,s,h,b _#imm
8157
8158 sqshl 2d,4s,2s,8h,4h,16b,8b _#imm
8159 uqshl 2d,4s,2s,8h,4h,16b,8b _#imm
8160 sqshlu 2d,4s,2s,8h,4h,16b,8b _#imm
8161
8162 sqxtn s_d,h_s,b_h
8163 uqxtn s_d,h_s,b_h
8164 sqxtun s_d,h_s,b_h
8165
8166 sqxtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
8167 uqxtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
8168 sqxtun{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
8169
8170 srhadd 4s,2s,8h,4h,16b,8b
8171 urhadd 4s,2s,8h,4h,16b,8b
8172
8173 sshl (reg) d
8174 ushl (reg) d
8175 sshr (imm) d
8176 ushr (imm) d
8177 ssra (imm) d
8178 usra (imm) d
8179
8180 srshl (reg) d
8181 urshl (reg) d
8182 srshr (imm) d
8183 urshr (imm) d
8184 srsra (imm) d
8185 ursra (imm) d
8186
8187 sshl 2d,4s,2s,8h,4h,16b,8b
8188 ushl 2d,4s,2s,8h,4h,16b,8b
8189 sshr 2d,4s,2s,8h,4h,16b,8b
8190 ushr 2d,4s,2s,8h,4h,16b,8b
8191 ssra 2d,4s,2s,8h,4h,16b,8b
8192 usra 2d,4s,2s,8h,4h,16b,8b
8193
8194 srshl 2d,4s,2s,8h,4h,16b,8b
8195 urshl 2d,4s,2s,8h,4h,16b,8b
8196 srshr 2d,4s,2s,8h,4h,16b,8b
8197 urshr 2d,4s,2s,8h,4h,16b,8b
8198 srsra 2d,4s,2s,8h,4h,16b,8b
8199 ursra 2d,4s,2s,8h,4h,16b,8b
8200
8201 sshll{2} (imm) 2d_2s/4s 4s_4h/8h, 8h_8b/16b
8202 ushll{2} (imm) 2d_2s/4s 4s_4h/8h, 8h_8b/16b
8203
8204 suqadd d,s,h,b
8205 suqadd 2d,4s,2s,8h,4h,16b,8b
8206
8207 tbl 8b_{16b}_8b, 16b_{16b}_16b
8208 tbl 8b_{16b,16b}_8b, 16b_{16b,16b}_16b
8209 tbl 8b_{16b,16b,16b}_8b, 16b_{16b,16b,16b}_16b
8210 tbl 8b_{16b,16b,16b,16b}_8b, 16b_{16b,16b,16b,16b}_16b
8211
8212 tbx 8b_{16b}_8b, 16b_{16b}_16b
8213 tbx 8b_{16b,16b}_8b, 16b_{16b,16b}_16b
8214 tbx 8b_{16b,16b,16b}_8b, 16b_{16b,16b,16b}_16b
8215 tbx 8b_{16b,16b,16b,16b}_8b, 16b_{16b,16b,16b,16b}_16b
8216
8217 trn1 2d,4s,2s,8h,4h,16b,8b
8218 trn2 2d,4s,2s,8h,4h,16b,8b
8219
8220 urecpe 4s,2s
8221
8222 ursqrte 4s,2s
8223
8224 usqadd d,s,h,b
8225 usqadd 2d,4s,2s,8h,4h,16b,8b
8226
8227 uzp1 2d,4s,2s,8h,4h,16b,8b
8228 uzp2 2d,4s,2s,8h,4h,16b,8b
8229
8230 xtn{2} 2s/4s_2d, 4h/8h_4s, 8b/16b_8h
8231
8232 zip1 2d,4s,2s,8h,4h,16b,8b
8233 zip2 2d,4s,2s,8h,4h,16b,8b
8234
8235 ======================== MEM ========================
8236
8237 ld1 (multiple 1-element structures to 1/2/3/4 regs)
8238 ld1 (single 1-element structure to one lane of 1 reg)
8239 ld1r (single 1-element structure and rep to all lanes of 1 reg)
8240
8241 ld2 (multiple 2-element structures to 2 regs)
8242 ld2 (single 2-element structure to one lane of 2 regs)
8243 ld2r (single 2-element structure and rep to all lanes of 2 regs)
8244
8245 ld3 (multiple 3-element structures to 3 regs)
8246 ld3 (single 3-element structure to one lane of 3 regs)
8247 ld3r (single 3-element structure and rep to all lanes of 3 regs)
8248
8249 ld4 (multiple 4-element structures to 4 regs)
8250 ld4 (single 4-element structure to one lane of 4 regs)
8251 ld4r (single 4-element structure and rep to all lanes of 4 regs)
8252
8253 ldnp q_q_addr,d_d_addr,s_s_addr (load pair w/ non-temporal hint)
8254 addr = reg + uimm7 * reg_size
8255
8256 ldp q_q_addr,d_d_addr,s_s_addr (load pair)
8257 addr = [Xn|SP],#imm or [Xn|SP,#imm]! or [Xn|SP,#imm]
8258
8259 ldr q,d,s,h,b from addr
8260 addr = [Xn|SP],#imm or [Xn|SP,#imm]! or [Xn|SP,#imm]
8261
8262 ldr q,d,s from pc+#imm19
8263
8264 ldr q,d,s,h,b from addr
8265 addr = [Xn|SP, R <extend> <shift]
8266
8267 ldur q,d,s,h,b from addr
8268 addr = [Xn|SP,#imm] (unscaled offset)
8269
8270 st1 (multiple 1-element structures from 1/2/3/4 regs)
8271 st1 (single 1-element structure for 1 lane of 1 reg)
8272
8273 st2 (multiple 2-element structures from 2 regs)
8274 st2 (single 2-element structure from 1 lane of 2 regs)
8275
8276 st3 (multiple 3-element structures from 3 regs)
8277 st3 (single 3-element structure from 1 lane of 3 regs)
8278
8279 st4 (multiple 4-element structures from 4 regs)
8280 st4 (single 4-element structure from one lane of 4 regs)
8281
8282 stnp q_q_addr, d_d_addr, s_s_addr
8283 addr = [Xn|SP, #imm]
8284
8285 stp q_q_addr, d_d_addr, s_s_addr
8286 addr = [Xn|SP], #imm or [Xn|SP, #imm]! or [Xn|SP, #imm]
8287
8288 str q,d,s,h,b_addr
8289 addr = [Xn|SP], #simm or [Xn|SP, #simm]! or [Xn|SP, #pimm]
8290
8291 str q,d,s,h,b_addr
8292 addr = [Xn|SP, R <extend> <shift]
8293
8294 stur q,d,s,h,b_addr
8295 addr = [Xn|SP,#imm] (unscaled offset)
8296
8297 ======================== CRYPTO ========================
8298
8299 aesd 16b (aes single round decryption)
8300 aese 16b (aes single round encryption)
8301 aesimc 16b (aes inverse mix columns)
8302 aesmc 16b (aes mix columns)
8303
8304 sha1c q_s_4s
8305 sha1h s_s
8306 sha1m q_s_4s
8307 sha1p q_s_4s
8308 sha1su0 4s_4s_4s
8309 sha1su1 4s_4s
8310
8311 sha256h2 q_q_4s
8312 sha256h q_q_4s
8313 sha256su0 4s_4s
8314 sha256su1 4s_4s_4s
8315 */
Instrumentation framework for detecting many memory management and threading bugs, and profile your programs in detail.